Integrated
Circuit
Systems, Inc.
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Recommended Application:
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A
• Optimized for DDR2 400/533/667 JEDEC 4 Rank
VLP DIMMS
Product Features:
• 28-bit 1:1 registered buffer with parity check
functionality
• Supports SSTL_18 JEDEC specification on data
inputs and outputs
• Supports LVCMOS switching levels on RESET input
• 50% more dynamic driver strength than standard
SSTU32864
• Low voltage operation
VDD = 1.7V to 1.9V
• Available in 96 BGA package
28-Bit Registered Buffer for DDR2
Functionality Truth Table
Pin Configuration
96 Ball BGA
(Top View)
In puts Outputs
RESET DCS0 DCS1 CK
CK
Dn,
DODTn,
DCKEn
Qn QCS QODT,
QCKE
HLL↑LLLL
HLL
↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
↑↓
HHLH
H L L L or H L or H X Q
0
Q
0
Q
0
HLH LLLL
HLH HHLH
H L H L or H L or H X Q
0
Q
0
Q
0
HHL LLHL
HHL HHHH
H H L L or H L or H X Q
0
Q
0
Q
0
L or HL or H X
HHH LQ
0
HL
HHH H
Q
0
HH
HHH
Q
0
Q
0
Q
0
LX or
floating
X or
floating
X or
floating
X or
floating
X or
floating LLL
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
65
4
3
21
2
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Ball Assignments
28 bit 1:1 Register
A
DCKE0 D0 VDD QCKE0 QCKE1
B
D1 GND GND Q0 Q1
C
D2 DODT1 VDD VDD Q2 Q21
D
DODT0 PTYERR GND GND QODT0
E
D3 D4 VDD VDD Q3 Q4
F
D5 D6 GND GND Q5 Q6
G
PAR_IN RESET VDD VDD NC NC
H
CK DCS0 GND GND QCS0 QCS1
J
CK DCS1 VDD VDD NC NC
K
D7 D8 GND GND Q7 Q8
L
D9D10 VDD VDD Q9Q10
M
D11 D12 GND GND Q11 Q12
N
D13 D14 VDD VDD Q13 Q14
P
D15 D16 GND GND Q15 Q16
R
D17 D18 VDD VDD Q17 Q18
T
D19D20 VDD Q19Q20
123456
DCKE1
VREF
D21
QODT1
3
1222F—3/13/07
ICSSSTUB32872A
Advance Information
General Description
This 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are
LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load.
The ICSSSTUB32872A operates from a differential clock (CK and CK). Data are registered at the crossing of CK
going high, and CK going low.
The device supports low-power standby operation. When the reset input (RESET) is low, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are
allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced
low. The LVCMOS RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held
in the low state during power up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK
and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the
register will be cleared and the outputs will be driven low quickly, relative to the time to disable the
differential input receivers. However, when coming out of reset, the register will become active quickly,
relative to the time to enable the differential input receivers. As long as the data inputs are low, and the
clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully
enabled, the design of the ICSSSTUB32872A must ensure that the outputs will remain low, thus ensuring no
glitches on the output.
The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when
both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function
normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs
low and the PTYERR output high.
The ICSSSTU32872A includes a parity checking function. The ICSSSTUB32872A accepts a parity bit from the
memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
Package options include 96-ball Thin Profile Fine Pitch BGA (TFBGA, MO-TBD).
Inputs Output
RESET DCS0 DCS1 CK CK of inputs = H
(D0-D21) PARIN* PTYERR**
HLH Even L H
HLH Odd L L
HLH Even H L
HLH Odd H H
HHL Even L H
HHL Odd L L
HHL Even H L
HHL Odd H H
HHH XX
PTYERR
0
PTYERR
0
H X X L or H L or H X X
LX or
floating
X or
floating
X or
floating
X or
floating X or floating X or
floating H
*PARIN arrives one clock cycle after the data to which it applies.
** This transition assumes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR
is
low, it stays latched low for two clock cycles or until RESET is driven low.
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
4
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Ball Assignment
Signal Group Signal Name Type Description
Ungated inputs DCKE0, DCKE1,
DODT0, DODT1
SSTL_18 DRAM function pins not associated with Chip Select.
Chip Select
gated inputs
D0 ... D21 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW.
Chip Select
inputs
DCS0 , DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
low when a valid address/command is present. The register
can be programmed to re-drive all D-inputs
Re-driven
outputs
Q0...Q21,
QCS0-1,
QCKE0-1,
QODT0-1
SSTL_18
Outputs of the register, valid after the specified clock count
and immediately following a rising edge of the clock.
Parity input PARIN SSTL_18 Input parity is received on pin PARIN and should maintain
odd parity across the D0...D20 inputs, at the rising edge of the
clock.
Parity error
output
PTYERR Open drain When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR will be active for two clock cycles, and delayed by
an additional clock cycle for compatibility with final parity
out timing on the industry-standard DDR-II register with
parity (in JEDEC definition).
Clock inputs CK, CK SSTL_18 Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the positive
clock input (CK).
Miscellaneous
inputs RESET 1.8 V
LVCMOS
Asynchronous reset input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET
also resets the PTYERR signal.
VREF 0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
when at least
one Chip Slect input is LOW.
5
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Block Diagram
DQ
R
DQ
R
DQ
R
DQ
R
DQ
R
DQ
R
DQ
R
PARIN
D0
D21
VREF
(CS ACTIVE)
DCS0
DCS1
DCKE0,
DCKE1
DODT0,
DODT1
RESET
CK
CK
22
PA R I T Y
GENERATOR
AND
CHECKER
Q0
Q21
QCS0
QCS1
QCKE0,
QCKE1
QODT0,
QODT1
PTYERR
2
2
2
2
6
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Parity Functionality Block Diagram
D
21
D
DLATCHING AND
RESET FUNCTION
see Note (1)
PTYERR
DQn
Dn
PARIN
CLOCK
Q
002aaa417
21
(1) This function holds the error for two
cycles. See functional description and
timing diagram.
7
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Register Timing
CK
Dn
(1)
Qn
tsu
CK
n n + 1 n + 2 n + 3 n + 4
DCSn
RESET
tACT th
tPDM, tPDMSS
CK to Q
PARIN
tsu th
tPHL, tPLH
CK to PTYERR
tPHL
CK to PTYERR
PTYERR
H, L, or X H or L
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a
minimum time of t (max) to avoid false error.
ACT
Figure 4 RESET switches from L to H
—
8
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Register Timing
Figure 5 — RESET being held HIGH
CK
Dn
(1)
Qn
tsu
002aaa984
CK
n n + 1 n + 2 n + 3 n + 4
DCSn
RESET
th
tPDM, tPDMSS
CK to Q
PARIN
th
tPHL, tPLH
CK to PTYERR
PTYERR
Output signal is dependent on the prior unknown event H or L
Unknown input event
tsu
9
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Register Timing
Figure 6 — RESET
CK
(1)
DCSn
RESET
tINACT
tRPHL
RESET to Q
PA R I N
(1)
tRPLH
RESET to PTYERR
PTYERR
H, L, or X H or L
CK
(1)
Dn
(1)
Qn
switches from H to L
(1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic
levels (not floating) for a minimum time of t (max)
INACT
10
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V
Input Voltage1, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD +2.5V
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDDQ + 0.5V
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50mA
Continuous Output Current. . . . . . . . . . . . . . . ±50mA
VDD or GND Current/Pin . . . . . . . . . . . . . . . . ±100mA
Package Thermal Impedance3. . . . . . . . . . . . . . . 36°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This value is limited to 2.5V maximum.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Recommended Operating Conditions
PARAMETER MIN TYP MAX UNITS
VDDQ 1.7 1.8 1.9
VREF 0.49 x VDD 0.5 x VDD 0.51 x VDD
VTT VREF - 0.04 VREF VREF + 0.04
VIInput Voltage 0 VDDQ
VIH
(
DC
)
DC Input High Voltage VREF + 0.125
VIH
(
AC
)
AC Input High Voltage VREF + 0.250
VIL
(
DC
)
DC Input Low Voltage VREF - 0.125
VIL
(
AC
)
AC Input Low Voltage VREF - 0.250
VIH Input High Voltage Level 0.65 x VDDQ
VIL Input Low Voltage Level 0.35 x VDDQ
VICR Common mode Input Range 0.675 1.125
VID Differential Input Voltage 0.600
IOH -8
IOL 8
TA070°C
1Guaranteed by design, not 100% tested in production.
mA
Note: Rst and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless Rst is low.
V
DESCRIPTION
I/O Supply Voltage
Reference Voltage
Operating Free-Air Temperature
RESET
CK, CK
Low-Level Output Current
Termination Voltage
High-Level Output Current
Data Inputs
11
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN MAX
dV/dt_r 1 4 V/ns
dV/dt_f 1 4 V/ns
dV/dt_Δ
1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER V
DD
= 1.8V ± 0.1V UNIT
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL PARAMETERS VDDQ MIN TYP MAX UNITS
VOH IOH = -8mA 1.7V 1.2
VOL IOL = 8mA 1.7V 0.5
IIAll Inputs VI = VD
D
or GND 1.9V ±5 µA
Standby (Static) RESET = GND 200 µA
Operating (Static) VI = VIH(AC) or VIL(AC),
RESET = VD
D
150 mA
Dynamic operating
(clock only)
RESET = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching
50% duty cycle.
TBD µA/clock
MHz
Dynamic Operating
(per each data
input)
RESET = VDD,
VI = VIH(AC) or VIL (AC),
CLK and CLK switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
TBD µA/ clock
MHz/data
Data Inputs 2.5 5
CLK and CLK 2 3.8
RESET 4.5 pF
Notes:
1 - Guaranteed by design, not 100% tested in production.
Ci
VI = VDDQ or GND
IDD
IDDD
IO = 0
CONDITIONS
VI = VREF ±350mV
VIC
R
= 1.25V, VI
(
PP
)
= 360mV pF
V
1.8V
1.9V
12
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN MAX
fclock Clock frequency 410 MHz
t
W
Pulse duration 1 ns
tACT Differential inputs active time 10 ns
tINACT Differential inputs inactive time 15 ns
tSData before CK↑, CK↓0.6
DCS0, DSC1 before CK↑,
C
K↓,
C
S
R
high 0.7
Hold time DCS, DODT, DCKE and Dn
after CK↑,
C
K↓0.6 ns
Hold time PAR_IN after CK↑, CK↓0.5 ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CK/
C
K signal input slew rate of 1V/ns.
SYMBOL
Notes:
tH
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
VDD = 1.8V ±0.1V UNITSPARAMETERS
nsSetup time
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol Parameter Measurement Conditions MIN MAX Units
fmax Max input clock frequency 410 MHz
tPDM
Propagation delay, single
bit switchin
g
CK↑ and CK↓ to Qn 1.25 1.9 ns
tLH
Low to High propagation
delay 1.2 3 ns
tHL
High to low propagation
delay 0.9 3 ns
tPDMSS
Propagation delay
simultaneous switchin
g
CK↑ and CK↓ to Qn 2 ns
tPHL
High to low propagation
delay RESET ↓ to Qn↓3ns
tPLH
Low to High propagation
delay RESET↓ to PTYERR↑3ns
1. Guaranteed by desi
g
n, not 100% tested in production.
CK↑ and CK↓ to PTYERR
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1222F—3/13/07
ICSSSTUB32872A
Advance Information
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM.
R
L
= 1000Ω
C
L
= 30 pF
(see Note 1)
LOAD CIRCUIT
t
w
V
ICR
V
ICR
Inpu t
V
IH
V
IL
VOLTAGE WAVEFORMS – PULSE DURATION
V
REF
V
REF
Inpu t
t
su
t
h
V
ID
V
ICR
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
V
ICR
V
ID
V
ICR
Output
V
OL
V
OH
V
TT
V
TT
t
PHL
t
PLH
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
t
RPHL
V
OL
V
OH
V
IL
V
IH
Output
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
V
DD
/2
V
TT
t
act
t
inact
LV CM OS
Input
RST
VOLTAGE AND CURRENT WAVEFORMS
I
DD
(see
Note 2)
90%
10%
INPUTS ACTIVE AND INACTIVE TIMES
0 V
V
DD
Tes t Po in t
V
DD
/2 V
DD
/2
VCMOS
Inp ut
RST
TL=350ps, 50Ω
DUT
CK Out
TL=50Ω
CK Inputs
V
ID
CK
CK
CK
CK
R
L
= 100Ω
CK
Tes t Po in t
Tes t Po in t
R
L
= 1000Ω
VDD
Figure 6 Parameter Measurement Information (V = 1.8V 0.1V)
—
DD
±
14
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO =
50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Tes t Po in t
DUT
Out
dt_f VOL
VOH
VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT
80%
Output
20%
dv_f
RL = 50Ω
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT
Tes t Po in t
DUT
Out
dt_r
VOL
VOH
VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT
80%
Output
20%
dv _r
RL = 50Ω
VDD
Figure 7 Output Slew-Rate Measurement Information (V = 1.8V 0.1V)
DD ±
—
15
1222F—3/13/07
ICSSSTUB32872A
Advance Information
3 Test circuits and switching waveforms (cont’d)
3.3 Error output load circuit and voltage measurement information (V
DD
=1.8V±0.1V)
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z
o
= 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Figure 28 — Load circuit, error output measurements
—
—
—
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Test Point
DUT
Out
RL = 1K
VDD
LVCMOS
RST
Input
PLH
t
Output
Waveform 2
CC
V/2
0.15 V
CC
V
0 V
OH
V
0 V
Figure 29
Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
Timing
Inputs
Output
Waveform 1
PHL
t
ICR
V
CC
V
/2
ICR
V
VI(PP)
CC
V
OL
V
Timing
Inputs
Output
Waveform 2
PHL
t
ICR
VICR
V
VI(PP)
OH
V
V
0
0.15 V
Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
Figure 30
Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
Figure 31
_ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _
Ω
Ω
16
1222F—3/13/07
ICSSSTUB32872A
Advance Information
3 Test circuits and switching waveforms (cont’d)
3.4 Partial-parity-out load circuit and voltage measurement information (V
DD
=1.8V±0.1V)
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z
o
= 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Figure 32 — Partial-parity-out load circuit,
VTT = VDD/2
tPLH and tPHL are the same as tPD.
VI(PP) = 600 mV
Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
VTT = VDD/2
tPLH and tPHL are the same as tPD.
VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = VREF - 250 mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs.
Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
VOH
VOL
OUTPUT
tPLH
002aaa375
VTT
VICR VICR
tPHL
CK
CK
Vi(p-p)
tPHL
002aaa376
LVCMOS RST
INPUT
OUTPUT VTT
VDD/2
VIH
VIL
VOH
VOL
DUT
Out
Test Point
RL=
CL=
5 pF
(see Note A)
1 k
Ω
Ω
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1222F—3/13/07
ICSSSTUB32872A
Advance Information
Ordering Information
ICSSSTUB32872Az(LF)T
- e - TYP
b
REF
b
REF
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
not used)
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
not used)
Numeric Designations
for Horizontal Grid
Numeric Designations
for Horizontal Grid
h
TYP
h
TYP
c
REF
c
REF
A
B
C
D
TOP VIEW
A1
3 2 1
4
Seating
Plane
Seating
Plane
C
T
0.12 C
d TYP
E
D
D1D1D1D1D1
- e -- e -
- e -
E1
TYP
TYP
Example:
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
H = LFBGA (reduced size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y z (LF) T
D E T e HORIZ VERT TOTAL d h b c
Min/Max Min/Max Min/Max
13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 0.25/0.41 0.75 0.75
11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 0.25/0.35 0.875 0.875
MO-205
10-0055C
* Source Ref.: JEDEC Publication 95,
ALL DIMENSIONS IN MILLIMETERS
REF. DIMENSIONS ----- BALL GRID ----- Max.
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
18
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Revision History
Rev. Issue Date Description Page #
A 5/2/2006 Initial Release. -
B 12/12/2006 Electrical table, Ci Data input max changed from 3.5 to 5.0, CLK max
chan
g
ed from 3 to 3.8 11
C 12/20/2006 Timing table, ts Data before CK changed from 0.5 to 0.7, th DCS after CK
chan
g
ed from 0.5 to 0.6 12
D 12/21/2006
Applications, removed "800"; Electrical table, Idd Operating max changed
from 80 to 150, Ci RESET typ changed from 2.5 to 4.5; Timing table, th Hold
Time, changed Q to Dn, Switching table, changed tpdm max from 1.7 to 1.9,
thl min from 1 to 0.9, and tpdmss max from 1.9 to 2.
1, 11, 12
E 3/6/2007 Timing table, ts Data before CK changed from 0.7 to 0.6; Switching table,
fixed t
yp
os. 12
F 3/13/2007
Page 1, Recc. List, changed 3rd bullet to "Provides complete DDR DIMM
solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A"; page 11,
fixed t
yp
os.
1, 11
