ADNS-6010
Laser Mouse Sensor
Data Sheet
Description
The Avago Technologies ADNS-6010 sensor along with
the ADNS-6120 or ADNS-6130-001 lens, ADNS-6230-
001 clip and ADNV-6340 laser diode form a complete
and compact laser mouse tracking system. It is the
world’s first laser-illuminated systems enabled for high
performance navigation. Driven by Avago Technologies
LaserStream, it can operate on many surface that prove
difficult or traditional LED-based optical navigation. It’s
high-performance architecture is capable of sensing
high-speed mouse motion -with resolution up to 2000
counts per inch, velocities up to 45 inches per second
(ips) and accelerations up to 20g. This sensor is powered
for the extremely high sensitive user
There are no moving parts, in the complete assembly for
ADNS-6010 laser mouse system, thus it is high reliability
and less maintenance for the end user. In addition, preci-
sion optical alignment is not required, facilitating high
volume assembly.
Theory of Operation
The ADNS-6010 is based on LaserStream Technology,
which measures changes in position by optically acquir-
ing sequential images (frames) and mathematically de-
termining the direction and magnitude of movement.
ADNS-6010 contains an Image Acquisition System (IAS),
a Digital Signal Processor (DSP), and a four wire serial
port. The IAS acquires microscopic surface images via
the lens and illumination system. These images are
processed by the DSP to determine the direction and
distance of motion. The DSP calculates the 'x and 'y
relative displacement values. An external microcontroller
reads the 'x and 'y information from the sensor serial
port. The microcontroller then translates the data into
PS2 or USB signals before sending them to the host PC
or game console.
Features
x High speed motion detection – up to 45 ips and 20g
x New LaserStream architecture for greatly improved
optical navigation technology
x Programmable frame rate over 7080 frames per
second
x SmartSpeed self-adjusting frame rate for optimum
performance
x Serial port burst mode for fast data transfer
x 400, 800, 1600 or 2000 cpi selectable resolution
x Single 3.3 volt power supply
x Four-wire serial port along with Power Down, and
Reset pins
x Laser fault detect circuitry on-chip for Eye Safety
Compliance
Applications
x Mice for game consoles and computer games
x Mice for desktop PC’s, Workstations, and portable
PC’s
x Laser Trackballs
x Integrated input devices
2
1
3
4
2
5
6
7
8
9
10
GND
LASER_NEN
NCS
MISO
SCLK
VDD3
NC
RBIN
GND
REFC
GUARD
REFB
NC
RESET
NPD
OSC_OUT
MOSI
OSC_IN
VDD3
20
18
17
19
16
15
14
13
12
11
TOP VIEW
PINOUT
A6010
XYYWWZ
XY_LASER
Pin Name Description
1 NCS Chip select
(active low input)
2 MISO Serial data output
(Master In/Slave Out)
3 SCLK Serial clock input
4 MOSI Serial data input
(Master Out/Slave In)
5 NC No Connection
6 RESET Reset input
7 NPD Power down (active low input)
8 OSC_OUT Oscillator output
9 GUARD Oscillator GND for PCB guard
(optional)
10 OSC_IN Oscillator input
11 REFC Reference capacitor
12 REFB Reference capacitor
13 RBIN Set XY_LASER current
14 XY_LASER LASER current output
15 NC No Connection
16 VDD3 Supply voltage
17 GND Ground
18 VDD3 Supply voltage
19 GND Ground
20 LASER_NEN Laser enable (active low)
Pinout
Figure 1. Package outline drawing (top view)
3
Figure 2. Package outline drawing
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD
A6010
4
Overview of Laser Mouse Sensor Assembly
Figure 3. Assembly drawing of ADNS-6010 (top, front and cross-sectional view)
5
2D Assembly Drawing of ADNS-6010, PCBs and Base Plate
Figure 4. Exploded view drawing
ADNS-6010 (sensor)
Customer Supplied PCB
ADNS-6120 (lens)*
Customer Supplied Base Plate
With Recommended Features
Per IGES Drawing
Customer Supplied VCSEL PCB
ADNV-6340 (VCSEL)
ADNS-6230-001 (clip)
Shown with ADNS-6120 or ADNS-6130-001 Laser Mouse
Lens, ADNS-6230-001 VCSEL Assembly Clip and ADNV-
6340 VCSEL. The components interlock as they are
mounted onto defined features on the base plate.
The ADNS-6010 laser mouse sensor is designed for
mounting on a through hole PCB, looking down. There
is an aperture stop and features on the package that
align to the lens.
The ADNV-6340 VCSEL provides a laser diode with a
single longitudinal and a single transverse mode. It is
particularly suited as lower power consumption and
highly coherent replacement of LEDs. It also provides
wider operation range while still remaining within single-
mode, reliable operating conditions.
The ADNS-6120 or ADNS-6130-001 Laser Mouse Lens is
designed for use with ADNS-6010 sensor and the illumi-
nation subsystem provided by the VCSEL assembly clip
and the VCSEL. Together with the VCSEL, the ADNS-6120
or ADNS-6130-001 lens provides the directed illumina-
tion and optical imaging necessary for proper operation
of the Laser Mouse Sensor. ADNS-6120 or ADNS-6130-
001 is a precision molded optical component and should
be handled with care to avoid scratching of the optical
surfaces. ADNS-6120 has a large round flange to provide
a long creepage path for any ESD events that occur at the
opening of the base plate.
The ADNS-6230-001 VCSEL Assembly Clip is designed to
provide mechanical coupling of the ADNV-6340 VCSEL
to the ADNS-6120 or ADNS-6130-001 lens. This coupling
is essential to achieve the proper illumination alignment
required for the sensor to operate on a wide variety of
surfaces.
Avago Technologies provides an IGES file drawing de-
scribing the base plate molding features for lens and
PCB alignment.
*or ADNS-6130-001 for trim lens
6
Figure 5. Recommended PCB mechanical cutouts and spacing
Assembly Recommendation
1. Insert the sensor and all other electrical components
into the application PCB (main PCB board and VCSEL
PCB board).
2. Wave solder the entire assembly in a no-wash solder
process utilizing a solder fixture. The solder fixture
is needed to protect the sensor during the solder
process. It also sets the correct sensor-to -PCB
distance, as the lead shoulders do not normally rest
on the PCB surface. The fixture should be designed
to expose the sensor leads to solder while shielding
the optical aperture from direct solder contact.
3. Place the lens onto the base plate.
4. Remove the protective kapton tape from the optical
aperture of the sensor. Care must be taken to keep
contaminants from entering the aperture.
5. Insert the PCB assembly over the lens onto the base
plate. The sensor aperture ring should self-align to
the lens. The optical position reference for the PCB
is set by the base plate and lens. Note that the PCB
motion due to button presses must be minimized to
maintain optical alignment.
6. Remove the protective kapton tape from the VCSEL.
7. Insert the VCSEL assembly into the lens.
8. Slide the clip in place until it latches. This locks the
VCSEL and lens together.
9. Tune the laser output power from the VCSEL to meet
the Eye Safe Class I Standard as detailed in the LASER
Power Adjustment Procedure.
10. Install the mouse top case. There must be a feature
in the top case (or other area) to press down onto the
sensor to ensure the sensor and lens are interlocked
to the correct vertical height.
7
Design considerations for improving ESD Performance
For improved electrostatic discharge performance,
typical creepage and clearance distance are shown in
the table below. Assumption: base plate construction as
per the Avago Technologies supplied IGES file and ADNS-
6130-001 trim lens (or ADNS-6120 round lens).
Figure 6. Cross section of PCB assembly
LENS
BASE PLATE
SENSOR
VCSEL PCB
VCSEL
PCB
CLIP
Figure 7. Schematic Diagram for 3-Button Scroll Wheel USB PS/2 Mouse
Typical Distance Millimeters
Creepage 12.0
Clearance 2.1
The lens flange can be sealed (i.e. glued) to the base
plate. Note that the lens material is polycarbonate and
therefore, cyanoacrylate based adhesives or other adhe-
sives that may damage the lens should NOT be used.
USB Microcontroller
14
5
Vcc
9
GND
16
15
Vreg
11
19
17
GND
12
13 XTALOUT
20
*Outputs configured
as open drain if NOT
using level shif ter
D1
VCSEL
P0.5*
P0.4*
P0.7*
P0.6
P1.4
P0 . 2
P0 . 0
P0 . 3
P1.5
VPP
R4 20 K
Vcc
P1.0
P1.1
P1.2
P1.3
P1.6
P1.7
P0.1
R3 20 K
ADNS-6010
Vcc
QA
QB
Rbin
Selected to
match laser
RBIN
24 MOSI
23
SCLK
21
MISO
22
R2
20K
NCS
3RESET
NPD
4
R1
20K
R9
10 K
R10
10 K
24 MHz
OSC_OUT
OSC_IN
GUARD
X1
REFC
REFB
C9
0.1
C8
2.2
LASER _NEN
XY _LASER
Q2
2N3906
C2
0. 1
C3
0.1
GND
GND
VDD3
VDD3
Vout Vin
Gnd
+3.3V
C7
4.7
C4
0.1
C6
4.7
1
2
3
Vcc
LP2950ACZ-3.3
3.3V Regulator
Vcc
3
SW4
ALPS
EC10E
Scroll wheel encoder
__
CS
SCLK
SI
S0
VCC
___
WP
____
HLD
GND
1
6
5
2
8
3
7
4
R7 100K
C5
0.1
N/ C
N/ C
D-/SDAT
D+/ SCLK
XTALIN/P2.1
6
8
1
2
3
4
Vcc
VBUS
D+
D-
USB Port
R5
1.30K
C1
0.1
Buttons SW2
SW1
SW3
middle
right
left
25LC160A 16KBit EEPROM (optional)
7
18
1
2
10
1
2
R6
2.7K
C10
470pF
Murata
CSALS24MOX53-B0
Optional
Ground
Plane
6
9
13
7
15
4
1
5
19
12
11
20
3
2
10
14
8
17
16 18
3
7
C2
0. 1
1
2
2
5
6
3
9
8
74VHC125 Level Shifter
14
41
10
Hi-Z Configuration
C10 to be as close as
possible to VCSEL
8
Notes (for Figure 7)
x Caps for pins 11, 12, 16 and 18 MUST have trace lengths LESS than
5 mm on each side.
x Pins 16 and 18 caps MUST use pin 17 GND.
x Pin 9, if used, should not be connected to PCB GND to reduce po-
tential RF emissions.
x The 0.1 uF caps must be ceramic.
x Caps should have less than 5 nH of self inductance.
x Caps should have less than 0.2 W ESR.
x NC pins should not be connected to any traces.
x Surface mount parts are recommended.
x Care must be taken when interfacing a 5V microcontroller to
the ADNS-6010. Serial port inputs on the sensor should be con-
nected to open-drain outputs from the microcontroller or use an
active drive level shifter. NPD and RESET should be connected
to 5V microcontroller outputs through a resistor divider or other
level shifting technique.
x VDD3 and GND should have low impedance connections to the
power supply.
x Because the RBIN pin sets the XY_LASER current, the following PC
board layout practices should be followed to reduce the chance
of uncontrolled laser drive current caused from a leakage path
between RBIN and ground. One hypothetical source of such a
leakage path is PC board contamination due to a liquid, such as a
soft drink, being deposited on the printed circuit board.
o The RBIN resistor should be located close to the sensor pin
13. The traces between the resistor and the sensor should be
short.
o The pin 13 solder pad and all exposed conductors connected
to pin 13 should be surrounded by a guard trace connected to
VDD3 and devoid of a solder mask.
o The pin 13 solder pad, the traces connected to pin 13, and the
RBIN resistor should be covered with a conformal coating.
o The RBIN resistor should be a thru-hole style to increase the
distance between its terminals. This does not apply if a confor-
mal coating is used.
External PROM
The ADNS-6010 must operate from externally loaded
programming. This architecture enables immediate
adoption of new features and improved performance
algorithms. The external program is supplied by Avago
Technologies as a file, which may be burned into a pro-
grammable device. The example application shown in
this document uses an EEPROM to store and load the
external program memory. A micro-controller with suf-
ficient memory may be used instead. On power-up and
reset, the ADNS-6010 program is downloaded into vola-
tile memory using the burst-mode procedure described
in the Synchronous Serial Port section. The program size
is 1986 x 8 bits.
Figure 8. Block diagram of ADNS-6010 optical mouse sensor
IMAGE
PROCESSOR
REFERENCE
VOLTAGE
FILTER NODE
3.3 V POWER
REFB
REFC
GND
RESONATOR
OSC_IN
OSC_OUT
MOSI
NCS
SCLK
VDD3
MISO
RESET
NPD
VOLTAGE REGULATOR
AND POWER CONTROL
Serial Port
CTRL
OSCILLATOR
LASER DRIVER
LASER_NEN
XY_LASER
RBIN
9
LASER Drive Mode
The LASER has 2 modes of operation: DC and Shutter. In
DC mode, the LASER is on at all times the chip is powered
except when in the power down mode via the NPD pin.
In shutter mode the LASER is on only during the portion
of the frame that light is required. The LASER mode is set
by the LASER_MODE bit in the Configuration_bits regis-
ter. For optimum product lifetime, Avago Technologies
recommends the default Shutter mode setting (except
for calibration and test).
Laser Bin Table
Bin Number
Rbin Resistor
Value (kohm)
Match_Bit
(Reg 0x2C, Bit7)
2A 18.7 0
3A 12.7 0
Eye Safety
The ADNS-6010 and the associated components in the
schematic of Figure 7 are intended to comply with Class
1 Eye Safety Requirements of IEC 60825-1. Avago Tech-
nologies suggests that manufacturers perform testing to
verify eye safety on each mouse. It is also recommended
to review possible single fault mechanisms beyond those
described below in the section “Single Fault Detection”.
Under normal conditions, the ADNS-6010 generates the
drive current for the laser diode (ADNV-6340). In order to
stay below the Class 1 power requirements, resistor Rbin
must be set at least as high as the value in the bin table
of Figure 7, based on the bin number of the laser diode
and LP_CFG0 and LP_CFG1 must be programmed to ap-
propriate values. Avago Technologies recommends using
the exact Rbin value specified in the bin table to ensure
sufficient laser power for navigation. The system com-
prised of the ADNS-6010 and ADNV-6340 is designed to
maintain the output beam power within Class 1 require-
ments over component manufacturing tolerances and
the recommended temperature range when adjusted per
the procedure below and when implemented as shown
in the recommended application circuit of Figure 7. For
more information, please refer to Avago Technologies La-
ser Mouse Eye Safety Calculation Application Note 5088.
Parameter Symbol Minimum Maximum Units Notes
Laser output power LOP 716 uW Per conditions above
LASER Power Adjustment Procedure
1. The ambient temperature should be 25C +/- 5C.
2. Set VDD3 to its permanent value.
3. Ensure that the laser drive is at 100% duty cycle.
4. Program the LP_CFG0 and LP_CFG1 registers to
achieve an output power as close to 506uW as
possible without exceeding it.
Good engineering practices should be used to guarantee
performance, reliability and safety for the product design.
Avago Technologies has additional information and de-
tail, such as firmware practices, PCB layout suggestions,
and manufacturing procedures and specifications that
could be provided.
LASER Output Power
The laser beam output power as measured at the navi-
gation surface plane is specified below. The following
conditions apply:
1. The system is adjusted according to the above
procedure.
2. The system is operated within the recommended
operating temperature range.
3. The VDD3 value is no greater than 50mV above its
value at the time of adjustment.
4. No allowance for optical power meter accuracy is
assumed.
Disabling the LASER
LASER_NEN is connected to the base of a PNP transistor
which when ON connects VDD3 to the LASER. In normal
operation, LASER_NEN is low. In the case of a fault con-
dition (ground at XY_LASER or RBIN), LASER_NEN goes
high to turn the transistor off and disconnect VDD3 from
the LASER.
10
Figure 10. Distance from lens reference plane to surface
Single Fault Detection
ADNS-6010 is able to detect a short circuit, or fault,
condition at the RBIN and XY_LASER pins, which could
lead to excessive laser power output. A low resistance
path to ground on either of these pins will trigger the
fault detection circuit, which will turn off the laser drive
current source and set the LASER_NEN output high.
When used in combination with external components
as shown in the block diagram below, the system will
prevent excess laser power for a single short to ground
at RBIN or XY_LASER by shutting off the laser. Refer to the
PC board layout notes for recommendations to reduce
the chance of high resistance paths to ground existing
due to PC board contamination.
In addition to the continuous fault detection described
above, an additional test is executed automatically
whenever the LP_CFG0 register is written to. This test
Figure 9. Single Fault Detection and Eye-safety Feature Block Diagram
will check for a short to ground on the XY_LASER pin,
a short to VDD3 on the XY_LASER pin, and will test the
fault detection circuit on the XY_LASER pin.
Regulatory Requirements
x Passes FCC B and worldwide analogous emission limits
when assembled into a mouse with shielded cable and
following Avago Technologies recommendations.
x Passes IEC-1000-4-3 radiated susceptibility level when
assembled into a mouse with shielded cable and
following Avago Technologies recommendations.
x Passes EN61000-4-4/IEC801-4 EFT tests when
assembled into a mouse with shielded cable and
following Avago Technologies recommendations.
x UL flammability level UL94 V-0.
Sensor
Sensor
PCB
Lens Surface
VCSEL PCB
VCSEL
VCSEL Clip
2.40
0.094
RBIN
LASER_NEN
XY_LASER
GND
ADNS-6010
LASER
DRIVER
VDD3
LASER
Microcontroller
RESET
NPD
voltage sense
current set
VDD3
fault control
block
11
Recommended Operating Conditions
Absolute Maximum Ratings
Parameter Symbol Minimum Maximum Units Notes
Storage Temperature TS-40 85 qC
Operating Temperature TA-15 55 qC
Lead Solder Temp 260 qC For 10 seconds, 1.6mm below seating
plane.
Supply Voltage VDD3 -0.5 3.7 V
ESD 2 kV All pins, human body model MIL 883
Method 3015
Input Voltage VIN -0.5 VDD3+0.5 V NPD, NCS, MOSI, SCLK, RESET, OSC_IN,
OSC_OUT, REFC, RBIN
Output current IOUT 7 mA MISO, LASER_NEN
Input Current IIN 15 mA XY_LASER current with RBIN 12.7KΩ
LP-CFG0 = 0x00; LP_CFG1 = 0xFF
Parameter Symbol Minimum Typical Maximum Units Notes
Operating Temperature TA040qC
Power supply voltage VDD3 3.10 3.30 3.60 Volts
Power supply rise time VRT 1 us 0 to 3.0V
Supply noise(Sinusoidal) VNB 30
80
mV
p-p
10kHz- 300KHZ
300KHz-50MHz
Oscillator Frequency fCLK 23 24 25 MHz Set by ceramic resonator
Serial Port Clock Frequency fSCLK 2
500
MHz
kHz
Active drive, 50% duty cycle
Open drain drive with pull-ups
on, 50 pF load
Resonator Impedance XRES 55 :
Distance from lens refer-
ence plane to surface
Z 2.18 2.40 2.62 mm Results in +/- 0.2 mm mini-
mum DOF, see Figure 10
Speed S 45 in/sec
Acceleration A 20 g
Frame Rate FR 2000 7080 Frames/s See Frame_Period register
section
Resistor value for LASER
Drive Current set
Rbin See Laser Bin Table kOhms ADNV-6340 VCSEL
Voltage at XY_LASER Vxy_laser 0.7 VDD3 V
12
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz.
Parameter Symbol Min. Typ. Max. Units Notes
VDD to RESET tOP 250 PsFrom VDD = 3.0V to RESET sampled
Data delay after
RESET
tPU-RESET 180 ms From RESET falling edge to valid motion data at 2000 fps
and shutter bound 20k.
Input delay after
reset
TIN-RST 550 PsFrom RESET falling edge to inputs active (NPD, MOSI,
NCS, SCLK)
Power Down tPD 600 PsFrom NPD falling edge to initiate the power down cycle
at 2000 fps (tpd = 1 frame period + 100Ps )
Wake from NPD tPUPD tCOMPUTE 75 ms From NPD rising edge to valid motion data at 2000 fps
and shutter bound 20k. Max assumes surface change
while NPD is low
Data delay after
NPD
tCOMPUTE 3.1 ms From NPD rising edge to all registers contain data from
new images at 2000 fps (See Figure 11).
RESET pulse width tPW-RESET 10 Ps
MISO rise time tr-MISO 40 200 ns CL = 50pF
MISO fall time tf-MISO 40 200 ns CL = 50pF
MISO delay after
SCLK
tDLY-MISO 120 ns From SCLK falling edge to MISO data valid, no load
conditions
MISO hold time thold-MISO 250 ns Data held until next falling SCLK edge
MOSI hold time thold-MOSI 200 ns Amount of time data is valid after SCLK rising edge
MOSI setup time tsetup-MOSI 120 ns From data valid to SCLK rising edge
SPI time between
write commands
tSWW 50 PsFrom rising SCLK for last bit of the first data byte, to ris-
ing SCLK for last bit of the second data byte.
SPI time between
write and read
commands
tSWR 50 PsFrom rising SCLK for last bit of the first data byte, to ris-
ing SCLK for last bit of the second address byte.
SPI time between
read and subse-
quent commands
tSRWtSRR 250 ns From rising SCLK for last bit of the first data byte, to fall-
ing SCLK for first bit of the second address byte.
SPI read address-
data delay
tSRAD 50 PsFrom rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read. All registers
except Motion & Motion_Burst
SPI motion read
address-data
delay
tSRAD-MOT 75 PsFrom rising SCLK for last bit of the address byte, to fall-
ing SCLK for first bit of data being read. Applies to 0x02
Motion, and 0x50 Motion_Burst, registers
NCS to SCLK active tNCS-SCLK 120 ns From NCS falling edge to first SCLK rising edge
SCLK to NCS inac-
tive
tSCLK-NCS 120 ns From last SCLK falling edge to NCS rising edge, for valid
MISO data transfer
NCS to MISO
high-Z
tNCS-MISO 250 ns From NCS rising edge to MISO high-Z state
PROM download
and frame capture
byte-to-byte delay
tLOAD 10 Ps(See Figure 24 and 25)
NCS to burst
mode exit
tBEXIT 4PsTime NCS must be held high to exit burst mode
Transient Supply
Current
IDDT 68 mA Max supply current during a VDD3 ramp from 0 to 3.6 V
Input Capacitance C IN 14-22 pF OSC_IN, OSC_OUT
13
Figure 11. NPD Rising Edge Timing Detail
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3 V.
Parameter Symbol Minimum Typical Maximum Units Notes
DC Supply Current IDD_AVG 53 mA DC average at 7080 fps.
No DC load on XY_LASER, MISO.
Power Down Supply
Current
IDDPD 590 PANPD=GND; SCLK, MOSI, NCS=GND
or VDD3; RESET=0V or GND
Input Low Voltage VIL 0.8 V SCLK, MOSI, NPD, NCS, RESET
Input High Voltage VIH 0.7 * VDD3 V SCLK, MOSI, NPD, NCS, RESET
Input hysteresis VI_HYS 200 mV SCLK, MOSI, NPD, NCS, RESET
Input current,
pull-up disabled
IIH_DPU 0 ±10 PAVin=0.8*VDD3, SCLK, MOSI, NCS
Input current,
CMOS inputs
IIH 0 ±10 PANPD, RESET, Vin=0.8*VDD3
Output current,
pulled-up inputs
IOH_PU 150 300 600 PAVin=0.2V, SCLK, MOSI, NCS;
See bit 2 in Extended_Config register
XY_LASER Current ILAS 146/Rbin AV
xy_laser >= 0.7 VLP_CFG0 = 0x00,
LP_CFG1 = 0xFF
XY_LASER Current
(fault mode)
ILAS 500 uA Rbin < 50 Ohms, or VXY_LASER <0.2V
Output Low Voltage,
MISO, LASER_NEN
VOL 0.5 V Iout=2mA, MISOIout= 1mA,
LASER_NEN
Output High Voltage,
MISO, LASER_NEN
VOH 0.8*VDD3 V Iout=-2mA, MISOIout= -0.5 mA,
LASER_NEN
XY_LASER Current
(no Rbin)
ILAS_NRB 1 mA Rbin = open
LASER
CURRENT
(shutter mode)
Oscillator Start
NPD
250 us
Reset
Count
340 us
SCLK
Optional SPI transactions
with old image data
590 us
COMPUTE = 590us + 5 Frame Periods
“Motion” bit set if
motion was detected.
First read dX = dY = 0
Frame
2
Frame
3
Frame
4
Frame
5
Frame
1
t
14
Figure 14. Average Supply Current vs. Frame Rate
Average Supply Current vs. Frame Rate
VDD = 3.6 V
60%
50%
79%
94%
100%
30.0%
40.0%
50.0%
60.0%
70.0%
80.0%
90.0%
100.0%
2000 3000 4000 5000 6000 7000 8000
Frame Rate (Hz)
Relative Current
Relationship of mouse count to distance = m (mouse count) / n (cpi)
eg: Deviation of 7 mouse count = 7/800 = 0.00875 inch ~ 0.009 inch; where m = 7, n = 800
Figure 13. Average Error vs. Distance at 2000cpi (mm)
Typical Performance Characteristics
Typical Resolution vs. Z
0
400
800
1200
1600
2000
2400
1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3
Distance from Lens Refremce Plane to Surface, Z (mm)
Resolution (counts/inch)
Z
DOF
DOF
Recommended
Operating Region
Black Formica
White Melamine
Bookshelf
Manila
Photo Paper
Figure 12. Mean Resolution vs. Z at 2000cpi
Typical Path Deviation
Largest Single Perpendicular Deviation From A Straight Line At 45 Degrees
Path Length = 4 inches; Speed = 6 ips ; Resolution = 2000 cpi
0
5
10
15
20
25
30
35
40
45
50
1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3
Distance From Lens Reference Plane To Navigation Surface (mm)
Maximun Distance (mouse count)
Black Formica
White Melamine
Bookshelf
Manila
Photo Paper
15
Synchronous Serial Port
The synchronous serial port is used to set and read pa-
rameters in the ADNS-6010, and to read out the motion
information. The serial port is also used to load PROM
data into the ADNS-6010.
The port is a four wire port. The host micro-controller al-
ways initiates communication; the ADNS-6010 never ini-
tiates data transfers. The serial port cannot be activated
while the chip is in power down mode (NPD low) or reset
(RESET high). SCLK, MOSI, and NCS may be driven directly
by a 3.3V output from a micro-controller, or they may be
driven by an open drain configuration by enabling on-
chip pull-up current sources. The open drain drive allows
the use of a 5V micro-controller without any level shifting
components. The port pins may be shared with other SPI
slave devices. When the NCS pin is high, the inputs are
ignored and the output is tri-stated.
The lines that comprise the SPI port are:
SCLK: Clock input. It is always generated by the master
(the micro-controller.)
MOSI: Input data. (Master Out/Slave In)
MISO: Output data. (Master In/Slave Out)
NCS: Chip select input (active low). NCS needs to be
low to activate the serial port; otherwise, MISO
will be high Z, and MOSI & SCLK will be ignored.
NCS can also be used to reset the serial port in
case of an error.
Figure 15. Relative Responsivity
Relative Responsivity for ADNS-6010
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
400 500 600 700 800 900 1000
Wavelength (nm)
Relative responsivity
Chip Select Operation
The serial port is activated after NCS goes low. If NCS
is raised during a transaction, the entire transaction is
aborted and the serial port will be reset. This is true
for all transactions including PROM download. After a
transaction is aborted, the normal address-to-data or
transaction-to-transaction delay is still required before
beginning the next transaction. To improve communica-
tion reliability, all serial transactions should be framed by
NCS. In other words, the port should not remain enabled
during periods of non-use because ESD and EFT/B events
could be interpreted as serial communication and put
the chip into an unknown state. In addition, NCS must
be raised after each burst-mode transaction is complete
to terminate burst-mode. The port is not available for
further use until burst-mode is terminated.
16
Figure 17. Write Operation
Figure 16. MOSI Setup and Hold Time
A
6 A
5 A
2
A
3
A
4 A
0
A
1 D
7 D
4
D
5
D
6 D
0
D
1
D
2
D
3
15
7 8 9 10 11 12 13 14 16
2 3 4 5 6
1
SCLK
MOSI
MOSI Driven by Micro
1
1
1
A
6
2
NCS
MISO
Write Operation
Write operation, defined as data going from the micro-
controller to the ADNS-6010, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address (seven bits) and has a “1” as its MSB
to indicate data direction. The second byte contains
the data. The ADNS-6010 reads MOSI on rising edges
of SCLK.
SCLK
MOSI
tsetup , MOSI
Hold,MOSI
t
Read Operation
A read operation, defined as data going from the ADNS-
6010 to the micro-controller, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address, is sent by the micro-controller over
MOSI, and has a “0” as its MSB to indicate data direction.
The second byte contains the data and is driven by the
ADNS-6010 over MISO. The sensor outputs MISO bits on
falling edges of SCLK and samples MOSI bits on every ris-
ing edge of SCLK.
NOTE: The 250 ns minimum high state of SCLK is also the
minimum MISO data hold time of the ADNS-6010. Since
the falling edge of SCLK is actually the start of the next
read or write command, the ADNS-6010 will hold the
state of data on MISO until the falling edge of SCLK.
Figure 18. Read Operation
1 2 3 4 5 6 7 8
SCLK
Cycle #
SCLK
MOSI 0 A
6 A
5 A
4 A
3 A
2 A
1 A
0
9 10 11 12 13 14 15 16
MISO D
6 D
5 D
4 D
3 D
2 D
1 D
0
D
7
NCS
tSRAD delay
17
Figure 20. Timing between two write commands
Figure 21. Timing between write and read commands
Figure 19. MISO Delay and Hold Time
SCLK
MISO D0
t
tDLY-MISO
HOLD-MISO
Figure 22. Timing between read and either write or subsequent read commands
SCLK
Address Data
≥ tSWW
50 μs
Write Operation
Address Data
Write Operation
Address Data
Write Operation
Address
Next Read
Operation
≥t
SWR
50 μs
SCLK
Next Read or
Write Operation
Data
SRAD
50 μs for non-motion read
SRAD MOT
75 μs for register 0x02
Read Operation
Address
t
SRW
& t
SRR
>250 ns
Address
SCLK
≥ t
t
The falling edge of SCLK for the first address bit of either
the read or write command must be at least 250 ns after
the last SCLK rising edge of the last data bit of the previ-
ous read operation. In addition, during a read operation
SCLK should be delayed after the last address data bit
to ensure that the ADNS-6010 has time to prepare the
requested data.
Burst Mode Operation
Burst mode is a special serial port operation mode which
may be used to reduce the serial transaction time for
three predefined operations: motion read and PROM
download and frame capture. The speed improvement is
achieved by continuous data clocking to or from multiple
registers without the need to specify the register address,
and by not requiring the normal delay period between
data bytes.
Required timing between Read and Write Commands
(tsxx)
There are minimum timing requirements between read
and write commands on the serial port.
If the rising edge of the SCLK for the last data bit of the
second write command occurs before the 50 microsec-
ond required delay, then the first write command may
not complete correctly.
If the rising edge of SCLK for the last address bit of
the read command occurs before the 50 microsecond
required delay, the write command may not complete
correctly.
18
4. Write 0x18 to register 0x14 (SROM_Enable register)
5. Begin burst mode write of data file to register 0x60
(SROM_Load register)
After the first data byte is complete, the PROM or micro-
controller must write subsequent bytes by presenting
the data on the MOSI line and driving SCLK at the normal
rate. A delay of at least tLOAD must exist between data
bytes as shown. After the download is complete, the
micro-controller must raise the NCS line for at least tBEXIT
to terminate burst mode. The serial port is not available
for use until it is reset with NCS, even for a second burst
transmission.
Avago Technologies recommends reading the SROM_ID
register to verify that the download was successful. In
addition, a self-test may be executed, which performs a
CRC on the SROM contents and reports the results in a
register. The test is initiated by writing a particular value
to the SROM_Enable register; the result is placed in the
Data_Out register. See those register descriptions for
more details.
Avago Technologies provides the data file for download;
the file size is 1986 data bytes. The chip will ignore any
additional bytes written to the SROM_Load register after
the SROM file.
Figure 23. Motion burst timing.
Figure 24. PROM Download Burst Mode
Motion_Burst Register Address Read First Byte
First Read Operation Read Second Byte
≥ t
SRAD-MOT
Read Third Byte
75 μs
SCLK
NCS
address ke
y
data address b
y
te 0
MOSI
SCLK
t
NCS-SCLK
SROM_Enable reg write SROM_Load reg write
exit burst mode
enter burst
mode
≥
4
μ
s
t
LOAD
t
LOAD
b
y
te 1 b
y
te 1985
t
BEXIT
>120ns
address
soonest to read SROM_ID
SROM_Enable reg write
≥
1 frame
period
≥ 10
μ
s
≥ 10
μ
s
≥ 10
μ
s
≥ 100
μ
s
≥ 40
μ
s
Motion Read
Reading the Motion_Burst register activates this mode.
The ADNS-6010 will respond with the contents of the
Motion, Delta_X, Delta_Y, SQUAL, Shutter_Upper, Shut-
ter_Lower, and Maximum_Pixel registers in that order.
After sending the register address, the micro-control-
ler must wait tSRAD-MOT and then begin reading data.
All 64 data bits can be read with no delay between
bytes by driving SCLK at the normal rate. The data are
latched into the output buffer after the last address bit
is received. After the burst transmission is complete, the
micro-controller must raise the NCS line for at least tBEXIT
to terminate burst mode. The serial port is not available
for use until it is reset with NCS, even for a second burst
transmission.
PROM Download
This function is used to load the Avago Technologies-
supplied firmware file contents into the ADNS-6010. The
firmware file is an ASCII text file with each 2-character
byte on a single line.
The following steps activate this mode:
1. Perform hardware reset by toggling the RESET pin
2. Write 0x1D to register 0x14 (SROM_Enable register)
3. Wait at least 1 frame period
19
Frame Capture
This is a fast way to download a full array of pixel values
from a single frame. This mode disables navigation and
overwrites any downloaded firmware. A hardware reset
is required to restore navigation, and the firmware must
be reloaded.
To trigger the capture, write to the Frame_Capture reg-
ister. The next available complete 1 2/3 frames (1536
values) will be stored to memory. The data are retrieved
by reading the Pixel_Burst register once using the nor-
mal read method, after which the remaining bytes are
clocked out by driving SCLK at the normal rate. The byte
time must be at least tLOAD. If the Pixel_Burst register is
read before the data is ready, it will return all zeros.
To read a single frame, read a total of 900 bytes. The next
636 bytes will be approximately 2/3 of the next frame.
The first pixel of the first frame (1st read) has bit 6 set to
1 as a start-of-frame marker. The first pixel of the second
partial frame (901st read) will also have bit 6 set to 1. All
other bytes have bit 6 set to zero. The MSB of all bytes is
set to 1. If the Pixel_Burst register is read past the end of
the data (1537 reads and on) , the data returned will be
zeros. Pixel data is in the lower six bits of each byte.
After the download is complete, the micro-controller
must raise the NCS line for at least tBEXIT to terminate
burst mode. The read may be aborted at any time by
raising NCS.
Alternatively, the frame data can also be read one byte at
a time from the Frame_Capture register. See the register
description for more information.
frame capture reg
NCS
address data address address
MOSI
SCLK
P0 P1 P899
MISO
t
NCS-SCLK
>120ns
frame capture reg write pixel dump reg read
exit burst mode
enter burst
mode
t
CAPTURE
t
LOAD
soonest to begin again
P0 bit 6 set to 1 all MSB = 1 see note 2
Notes:
1. MSB = 1 for all bytes. Bit 6 = 0 for all bytes except pixel 0 of both frames which has bit 6 = 1 for use as a frame marker.
2. Reading beyond pixel 899 will return the first pixel of the second partial frame.
3. t
CAPTURE
= 10 s + 3 frame periods.
4. This figure illustrates reading a single complete frame of 900 pixels. An additional 636 pixels from the next frame are available.
t
BEXIT
t
LOAD
t
SRAD
≥ 4
μ
s
≥ 10
μ
s
≥ 10
μ
s
≥ 10
μ
s
≥ 50 μ
s
Figure 25. Frame capture burst mode timing
20
Figure 26. Pixel address map (surface referenced)
Cable
RBLB
A6010
10
120
11
Top Xray View of Mouse
Positive X
Positive Y
899 898 897 896 895 894 893 892 891 890 889 888 887 886 885 884 883 882 881 880 879 878 877 876 875 874 873 872 871 870
869 868 867 866 865 864 863 862 861 860 859 858 857 856 855 854 853 852 851 850 849 848 847 846 845 844 843 842 841 840
839 838
etc.
61 60
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
expanded view of the
surface as viewed
through the lens
last output
first output
The pixel output order as related to the surface is shown below.
Error detection and recovery
1. The ADNS-6010 and the micro-controller might get
out of synchronization due to ESD events, power
supply droops or micro-controller firmware flaws. In
such a case, the micro-controller should pulse NCS
high for at least 1 ms. The ADNS-6010 will reset the
serial port (but not the control registers) and will be
prepared for the beginning of a new transmission
after the normal transaction delay.
2. Invalid addresses: Writing to an invalid address will
have no effect. Reading from an invalid address will
return all zeros.
3. Termination of a transmission by the micro-controller
may sometimes be required (for example, due to a
USB suspend interrupt during a read operation). To
accomplish this the micro-controller should raise
NCS. The ADNS-6010 will not write to any register
and will reset the serial port (but not the control
registers) and be prepared for the beginning of future
transmissions after NCS goes low. The normal delays
between reads or writes (tSWW, tswr, tSRAD, tSRAD-mot)
are still required after aborted transmissions.
4. The micro-controller can verify success of write
operations by issuing a read command to the same
address and comparing written data to read data.
5. The micro-controller can verify the synchronization
of the serial port by periodically reading the product
ID and inverse product ID registers.
6. The microcontroller can read the SROM_ID register
to verify that the sensor is running downloaded
PROM code. ESD or similar noise events may cause
the sensor to revert to native ROM execution. If this
should happen, pulse RESET and reload the SROM
code.
21
State of Signal Pins After VDD is Valid
Pin Before Reset During Reset After Reset
SPI pullups undefined off on (default)
NCS hi-Z control
functional
hi-Z control
functional
functional
MISO driven or hi-Z
(per NCS)
driven or hi-Z
(per NCS)
low or hi-Z
(per NCS)
SCLK undefined ignored functional
MOSI undefined ignored functional
XY_LASER undefined hi-Z functional
RESET functional high
(externally driven)
functional
NPD undefined ignored functional
LASER_NEN undefined high (off) functional
State of Signal Pins During Power Down
Pin NPD low After wake from PD
SPI pullups off pre-PD state
NCS hi-Z control functional functional
MISO low or hi-Z (per NCS) pre-PD state or hi-Z
SCLK ignored functional
MOSI ignored functional
XY_LASER high (off ) functional
RESET functional functional
NPD low (driven externally) functional
REFC VDD3 REFC
OSC_IN low OSC_IN
OSC_OUT high OSC_OUT
LASER_NEN high (off ) functional
Reset Circuit
The ADNS-6010 does not perform an internal power up
self-reset; the reset pin must be raised and lowered to
reset the chip. This should be done every time power is
applied. During power-up there will be a period of time
after the power supply is high but before any clocks are
available. The table below shows the state of the various
pins during power-up and reset when the RESET pin is
driven high by a micro-controller.
Notes on Power-up and the serial port
Power Down Circuit
The following table lists the pin states during power
down.
The chip is put into the power down (PD) mode by low-
ering the NPD input. When in PD mode, the oscillator is
stopped but all register contents are retained. To achieve
the lowest current state, all inputs must be held exter-
nally within 200mV of a rail, either ground or VDD3. The
chip outputs are driven low or hi-Z during PD to prevent
current consumption by an external load.
22
Registers
The ADNS-6010 registers are accessible via the serial port. The registers are used to read motion data and status as
well as to set the device configuration.
Address Register Read/Write Default Value
0x00 Product_ID R 0x1C
0x01 Revision_ID R 0x20
0x02 Motion R 0x20
0x03 Delta_X R 0x00
0x04 Delta_Y R 0x00
0x05 SQUAL R 0x00
0x06 Pixel_Sum R 0x00
0x07 Maximum_Pixel R 0x00
0x08 Reserved
0x09 Reserved
0x0a Configuration_bits R/W 0x49
0x0b Extended_Config R/W 0x08
0x0c Data_Out_Lower R Any
0x0d Data_Out_Upper R Any
0x0e Shutter_Lower R 0x85
0x0f Shutter_Upper R 0x00
0x10 Frame_Period_Lower R Any
0x11 Frame_Period_Upper R Any
0x12 Motion_Clear W Any
0x13 Frame_Capture R/W 0x00
0x14 SROM_Enable W 0x00
0x15 Reserved
0x16 Configuration II R/W 0x34
0x17 Reserved
0x18 Reserved
0x19 Frame_Period_Max_Bound Lower R/W 0x90
0x1a Frame_Period_Max_Bound_Upper R/W 0x65
0x1b Frame_Period_Min_Bound_Lower R/W 0x7E
0x1c Frame_Period_Min_Bound_Upper R/W 0x0E
0x1d Shutter_Max_Bound_Lower R/W 0x20
0x1e Shutter_Max_Bound_Upper R/W 0x4E
0x1f SROM_ID R Version dependent
0x20-0x2b Reserved
0x2c LP_CFG0 R/W 0x7F
0x2d LP_CFG1 R/W 0x80
0x2e-0x3c Reserved
0x3d Observation R/W 0x00
0x3e Reserved
0x3f Inverse Product ID R 0xE3
0x40 Pixel_Burst R 0x00
0x50 Motion_Burst R 0x00
0x60 SROM_Load W Any
23
Revision_ID Address: 0x01
Access: Read Default Value: 0x20
Bit76543210
Field RID7RID6RID5RID4RID3RID2RID1RID0
Data Type: 8-Bit unsigned integer.
USAGE: This register contains the IC revision. It is subject to change when new IC versions are released.
NOTE: The downloaded SROM firmware revision is a separate value and is available in the SROM_ID register.
Product_ID Address: 0x00
Access: Read Default Value: 0x1C
Bit765432 1 0
Field PID7PID6PID5PID4PID3PID2PID1PID0
Data Type: 8-Bit unsigned integer
USAGE: This register contains a unique identification assigned to the ADNS-6010. The value in this register does not
change; it can be used to verify that the serial communications link is functional.
24
Motion Address: 0x02
Access: Read Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field MOT Reserved LP_Valid OVF Reserved RES1 Fault RES0
Data Type: Bit field.
USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then
the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have
overflowed, if fault is detected, and the current resolution setting.
Notes for Motion:
1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_
X and Delta_Y registers. If Delta_X and Delta_Y are not read before the motion register is read a second time, the
data in Delta_X and Delta_Y will be lost.
2. Avago Technologies RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially. See Motion burst
mode also.
3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers
overflows, then absolute path data is lost and the OVF bit is set. This bit is cleared once some motion has been
read from the Delta_X and Delta_Y registers, and if the buffers are not at full scale. Since more data is present in
the buffers, the cycle of reading the Motion, Delta_X and Delta_Y registers should be repeated until the motion bit
(MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative
full scale. If the motion register has not been read for long time, at 400 cpi it may take up to 16 read cycles to clear
the buffers, at 2000 cpi, up to 80 cycles. Alternatively, writing to the Motion_Clear register (register 0x12) will clear
all stored motion at once.
Field Name Description
MOT Motion since last report
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers
LP_Valid This bit is an indicator of complementary value contained in registers 0x2C and 0x2D.
0 = register 0x2C and 0x2D do not have complementary values
1 = register 0x2C and 0x2D contain complementary values
OVF Motion overflow, 'Y and/or 'X buffer has overflowed since last report
0 = no overflow
1 = overflow has occurred
Fault Indicates that the RBIN and/or XY_LASER pin is shorted to GND.
0 = no fault detected
1 = fault detected
RES1, RES0 Resolution in counts per inch (cpi). Resolution values are approximate.
Cpi Bit2(RES1) Bit0(RES0)
400 0 0
800 0 1
1600 1 0
2000 1 1
Please see register 0x0a to set cpi
25
Delta_X Address: 0x03
Access: Read Default Value: 0x00
Bit7654 3 210
Field X7X6X5X4X3X2X1X0
Data Type: Eight bit 2’s complement number.
USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the reg-
ister.
00 01 02 7E 7F
+127+126+1 +2
FFFE8180
0-1-2-127-128
Motion
Delta_X
Delta_Y Address: 0x04
Access: Read Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field Y7Y6Y5Y4Y3Y2Y1Y0
Data Type: Eight bit 2’s complement number.
USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the reg-
ister.
00 01 02 7E 7F
+127+126+1 +2
FFFE8180
0-1-2-127-128
Motion
Delta_Y
26
Figure 27. SQUAL Values at 2000cpi (White Paper)
Figure 28. Mean SQUAL vs. Z (White Paper)
SQUAL Values (White Paper)
At Z=0mm, Circle@7.5" diameter, Speed-6ips
0
10
20
30
40
50
60
70
80
90
1 51 101 151 201 251 301 351 401 451 501 551 601 651
Counts
SQUAL Value (counts)
Mean SQUAL vs. Z (White Paper)
2000 cpi, Circle@7.5" diameter, Speed-6ips
0
20
40
60
80
100
120
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8
Distance of Lens Reference Plane to Surface, Z (mm)
SQUAL Vaalue (counts)
Avg-3sigma
Avg
Avg+3sigma
SQUAL Address: 0x05
Access: Read Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field SQ7SQ6SQ5SQ4SQ3SQ2SQ1SQ0
Data Type: Upper 8 bits of a 10-bit unsigned integer.
USAGE: SQUAL (Surface Quality) is a measure of ¼ of the number of valid features visible by the sensor in the current
frame. Use the following formula to find the total number of valid features.
Number of features = SQUAL register value *4
The maximum SQUAL register value is 169. Since small changes in the current frame can result in changes in SQUAL,
variations in SQUAL when looking at a surface are expected. The graph below shows 700 sequentially acquired SQUAL
values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero if there is no surface below
the sensor. SQUAL remains fairly high throughout the Z-height range.
27
Reserved Address: 0x08
Reserved Address: 0x09
Pixel_Sum Address: 0x06
Access: Read Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field AP7AP6AP5AP4AP3AP2AP1AP0
Data Type: High 8 bits of an unsigned 16-bit integer.
USAGE: This register is used to find the average pixel value. It reports the upper byte of a 16-bit counter which sums
all 900 pixels in the current frame. It may be described as the full sum divided by 256. To find the average pixel value,
use the following formula:
Average Pixel = Register Value * 256 / 900 = Register Value/3.51
The maximum register value is 221 (63 * 900/256 truncated to an integer). The minimum
is 0. The pixel sum value can change on every frame.
Maximum_Pixel Address: 0x07
Access: Read Default Value: 0x00
Bit765 4 32 10
Field 0 0 MP5MP4MP3MP2MP1MP0
Data Type: Six bit number.
USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The maximum pixel value
can vary with every frame.
28
Configuration_bits Address: 0x0a
Access: Read/Write Default Value: 0x49
Bit 7 6 5 4 3 2 1 0
Field 0 LASER_MODE Sys Test RES1 1 RES0 Reserved Reserved
Data Type: Bit field
USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are the bits, their default
values, and optional values.
Field Name Description
BIT 7 Must always be zero
LASER_MODE LASER Shutter Mode
0 = Shutter mode off (LASER always on)
1 = Shutter mode on (LASER only on when illumination is required)
Sys Test System Tests
0 = no tests
1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower
registers.
NOTE: The test will fail if SROM is loaded. Perform a hardware reset before executing this test.
Reload SROM after the test is completed.
NOTE: The test will fail if a laser fault condition exists.
NOTE: Since part of the system test is a RAM test, the RAM and SROM will be overwritten with the
default values when the test is done. If any configuration changes from the default are needed for
operation, make the changes AFTER the system test is run.
The system test takes 200ms (@24MHz) to complete.
NOTE: Do not access the Synchronous Serial Port during system test.
RES Resolution in counts per inch. Resolution values are approximate.
Cpi Bit4(RES1) Bit2(RES0)
400 0 0
800 1 0
1600 0 1
2000 1 1
Also see register 0x02i
BIT 3 Must always be one
29
Extended_Config Address: 0x0b
Access: Read/Write Default Value: 0x08
Bit 7 6 5 4 3 2 1 0
Field Busy Reserved Reserved Reserved 1 Serial_NPU NAGC Fixed_FR
Data Type: Bit field
USAGE: Register 0x0b allows the user to change the configuration of the sensor. Shown below are the bits, their default
values, and optional values.
Field Name Description
Busy Read-only bit. Indicates if it is safe to write to one or more of the following registers:
Frame_Period_Max_Bound_Upper and Frame_Period_Max_Bound_Lower
Frame_Period_Min_Bound_Upper and Frame_Period_Min_Bound_Lower
Shutter_Max_Bound_Upper and Shutter_Max_Bound_Lower
After writing to the Frame_Period_Maximum_Bound_Upper register, at least two frames
must pass before writing again to any of the above registers. This bit may be used in lieu of a
timer since the actual frame rate may not be known when running in auto mode.
0 = writing to the registers is allowed
1 = do not write to the registers yet
BIT 3 Must always be one
Serial_NPU Disable serial port pull-up current sources on SCLK, MOSI and NCS
0 = no, current sources are on
1 = yes, current sources are off
NAGC Disable AGC. Shutter will be set to the value in the Shutter_Maximum_Bound registers.
0 = no, AGC is active
1 = yes, AGC is disabled
Fixed_FR Fixed frame rate (disable automatic frame rate control). When this bit is set, the frame rate
will be determined by the value in the Frame_Period_Maximum_Bound registers.
0 = automatic frame rate
1 = fixed frame rate
30
Data_Out_Lower Address: 0x0c
Access: Read Default Value: Undefined
Bit 7 6 5 4 3 2 1 0
Field DO7DO6DO5DO4DO3DO2DO1DO0
Data_Out_Upper Address: 0x0d
Access: Read Default Value: Undefined
Bit76543210
Field DO15 DO14 DO13 DO12 DO11 DO10 DO9DO8
Data Type: Sixteen bit word
USAGE: Data in these registers come from the system self test or the SROM CRC test. The data can be read out in
either order.
System Test: This test is initiated via the Configuration_Bits register. It performs several tests to verify that the hardware
is functioning correctly. Perform a hardware reset just prior to running the test. SROM contents and register settings
will be lost.
SROM Content: Performs a CRC on the SROM contents. The test is initiated by writing a particular value to the SROM_
Enable register.
Data_Out_Upper Data_Out_Lower
System test results: 0xA9 0xD5
SROM CRC Test Result: 0xBE 0xEF
31
Figure 29. Shutter Values at 2000cpi (White Paper)
Shutter Value (White Paper)
At Z=0mm, Circle@7.5" diameter, Speed-6ips
0
20
40
60
80
100
120
140
160
1 51 101 151 201 251 301 351 401 451 501 551 601 651
Counts
Shutter Value (counts)
Shutter_Lower Address: 0x0e
Access: Read Default Value: 0x85
Bit7654 321 0
Field S7S6S5S4S3S2S1S0
Shutter_Upper Address: 0x0f
Access: Read Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field S15 S14 S13 S12 S11 S10 S9S8
Data Type: Sixteen bit unsigned integer.
USAGE: Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be read consecutively. The
shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value
is checked and automatically adjusted to a new value if needed on every frame when operating in default mode. When
the shutter adjusts, it changes by ± 1/16 of the current value. The shutter value can be set manually by setting the
AGC mode to Disable using the Extended_Config register and writing to the Shutter_Max_Bound registers. Because
the automatic frame rate feature is related to shutter value it may also be appropriate to enable the Fixed Frame Rate
mode using the Extended_Config register.
Shown below is a graph of 700 sequentially acquired shutter values, while the sensor was moved slowly over white
paper.
32
Figure 30. Mean Shutter vs. Z (White Paper)
The maximum value of the shutter is dependent upon the setting in the Shutter_Max_
Bound_Upper and Shutter_Max_Bound_Lower registers.
Mean Shutter vs. Z (White Paper)
2000dpi, Circle@7.5" diameter, Speed-6ips
0
20
40
60
80
100
120
140
160
180
200
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8
Distance from Lens Reference Plane to Surface, Z (mm)
Shutter Value (counts)
Avg-3sigma
Avg
Avg+3sigma
33
Motion_Clear Address: 0x12
Access: Write Default Value: Undefined
Data Type: Any.
USAGE: Writing any value to this register will cause the Delta_X, Delta_Y, and internal motion registers to be cleared.
Use this as a fast way to reset the motion counters to zero without resetting the entire chip.
Frame_Period_Lower Address: 0x10
Access: Read Default Value: Undefined
Bit 7 6 5 4 3 2 1 0
Field FP7FP6FP5FP4FP3FP2FP1FP0
Frame_Period_Upper Address: 0x11
Access: Read Default Value: Undefined
Bit7654321 0
Field FP15 FP14 FP13 FP12 FP11 FP10 FP9FP8
Data Type: Sixteen bit unsigned integer.
USAGE: Read these registers to determine the current frame period and to calculate the frame rate. Units are clock
cycles. The formula is
Frame Rate = Clock Frequency/Register value
To read from the registers, read Frame_Period_Upper first followed by Frame_Period Lower. To set the frame rate
manually, disable automatic frame rate mode via the Extended_Config register and write the desired count value to
the Frame_Period_Max_Bound registers.
The following table lists some Frame_Period values for popular frame rates with a 24MHz clock.
Frames/second Counts Frame_Period
Decimal Hex Upper Lower
7080 3,390 0D3E 0D 3E
5000 4,800 12C0 12 C0
3000 8,000 1F40 1F 40
2000 12,000 2EE0 2E E0
34
Frame_Capture Address: 0x13
Access: Read/Write Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field FC7FC6FC5FC4FC3FC2FC1FC0
Data Type: Bit field.
USAGE: Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel values to be stored
to SROM RAM. Writing to this register is required before using the Frame Capture burst mode to read the pixel values
(see the Synchronous Serial Port section for more details). Writing to this register will stop navigation and cause any
firmware loaded in the SROM to be overwritten. A hardware reset is required to restore navigation, and the firmware
must be reloaded using the PROM Download burst method.
This register can also be used to read the frame capture data. The same data available by reading the Pixel_Burst
register using burst mode is available by reading this register in the normal fashion. The data pointer is automatically
incremented after each read so all 1536 pixel values (1 and 2/3 frames) may be obtained by reading this register 1536
times in a row. Both methods share the same pointer such that reading pixel values from this register will increment
the pointer causing subsequent reads from the Pixel_Burst register (without initiating a new frame dump) to start at
the current pointer location. This register will return all zeros if read before the frame capture data is ready. See the
Frame Capture description in the Synchronous Serial Port section for more information.
This register will not retain the last value written. Reads will return zero or frame capture data.
SROM_Enable Address: 0x14
Access: Write Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field SE7SE6SE5SE4SE3SE2SE1SE0
Data Type: 8-bit number.
USAGE: Write to this register to start either PROM download or SROM CRC test.
Write 0x1D to this register, wait at least 1 frame period, and write 0x18 to this register before downloading PROM
firmware to the SROM_Load register. The download will not be successful unless this sequence is followed. See the
Synchronous Serial port section for details.
Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period, then read result from the Data_Out_Lower
and Data_Out_Upper registers. Navigation is halted and the SPI port should not be used during this test.
Reserved Address: 0x15
35
Configuration II Address: 0x16
Access: Read/Write Default Value: 0x34
Bit 7 6 5 4 3 2 1 0
Field Reserved Reserved Reserved Reserved Reserved 1 Force_disable Reserved
Data Type: Bit field
USAGE: Write to this register
Reserved Address: 0x17-0x18
Field Name Description
BIT 2 Must be set to one
Force_disable 0 = LASER_NEN functions as normal
1 = LASER_NEN output high. May be useful for product test.
36
Frame_Period_Max_Bound_Lower Address: 0x19
Access: Read/Write Default Value: 0x90
Bit 7 6 5 4 3 2 1 0
Field FBM7FBM6FBM5FBM4FBM3FBM2FBM1FBM0
Frame_Period_Max_Bound_Upper Address: 0x1A
Access: Read/Write Default Value: 0x65
Bit7654321 0
Field FBM15 FBM14 FBM13 FBM13 FBM11 FBM10 FBM9FBM8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be selected by the auto-
matic frame rate control, or sets the actual frame period when operating in manual mode. Units are clock cycles. The
formula is
Frame Rate = Clock Frequency / Register value
To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by
Upper. To set the frame rate manually, disable automatic frame rate mode via the Extended_Config register and write
the desired count value to these registers.
Writing to the Frame_Period_Max_Bound_Upper and Lower registers also activates any new values in the following
registers:
x Frame_Period_Max_Bound_Upper and Lower
x Frame_Period_Min_Bound_Upper and Lower
x Shutter_Max_Bound_Upper and Lower
Any data written to these registers will be saved but will not take effect until the write to the Frame_Period_Max_
Bound_Upper and Lower is complete. After writing to this register, two complete frame times are required to imple-
ment the new settings. Writing to any of the above registers before the implementation is complete may put the chip
into an undefined state requiring a reset. The “Busy” bit in the Extended_Config register may be used in lieu of a timer
to determine when it is safe to write. See the Extended_Config register for more details.
The following table lists some Frame_Period values for popular frame rates (clock rate = 24MHz). In addition, the three
bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound t Frame_Period_Min_Bound + Shutter_Max_Bound.
Frames/second Counts Frame_Period
Decimal Hex Upper Lower
7080 3,390 0D3E 0D 3E
5000 4,800 12C0 12 C0
3000 8,000 1F40 1F 40
2000 12,000 2EE0 2E E0
37
Frame_Period_Min_Bound_Lower Address: 0x1B
Access: Read/Write Default Value: 0x7E
Bit 7 6 5 4 3 2 1 0
Field FBm7FBm6FBm5FBm4FBm3FBm2FBm1FBm0
Frame_Period_Min_Bound_Upper Address: 0x1C
Access: Read/Write Default Value: 0x0E
Bit76543210
Field FBm15 FBm14 FBm13 FBm13 FBm11 FBm10 FBm9FBm8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) which may be selected by the automatic
frame rate control. Units are clock cycles. The formula is
Frame Rate = Clock Rate / Register value
To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by
Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. The minimum allowed write
value is 0x0D3E; the maximum is 0xFFFF.
Reading this register will return the most recent value that was written to it. However, the value will take effect only
after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_
Bound_Upper, wait at least two frame times before writing to Frame_Period_Min_Bound_Upper or Lower again. The
“Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the
Extended_Config register for more details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound t Frame_Period_Min_Bound + Shutter_Max_Bound.
38
SROM_ID Address: 0x1F
Access: Read Default Value: Version dependent
Bit7654321 0
Field SR7SR6SR5SR4SR3SR2SR1SR0
Data Type:8-Bit unsigned integer.
USAGE: Contains the revision of the downloaded Shadow ROM firmware. If the firmware has been successfully down-
loaded and the chip is operating out of SROM, this register will contain the SROM firmware revision, otherwise it will
contain 0x00.
Note: The IC hardware revision is available by reading the Revision_ID register (register 0x01).
Shutter_Max_Bound_Lower Address: 0x1D
Access: Read/Write Default Value: 0x20
Bit765432 10
Field SB7SB6SB5SB4SB3SB2SB1SB0
Shutter_Max_Bound_Upper Address: 0x1E
Access: Read/Write Default Value: 0x4E
Bit 7 6 5 4 3 2 1 0
Field SB15 SB14 SB13 SB12 SB11 SB10 SB9SB8
Data Type: 16-bit unsigned integer.
USAGE: This value sets the maximum allowable shutter value when operating in automatic mode. Units are clock cycles.
Since the automatic frame rate function is based on shutter value, the value in these registers can limit the range of the
frame rate control. To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower
first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. To set the
shutter manually, disable the AGC via the Extended_Config register and write the desired value to these registers.
Reading this register will return the most recent value that was written to it. However, the value will take effect only
after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_Bound_
Upper, wait at least two frame times before writing to Shutter_Max_Bound_Upper or Lower again. The “Busy” bit in the
Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config
register for more details.
In addition, the three bound registers must also follow this rule when set to non-default values:
Frame_Period_Max_Bound t Frame_Period_Min_Bound + Shutter_Max_Bound.
39
LP_CFG0 Address: 0x2C
Access: Read/Write Default Value: 0x7F
Bit 7 6 5 4 3 2 1 0
Field Match LP6LP5LP4LP3LP2LP1LP0
Data Type: 8-bit unsigned integer
USAGE: This register is used to set the laser current and bin matching parameter. It is to be used together with register
0x2D where register 0x2D must contain the complement of register 0x2C in order for the laser current to be pro-
grammed. Writing to this register causes a fault test to be performed on the XY_LASER pin. The test checks for stuck
low and stuck high conditions. During the test, LASER_NEN will be driven high and XY_LASER will pulse high for 12us
and pulse low for 12us (times are typical). Both pins will return to normal operation if no fault is detected.
LP_CFG1 Address: 0x2D
Access: Read/Write Default Value: 0x80
Bit 7 6 5 4 3 2 1 0
Field LPC7LPC6LPC5LPC4LPC3LPC2LPC1LPC0
Data Type: 8-bit unsigned integer
USAGE: The value in this register must be a complement of register 0x2C for laser current to be as programmed, oth-
erwise the laser current is set to 33.85%. Registers 0x2C and 0x2D may be written in any order after power ON reset
or SROM download.
Field Name Description
Match Match the sensor to the VCSEL characteristics. Set per the bin table specification for the
VCSEL bin in use.
LP6 - LP0Controls the 7 bit DAC for adjusting laser current.One step is equivalent to (1/192)*100% =
0.5208% drop of relative laser current.Refer to the table below for example of relative laser
current settings.
LP6- LP3LP2LP1LP0Relative Laser Current
0000 0 0 0 100%
0000 0 0 1 99.48%
0000 0 1 0 98.96%
0000 0 1 1 98.43%
0000 1 0 0 97.92%
:::: :
1111 1 0 1 34.90%
1111 1 1 0 34.38%
1111 1 1 1 33.85%
40
Observation Address: 0x3D
Access: Read/Write Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field OB7Reserved OB5Reserved Reserved Reserved OB1OB0
Data Type: Bit field
USAGE: Each bit is set by some process or action at regular intervals, or when the event occurs. The user must clear
the register by writing 0x00, wait an appropriate delay, and read the register. The active processes will have set their
corresponding bit(s). This register may be used as part of a recovery scheme to detect a problem caused by EFT/B or
ESD.
Reserved Address: 0x3E
Reserved Address: 0x2f-0x3C
Inverse_Product_ID Address: 0x3F
Access: Read Default Value: 0xE3
Bit 7 6 5 4 3 2 1 0
Field NPID7NPID6NPID5NPID4NPID3NPID2NPID1NPID0
Data Type: Inverse 8-Bit unsigned integer
USAGE: This value is the inverse of the Product_ID, located at the inverse address. It can be used to test the SPI port.
Field Name Description
OB70 = Chip is not running SROM code
1 = Chip is running SROM code
OB50 = NPD pulse was not detected
1 = NPD pulse was detected
OB1Set once per frame
OB0Set once per frame
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-1410EN - December 4, 2009
SROM_Load Address: 0x 60
Access: Write Default Value: N/A
Bit76543210
Field SL7SL6SL5SL4SL3SL2SL1SL0
Data Type: Eight bit unsigned integer
USAGE: The SROM_Load register is used for high-speed programming of the ADNS-6010 from an external PROM or
microcontroller. See the Synchronous Serial Port section for use details.
Motion_Burst Address: 0x50
Access: Read Default Value: 0x00
Bit 7 6 5 4 3 2 1 0
Field MB7MB6MB5MB4MB3MB2MB1MB0
Data Type: Various, depending on data
USAGE: The Motion_Burst register is used for high-speed access to the Motion, Delta_X, Delta_Y, SQUAL, Shutter_Up-
per, Shutter_Lower, and Maximum_Pixel registers. See the Synchronous Serial Port section for use details.
Pixel_Burst Address: 0x40
Access: Read Default Value: 0x00
Bit7 6 543210
Field PB7PB6PB5PB4PB3PB2PB1PB0
Data Type: Eight bit unsigned integer
USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values from one and 2/3 complete frame.
See the Synchronous Serial Port section for use details.
