1
LT1425
Isolated Flyback
Switching Regulator
■
No Transformer “Third Winding” or Optoisolator
Required
■
±5% Accurate Output Voltage Without User Trims
(See Circuit Below)
■
Resistor Programmable Output Voltage
■
Regulation Maintained Well Into Discontinuous
Mode (Light Load)
■
Optional Load Compensation
■
Operating Frequency: 285kHz
■
Easily Synchronized to External Clock
■
Available in 16-Pin Narrow SO Package
FEATURES
The LT
®
1425 is a monolithic high power switching regu-
lator specifically designed for the isolated flyback topol-
ogy. No “third winding” or optoisolator is required; the
integrated circuit senses the isolated output voltage
directly from the primary side flyback waveform. A high
current, high efficiency switch is included on the die along
with all oscillator, control and protection circuitry.
The LT1425 operates with input supply voltages from 3V
to 20V and draws only 7mA quiescent current. It can
deliver output power up to 6W with no external power
devices. By utilizing current mode switching techniques, it
provides excellent AC and DC line regulation.
The LT1425 has a number of features not found on other
switching regulator ICs. Its unique control circuitry can
maintain regulation well into discontinuous mode in most
applications. Optional load compensation circuitry allows
for improved load regulation. An externally activated shut-
down mode reduces total supply current to 15µA for
standby operation.
DESCRIPTION
U
TYPICAL APPLICATION
U
+
11
ISOLATED
–9V ±5% AT
20mA TO 200mA
V–
1425 TA01
*DALE LPE 4841-330MB
12
5V
D1
1N5819
500V
ISOLATION BARRIER
T1*
15
6
4
3
R1
22.6k
1%
5
14
13
710
V
IN
LT1425
SGND PGND
VSW
RFB
RREF
ROCOMP
SHDN
SYNC
VC
RCCOMP
R2
3.01k
1%
R3
15k
C4
0.1µF
C3
1000pF
C1
100µF
10V
C2
47µF
16V
+
••
F
OUTPUT CURRENT (mA)
0
OUTPUT VOLTAGE (V)
8.5
9.0
8.9
8.8
8.7
8.6
9.5
9.4
9.3
9.2
9.1
50 100
1425 TA02
150 200
Load Regulation
5V to Isolated –9VOUT
APPLICATIONS
U
■
Isolated Flyback Switching Regulators
■
Ethernet Isolated 5V to –9V Converters
■
Medical Instruments
■
Isolated Telecom Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
2
LT1425
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
T
JMAX
= 145°C, θ
JA
= 75°C/ W
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
NC
R
FB
V
C
R
REF
SYNC
SGND
GND
GND
SHDN
R
OCOMP
R
CCOMP
V
IN
V
SW
PGND
GND
ORDER PART
NUMBER
LT1425CS
LT1425IS
ELECTRICAL CHARACTERISTICS
VIN = 5V, TJ = 25°C, VSW open, VC = 1.4V, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Feedback Amplifier
I
REF
Reference Current Measured at R
FB
Pin with R
REF
= 3.000k 402 408 414 µA
●396 420 µA
I
IN
R
REF
Pin Input Current 500 nA
g
m
Feedback Amplifier Transconductance ∆I
C
= ±10µA (Note 2) ●400 1000 1600 µmho
I
SOURCE
, I
SINK
Feedback Amplifier Source or Sink Current ●30 50 80 µA
V
CL
Feedback Amplifier Clamp Voltage 1.9 V
Reference Voltage/Current Line Regulation 5V ≤ V
IN
≤ 18V ●0.01 0.04 %/V
Voltage Gain (Note 3) 500 V/V
V
IN
Sense Error ●10 25 mV
Output Switch
BV Output Switch Breakdown Voltage I
C
= 5mA ●35 50 V
V(V
SW
) Output Switch ON Voltage I
SW
= 1A ●0.55 0.85 V
I
LIM
Switch Current Limit Duty Cycle = 50%, 0°C ≤ T
J
≤ 100°C●1.35 1.60 1.9 A
Duty Cycle = 50%, –40°C ≤ T
J
≤ 100°C●1.25 1.60 1.9 A
Duty Cycle = 80% 1.30 A
Current Amplifier
Control Pin Threshold Duty Cycle = Minimum 0.95 1.2 1.3 V
●0.85 1.4 V
Control Voltage to Switch Transconductance 2 A/V
Timing
f Switching Frequency 260 285 300 kHz
●240 320 kHz
t
ON
Minimum Switch ON Time 170 210 260 ns
t
ED
Flyback Enable Delay Time 150 ns
t
EN
Minimum Flyback Enable Time 180 ns
Maximum Switch Duty Cycle ●85 90 95 %
Consult factory for Military grade parts.
(Note 1)
Supply Voltage ........................................................ 20V
Switch Voltage......................................................... 35V
SHDN, SYNC Pin Voltage........................................... 7V
R
FB
Pin Current....................................................... 2mA
Operating Junction Temperature Range
Commercial .......................................... 0°C to 100°C
Industrial ......................................... –40°C to 100°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
3
LT1425
ELECTRICAL CHARACTERISTICS
VIN = 5V, TJ = 25°C, VSW Open, VC = 1.4V, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Load Compensation
∆V
RCCOMP
/∆I
SW
0.45 Ω
SYNC Function
Minimum SYNC Amplitude ●1.5 2.2 V
Synchronization Range 320 450 kHz
SYNC Pin Input Resistance 40 kΩ
Power Supply
V
IN(MIN)
Minimum Input Voltage ●2.8 3.1 V
I
CC
Supply Current ●7.0 9.5 mA
Shutdown Mode Supply Current ●15 40 µA
Shutdown Mode Threshold ●0.4 0.9 1.3 V
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Switch Saturation Voltage vs
Switch Current
TEMPERATURE (°C)
–50
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4 25 75
1425 G03
–25 0 50 100 125
INPUT VOLTAGE (V)
Switch Current Limit vs
Duty Cycle Minimum Input Voltage vs
Temperature
SWITCH CURRENT (A)
0
SWITCH SATURATION VOLTAGE (V)
1.2
1.0
0.8
0.6
0.4
0.2
00.6 1.0
1425 G01
0.2 0.4 0.8 1.2 1.4
125°C
25°C
–55°C
DUTY CYCLE (%)
0
SWITCH CURRENT LIMIT (A)
40
1425 G02
10 20 30 50 60 70 80 90 100
2.0
1.5
1.0
0.5
0
T
A
= 25°C
The ● denotes the specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Feedback amplifier transconductance is R
REF
referred.
Note 3: Voltage gain is R
REF
referred.
4
LT1425
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Feedback Amplifier Output
Current vs RREF Pin Voltage
RREF NODE VOLTAGE (V)
1.05
60
40
20
0
–20
–40
–60
–80 1.20 1.30
1425 G04
1.10 1.15 1.25 1.35 1.40
FEEDBACK AMPLIFIER OUTPUT CURRENT (µA)
25°C
125°C
–55°C
TEMPERATURE (°C)
–50
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75 25 75
1425 G06
–25 0 50 100 125
VC PIN VOLTAGE (V)
VC HIGH CLAMP
VC THRESHOLD
VC Pin Threshold and High Clamp
Voltage vs Temperature
TEMPERATURE (°C)
–50
1400
1200
1000
800
600
400
200
025 75
1425 G05
–25 0 50 100 125
TRANSCONDUCTANCE (µmho)
Error Amplifier Transconductance
vs Temperature (RREF Referred)
Switching Frequency vs
Temperature SHDN Pin Input Current vs
Voltage
Minimum Synchronization
Voltage vs Temperature
TEMPERATURE (°C)
–50
300
295
290
285
280
275
270
265 25 75
1425 G07
–25 0 50 100 125
SWITCHING FREQUENCY (kHz)
TEMPERATURE (°C)
–50
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75 25 75
1425 G08
–25 0 50 100 125
MINIMUM SYNCHRONIZATION VOLTAGE (VP-P)
SHDN PIN VOLTAGE (V)
0
1
0
–1
–2
–3
–4 4
1425 G09
1235
SHDN PIN INPUT CURRENT (µA)
T
A
= 25°C
Minimum Switch ON Time vs
Temperature Flyback Enable Delay Time vs
Temperature
TEMPERATURE (°C)
–50
300
275
250
225
200
175
150
125 25 75
1425 G10
–25 0 50 100 125
SWITCH ON TIME (ns)
TEMPERATURE (°C)
–50
250
225
200
175
150
125
100
75 25 75
1425 G11
–25 0 50 100 125
ENABLE DELAY TIME (ns)
TEMPERATURE (°C)
–50
275
250
225
200
175
150
125
100 25 75
1425 G12
–25 0 50 100 125
ENABLE TIME (ns)
Minimum Flyback Enable Time vs
Temperature
5
LT1425
PIN FUNCTIONS
UUU
GND (Pins 1, 8, 9, 16): Ground. These pins connect to the
substrate of the die and are separate from the power
ground and signal ground. They should connect directly to
a good quality ground plane.
R
FB
(Pin 3): Input Pin for External “Feedback” Resistor
Connected to Transformer Primary (V
SW
). The ratio of this
resistor to the R
REF
resistor, times the internal bandgap
(V
BG
) reference, is the primary determinant of the output
voltage (plus the effect of any nonunity transformer turns
ratio). The average current through this resistor during the
flyback period should be approximately 400µA. See Appli-
cations Information for more details.
V
C
(Pin 4): Control Voltage. This pin is the output of the
feedback amplifier and the input of the current compara-
tor. Frequency compensation of the overall loop is effected
by placing a capacitor between this node and ground.
R
REF
(Pin 5): Input Pin for External Ground-Referred
“Reference” Resistor. This resistor should be in the range
of 3k, but for convenience, need not be this value precisely.
See Applications Information for more details.
SYNC (Pin 6): Pin to Synchronize Internal Oscillator to
External Frequency Reference. It is directly logic compat-
ible and can be driven with any signal between 10% and
90% duty cycle. If unused, this pin can be left floating;
however, for best noise immunity the pin should be
grounded.
SGND (Pin 7): Signal Ground. This pin is a clean ground.
The internal reference and feedback amplifier are referred
to it. Keep the ground path connection to R
REF
and the V
C
compensation capacitor free of large ground currents.
PGND (Pin 10): Power Ground. This pin is the emitter of
the power switch device and has large currents flowing
through it. It should be connected directly to a good quality
ground plane.
V
SW
(Pin 11): This is the collector node of the output
switch and has large currents flowing through it. Keep the
traces to the switching components as short as possible
to minimize electromagnetic radiation and voltage spikes.
V
IN
(Pin 12): Supply Voltage. Bypass input supply pin with
10µF or more. The part goes into undervoltage lockout
when V
IN
drops below 2.8V. Undervoltage lockout stops
switching and pulls the V
C
pin low.
R
CCOMP
(Pin 13): Pin for the External Filter Capacitor for
Load Compensation Function. A common 0.1µF
ceramic capacitor will suffice for most applications. See
Applications Information for further details.
R
OCOMP
(Pin 14): Input Pin for Optional External Load
Compensation Resistor. Use of this pin allows nominal
compensation for nonzero output impedance in the power
transformer secondary circuit, including secondary wind-
ing impedance, output Schottky diode impedance and
output capacitor ESR. In less demanding applications this
resistor is not needed. See Applications Information for
more details.
SHDN (Pin 15): Shutdown. This pin is used to turn off the
regulator and reduce V
IN
input current to a few tens of
microamperes. The SHDN pin can be left floating when
unused.
6
LT1425
BLOCK DIAGRAM
W
FLYBACK ERROR A PLIFIER DIAGRA
WW
+
–
D1
T1
•
•
ISOLATED
V
OUT
C1
+
V
IN
V
SW
V
C
C
EXT
R
FB
R
FB
R
REF
R
REF
V
BG
Q4
D2
Q1
Q2 Q3
V
IN
I
I
M
I
M
I
FXD
ENABLE
1425 EA
–
+
LOAD
COMPENSATION
CURRENT
AMPLIFIER
DRIVERLOGIC
285kHz
OSCILLATOR
2.6V
REGULATOR
SHDN
FLYBACK
ERROR
AMPLIFIER
COMP
R
CCOMP
R
OC0MP
R
REF
V
SW
R
SENSE
PGND
1425 BD
V
C
SGND
GND IS OMITTED FOR CLARITY
V
IN
R
FB
SYNC
7
LT1425
TI I G DIAGRA
WW
U
VSW
VOLTAGE
VIN
GND
OFF ON
MINIMUM tON ENABLE DELAY
MINIMUM ENABLE TIME
1425 TD
OFF ON
SWITCH
STATE
FLYBACK AMP
STATE
0.80×
VFLBK
VFLBK
COLLAPSE
DETECT
ENABLEDDISABLED DISABLED
OPERATION
U
The LT1425 is a current mode switching regulator IC that
has been designed specifically for the isolated flyback
topology. The special problem normally encountered in
such circuits is that information relating to the output
voltage on the isolated secondary side of the transformer
must be communicated to the primary side in order to
maintain regulation. Historically, this has been done with
optoisolators or extra transformer windings. Optoisolator
circuits waste output power and the extra components
they require increase the cost and physical volume of the
power supply. Optoisolators can also exhibit trouble due
to limited dynamic response (temporal), nonlinearity,
unit-to-unit variation and aging over life. Circuits
employing extra transformer windings also exhibit defi-
ciencies. The extra winding adds to the transformer’s
physical size and cost. Dynamic response is often
mediocre. There is usually no method for maintaining
load regulation versus load.
The LT1425 derives its information about the isolated
output voltage by examining the primary side flyback
pulse waveform. In this manner no optoisolator nor extra
transformer winding is required. This IC is a quantum
improvement over previous approaches because: target
output voltage is directly resistor-programmable, regu-
lation is maintained well into discontinuous mode and
optional load compensation is available.
The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in tradi-
tional designs including: internal bias regulator, oscilla-
tor, logic, current amplifier and comparator, driver and
output switch. The novel sections include a special
flyback error amplifier and a load compensation mecha-
nism. Also, due to the special dynamic requirements of
flyback control, the logic system contains additional
functionality not found in conventional designs.
8
LT1425
OPERATION
U
Within the dashed lines in the Block Diagram can be found
the R
REF
, R
FB
and R
OCOMP
resistors. They are external
resistors on the user-programmable LT1425. The capaci-
tor connected to the R
CCOMP
pin is also external.
The LT1425 operates much the same as traditional current
mode switchers, the major difference being a different
type of error amplifier which derives its feedback informa-
tion from the flyback pulse. Due to space constraints, this
discussion will not reiterate the basics of current mode
switcher/controllers and isolated flyback converters. A
good source of information on these topics is LTC’s
Application Note 19.
ERROR AMPLIFIER—PSEUDO DC THEORY
Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when output switch Q4
turns off, its collector voltage rises above the V
IN
rail. The
amplitude of this flyback pulse, i.e., the difference between
it and V
IN
, is given as:
V
FLBK
=
V
F
= D1 forward voltage
I
SEC
= Transformer secondary current
ESR = Total impedance of secondary circuit
N
SP
= Transformer effective secondary-to-primary
turns ratio
V
OUT
+ V
F
+ (I
SEC
)(ESR)
N
SP
The flyback voltage is then converted to a current by the
action of R
FB
and Q1. Nearly all of this current flows
through resistor R
REF
to form a ground-referred voltage.
This is then compared to the internal bandgap reference by
the differential transistor pair Q2/Q3. The collector current
from Q2 is mirrored around and subtracted from fixed
current source I
FXD
at the V
C
pin. An external capacitor
integrates this net current to provide the control voltage to
set the current mode trip point.
The relatively high gain in the overall loop will then cause
the voltage at the R
REF
resistor to be nearly equal to the
bandgap reference V
BG
. (V
BG
is not present in final output
voltage setting equation. See Applications Information
section.) The relationship between V
FLBK
and V
BG
may
then be expressed as:
V
FLBK
R
FB
V
FLBK
= V
BG
α = Ratio of Q1 I
C
to I
E
V
BG
= Internal bandgap reference
α= or,
R
FB
R
REF
V
BG
R
REF
)
)
1
α
)
)
Combination with the previous V
FLBK
expression yields an
expression for V
OUT
, in terms of the internal reference,
programming resistors, transformer turns ratio and diode
forward voltage drop:
V
OUT
= V
BG
– V
F
– I
SEC
(ESR)
R
FB
R
REF
)
)
N
SP
α
)
)
Additionally, it includes the effect of nonzero secondary
output impedance. See Load Compensation for details.
The practical aspects of applying this equation for V
OUT
are
found in the Applications Information section.
So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the dashed line connections to the
block labeled “ENABLE.” Timing signals are then required
to enable and disable the flyback amplifier.
ERROR AMPLIFIER—DYNAMIC THEORY
There are several timing signals that are required for
proper LT1425 operation. Please refer to the Timing
Diagram.
Minimum Output Switch ON Time
The LT1425 effects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse, and output voltage informa-
tion is no longer available. This would cause irregular loop
response and start-up/latchup problems. The solution
chosen is to require the output switch to be on for an
absolute minimum time per each oscillator cycle. This in
turn establishes a minimum load requirement to maintain
9
LT1425
OPERATION
U
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
only during a portion of the cycle time. This can vary from
the fixed “minimum enable time” described to a maximum
of roughly the OFF switch time minus the enable delay
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and V
C
node slew rate.
LOAD COMPENSATION THEORY
The LT1425 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
transformer secondary and output capacitor. This has
been represented previously by the expression (I
SEC
)(ESR).
However, it is generally more useful to convert this expres-
sion to an effective output impedance. Because the sec-
ondary current only flows during the off portion of the duty
cycle, the effective output impedance equals the lumped
secondary impedance times the inverse of the OFF duty
cycle. That is,
R
OUT
= ESR
where,
R
OUT
= Effective supply output impedance
ESR = Lumped secondary impedance
DC OFF = OFF duty cycle
1
DC OFF
)
)
Expressing this in terms of the ON duty cycle, remember-
ing DC OFF = 1 – DC,
R
OUT
= ESR
DC = ON duty cycle
1
1 – DC
)
)
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external R
FB
resistor
value adjusted to compensate for nominal expected error.
In more demanding applications, output impedance error
regulation. See Applications Information section for fur-
ther details.
Enable Delay
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
former primary side voltage waveform approximately rep-
resents the output voltage. This is partly due to rise time
on the V
SW
node, but more importantly due to transformer
leakage inductance. The latter causes a voltage spike on
the primary side not directly related to output voltage.
(Some time is also required for internal settling of the
feedback amplifier circuitry.)
In order to maintain immunity to these phenomena, a fixed
delay is introduced between the switch turn-off command
and the enabling of the feedback amplifier. This is termed
“enable delay.” In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Applications
Information section for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, that compares the flyback
voltage (R
REF
referred) to a fixed reference, nominally
80% of V
BG
. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodates both continuous and discontinuous mode
operation.
Minimum Enable Time
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lock-up, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the V
C
node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
the low load level at which output voltage regulation is lost.
See Applications Information section for details.
10
LT1425
OPERATION
U
may be minimized by the use of the load compensation
function.
To implement the load compensation function, a voltage is
developed that is proportional to average output switch
current. This voltage is then impressed across the external
R
OCOMP
resistor and the resulting current is then sub-
tracted from the R
FB
node. As output loading increases,
average switch current increases to maintain rough output
voltage regulation. This causes an increase in R
OCOMP
resistor current subtracted from the R
FB
node, through
which feedback loop action causes a corresponding
increase in target output voltage.
Assuming a relatively fixed power supply efficiency, Eff,
Power Out = (Eff)(Power In)
(V
OUT
)(I
OUT
) = (Eff)(V
IN
)(I
IN
)
Average primary side current may be expressed in terms
of output current as follows:
I
IN
= I
OUT
V
OUT
(V
IN
)(Eff)
)
)
Combining the efficiency and voltage terms in a single
variable,
I
IN
= K1(I
OUT
)
where,
K1
= V
OUT
(V
IN
)(Eff)
)
)
Switch current is converted to voltage by a sense resistor
and amplified by the current sense amplifier with associ-
ated gain G. This voltage is then impressed across the
external R
OCOMP
resistor to form a current that is
subtracted from the R
FB
node. So the effective change in
V
OUT
target is:
∆VOUT = K1(∆IOUT) RFB
(RSENSE)(G)
ROCOMP
)
)
Expressing the product of R
SENSE
and G as the data sheet
value of ∆V
RCCOMP
/∆I
SW
,
∆V
RCCOMP
∆I
SW
)
)
∆V
RCCOMP
∆I
SW
)
)
R
FB
R
OCOMP
)
)
R
OUT
= K1 and,
R
FB
R
OUT
)
)
R
OCOMP
= K1
∆V
RCCOMP
∆I
SW
)
)
= Data sheet value for R
CCOMP
pin
action vs switch current
where,
K1 = Dimensionless variable related to V
IN
,
V
OUT
and efficiency as above
R
FB
= External “feedback” resistor value
R
OUT
= Uncompensated output impedance
∆V
RCCOMP
∆I
SW
∆V
OUT
∆I
OUT
)
)
R
FB
R
OCOMP
)
)
= K1
Nominal output impedance cancellation is obtained by
equating this expression with R
OUT
. The practical aspects
of applying this equation to determine an appropriate
value for the R
OCOMP
resistor are found in the Applications
Information section.
11
LT1425
APPLICATIONS INFORMATION
WUU U
R
OCOMP
, the external resistor value required for its nomi-
nal compensation:
1
1 – DC
)
)
ROUT = ESR
∆VRCCOMP
∆ISW
)
)
RFB
ROUT
)
)
ROCOMP = K1
While the value for R
OCOMP
may therefore be theoretically
determined, it is usually better in practice to employ
empirical methods. This is because several of the required
input variables are difficult to estimate precisely. For
instance, the ESR term above includes that of the trans-
former secondary, but its effective ESR value depends on
high frequency behavior, not simply DC winding resis-
tance. Similarly, K1 appears to be a simple ratio of V
IN
to
V
OUT
times (differential) efficiency, but theoretically esti-
mating efficiency is not a simple calculation. The sug-
gested empirical method is as follows:
Build a prototype of the desired supply using the
eventual secondary components. Temporarily ground
the R
CCOMP
pin to disable the load compensation func-
tion. Operate the supply over the expected range of
output current loading while measuring the output
voltage deviation. Approximate this variation as a single
value of R
OUT
(straight line approximation). Calculate a
value for the K1 constant based on V
IN
, V
OUT
and the
measured (differential) efficiency. They are then com-
bined with the data sheet typical value for (∆V
RCCOMP
/
∆I
SW
) to yield a value for R
OCOMP
.
Verify this result by connecting a resistor of roughly this
value from the R
OCOMP
pin to ground. (Disconnect the
ground short to R
CCOMP
and connect the requisite
0.1µF filter capacitor to ground.) Measure the output
impedance with the new compensation in place. Modify
the original R
OCOMP
value if necessary to increase or
decrease the effective compensation.
Once the proper load compensation resistor has been
chosen, it may be necessary to adjust the value of the
R
FB
resistor. This is because the load compensation
system exhibits some nonlinearity. In particular, the
circuit can shift the reference current by a noticeable
SELECTING R
FB
AND R
REF
RESISTOR VALUES
The expression for V
OUT
developed in the Operation
section can be rearranged to yield the following expres-
sion for R
FB
:
V
OUT
+ V
F
+ I
SEC
(ESR)
V
BG
))
))
R
FB
= R
REF
α
N
SP
The unknown parameter α, which represents the fraction
of R
FB
current flowing into the R
REF
node, can be repre-
sented instead by specified data sheet values as follows:
V
BG
(I
REF
)(3k)
)
)
(I
REF
)(α)(3k) = V
BG
α =
Allowing the expression for R
FB
to be rewritten as:
VOUT + VF + ISEC(ESR)
IREF(3k)NSP
)
)
RFB = RREF
where,
VOUT = Desired output voltage
VF = Switching diode forward voltage
(ISEC)(ESR) = Secondary resistive losses
IREF = Data sheet reference current value
NSP = Effective secondary-to-primary turns ratio
Strictly speaking, the above equation defines R
FB
not as an
absolute value, but as a ratio of R
REF
. So the next question
is, “What is the proper value for R
REF
?” The answer is that
R
REF
should be approximately 3k. This is because the
LT1425 is trimmed and specified using this value of R
REF
.
If the impedance of R
REF
varies considerably from 3k,
additional errors will result. However, a variation in R
REF
of several percent or so is perfectly acceptable. This yields
a bit of freedom in selecting standard 1% resistor values
to yield nominal R
FB
/R
REF
ratios.
SELECTING R
OCOMP
RESISTOR VALUE
The Operation section previously derived the following
expressions for R
OUT
, i.e., effective output impedance and
12
LT1425
APPLICATIONS INFORMATION
WUU U
amount when output switch current is zero. Please refer
to Figure 1 which shows nominal reference current shift
at zero load for a range of R
OCOMP
values. Example: for
a load compensation resistor of 12k, the graph indi-
cates a 1.0% shift in reference current. The R
FB
resistor
value should be adjusted down by about 1.0% to
restore the original target output voltage.
integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which
yield more freedom in setting total turns and mutual
inductance. Turns ratio can then be chosen on the basis of
desired duty cycle. However, remember that the input
supply voltage plus the secondary-to-primary referred
version of the flyback pulse (including leakage spike) must
not exceed the allowed output switch breakdown rating.
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after output switch turn-off.
This is increasingly prominent at higher load currents
where more stored energy must be dissipated. In many
cases a “snubber” circuit will be required to avoid over-
voltage breakdown at the output switch node. LTC’s
Application Note 19 is a good reference on snubber
design.
In situations where the flyback pulse extends beyond the
enable delay time, the output voltage regulation will be
affected to some degree. It is important to realize that the
feedback system has a deliberately limited input range,
roughly ±50mV referred to the R
REF
node, and this works
to the user’s advantage in rejecting large, i.e., higher
voltage leakage spikes. In other words, once a leakage
spike is several volts in amplitude, a further increase in
amplitude has little effect on the feedback system. So the
user is generally advised to arrange the snubber circuit to
clamp at as high a voltage as comfortably possible,
observing switch breakdown, such that leakage spike
duration is as short as possible.
As a rough guide, total leakage inductances of several
percent (of mutual inductance) or less may require a
snubber, but exhibit little to no regulation error due to
leakage spike behavior. Inductances from several percent
up to perhaps ten percent cause increasing regulation
error.
Severe leakage inductances in the double digit percentage
range should be avoided if at all possible as there is a
potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leak-
age spike becomes such a large portion of the flyback
waveform that the processing circuitry is fooled into
thinking that the leakage spike itself is the real flyback
In less critical applications, or when output current
remains relatively constant, the load compensation func-
tion may be deemed unnecessary. In such cases, a
reduced component solution may be obtained as follows:
Leave the R
OCOMP
node open (R
OCOMP
= ∞), and replace
the filter capacitor normally on the R
CCOMP
node with a
short to ground.
TRANSFORMER DESIGN CONSIDERATIONS
Transformer specification and design is perhaps the most
critical part of applying the LT1425 successfully. In addi-
tion to the usual list of caveats dealing with high frequency
isolated power supply transformer design, the following
information should prove useful.
Turns Ratio
Note that due to the use of an R
FB
/R
REF
resistor ratio to set
output voltage, the user has relative freedom in selecting
transformer turns ratio to suit a given application. In other
words, “screwball” turns ratios like “1.736:1.0” can scru-
pulously be avoided! In contrast, simpler ratios of small
R
OCOMP
(kΩ)
1
∆I
REF
(%)
2
10 100 1000
1425 F01
1
0
Figure 1
13
LT1425
APPLICATIONS INFORMATION
WUU U
degrades load regulation (at least before load compensa-
tion is employed).
Bifilar Winding
A bifilar or similar winding technique is a good way to
minimize troublesome leakage inductances. However,
remember that this will increase primary-to-secondary
capacitance and limit the primary-to-secondary break-
down voltage, so bifilar winding is not always practical.
Finally, the LTC Applications group is available to assist
in the choice and/or design of the transformer. Happy
Winding!
OUTPUT VOLTAGE ERROR SOURCES
Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error—the internal or external resistor divider
network that connects to V
OUT
and the internal IC refer-
ence. The LT1425, which senses the output voltage in both
a dynamic and an isolated manner, exhibits additional
potential error sources to contend with. Some of these
errors are proportional to output voltage, others are fixed
in an absolute millivolt sense. Here is a list of possible
error sources and their effective contribution:
Internal Voltage Reference
The internal bandgap voltage reference is, of course,
imperfect. Its error, both at 25°C and over temperature is
already included in the specifications for Reference
Current.
User Programming Resistors
Output voltage is controlled by the ratio of R
FB
to R
REF
.
Both are user supplied external resistors. To the extent
that the resistor ratio differs from the ideal value, the
output voltage will be proportionally affected.
Schottky Diode Drop
The LT1425 senses the output voltage from the trans-
former primary side during the flyback portion of the cycle.
This sensed voltage therefore includes the forward drop,
V
F
, of the rectifier (usually a Schottky diode). The nominal
signal! It then reverts to a potentially stable state whereby
the top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This will typically reduce the output volt-
age abruptly to a fraction, perhaps between one-third to
two-thirds of its correct value. If load current is reduced
sufficiently, the system will snap back to normal opera-
tion. When using transformers with considerable leakage
inductance, it is important to exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This will usually be
evident by simultaneously monitoring the V
SW
waveform
on an oscilloscope to observe leakage spike behavior
firsthand. A final note, the susceptibility of the system to
bistable behavior is somewhat a function of the load I/V
characteristics. A load with resistive, i.e., I = V/R behavior
is the most susceptible to bistability. Loads which exhibit
“CMOSsy”, i.e., I = V
2
/R behavior are less susceptible.
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the second-
ary in particular exhibits an additional phenomenon. It
forms an inductive divider on the transformer secondary,
that reduces the size of the primary-referred flyback pulse
used for feedback. This will increase the output voltage
target by a similar percentage. Note that unlike leakage
spike
behavior, this phenomenon is load independent. To
the extent that the secondary leakage inductance is a
constant percentage of mutual inductance (over manufac-
turing variations), this can be accommodated by adjusting
the R
FB
/R
REF
resistor ratio.
Winding Resistance Effects
Resistance in either the primary or secondary will act to
reduce overall efficiency (P
OUT
/P
IN
). Resistance in the
secondary increases effective output impedance which
14
LT1425
APPLICATIONS INFORMATION
WUU U
“collapse,” thereby supporting operation well into discon-
tinuous mode. Nevertheless, there still remain constraints
to ultimate low load operation. They relate to the minimum
switch ON time and the minimum enable time. Discontinu-
ous mode operation will be assumed in the following
theoretical derivations.
As outlined in the Operation section, the LT1425 utilizes a
minimum output switch ON time, t
ON
. This value can be
combined with expected V
IN
and switching frequency to
yield an expression for minimum delivered power.
1
2
)
)
f
L
PRI
)
)
Min Power = (V
IN
• t
ON
)
2
= (V
OUT
)(I
OUT
)
This expression then yields a minimum output current
constraint:
1
2
)
)
f
(L
PRI
)(V
OUT
)
)
)
I
OUT(MIN)
=
where,
f = Switching frequency (nominally 285kHz)
L
PRI
= Transformer primary side inductance
V
IN
= Input voltage
V
OUT
= Output voltage
t
ON
= Output switch minimum ON time
(V
IN
• t
ON
)
2
An additional constraint has to do with the minimum
enable time. The LT1425 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, t
ED
, plus the
minimum enable time, t
EN
. Minimum power delivered to
the load is then:
1
2
)
)
f
L
SEC
)
)
Min Power = [V
OUT
• (t
EN
+ t
ED
)]
2
= (V
OUT
)(I
OUT
)
which yields a minimum output constraint:
V
F
of this diode should therefore be included in R
FB
calculations. Lot-to-lot and ambient temperature varia-
tions will show up as output voltage shift/drift.
Secondary Leakage Inductance
Leakage inductance on the transformer secondary
reduces the effective primary-to-secondary turns ratio
(N
P
/N
S
) from its ideal value. This will increase the output
voltage target by a similar percentage. To the extent that
secondary leakage inductance is constant from part-to-
part, this can be accommodated by adjusting the R
FB
to
R
REF
resistor ratio.
Output Impedance Error
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the R
FB
value adjusted for nominal expected error. In
more demanding applications, output impedance error
may be minimized by the use of the load compensation
function (see Load Compensation).
V
IN
Sense Error
The LT1425 determines the size of the flyback pulse by
comparing the V
SW
signal to V
IN
, through R
FB
. This
comparison is not perfect, in the sense that an offset exists
between the sensing mechanism and the actual V
IN
. This
is expressed in the data sheet as V
IN
sense error. This error
is fixed in absolute millivolt terms relative to V
OUT
(with the
exception that it is reflected to V
OUT
by any nonunity
secondary-to-primary turns ratio).
MINIMUM LOAD CONSIDERATIONS
The LT1425 generally provides better low load perfor-
mance than previous generation switcher/controllers
utilizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
15
LT1425
APPLICATIONS INFORMATION
WUU U
minimum switch ON time, irrespective of current trip
point. If the duty cycle exhibited by this minimum ON time
is greater than the ratio of secondary winding voltage
(referred-to-primary) divided by input voltage, then peak
current will not be controlled at the nominal value, and will
cycle-by-cycle ratchet up to some higher level. Expressed
mathematically, the requirement to maintain short-circuit
control is:
V
F
+ (I
SC
)(R
SEC
)
(V
IN
)(N
SP
)
)
)
(t
ON
)(f) <
where,
t
ON
= Output switch minimum ON time
f = Switching frequency
I
SC
= Short-circuit output current
V
F
= Output diode forward voltage at I
SC
R
SEC
= Resistance of transformer secondary
V
IN
= Input voltage
N
SP
= Secondary-to-primary turns ratio
(N
SEC
/N
PRI
)
Trouble will typically only be encountered in applications
with a relatively high product of input voltage times
secondary-to-primary turns ratio. Additionally, several
real world effects such as transformer leakage inductance,
AC winding losses and output switch voltage drop com-
bine to make this simple theoretical calculation a conser-
vative estimate. In cases where short-circuit protection is
mandatory and this theoretical calculation indicates cause
for concern, the prototype should be observed directly as
follows: short the output while observing the V
SW
signal
with an oscilloscope. The measured output switch ON
time can then be compared against the specifications for
minimum t
ON
.
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The narrow 16-pin package is rated
at 75°C/W.
1
2
)
)
f(V
OUT
)
L
SEC
)
)
I
OUT(MIN)
=
where,
f = Switching frequency (nominally 285kHz)
L
SEC
= Transformer secondary side inductance
V
OUT
= Output voltage
t
ED
= Enable delay time
t
EN
= Minimum enable time
(t
ED
+ t
EN
)
2
Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica-
tion will be either “output switch minimum ON time”
constrained, or “minimum flyback pulse time” constrained.
(A final note—L
PRI
and L
SEC
refer to transformer induc-
tance as seen from the primary or secondary side respec-
tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
The LT1425 is a current mode controller. It uses the V
C
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V
C
node, nominally 1.9V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit, which is
somewhat duty cycle dependent due to internal slope
compensation action.
Short-circuit conditions are handled by the same mecha-
nism. The output switch turns on, peak current is quickly
reached and the switch is turned off. Because the output
switch is only on for a small fraction of the available period,
internal power dissipation is controlled. (The LT1425
contains an internal overtemperature shutdown circuit,
that disables switch action, just in case.)
While the majority of users will not experience a problem,
there is however, a possibility of loss of current limit under
certain conditions. Remember that the LT1425 exhibits a
16
LT1425
APPLICATIONS INFORMATION
WUU U
Average supply current (including driver current) is:
ISW
35
)
)
IIN = 7mA + DC
where,
ISW = Switch current
DC = On switch duty cycle
Switch power dissipation is given by:
P
SW
= (I
SW
)
2
(R
SW
)(DC)
R
SW
= Output switch ON resistance
Total power dissipation of the die is the sum of supply
current times supply voltage plus switch power:
P
D(TOTAL)
= (I
IN
• V
IN
) + P
SW
FREQUENCY COMPENSATION
Loop frequency compensation is performed by connect-
ing a capacitor from the output of the error amplifier (V
C
pin) to ground. An additional series resistor, often
required in traditional current mode switcher controllers
is usually not required, and can even prove detrimental.
The phase margin improvement traditionally offered by
this extra resistor will usually be already accomplished by
the nonzero secondary circuit impedance, which adds a
“zero” to the loop response.
In further contrast to traditional current mode switchers,
V
C
pin ripple is generally not an issue with the LT1425. The
dynamic nature of the clamped feedback amplifier forms
an effective track/hold type response, whereby the V
C
voltage changes during the flyback pulse, but is then
“held” during the subsequent “switch ON” portion of the
next cycle. This action naturally holds the V
C
voltage stable
during the current comparator sense action (current mode
switching).
PCB LAYOUT CONSIDERATIONS
For maximum efficiency, switch rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power paths (primary
and
secondary). B field (magnetic)
radiation is minimized by keeping output diode, switch pin
and output bypass capacitor leads as short as possible. E
field radiation is kept low by minimizing the length and
area of all traces connected to the switch pin. A ground
plane should always be used under the switcher circuitry
to prevent interplane coupling.
The high speed switching current paths are shown sche-
matically in Figure 2. Minimum lead length in these paths
are essential to ensure clean switching and minimal EMI.
The path containing the input capacitor, transformer pri-
mary, output switch, the path containing the transformer
secondary, output diode and output capacitor are the only
ones containing nanosecond rise and fall times. Keep
these paths as short as possible.
HIGH
FREQUENCY
CIRCULATING
PATH
•
•
V
OUT
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
ISOLATED
LOAD
1425 F02
F
Figure 2
17
LT1425
TYPICAL APPLICATIONS
U
The following are several application examples of the
LT1425. The first shows an isolated LAN supply which
provides –9V with ±1% load regulation for output cur-
rents of 0mA to 250mA. An alternate transformer, the
Coiltronics part, provides a complete PCMCIA Type II
height solution. The LT1425 offers excellent load regula-
tion and fast dynamic response not found in similar
isolated flyback schemes.
The next example shows a ±15V supply with 1.5kV of
isolation. The sum of line/load/cross regulation is better
than ±3%. Full load efficiency is between 72% (V
IN
= 5V)
and 80% (V
IN
= 15V). The isolation is ultimately limited
only by bobbin selection and transformer construction.
The “–48V to 5V Isolated Telecom Supply” uses an
external cascoded 200V MOSFET to extend the LT1425’s
35V maximum switch voltage limit. The input voltage
range (–36V to –72V) also exceeds the LT1425’s 20V
maximum input voltage, so a bootstrap winding is used.
D1, D2, Q2 and Q3 and associated components for the
necessary start-up circuitry with hysteresis. When C1
charges to 15V, switching begins and the bootstrap wind-
ing begins to supply power before C1 has a chance to
discharge to 11V. Feedback voltage is fed directly through
a resistor divider to the R
REF
pin. The load compensation
circuitry is bypassed, resulting in ±5% load regulation.
Finally, the “12V to 5V Isolated Converter” is similar to the
previous example in that a cascoded MOSFET is used to
prevent voltage breakdown of the output switch. But
because the nominal 12V input is well within the range of
the V
IN
pin, no bootstrap winding is required and normal
load compensation function is provided. Diode D1, tran-
sistor Q1 and associated components provide an under-
voltage lockout function via the SHDN pin. The off-the-
shelf transformer provides up to 5W of isolated regulated
power.
–9V Isolated LAN Supply
Transformer T1
LPRI RATIO ISOLATION (L × W × H) I
OUT
EFFICIENCY D1 D2 R1, R2 C5, C6 R3
DALE
LPE-4841-A307 36µH 1:1:1 500VAC 10.7 × 11.5 × 6.3mm 250mA 76% NOT USED NOT USED 47Ω330pF 13.3k
COILTRONICS
CTX02-13483 27µH 1:1 500VAC 14 × 14 × 2.2mm 200mA 70% 1N5248 MBR0540TL1 75Ω220pF 5.9k
1424/25 TA03
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
NC
R
FB
V
C
R
REF
SYNC
SGND
GND
3.01k
1%
R3
R1
R2
2
4
1
3
7
MBRS130LT3
T1
6
22.1k
1%
0.1µF
LT1425
47pF
C5
C6
C3
10µF
25V
C4
10µF
25V
1.8k
OUT
COM
–9V
1000pF
C1
10µF
25V
5V
INPUT
COM
C2
10µF
25V
0.1µF
100k
GND
SHDN
R
OCOMP
R
CCOMP
V
IN
V
SW
PGND
GND
C1, C2, C3, C4 = MARCON THCS50E1E106Z CERAMIC
CAPACITOR, SIZE 1812. (847) 696-2000
D1
D2
18
LT1425
TYPICAL APPLICATIONS
U
±15V Isolated Power Supply
+
+
+
1425 TA04
LT1425
MBRS1100T3
MBRS1100T3
45
6
7
T1*
3
2
18
GND
NC
R
FB
V
C
R
REF
SYNC
SGND
GND
GND
SHDN
R
OCOMP
R
CCOMP
PIN 3 TO 4, 7 TURNS BIFILAR 34AWG
*PHILIPS EFD-15-3F3 CORE
GAP FOR PRIMARY
L = 40µH
0.12 INCH MARGIN TAPE
PIN 7 TO 8, 28 TURNS 40AWG
PIN 5 TO 6, 28 TURNS 40AWG
PIN 1 TO 2, 7 TURNS BIFILAR 34AWG
3 LAYERS 2 MIL
POLYESTER FILM
V
IN
V
SW
PGND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
3.01k
1%
1N759
18.4k
0.1%
3k
15V
60mA
–15V
60mA
OUT
COM
7.32k
1%
75Ω
5V TO
15V
INPUT
COM
0.1µF
220pF
1µF
22µF
35V
15µF
35V
3k
15µF
35V
1000pF
0.1µF
130Ω330pF
9
MBR0540LT1
+
++
1425 TA06
BAV21
BAV21
MUR120
LT1425
5k
18Ω
MBR745
10Ω
47
8
T1*
3
2
1
GND
NC
R
FB
V
C
R
REF
SYNC
SGND
GND
GND
SHDN
R
OCOMP
R
CCOMP
V
IN
V
SW
PGND
GND
1
2
3
4
5
6
7
8
16
T1
6
5
15
14
13
12
11
10
3.16k
1%
Q2
2N3906 Q3
2N3904
Q1
IRF620
D1
7.5V
1N755
D2
7.5V
1N755
30.1k
1%
R2
18Ω
R1
24k 50Ω
1W
510Ω
10k
2.4k
100k
INPUT
COM
–36V TO
–72V
3.3µF
150pF
0.1µF
0.1µFC1
27µF
35V
150µF
6.3V
150µF
6.3V
5V
2A
OUT
COM
1000pF
470pF
9
PIN 3 TO 4, 15 TURNS BIFILAR 31AWG
*PHILIPS EFD-15-3F3 CORE
GAP FOR PRIMARY
L = 100µH
PIN 7 TO 8, 6 TURNS QUADFILAR 29AWG
PIN 5 TO 6, 15 TURNS BIFILAR 33AWG
PIN 1 TO 2, 15 TURNS BIFILAR 31AWG
1 LAYER 2 MIL
POLYESTER FILM
2 LAYERS 2 MIL
POLYESTER FILM
–48V to 5V Isolated Telecom Supply
19
LT1425
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.016 – 0.050
0.406 – 1.270
0.010 – 0.020
(0.254 – 0.508)× 45°
0° – 8° TYP
0.008 – 0.010
(0.203 – 0.254)
12345678
0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.386 – 0.394*
(9.804 – 10.008)
0.228 – 0.244
(5.791 – 6.197)
12 11 10 9
S16 0695
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
20
LT1425
1425fa LT/TP 1198 2K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CO RPORATION 1997
TYPICAL APPLICATION
U
12V to 5V Isolated Converter
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1105 Off-Line Switching Regulator Built-In Isolated Regulation Without Optoisolator
LTC®1145/46 Isolated Digital Data Transceivers Up to 200kbps Data Rate, UL Listed
LT1170/71/72 5A/3A/1.25A Flyback Regulators Isolated Flyback Mode for Higher Currents
LT1372/77 500kHz/1MHz Boost/Flyback Regulators Uses Ultrasmall Magnetics
LT1424 Application Specific Isolated Regulator 8-Pin Fixed Voltage Version of LT1425
++
+
220µF
10V
1425 TA05
LT1425
MBRS340T3
2
5
1
4
6
3
10
7
11
8
12
9
GND
NC
R
FB
V
C
R
REF
SYNC
SGND
GND
GND
SHDN
R
OCOMP
R
CCOMP
V
IN
V
SW
PGND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
3.01k
1%
25.5k
1%
9.3k
1%
MMFT1N10E
2.4k
12V
INPUT
COM
0.1µF
22µF
35V 220µF
10V 200Ω
5V
1A
OUT
COM
COILTRONICS
VP1-0190
TURNS RATIO 1 : 1 : 1 : 1 : 1 : 1
12µH PER WINDING
407-241-7876
1000pF
1000pF
MUR120
Q1
2N3906
0.1µF
100Ω
10Ω
1.8k
330pF
9
D1
1N755
7.5V
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
