MAX8563EEE+T - Maxim Integrated - Datasheet.Directory

General Description

The MAX8563/MAX8564/MAX8564A ultra-low-output dual

and triple LDO controllers allow flexible and inexpensive

point-of-load voltage conversion in motherboards,

desknotes, notebooks, and other applications.

These parts feature a 0.5V reference voltage with ±1%

accuracy providing tight regulation of the output volt-

age. The MAX8563 has three n-channel MOSFET con-

troller outputs, and the MAX8564/MAX8564A has two

controller outputs.

Each controller output is adjustable from 0.5V to 3.3V

when VDD = 12V and between 0.5V and 1.8V when VDD

= 5V. Each output is independently enabled and asserts

a POK signal when the output reaches 94% of the set

value. Each output is protected against a soft short-circuit

condition by an undervoltage comparator that disables

the output when it drops to under 80% of the set voltage

for more than 50µs. For a catastrophic short condition, the

regulators are shut down immediately if the output drops

below 60% of the set voltage.

The MAX8563 is available in a 16-pin QSOP

package, and the MAX8564/MAX8564A are available

in a 10-pin µMAX®package.

Applications

Features

♦MAX8563: 3 Outputs

♦MAX8564/MAX8564A: 2 Outputs

♦±1% Feedback Regulation

♦Adjustable Output Voltage Down to 0.5V

♦Can Use Ceramic Output Capacitors

♦Wide Supply Voltage Range Permits Operation

from 5V or 12V Rails

♦Individual Enable Control and POK Signal Allows

Sequencing

♦Overload Protection Against Soft Short-Circuit

Condition

♦Undervoltage Short-Circuit Protection

♦Drive n-Channel MOSFETs

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3290; Rev 2; 6/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-

PACKAGE

PKG

CODE

MAX8563EEE

-40°C to +85°C

16 QSOP E16-1

MAX8564EUB

-40°C to +85°C

10 µMAX U10-2

MAX8564AEUB+ -40°C to +85°C

10 µMAX U10-2

OFF

DRV1

FB1

EN1

POK1

GND

N.C.

DRV3

FB3

VDD

DRV2

FB2

EN2

POK2

N.C.

POK3

EN3

MAX8563

1.8V ±5% IN

C5 R2

OUT1

1.5V/1.5A

POK1

3.3V ±5% IN

OUT3

2.5V/2A*

C10

R4 C6

C2 C3

OUT2

1.05V/3A

POK2

POK3

5V OR 12VIN

1.2V ±5% IN

*2.5V OUTPUT ONLY WITH VDD = 12V

Typical Operating Circuit

Pin Configurations appear at end of data sheet.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

+Denotes lead-free package.

Motherboards

Dual/Triple Power Supplies

Desknotes and Notebooks

Graphic Cards

Ultra-Low-Dropout

Voltage Regulators

Low-Voltage DSP, µP, and

Microcontroller Power

Supplies

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = VEN1 = VEN2 = VEN3 = 5V, VGND = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to GND............................................................-0.3V to +14V

DRV1, DRV2, DRV3, EN1, EN2,

EN3 to GND............................................-0.3V to (VDD + 0.3V)

FB1, FB2, FB3, POK1, POK2, POK3 to GND ...........-0.3V to +6V

Continuous Power Dissipation (TA = +70°C)

10-Pin µMAX (derate 5.6mW/°C above +70°C) ........444.4mW

16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER CONDITIONS

MIN TYP MAX

UNITS

GENERAL

VDD Voltage Range 4.5

13.2

VDD Undervoltage-Lockout Threshold Rising, 200mV hysteresis (typ)

3.56 3.76 4.00

VEN_ = VDD = 12V (MAX8563)

930 1600

VDD Quiescent Current VEN_ = VDD = 12V (MAX8564/MAX8564A)

660 1200

µA

VDD Shutdown Current EN1 = EN2 = EN3 = GND, VDD = 12V 25 µA

LDOs

TA = 0°C to +85°C

0.494

0.5

0.504

FB_ Accuracy TA = -40°C to +85°C

0.489 0.509

TA = +25°C

-100 +100

FB_ Input Bias Current TA = +85°C -8 nA

MAX8563, MAX8564

100

DRV_ Soft-Start Charging Current MAX8564A 10 µA

TA = 0°C to +85°C 4

DRV_ Max Sourcing Current VFB_ = 0.45V TA = -40°C to +85°C 3 7 mA

TA = 0°C to +85°C 3

DRV_ Max Sinking Current VFB_ = 0.6V TA = -40°C to +85°C 1.8 7 mA

VDD = 5V, VFB_ = 0.46V 4.7

DRV_ Max Voltage VDD = 13.2V, VFB_ = 0.46V 8.0

10.9

FB_ Slow Short-Circuit Threshold Measured at FB_ (falling)

400

FB_ Fast Short-Circuit Threshold Measured at FB_ (falling)

300

Slow Short-Circuit Timer 50 µs

FB_ to DRV_ Transconductance

0.115 0.24 0.460

Mho

LOGIC

EN_ Input Low Level 0.7 V

EN_ Input High Level 1.3 V

TA = +25°C -0.1 +0.1

EN_ Input Leakage Current VEN_ = 0 and VDD,

VDD = 13.2V

TA = +85°C 0.001

µA

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD = VEN1 = VEN2 = VEN3 = 5V, VGND = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)

PARAMETER CONDITIONS

MIN

TYP

MAX

UNITS

POK_ Threshold Falling Measured at FB_ (falling)

425 440

455 mV

POK_ Threshold Rising at Startup Measured at FB_ (rising)

455 470

485 mV

POK_ Output Low Level Sinking 1mA, VDD = 4.5V, VFB_ = 0.4V 0.1 V

TA = +25°C

0.1

POK_ Output High Leakage VDD = 5.5V

TA = +85°C 0.001

µA

Note 1: Specifications are production tested at TA= +25°C. Maximum and minimum specifications over temperature are guaranteed by

design.

Typical Operating Characteristics

(Circuit of Figure 1, TA = +25°C.)

OUTPUT VOLTAGE vs. INPUT VOLTAGE

MAX8563 toc01

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

1.91.81.71.61.51.41.31.21.1

1.1

1.2

1.3

1.4

1.5

1.6

1.0

1.0 2.0

VDD = 5V VOUT1

VOUT2

OUTPUT VOLTAGE vs. INPUT VOLTAGE

MAX8563 toc02

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

3.41.4 2.2 2.61.8 3.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

1.0

VDD = 12V VOUT3

VOUT1

VOUT2

OUTPUT VOLTAGE vs. OUTPUT CURRENT

MAX8563 toc03

OUTPUT CURRENT (A)

OUTPUT VOLTAGE (V)

2.52.01.51.00.5

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

1.0

03.0

VDD = 12V

VOUT3

VOUT1

VOUT2

FEEDBACK VOLTAGE

vs. TEMPERATURE

MAX8563 toc04

TEMPERATURE (°C)

FEEDBACK VOLTAGE (V)

603510-15

0.4988

0.4990

0.4992

0.4994

0.4996

0.4998

0.5000

0.4986

-40 85

VDD = 5V

VDD = 12V

PSRR vs. FREQUENCY

MAX8563 toc05

FREQUENCY (Hz)

PSRR (dB)

10k1k

100

100 100k

VOUT1 = 1.5V

VIN1 = 2V

LOAD = 1.25Ω

VDD = 12V

LOAD TRANSIENT

MAX8563 toc06

IOUT2

VDRV2

VIN2

VOUT2 20mV/div

AC-COUPLED

2V/div

200mV/div

AC-COUPLED

2A/div

10μs/div

VDD = 12V

FIGURE 1, C7 = 100μF 6TPE100MI

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

4 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Circuit of Figure 1, TA = +25°C.)

POWER-ON SEQUENCING WITH VDD

MAX8563 toc07

VDD

VPOK1

VIN1

VOUT1 2V/div

2V/div

20V/div

20ms/div

POWER-ON SEQUENCING WITH VIN

MAX8563 toc08

VDD

VPOK1

VOUT1

VIN1 2V/div

2V/div

20V/div

10ms/div

ENABLE CONFIGURED AS

SHOWN IN FIGURE 4

RD = 100kΩ, RE = 4kΩ

ENABLE-ON SEQUENCING

MAX8563 toc09

VIN1

VPOK1

VOUT1

EN1

2V/div

20ms/div

SHORT-CIRCUIT PROTECTION

MAX8563 toc10

IOUT1

VDRV1

VOUT1

5A/div

2V/div

1V/div

20μs/div

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

_______________________________________________________________________________________ 5

VDD

0.5V

POK

COMPARATOR

LDO

CONTROLLER 1

LDO

CONTROLLER 2

LDO

CONTROLLER 3

0.5V

REF

VL UVLO

VDD

EN1

POK1

GND

EN2

POK2

EN3

POK3 FB3

DRV3

DRV2

FB1

FB2

DRV1

MAX8563

MAX8564

MAX8564A

Functional Diagram

Pin Description

NAME

MAX8563

MAX8564/

MAX8564A

FUNCTION

1 DRV1 DRV1

Output n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 1.

DRV1 is internally pulled to ground when EN1 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

2FB1 FB1

Feed b ack Inp ut for Outp ut 1. C onnect to the center of a r esi stor - d i vi d er b etw een outp ut 1 and GN D to

set the outp ut vol tag e of outp ut 1. The feed b ack r eg ul ati on vol tag e i s 0.500V . S ee the Outp ut V ol tag e

S etti ng secti on.

3 EN1 EN1 Enable Control for Output 1. Drive logic high to enable output 1, or logic low to disable the

output. Connect to VDD for always-on operation.

4 POK1 POK1 Output 1 Power-Good Signal. Open-drain output pulls low when output 1 is 12% below the

nominal regulated voltage.

5 GND GND Ground

— POK2 Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the

nominal regulated voltage.

N.C. — No Internal Connection

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

6 _______________________________________________________________________________________

Pin Description (continued)

NAME

MAX8563

MAX8564/

MAX8564A

FUNCTION

— EN2 Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the

output. Connect to VDD for always-on operation.

DRV3 —

O utp ut 3 n- M O S FE T D r i ve. D r i ves the g ate of an exter nal n- channel M O S FE T to r eg ul ate outp ut 3.

DRV3 is internally pulled to ground when EN3 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

— FB2

Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and

GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the

Output Voltage Setting section.

FB3 —

Feedback Input for Output 3. Connect to the center of a resistor-divider between output 3 and

GND to set the output voltage of output 3. The feedback regulation voltage is 0.500V. See the

Output Voltage Setting section.

— DRV2

O utp ut 2 n- M O S FE T D r i ve. D r i ves the g ate of the exter nal n- channel M OS FE T to r eg ul ate outp ut 2.

DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

EN3 — Enable Control for Output 3. Drive logic high to enable output 3, or logic low to disable the

output. Connect to VDD for always-on operation.

—V

DD +5V or +12V Supply Input. Connect to external +5V or +12V supply rail. Bypass with a 0.1µF

ceramic or larger capacitor.

POK3 — Output 3 Power-Good Signal. Open-drain output pulls low when output 3 is 12% below the

nominal regulated voltage.

11 N.C. — No Internal Connection

12 POK2 — Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the

nominal regulated voltage.

13 EN2 — Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the

output. Connect to a VDD for always-on operation.

14 FB2 —

Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and

GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the

Output Voltage Setting section.

15 DRV2 —

O utp ut 2 n- M O S FE T D r i ve. D r i ves the g ate of the exter nal n- channel M OS FE T to r eg ul ate outp ut 2.

DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

16 VDD —+5V or +12V Supply Input. Connect to an external +5V or +12V supply rail. Bypass with a 0.1µF

ceramic or larger capacitor.

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

_______________________________________________________________________________________ 7

Typical Application Circuits

MAX8563: Triple Output

OFF

DRV1

FB1

EN1

POK1

GND

N.C.

DRV3

FB3

VDD

DRV2

FB2

EN2

POK2

N.C.

POK3

EN3

MAX8563

1.8V ±5% IN

C5 R2

OUT1

1.5V/1.5A

POK1

3.3V ±5% IN

OUT3

2.5V/2A*

C10

R4 C6

C2 C3

OUT2

1.05V/3A

POK2

POK3

5V OR 12VIN

1.2V ±5% IN

*2.5V OUTPUT ONLY WITH VDD = 12V

Figure 1. MAX8563 Typical Application Circuit

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

8 _______________________________________________________________________________________

Typical Application Circuits (continued)

MAX8564/MAX8564A: Dual Output

Figure 2. MAX8564/MAX8564A Typical Application Circuit

MAX8563 External Component List

COMPONENTS

QTY

DESCRIPTION

C1, C3, C8

2.2µF, 10V X5R ceramic capacitors

(optional 100µF, 18mΩ, 6.3V

aluminum electrolytic, Sanyo

GTPE100MI in parallel)

0.1µF, 16V X7R ceramic capacitor

C4, C7, C9

100µF, 18mΩ, 6.3V aluminum

electrolytic capacitors

Sanyo GTPE100MI

C5, C6, C10

1µF, 16V X7R ceramic capacitors

Q1/Q2 (dual)

Dual n-channel MOSFETs, 30V, 18mΩ

Vishay Si4922DY

n-channel MOSFET, 30V, 50mΩ

Fairchild Semiconductor FDD6630A

665Ω ±1% resistor

620Ω ±5% resistor

332Ω ±1% resistor

390Ω ±5% resistor

182Ω ±1% resistor

165Ω ±1% resistor

910Ω ±5% resistor

1kΩ ±1% resistor

249Ω ±1% resistor

MAX8564/MAX8564A External

Component List

COMPONENTS

QTY

DESCRIPTION

C11

0.1µF, 16V X7R ceramic capacitor

C12, C14

100µF, 18mΩ, 6.3V aluminum

electrolytic capacitors

Sanyo GTPE100MI

C15, C17

2.2µF, 10V X5R ceramic capacitors

(optional 100µF, 18mΩ, 6.3V

aluminum electrolytic, Sanyo

GTPE100MI in parallel)

C18, C20

1µF, 16V X7R ceramic capacitors

Q4/Q5 (dual)

Dual n-channel MOSFETs, 30V, 18mΩ

Vishay Si4922DY

R13

165Ω ±1% resistor

R14

182Ω ±1% resistor

R15

390Ω ±5% resistor

R16

665Ω ±1% resistor

R17

332Ω ±1% resistor

R18

620Ω ±5% resistor

OFF

DRV1

FB1

EN1

POK1

GND

VDD

DRV2

FB2

EN2

POK2

MAX8564

MAX8564A

1.8V ±5% IN

C15

C20 R18

R16

C14

OUT1

1.5V/1.5A

R17

POK1

R13

R14

R15 C18

C11 C17

C12

OUT2

1.05V/3A

POK2

5V OR 12VIN

1.2V ±5% IN

Detailed Description

The MAX8563/MAX8564/MAX8564A triple and dual

LDO controllers allow flexible and inexpensive voltage

conversion by controlling the gate of an external

n-MOSFET in a source-follower configuration. The

MAX8563/MAX8564/MAX8564A consist of multiple

identical LDO controllers. Each LDO controller features

an enable input (EN_) and a power-OK output (POK_).

The MAX8563/MAX8564/MAX8564A also include a 0.5V

reference, an internal regulator, and an undervoltage

lockout (UVLO). The transconductance amplifier mea-

sures the feedback voltage on FB_ and compares it to

an internal 0.5V reference connected to the positive

input. If the voltage on FB_ is lower than 0.5V, the cur-

rent output on the gate-drive output DRV_ is increased.

If the voltage on FB_ is higher than 0.5V, the current out-

put on the gate-drive output is decreased.

Bias Voltage (VDD), UVLO, and Soft-Start

The MAX8563/MAX8564/MAX8564A bias current

for internal circuitry is supplied by VDD. The VDD voltage

range is from 4.5V to 13.2V. If VDD drops below 3.76V

(typ), the MAX8563/MAX8564/MAX8564A assume that

the supply and reference voltages are too low and acti-

vate the UVLO circuitry. During UVLO, the internal regu-

lator (VL) and the internal bandgap reference are forced

off, DRV_ is pulled to GND, and POK_ is pulled low.

Before any internal startup circuitry is activated, VDD must

be above the UVLO threshold. After UVLO indicates that

VDD is high enough, the internal VL regulator, the internal

bandgap reference, and the bias currents are activated.

If EN_ is logic-high after the internal reference and bias

currents are activated, then the corresponding DRV_ out-

put initiates operation in soft-start mode. Once the voltage

on FB_ reaches 94% of the regulation threshold, the full

output current of the LDO controller is permitted.

When an LDO is activated, the respective DRV_ is pulled

up from GND with a typical soft-start current of DRV soft-

start. The soft-start current limits the slew of the output

voltage and limits the initial spike of current that the drain

of the external n-MOSFET receives. The size of the com-

pensation capacitor (CC) limits the slew rate (see Figure

3). This output voltage slew rate is equal to (DRV_soft-

start /CC)mV/ms, where CCis in µF. The maximum startup

drain current is the ratio of COUT to CCmultiplied by the

soft-start current.

Input Voltage (Drain Voltage of the

External n-MOSFET)

The minimum input voltage to the drain of the n-MOSFET

is a function of the desired output voltage and the

dropout voltage of the n-MOSFET. Details on calculating

this value are covered in the Power MOSFET Selection

section.

The maximum input voltage to the drain of the n-MOSFET

is a function of the breakdown voltage and the thermal

conditions during operation. The breakdown voltage from

drain to source is normally provided in the MOSFET data

sheet. The theoretical maximum input voltage is the set

output voltage plus the breakdown voltage. The thermal

constraint is usually the largest concern when discussing

maximum input voltage. Details on calculating this value

are covered in the Power MOSFET Selection section. The

MOSFET package and thermal relief on the board are

the largest contributors to removing heat from the

n-MOSFET. Since output voltage is normally set and

maximum output current is fixed, the input voltage

becomes the only variable that determines the maxi-

mum power dissipated. Thus, the maximum input volt-

age is limited by the power capability of the n-MOSFET,

if it is less than the breakdown voltage, which is most

often the case. Ensure input capacitors handle the

maximum input voltage.

During a power-up sequence where VDD and EN_ rise

before the input to the drain of the n-MOSFET, the

MAX8563/MAX8564/MAX8564A drive DRV_ high but the

output does not rise. As DRV_ rails and VFB_ is still below

80% of the regulation voltage, the MAX8563/MAX8564/

MAX8564A assume that an output short-circuit fault is

present and shut down that regulator. To avoid this error

condition, connect a resistor-divider from VDD to IN_ with

the middle node connected to the respective EN_ (see

Figure 4). Use the following equations to calculate the

resistor values.

When VIN_ is off or at a low-voltage state:

When VIN_ is on or at a high-voltage state:

07. __

⎛

⎝

⎜⎞

⎠

⎟×

()

+−

RR VV V

ED DD IN IN

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

_______________________________________________________________________________________ 9

DRV_

MAX8563

MAX8564

MAX8564A

VIN_

CCRC

COUT

OUT1

Figure 3. Soft-Start and Compensation Schematic

MAX8563/MAX8564/MAX8564A

Set RD= 100kΩ. The above equations also assume that

VDD > VIN_ > 1V when VIN_ is on or at a high-voltage

state, and that VDD > 3V.

Example: Connect 100kΩfrom EN to VDD and 4kΩfrom

EN_ to IN_. Thus, when VDD = 12V and VIN_ = 0V, then

VEN_ = 0.46V. When VDD = 12V and VIN_ = 1.2V, then

VEN_ = 1.6V.

Alternately, to avoid fault shutdown due to the delay of

VIN relative to VDD, pull EN_ low with a separate control

logic and only drive high when VIN reaches a steady-

state value.

Output Voltage

The output voltage range at the source of the n-MOSFET

is from 0.5V to 3.3V when VDD is 12V and from 0.5V to

1.8V when VDD is 5V. The maximum output voltage is a

function of the minimum gate-to-source voltage (VGS) of

the MOSFET and VDD.

The external n-MOSFET contains a parasitic diode from

source to drain. If the output is ever anticipated to

exceed the input, current flows from source to drain. If

this is undesirable, external protection is needed. A

simple solution is the placement of a diode in series,

from IN_ to the drain of the n-MOSFET, so that reverse

current is not possible. Due to the forward-voltage drop

of the diode, the maximum output voltage is reduced

and additional power is consumed in the diode.

Enable and POK

The MAX8563/MAX8564/MAX8564A have independent

enable control inputs (EN1, EN2, and EN3). Drive EN1

high to enable output 1. Drive EN2 high to enable out-

put 2. Drive EN3 high to enable output 3. When EN_ is

driven low, the corresponding DRV_ is internally pulled

to GND and POK_ is internally pulled low.

The POK_ is an open-drain output that provides the sta-

tus of the output voltage and pulls low depending upon

circuit conditions. During startup, once the FB_ reaches

the POK_ threshold, the POK_ signal goes high. The

POK_ threshold has 30mV of hysteresis. When the out-

put voltage drops 12% below the nominal regulated

voltage, POK_ pulls low. All POK_ outputs pull low

when UVLO is activated or when the internal VL regula-

tor and reference are not ready.

Output Undervoltage and

Overload Protection

When an overload event or short circuit occurs, the

device that is most vulnerable is the external n-MOSFET.

The MAX8563/MAX8564/MAX8564A monitor the output

voltage to protect the MOSFET. When DRV_ is at its maxi-

mum voltage and the output voltage drops below 80%

but is still greater than 60% of its nominal voltage for

more than 50µs, the MAX8563/MAX8564/MAX8564A

shut down that particular regulator output by pulling

DRV_ to GND. Note that there is an additional inherent

delay in turning off the MOSFET. The delay is a function

of the compensation capacitor and the MOSFET. If the

output recovers to greater than 80% within 50µs, it is not

considered to be in overload and no action is taken.

When the output voltage drops below 60% of its nominal

voltage, the MAX8563/MAX8564/MAX8564A immediately

shut down that particular regulator output by pulling

DRV_ to GND. To restart that particular LDO, VDD must

be recycled below the UVLO or the corresponding EN_

must be recycled. The overload protection is shown in

the Typical Operating Characteristics.

Design Procedure

Output Voltage Setting

The minimum output voltage for each controller of the

MAX8563/MAX8564/MAX8564A is typically 0.5V. The

maximum output voltage is adjustable up to 3.3V with

VDD = 12V, and up to 1.8V with VDD = 5V. To set the out-

put voltage, connect the FB_ pin to the center of a volt-

age-divider between OUT_ and GND (Figure 5). The

resistor-divider current should be at least 1mA per 1A of

maximum output current; i.e., for a 3A maximum output

current, set the resistor-divider bias current to ≥3mA:

BFB

OUT MIN

OUT MAX OUT MAX

() () ()

≤=× =1000 500

OUT MIN

OUT MAX

()

≥1000

13. __

⎛

⎝

⎜⎞

⎠

⎟×

()

+−

RR VV V

ED DD IN IN

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

10 ______________________________________________________________________________________

MAX8563

MAX8564

MAX8564A

EN_

VDD

IN_

Figure 4. Voltage-Divider on EN_

To set the output voltage to 0.5V, disconnect RBfrom

FB_ and connect it to OUT_; this change maintains the

minimum load requirement on the output. In this case,

RAcan vary from 1kΩto 10kΩ.

Input and Output Capacitor Selection

The input filter capacitor aids in providing low input

impedance to the regulator and also reduces peak cur-

rents drawn from the power source during transient

conditions. Use a minimum 2.2µF ceramic capacitor

from IN_ (drain of the external pass n-MOSFET) to GND

(see Figures 1 and 2). If large line transients or load

transients are expected, increase the input capaci-

tance to help minimize output voltage changes.

The output filter capacitor and its equivalent series

resistance (ESR) contribute to the stability of the regula-

tor (see the Stability Compensation section) and affect

the load-transient response. If large step loads (no load

to full load) are expected, and a very fast response

(less than a few microseconds) is required, use a

100µF, 18mΩPOSCAP for the output capacitor. If a

larger capacitance is desired, keep the capacitance

ESR product (COUT x RESR) in the 1µs to 5µs range.

If the application expects smaller load steps (less than

50% of full load), then use a 6.8µF ceramic capacitor or

larger per ampere of maximum output current. This

option reduces the size and cost of the regulator circuit.

Note that some ceramic dielectrics exhibit large capaci-

tance variation with temperature. Use X7R or X5R

dielectrics to ensure sufficient capacitance at all operat-

ing temperatures. Tantalum and aluminum capacitors

are not recommended.

Power MOSFET Selection

The MAX8563/MAX8564/MAX8564A use an n-channel

MOSFET as the series pass transistor instead of a p-

channel MOSFET to reduce cost. The selected MOS-

FET must have a gate threshold voltage that meets the

following criteria:

VGS_MAX ≤VDD - VOUT_

where VDD is the controller bias voltage, and VGS_MAX

is the maximum gate voltage required to yield the on-

resistance (RDS_ON) specified by the manufacturer’s

data sheet. RDS_ON multiplied by the maximum output

current (load current) is the maximum voltage dropout

across the MOSFET, VDS_MIN. Make sure that VDS_MIN

meets the condition below to avoid entering dropout,

where output voltage starts to decrease and any ripple

on the input also passes through to the output:

VIN_MIN > VDS_MIN + VOUT

where VIN_MIN is the minimum input voltage at the drain

of the MOSFET. VDS_MIN has a positive temperature

coefficient; therefore, the value of VDS_MIN at the highest

operating junction temperature should be used.

For thermal management, the maximum power dissipa-

tion in the MOSFET is calculated by:

PD= (VIN_MAX - VOUT) x IOUT_MAX

The MOSFET is typically in an SMT package. Refer to

the MOSFET data sheet for the PC board area needed

to meet the maximum operating junction temperature

required.

Stability Compensation

Connect a resistor, RC, and a capacitor, CC, in series

from the DRV_ pin to GND. The values of the compen-

sation network depend upon the external MOSFET

characteristics, the output current range, and the pro-

grammed output voltage. The following parameters are

needed from the MOSFET data sheet: the input capaci-

tance (CISS at VDS = 1V), the typical forward transcon-

ductance (gFS), and the current at which gFS was

measured (IDFS). Calculate the transconductance of

the FET at the maximum load current (IOUT_MAX):

C MAX FS OUT MAX

DFS

() _

=×

RR V

VRV

AB OUT

FB B OUT

=×

⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

⎥=××

()

−−12 1

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

______________________________________________________________________________________ 11

MAX8563

MAX8564

MAX8564A

FB_

OUT_

Figure 5. Adjustable Output Voltage

MAX8563/MAX8564/MAX8564A

For the best transient response in applications with

large step loads (see the Input and Output Capacitor

Selection section for output capacitance requirements),

use the following equations to select the compensation

components:

where COUT is the output capacitance and RESR is the

ESR of COUT.

To use a low-cost ceramic capacitor (see the Input and

Output Capacitor Selection section for load-transient

response characteristics), use the following equations

to select the compensation components:

Example

OUTPUT 1 of Figure 1 is used in this example. Table 1

shows the values required to calculate the compensa-

tion. The values were taken from the appropriate data

sheets and Figure 1.

PC Board Layout Guidelines

Due to the high-current paths and tight output accuracy

required by most applications, careful PC board layout is

required. An evaluation kit (MAX8563EVKIT) is available

to speed design.

It is important to keep all traces as short as possible to

maximize the high-current trace dimensions to reduce the

effect of undesirable parasitic inductance. The MOSFET

dissipates a fair amount of heat due to the high currents

involved, especially during large input-to-output voltage

differences. To dissipate the heat generated by the

MOSFET, make power traces very wide with a large

amount of copper area. An efficient way to achieve good

power dissipation on a surface-mount package is to lay

out copper areas directly under the MOSFET package on

multiple layers and connect the areas through vias. Use a

ground plane to minimize impedance and inductance. In

addition to the usual high-power considerations, here are

four tips to ensure high output accuracy:

• Ensure that the feedback connection to COUT_ is

short and direct.

• Place the feedback resistors next to the FB pin.

• Place RCand CCnext to the DRV_ pin.

• Ensure FB_ and DRV_ traces are away from noisy

sources to ensure tight accuracy.

gSx

Vx Fx Sx Sx

Sx V A

pF F use F

C MAX

()

. . .

., .

⎛

⎝

⎜⎞

⎠

⎟

()

−

30 15

88 12 4

016

1 5 100 12 4 12 4

18 1

12 4 1 5 1 5

2500 0 90 1

μμ

RRx

Vx Fx Sx m

FSxV A

use

C . .

. . .

. , .

()

59 1 5 100 12 4 18 1

1 124 15 15

599 4 620

ΩΩ

CCxg

gxVI C

Cxg

COUT C MAX

C MAX OUT OUT MAX

ISS

COUT

C C MAX

()

() _

()

−

ggR

gVI

RVxCg xR

Cxg V I

OUT OUT

C MAX C MAX ESR

C MAX OUT OUT MAX

ISS

OUT OUT C MAX ESR

C C MAX OUT OUT

() ()

() _

()

() _

×× ×

××+

()

⎡

⎣

⎢

⎤

⎦

⎥

×+

()

=× +

()

×+

−

016

59 1

MAXMAX

()

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

12 ______________________________________________________________________________________

Table 1. Parameters Required to

Calculate Compensation

PARAMETER

CONDITIONS

VALUE UNITS

MOSFET CISS

VDS = 1V 2500 pF

MOSFET GFS

IDFS = 8.8A

30 S

VOUT1 Figure 1 1.5 V

IOUT_MAX Figure 1 1.5 A

COUT1 Figure 1 100 µF

RESR Figure 1 18 mΩ

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

______________________________________________________________________________________ 13

DRV1 VDD

DRV2

FB2

EN2

POK2

N.C.

POK3

EN3

TOP VIEW

MAX8563

QSOP

FB1

EN1

N.C.

POK1

GND

DRV3

FB3

VDD

DRV2

FB2

EN2POK1

EN1

FB1

DRV1

MAX8564

MAX8564A

μMAX

POK2GND

Pin Configurations

Chip Information

TRANSISTOR COUNT: 1801

PROCESS: BiCMOS

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

14 ______________________________________________________________________________________

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

QSOP.EPS

21-0055

PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH

MAX8563/MAX8564/MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

10LUMAX.EPS

PACKAGE OUTLINE, 10L uMAX/uSOP

21-0061

REV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

TOP VIEW

FRONT VIEW

0.498 REF

0.0196 REF

6°

SIDE VIEW

BOTTOM VIEW

0° 0° 6°

0.037 REF

0.0078

MAX

0.006

0.043

0.118

0.120

0.199

0.0275

0.118

0.0106

0.120

0.0197 BSC

INCHES

0.0035

0.007

0.187

0.0157

0.114

DIM

0.116

0.114

0.116

0.002

MIN

-A

0.940 REF

0.500 BSC

0.090

0.177

4.75

2.89

0.40

0.200

0.270

5.05

0.70

3.00

MILLIMETERS

0.05

2.89

2.95

MIN

3.00

3.05

0.15

3.05

MAX

1.10

0.6±0.1

Ø0.50±0.1

4X S

A2 A

E1 L

GAGE PLANE

A2 0.030 0.037 0.75 0.95

Revision History

Pages changes at Rev 2: 1, 12, 14, 15