L5991
L5991A
PRI MARY CO NTR OLL ER WITH STAN DBY
CURRENT-M ODE CONT ROL PWM
SWITCHING FRE QU ENCY UP TO 1MHz
LOW STA RT-UP CURREN T (< 120µA)
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FO R PO W ER MO SF ET (1 A )
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
PROGR AMMA BLE DUT Y CYCLE
100% A ND 50% MAX IMUM DUTY C YCLE LI MIT
STANDBY FUNCTION
PROGR AMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PW M U V LO W I T H HYST ERES I S
IN/OUT SYNCHRONIZA TION
LATCHED DISA B LE
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE : DIP16 AND SO16
DESCRIPTION
This primary controller I.C., developed in BCD60II
technology, has been designed to implement off
line or DC-DC power supply applications using a
fixed frequency current mode control.
Based on a standard current mode PWM control-
ler this device includes some features such as
programmable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection and
for power management), precise maximum Duty
Cycle Control, 100ns leading edge blanking on
current sense, pulse by pulse current limit, over-
current protection with soft start intervention, and
Standby function for oscillator frequency reduction
when the converter is lightly loaded.
August 2001
®
+
-
+
-
TIMING
2
3
+
-
14
T
Vref
CLK
2.5V
+
-
1.2V
13
BLANKING
PWM
FAULT
SOFT-START
R
SQ
25V
15V/10V
VREF OK
DIS
+
-
E/A
1V R 2R
DIS
2.5V
7
6
5
11
10
9
48151
13V
PWM UVLO
12
SGND COMP
SS
ISEN
DIS
DC
RCT
SYNC DC-LIM V
CC
VREF
D97IN725A
VFB
PGND
OUT
V
C
OVER CURRENT
STAND-BY ST-BY
VREF
16
BLOCK DIAG RAM
ORDERING NUMBERS: L5991/L5991A (DIP16)
L5991D/L5991AD (SO16)
MULTIPOWER BCD TECHNOLOGY
DIP16 SO16
1/23
ABSOLUTE MAXIMU M RATINGS
Symbol Parameter Value Unit
VCC Supply Voltage (ICC < 50mA) (*) selflimit V
IOUT Output Peak Pulse Current 1.5 A
Analog Inputs & Outputs (6,7) -0.3 to 8 V
Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16) -0.3 to 6 V
Ptot Power Dissipation @ Tamb = 70°C (DIP16)
@ Tamb = 50°C (SO16) 1
0.83 W
W
TjJunction Temperature, Operating Range -40 to 150 °C
Tstg Storage Temperature, Operating Range -55 to 150 °C
(*) maximum package power dissipation limits must be observed
THERMAL DATA
Symbol Parameter Value Unit
Rth j-amb Thermal Resistance Junction -Ambient (DIP16) 80 °C/W
Thermal Resistance Junction -Ambient (SO16) 120 °C/W
P I N FU NCTI ON S
N. Name Function
1 SYNC Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct
2 RCT Oscillator pin for external CT, RA, RB components
3 DC Duty Cycle control
4 VREF 5.0V +/-1.5% reference voltage @ 25°C
5 VFB Error Amplifier Inverting input
6 COMP Error Amplifier Output
7 SS Soft start pin for external capacitor Css
8V
CC Supply for internal "Signal" circuitry
9V
CSupply for Power section
10 OUT High current totem pole output
11 PGND Power ground
12 SGND Signal ground
13 ISEN Current sense
14 DIS Disable. It must never be left floating. TIE to SGND if not used.
15 DC-LIM Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is
imposed
16 ST-BY Standby. Connect a resistor to RCT. Connect to VREF or floating if not used.
SYNC
RCT
DC
VREF
VFB
SS
COMP
1
3
2
4
5
6
7OUT
SGND
PGND
ISEN
DIS
DC-LIM
ST-BY16
15
14
13
12
10
11
VCC 8V
C
9
PIN CO NNEC TION
L5991 - L5991A
2/23
ELECTRI CAL CHARACTERI STICS (VCC = 15V; Tj = 0 to 105°C; RT = 13.3kΩ (*) CT = 1nF;
unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
REFERENCE SECTION
VREF Output Voltage Tj = 25°C; IO = 1mA 4.925 5.0 5.075 V
Line Regulation VCC = 12 to 20V; Tj = 25°C 2.0 10 mV
Load Regulation IO = 1 to 10mA; Tj = 25°C 2.0 10 mV
TSTemperature Stability 0.4 mV/°C
Total Variation Line, Load, Temperature 4.80 5.0 5.130 V
IOS Short Circuit Current Vref = 0V 30 150 mA
Power Down/UVLO VCC = 6V; Isink = 0.5mA 0.2 0.5 V
OSCILLATOR SECTION
Initial Accuracy pin 15 = Vref; Tj = 25°C; Vcomp = 4.5V 95 100 105 kHz
pin 15 = Vref; VCC = 12 to 20V
Vcomp = 4.5V 93 100 107 kHz
pin 15 = Vref; VCC = 12 to 20V
Vcomp = 2V 46.5 50 53.5 kHz
Duty Cycle pin 3 = 0,7V, pin 15 = VREF
pin 3 = 0.7V, pin 15 = OPEN 0
0%
%
pin 3 = 3.2V, pin 15 = VREF
pin 3 = 3.2V, pin 15 = OPEN 47
93 %
%
Duty Cycle Accuracy pin 3 = 2.79V, pin 15 = OPEN 75 80 85 %
Oscillator Ramp Peak 2.8 3.0 3.2 V
Oscillator Ramp Valley 0.75 0.9 1.05 V
ERROR AMPLIFIER SECTION
Input Bias Current VFB to GND 0.2 3.0 µA
VIInput Voltage VCOMP = VFB 2.42 2.5 2.58 V
GOPL Open Loop Gain VCOMP = 2 to 4V 60 90 dB
SVR Supply Voltage Rejection VCC = 12 to 20V 85 dB
VOL Output Low Voltage Isink = 2mA 1.1 V
VOH Output High Voltage Isource = 0.5mA, VFB = 2.3V 5 6 V
IOOutput Source Current VCOMP > 4V, VFB = 2.3V 0.5 1.3 2.5 mA
Output Sink Current VCOMP = 1.1V, VFB = 2.7V 2 6 mA
Unit Gain Bandwidth 1.7 4 MHz
SRSlew Rate 8 V/µs
PWM CURRENT SENSE SECTION
IbInput Bias Current Isen = 0 3 15 µA
ISMaximum Input Signal VCOMP = 5V 0.92 1.0 1.08 V
Delay to Output 70 100 ns
Gain 2.85 3 3.15 V/V
VtFault Threshold Voltage 1.1 1.2 1.3 V
SOFT START SECTION
ISSC SS Charge Current Tj = 25°C 142026µA
I
SSD SS Discharge Current VSS = 0.6V Tj = 25°C 5 10 15 µA
VSSSAT SS Saturation Voltage DC = 0% 0.6 V
VSSCLAMP SS Clamp Voltage 7 V
LEADING EDGE BLANKING
Internal Masking Time 100 ns
OUTPUT SECTION
VOL Output Low Voltage IO = 250mA 1.0 V
VOH Output High Voltage IO = 20mA; VCC = 12V 10 10.5 V
IO = 200mA; VCC = 12V 9 10 V
VOUT CLAMP Output Clamp Voltage IO = 5mA; VCC = 20V 13 V
Collector Leakage VCC = 20V VC = 24V 2 20 µA
(*) RT = RA//RB, RA = RB = 27kΩ, see Fig. 23.
L5991 - L5991A
3/23
6
8
20
30
V14 = 0, Pin2 = open
Tj = 25°C
04 812 16 20 24
0
0.05
0.1
0.15
0.2
4
Vcc [V]
Iq [mA ]
28
XY
Figure 1. L5991 - Quiescent current vs. input
voltage.
(X = 7.6V and Y= 8.4V for L5991A)
0 4 8 12 16 20 24
0
50
100
150
200
250
300
350
Vcc [V]
Iq [µ A]
V14 = Vref
Tj = 25 °C
XY
Figure 2. L5991 - Quiescent current vs. input
voltage (after disab le).
(X = 7.6V and Y= 8.4V for L5991A)
ELECTRI CAL CHARACTERI STICS (continued.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
OUTPUT SECTION
Fall Time CO = 1nF
CO = 2.5nF 20
35 60 ns
ns
Rise Time CO = 1nF
CO = 2.5nF 50
70 100 ns
ns
UVLO Saturation VCC = VC = 0 to VCCON; Isink = 10mA 1.0 V
SUPPLY SECTION
VCCON Startup voltage L5991
L5991A 14
7.8 15
8.4 16
9V
V
VCCOFF Minimum Operating
Voltage L5991
L5991A 9
710
7.6 11
8.2 V
V
Vhys UVLO Hysteresis L5991
L5991A 4.5
0.5 5
0.8 V
V
ISStart Up Current Before Turn-on at:
VCC = VC = VCCON -0.5V 40 75 120 µA
Iop Operating Current CT = 1nF, RT = 13.3kΩ, CO =1nF 9 13 mA
IqQuiescent Current (After turn on), CT = 1nF,
RT = 13.3kΩ, CO =0nF 7.0 10 mA
VZZener Voltage I8 = 20mA 21 25 30 V
STANDBY FUNCTION
VREF-VST-BY IST-BY = 2mA 45 mV
VT1 Standby Threshold Vcomp Falling 2.5 V
Vcomp Rising 4.0 V
SYNCHRONIZATION SECTION Master Operation
V1Clock Amplitude ISOURCE = 0.8mA 4 V
I1Clock Source Current Vclock = 3.5V 3 7 mA
Slave Operation
V1Sync Pulse Low Level 1 V
High Level 3.5 V
I1Sync Pulse Current VSYNC = 3.5V 0.5 mA
OVER CURRENT PROTECTION
VtFault Threshold Voltage 1.1 1.2 1.3 V
DISABLE SECTION
Shutdown threshold 2.4 2.5 2.6 V
Input Bias Current Vpin14 = 0 to 3V -1 1 µA
IqSH Quiescent current After
Disable VCC = 15V 330 µA
L5991 - L5991A
4/23
8 1012141618202224
7.0
7.5
8.0
8.5
9.0
V c c [V ]
Iq [mA ]
V 14 = 0, V5 = V ref
R t = 4.5Kohm ,Tj = 25°C
500Khz
300Khz
1Mhz
100Khz
Figure 3. Quiescent current vs. input voltage.
0 5 10 15 20 25
4.9
4.95
5
5.05
5.1
Iref [mA]
Vref [V]
Vcc=15V
Tj = 25°C
Figure 7. Reference voltage vs. load current.
-50 -25 0 25 50 75 100 125 150
4.9
4.95
5
5.05
5.1
T
j
(
°C
)
Vref [V])
Vcc = 15V
Ir ef = 1m A
Figure 8. Vref vs. j unction temperature.
8 10121416182022
0
6
12
18
24
30
36
Vcc [V]
Iq [mA ]
Co = 1nF, Tj = 25°C
DC = 0%
1MHz
500KHz
300KHz
100KHz
Figure 4. Quiescent current vs. i nput voltage
and switching frequency.
8 10121416182022
0
6
12
18
24
30
36
Vcc [V]
Iq [m A]
Co = 1nF, Tj = 25°C
D C = 100%
1MHz
500KHz
300KHz
100KHz
Figure 5. Quiescent current vs. input voltage
and swit c hing frequenc y .
-50 -25 0 25 50 75 100 125 150
0.01
0.1
1
10
100
Junction temperature [˚C]
[mA]
Start-up current
Vc=Vcc= Vccon-0.5V, before turn-on
Operating current
Vcc =15V, after turn-on
RT=13.3kΩ, CT=1nF
DC=75%, Co=1nF
Quiescent current
Vcc =15V, after turn-on
RT=13.3 kΩ, CT=1nF
DC = 0
Figure 6. IC Consumption vs. Temperature.
L5991 - L5991A
5/23
10
0 0.2 0.4 0.6 0.8 1 1.2
6
8
10
12
14
16
Isource [A ]
Vsa t = V [V]
Vcc = Vc = 15V
Tj = 25°C
Figure 11. Output saturation.
0 0.2 0.4 0.6 0.8 1 1.2
0
0.5
1
1.5
2
2.5
Isink [A ]
10
V s at = V [V ]
Vcc = Vc = 15V
T j = 25°C
Figure 12. Output saturation.
1 10 100 1000 10000
0
40
80
120
fsw (Hz)
SVRR (dB)
Vcc=15V
Vp-p=1V
Figure 10. Vref SVRR vs. switching frequency.
0 200 400 600 800 1,000 1,200 1,400
0
10
20
30
40
50
V p in 1 0 [mV ]
Ipin10 [mA]
Vcc < V ccon
before turn -on
Figure 13. UVLO Saturation
10 20 30 40
10
20
50
100
200
500
1000
2000
5000
Rt (kohm)
fsw (KHz)
100pF
220pF
470pF
1nF
2.2nF
5.6nF
Tj = 25°C
Vcc = 15V, V15 =0V
Figure 14. Timing resistor vs. switching frequency.
-50 -25 0 25 50 75 100 125 150
4.9
4.95
5
5.05
5.1
Tj (°C)
Vref [V]
Vcc = 15V
Iref= 20mA
Figure 9. Vref vs. junction temperature.
L5991 - L5991A
6/23
0.01 0.1 1 10 100 1000 10000 100000
0
50
100
150
20
40
60
80
100
120
140
f (KHz)
G [dB] Phase
Figure 20. E/A frequency response.
-50 -25 0 25 50 75 100 125 150
28
30
32
34
36
38
40
42
T
j
(
°C
)
Dela
y
to output (ns)
PIN10 = OPEN
1V pulse
on PIN13
Figure 19. Delay to output vs junction temperature.
-50 -25 0 25 50 75 100 125 150
280
290
300
310
320
Tj (°C)
fsw (KHz)
Rt= 4.5Kohm, Ct = 1nF
Vcc = 15 V, V15= 0
Figur e 16 . S w it c hin g frequenc y v s. temper atu re .
246810
300
600
900
1,200
1,500
Timing capacitor Ct [nF]
D e a d time [ns ]
Rt =4.5K ohm
V15 = 0V
V15 = Vref
Figure 17. Dead time vs Ct.
0 102030405060708090100
1
1.5
2
2.5
3
3.5
Duty Cycle [%]
DC Control Voltage Vpin3 [V]
Rt = 4.5Kohm,
Ct = 1nF
V15 = 0V
V15 = Vref
Figure 18. Maximum Duty Cycle vs Vpin3.
-50 -25 0 25 50 75 100 125 150
280
290
300
310
320
Tj (°C)
fsw (KHz)
Rt= 4.5Kohm, C t = 1nF
Vcc = 15V, V15=Vref
Figure 15. Switching frequency vs. tempera-
ture.
L5991 - L5991A
7/23
STANDBY FUNCTION
The standby function, optimized for flyback topol-
ogy, automatically detects a light load condition
for the converter and decreases the oscillator fre-
quency on that oc curre nce. The normal o scillation
frequency is automatically resumed when the out-
put load bu ilds up a nd exceeds a defined thresh-
old.
This function allows to minimize power losses re-
lated to switching frequency, which represent the
majority of losses in a lightly loaded flyback, with-
out giving up the advantages of a higher switching
frequency at heavy load.
This is accomplished by monitoring the output of
the Error Amplifier (VCOMP) that depends linearly
on the peak primary current, except for an offset.
If the the peak primary current decreases (as a r e-
sult of a decrease of the power demanded by the
load) and VCOMP falls below a fixed threshold
(VT1), the oscillator frequency will be set to a
lower value (fSB). When the peak primary current
increases and VCOMP exceeds a second threshold
(VT2) the oscillator frequency is set to the normal
value (fosc). An appropriate hysteresis (VT2-VT1)
prevents undesired frequency change when
power is such that VCOMP moves close to the
threshold. This operation is shown in fig. 21.
Both the normal and the standby frequency are
externally programmable. VT1 and VT2 are inter-
nally fixed but it is possible to adjust the thresh-
olds in terms of input power level.
APPLICATION INFORMATION
Detailed Pin Function Description
Pin 1. SYNC (In/Out Synchronization). This func-
tion allows the IC’s osc illator either to synchronize
other controllers (master) or to be synchronized to
an external frequency (slave).
As a master, the pin delivers positive pulses dur-
ing the falling edge of the oscillator (see pin 2). In
slave operation the circuit is edge triggered. Refer
to fig. 23 to see how it works. When several IC
work in parallel no master-slave designation is
needed because the fastest one becomes auto-
matically the master.
During the ramp-up of the oscillator the pin is
pulled low by a 600µA internal sink current gener -
ator. During the falling edge, that is when the
pulse i s released, the 600µA pull-down is discon-
nected. The pin becomes a generator whose
source capability is typically 7mA (with a voltage
still higher than 3.5V).
In fig. 22, some practical examples of synchroniz-
ing the L5991 are given.
Since the device automatically diminishes its op-
erating frequenc y under light load conditions, it is
reasonable to suppose that synchronization will
refer to normal operation and not to standby.
Pin 2. RCT (Oscillator). Two resistors (RA and RB)
and one capacitor (CT), connected as shown in
fig. 23, allow to set separately the operating fre-
quency of the oscillator in normal operation (fosc)
and in standby mode (fSB).
CT is charged from Vref throu gh RA and RB in nor-
mal operation (STANDBY = HIGH), through RA
only in standby ( STANDBY = LOW). See pin 16
description to see how the STANDBY signal is gen-
erated.
When the voltage on CT reaches 3V, the capaci-
tor is quickly internally discharged. As the voltage
has dropped to 1V it starts being charged again.
1234
VCOMP
Pin
fosc
fSB
Stand-by
Normal operation
VT
1
PNO
PSB
VT
2
Figure 21. Standby dynamic operation.
L5991 L5991
R
A
VREF
SYNCSYNC
RCTRCT
L4981A
(MASTER) L5991
(SLAVE)
R
A
VREFSYNC
RCT
R
OSC
C
OSC
C
T
L5991
(MASTER)
L4981A
(SLAVE)
SYNC
R
OSC
C
T
C
OSC
SYNC
(a) (b) (c)
R
A
D97IN728A
C
T
VREF
4
1
2
1
216
1817 4
2
1
RCT 12 4
16 17 18
ST-BY
16
R
B
ST-BY
16 R
B
R
B
16
ST-BY
Figure 22. Synchronizing the L5991.
L5991 - L5991A
8/23
The oscillation frequency can be established with
the aid of the diagrams of fig. 14, where RT will be
intended as the parallel of RA and RB in normal
operation and RT = RA in standby, or considering
the following approximate relationships:
fosc ≅ 1
CT ⋅ (0.693 ⋅ (RA // RB) + KT (1),
which gives the normal operating frequency, and:
fSB ≅ 1
CT ⋅ (0.693 ⋅ RA + KT) (2),
which gives the standby frequency, that is the one
the converter will operate at when lightly loaded.
In the above expressions, RA // RB means:
RA//RB = RA ⋅ RB
RA + RB,
while KT is defined as:
KT =
90 V15 = VREF
160 V15 = GND/OPEN (3),
and is related to the duration of the falling-edge of
the sawtooth:
Td ≈ 30 ⋅ 10−9 + KT ⋅ C T (4).
Td is also the duration of the sync pulses deliv-
ered at pin 1 and defines the upper extr eme of the
duty cycle range, Dx (see pin 15 for DX definition
and calculation) since the output is held low dur-
ing the falling edge.
In case V15 is connected to VREF, however, the
switching frequency will be a half the values taken
from fig. 14 or result ing from (1) and (2).
To prevent the oscillator frequency from switching
back and forth from fosc to fSB, the ratio fosc / fSB
must not exceed 5.5.
If during normal oper ation the IC is to be s ynchro-
nized to an external oscillator, RA, RB and CT
should be selected for a fosc lower than the master
frequency in any condition (typically, 10-20% ),
depending also on the tolerance of the parts.
Pin 3. DC (Duty Cycle Control). By biasing this
pin with a voltage between 1 and 3 V it is possible
to set t he m aximum duty c ycle bet ween 0 and the
upper extreme Dx (see pin 15).
If Dmax is the desired maximum duty cycle, the
voltage V3 to be applied to pin 3 is:
V3 = 5 - 2(2-Dmax) (5)
Dmax is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 24),
thus in case the device is synchronized to an ex-
ternal frequency fext (and therefore the oscillator
amplitude is reduced), ( 5) changes into:
V3 = 5 − 4 ⋅ exp
− Dmax
RT ⋅ CT ⋅ fext
(6)
A voltage below 1V will inhibit the driver output
stage. This could be used for a n ot-la tched device
disable, for example in case of overvoltage pro-
tection (see application ideas).
If no limitation on the maximum duty cycle is re-
quired (i.e. DMAX = DX), the pin has to be left float-
ing. An internal pull-up (see fig. 24) holds the volt-
age abov e 3V. Should the pin pick up noise (e.g.
+
-
R2R3
R1
CLAMP
D1
50Ω
R
A
C
T
D
RQ
600µA
D97IN729A
V
REF
RCT
SYNC
CLK
2
41
16ST-BY
R
B
STANDBY
Figure 23. Oscillator and synchronization internal schematic.
L5991 - L5991A
9/23
during ESD tests), it can be connected to VREF
through a 4.7kΩ res i st or.
Pin 4. VREF (Reference Voltage). The device is
provided with an accurate voltage reference
(5V±1.5%) able to deliver some mA to an external
circuit.
A small film capacitor (0.1 µF typ.), connected
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noise from affecting the reference.
Before device turn-on, this pin has a sink current ca-
pabili ty o f 0.5mA .
Pin 5. VFB (Error Amplifier Inverting Input). The
feedback signal is applied to this pin and is com-
pared to the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
The E/A features high gain-bandwidth product,
which allows to broaden the bandwidth of the
overall control loop, high slew-rate and current ca-
pability, which improves its large signal behavior.
Usually the compensation network, which stabi-
lizes the overall control loop, is connected be-
tween this pin and COMP (pin 6).
Pin 6. COMP (Error Amplifier Output). Usually,
this pin is used for frequency compensation and
the relevant network is connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L5991
E/A is a voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
ple of compensation techniques.
It is worth mentioning that the calculation of the
part values of the compensation network must
take the standby frequency operation into ac-
count. In particular, this means that the open-loop
crossover frequency must not exceed fSB/4 ÷
fSB/5.
The voltage on pin 6 is monitored in order to re-
duce the oscillator frequency when the converter
is lightly loaded (standby).
Pin 7. SS (Soft-Start). At device start-up, a ca-
pacitor (Css) connected between this pin and
SGND (pin 12) is charged by an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A output is clamped by the voltage
across Css itself and allowed to rise linearly, start-
ing from zero, up to the steady-state value im-
posed by the control loop. The maximum time in-
terval during which the E/A is clamped, referred to
as soft-start time, is approximately:
Tss ≅ 3 ⋅ Rsense ⋅ IQpk
ISSC ⋅ Css (7)
where Rsense is the current sense resistor (see pin
13) and IQpk is the switch peak current (flowing
through Rsense), which depends on the output
load. Usually , CSS is selected for a TSS in the or-
der of milliseconds .
As mentioned before, the soft-start intervenes
also in case of severe overload or short circuit on
the output. Referring to fig. 25, pulse-by-pulse
current limitation is somehow effective as long as
the ON-time of the power switch can be reduced
(from A to B). After the minimum ON-time is
reached (from B onwards) the current is out of
control.
To prevent this risk, a comparator trips an over-
current handling proce dure, named ’hiccup’ mode
operation, when a voltage above 1.2V (point C) is
detected on current sense input (ISEN, pin 13).
Basically, the IC is turned off and then soft-started
as long as the fault condition is detected. As a re-
sult, the operating point is moved abruptly to D,
creating a foldback effect. Fig. 26 illustrates the
operation.
The oscillation frequency appearing on the soft-
start capacitor in case of permanent fault, referred
to as ’hic c up" period, is approximately given by:
Thic ≅ 4.5 ⋅
1
ISSC + 1
ISSD
⋅ Css (8)
+
-
R2
R1
R
A
C
T
D97IN727A
V
REF
RCT
DC
TO PWM LOGIC
4
3
2
23K
28K
3µA
R
B
ST-BY 16
Figure 24. Duty cycle control.
V
OUT
T
ON
D.C.M. C.C.M.
D
A
BC
I
Qpk
T
ON(min)
1-2 ·I
Qpk
I
Qpk(max)
I
OUT
I
SHORT
I
OUT(max)
D97IN495
Figure 25. Regulation characteristic and re-
lated qua nti t i e s .
L5991 - L5991A
10/23
Since the system tries restarting each hiccup cy-
cle, there is not any latchoff risk.
"Hiccup" keeps the system in control in case of
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (from A to C). Other external protection cir-
cuits are needed if a better control of overloads i s
required.
Pin 8. VCC (Controller Supply). This pin supplies
the signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the current consumption is extremely low
(<150µA). This is particularly useful for reducing
the consumption of the start-up circuit (in the sim-
plest case, just one resistor), which is one of the
most significant contributions to power losses in
standby.
An internal Zener limits the voltage on VCC to
25V. The IC current consumption increases con-
siderably if this limit is exceeded.
A small film capacitor between this pin and SGND
(pin 12), placed as close as po ssible to the IC, is
recommended to filter high frequency noise.
Pin 9. VC (Supply of the Power Stage). It supplies
the driver o f the external switch and therefore ab-
sorbs a pulsed current. Thus it is rec ommended to
place a buffer capacitor (towards PGND, pin 11,
as close as possible to the IC) able to sustain
these current pulses and in order to avoid them
inducing disturbances.
This pin ca n be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 27,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
MOS. At turn-on the gate resistance is Rg + Rg’, at
turn-off is Rg only.
Pin 10. OUT (Driver Output). This pin is the out-
put of the driver stage of the external power
switch. Usually, this will be a PowerMOS, al-
though the driver is powerful enough to drive
BJT ’ s (1. 6 A so urce , 2A si nk, p ea k).
The driver is m ade up of a totem pole with a high-
side NPN Darlington and a low-side VDMOS, thus
there is no need of an external diode clamp to
prevent voltage from going below ground. An in-
ternal clamp limits the voltage delivered to the
gate at 13V. Thus it is possible to supply the
driver (Pin 9) with higher voltages without any risk
of damage for the gate oxide of the external MOS .
The clamp does not cause any additional in-
crease of power dissipation inside the chip since
the current peak of the gate charge occurs when
the gate voltage is few volts and the clamp is not
active. Besides, no current flows when the gate
voltage is 13V, steady state.
Under UVLO conditions an internal circuit (shown
7V
T
hic
time
SHORT
I
OUT
I
SEN
FAULT
SS
5V
0.5V
D98IN986
Figure 26. Hiccup mode operation.
OUT Rg
DRIVE &
CONTROL
13V
V
C
V
CC
Rg'
PGND
Rg(ON)=Rg+Rg'
Rg(OFF)=Rg
D97IN726
L5991
9
10
11
8
Figure 27. Turn-on and turn-off speeds adjust-
ment.
L5991 - L5991A
11/23
in fig.28) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from VCC = 0V up to the start-up threshold.
When the threshold is exceeded and the L5991
starts operating, VREFOK is pulled high (refer to fig.
28) and the circuit is disabled.
It is then possible to omit the "bleeder" resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Pin 11. PGND (Power Ground). The current loop
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
Pin 12. SGND (Signal Ground). This ground refer-
ences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND pat h.
Pin 13. ISEN (Current Sense). This pin is to be
connected to the "hot" lead of the current sense
resistor Rsense (being the other one grounded), to
get a voltage ramp which is an image of the cur-
rent of the switch (IQ). When this voltage is equal
to:
V13pk = IQpk ⋅ Rsense = VCOMP − 1.4
3 (9)
the conduction of the switch is terminated.
To increase the noise immunity, a "Leading Edge
Blanking" of about 100ns is internally realized as
shown in fig. 29. Because of that, the smoothing
RC filter between this pin and Rsense could be re-
moved or, at least, considerably reduced.
Pin 14. DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessary to pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the de-
vice to restart.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
30. It is also possible to realize an overvoltage
protection, as shown in the section " Application
Ideas".If used, bypass this pin to ground wit h a fil-
ter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
Pin 15 . DC-LIM ( Maximum Duty Cycle Lim it). The
upper extreme, Dx, of the duty cycle range de-
pends o n the voltage applied to this pin. Approxi-
mately,
Dx ≅ RT
RT + 230 (10)
if DC-LIM is grounded or left floating. Instead,
+
-
I
D97IN503
ISEN
0
3V
CLK
2V
+
-
+
-
1.2V
FROM E/A
OVERCURRENT
COMPARATOR
PWM
COMPARATOR TO PWM
LOGIC
TO FAULT
LOGIC
13
Figur e 29. Int e r na l LEB.
10
12 SGND
OUT
VREFOK
D97IN538
Figure 28. Pull-Down of the output in UVLO.
L5991 - L5991A
12/23
connecting DC-LIM to VREF (half duty cycle op-
tion), Dx will be set approximately at:
Dx ≅ RT
2 ⋅ RT + 26 0 (11)
and the outp ut switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram) is activated.
Fig. 31 shows the operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor CT (in order to get
duty cycles as close to 50% as possible) so the
oscillator frequency - with the same timing compo-
nents will be slightly higher.
Pin 16 . S-B Y (Standby Function). The resis tor RB,
along with RA, sets the operating frequency o f the
oscillator in normal operation (f osc). In fact, as long
as the STANDBY signal is high, the pin is inter-
nally connected to the r eference voltage VREF by
a N-channel FET (see fig. 32), so the timing ca-
pacitor CT is charged through RA and RB. When
the STA NDBY sig na l goes low th e N- chan nel F ET
is turned off and the pin becomes floating. RB is
+
-
C
D97IN502
DIS D
RQDISABLE
UVLO
2.5V
14
DISABLE
SIGNAL
Figure 30. Disable (Latched).
V15=GND
V5=V13=GND
V15=VREF
V5=V13=GND
td
td
tc
tc
V2
V10
V2
V10
DX = tc
tc + td
DX = tc
2 ·tc + td
D97IN498
Figure 31. Half duty cycle option.
-
+
-
+
2.5 2.5/4
R
STANDBY
10V
LEVEL SHIFT
COMP
FB VREF
ST-BY
4
16
6
RCT C
T
R
A
R
B
2
5
LOW
HIGH
STANDBY
D97IN752B
V
T1
2.5V V
T2
4V V
COMP
-
+
ISEN
13
R
DRIVER
OUT
STANDBY BLOCK
2R
Figure 32. Standby fu nction internal schematic and operation.
L5991 - L5991A
13/23
now disconnected and CT is charged through RA
only. In this way the oscillator frequency (fSB) will
be lower. Refer to pin 2 description to see how to
calculate the timing components.
Typical values for VT1 and VT2 are 2.5 V and 4V
respectively. This 1.5V hysteresis is enough to
prevent undesired frequency change up to a 5.5
to 1 fosc/ fSB ratio.
The value of VT1 is such that in a discontinuous
flyback the standby frequency is activated when
the input power is about 13% of the maximum. If
necessary, it is possible to decrease the power
threshold below 13% by adding a DC offset (Vo)
on the current sense pin (13, ISEN). This will also
allow a frequenc y change greater than 5.5 to 1.
The following equations, useful for des ign, apply:
PinSB = 1
2 ⋅ LP ⋅ ƒosc ⋅
0.367 − Vo
Rsense
2 (12),
PinNO = 1
2 ⋅ LP ⋅ ƒSB ⋅
0.867 − Vo
Rsense
2 (13),
ƒosc
ƒSB <
0.867 − Vo
0.367 − Vo
2 (14),
where PinSB is the input power below which the
L5991 recognizes a light load and switches the
oscillator frequency from ƒosc to fSB, PinNO is the
input power above which the L5991 switches
back from ƒSB to ƒosc and Lp the primary induc-
tance of the flyback transformer.
Connect to Vref or leave open this pin when
stand-by function is not used.
Layout hints
Generally speaking a proper circuitboard layout is
vital for correct operation but is not an easy task.
Careful component placing, correct traces routing,
appropriate traces widths and, in case of high
voltages, compliance with isolation distances are
the major issues. The L5991 eases this task by
putting two pins at disposal for separate current
returns of bias (SGND) and switch drive currents
(PGND) The matter is complex and only few im-
portant points will be here reminded.
1) All current returns (signal ground, power
ground, shielding, etc.) should be routed sepa-
rately and should be connected only at a single
ground point.
2) Noise coupling can be reduced by minimizing
the area circumscribed by current loops. This
applies particularly to loops where high pulsed
currents flow.
3) For high current paths, the traces should be
doubled on the other side of the PCB whenever
possible: this will reduce both the resistance
and the inductance of the wiring.
4) Magnetic field radiation (and stray inductance)
can be reduced by keeping all traces carrying
switched currents as short as possible.
5) In general, traces carrying signal currents
should run far from traces carrying pulsed cur-
rents or with quickly swinging voltages. From
this viewpoint, particular care should be taken
of the high impedance points (cur rent sense in-
put, feedbac k input, ...). It could be a good idea
to route signal traces on one PCB side and
power traces on the other side.
6) Provide adequate filtering of some crucial
points of the circuit, such as voltage references,
IC’s supply pins, etc.
L5991 - L5991A
14/23
APPLICATION IDEAS
Her e follows a series of i deas/ su ggest ions aimed at
either improving performance or solving common
application problems of L5991 based supplies.
C02
0.1µF
C01
0.1µF
F01 AC 250V T3.15A
88 to 270
VAC
BD01 R01 3.3
C03 220µF
400V R18
47K
3W
C10
10nF
100V
LF01
R03 47K
10 R08 22
13 R11 1K
12
C05
100pF
11
R10
0.22
C04 47µF
8
91416
R06 27
R12 330K
R13 47K
R9
24K
2
4
16
C07 1µF
R5
12K
6800pF
1
3
8
7
D06
1N4148
5
7
C09 8.2nF R21 100
C08
3.3nF
6
Q01
STP6
NA60FI
4N35
18
15
13
14
16
17
C56
470µF 25V
C57
470µF 25V
11
12
10
D04 1N4148
R07 47
D05
1N4937
C52
100µF
250V
C54
220µF 100V
R52
47
C58
47µF 25V
D55 BYW100-100
D56 BYW100-100
R53
4.7K
R54
1K
C61
0.056µF
R58
4.7K
Q51
TL431
VR51
100K
R55
300K R56
4.3K
C59
0.01µF
180V
65W
80V
10W
GND
6.3V
5W
+15V
5W
-15V
5W
D97IN730A
C62
100µF 100V
C55
1000µF
16V
D54 BYW100-100
D53 BYT11-600
D52 BYT13-800
C11 4700pF 4KV C12
R19 4.7M R20 4.7M
L5991
R04 47K
R16
750K
R17
750K
C06
C11 2.2nF
VAC(V)
Pin(W)
Pout(W)
88
2.95
110
3.10
220
3.90
270
4.40
2
Figure 33. Typical application circuit for computer monitors (90W).
L5991 - L5991A
15/23
4700pF 4KV 4700pF 4KV
4.7M
STP4NA60
4N35
220
2 x 330
µ
F
35V
1K
0.022
µ
F
2.7K
3.9K
28V / 0.7A
GND
470
µ
F
16V
BYW100-50
BYW98-100
BYW100-200
4.7M
12V / 1.5A
5V / 0.5A
C02
0.1
µ
F
C01
0.1
µ
F
F01 AC 250V T1A
85 TO
265 Vac
BD01 2.2
LF01
10K
1.1M
BC337
10 22
13 1K
12 470pF
11
0.47
1/2 W
33
µ
F/25V
8
91415
22
33K4.7K
47K
2
3
4
1
100nF
22K
3.3nF 16
7
330nF
470
470pF
6
BAT46
TL431
L5991
22V
1.1M STK2N50
1N4937
5
5.6K
N1
N2
N3
N4
Naux
5.6K
5.6K
2 x 470
µ
F
16V
5.1K 270K
100
µ
F
400V BZW06-154
D97IN618
VAC(V)
Pin(W)
Pout(W)
85
0.90
110
0.93
220
1.14
265
1.57
0.55
Figure 34. Typical application circuit for inkjet printers (40W).
L5991 - L5991A
16/23
L5991
12 413
SGND
VREF ISEN
OPTIONAL
D97IN751A
10
R
SENSE
R
A
R
Figur e 35. Sta ndby thres holds adjus tme nt.
D97IN761
L5991
PGND
ISEN
OUT
VC
SGND
VIN
ISOLATION
BOUNDARY
10
9
13
1112
Figure 36. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies.
L5991
V
REF
T
V
CC
V
IN
20V
D97IN762B
2.2MΩ33KΩ
SELF-SUPPLY
WINDING
8
4
12 11
47KΩ
STD1NB50-1
Figure 37. Low consumption start-up.
D97IN763
L5991 PGND
ISEN
OUT
VC
VIN
9
10
13
11
8
VCC
Figure 38. Bi polar tr ansistor driver.
L5991 - L5991A
17/23
D97IN507
+
-EA
R
i
+
1.3mA
R
d
R
2R
12
C
f
R
f
6
5
From V
O
2.5V
+
-EA
R
P
+
1.3mA
R
d
R
2R
12
C
f
R
f
6
5
From V
O
2.5V
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
C
P
R
i
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
VFB
VFB
COMP
COMP
SGND
SGND
Figure 39. Typical E /A compensation networks.
L5991
COMP
D97IN759
TL431
V
OUT
VFB
6
5
Figure 40. Feedback with optocoupler.
L5991
OPTIONAL
D97IN760A
I
V
REF
SGND
R
A
C
T
RCT
R
SLOPE
R
SENSE
ISEN
L5991
OPTIONAL
I
V
REF
SGND
R
A
C
T
RCT
R
SLOPE
R
SENSE
ISEN
L5991
OPTIONAL
OUT
SGND
R
R
SLOPE
R
SENSE
ISEN
C
SLOPE
4
2
13 12
4
2
13 12 13
12
10
R
B
16
ST-BY 16
ST-BY
R
B
Figure 41. Slope compensation techniques.
L5991 - L5991A
18/23
Figure 42. Protection against overvoltage/feedback disconnection (latched)
L5991
D97IN755A
DC
V
CC
VREF
R
START
3
12
8
4
11
Figure 43 Protection against overvoltage/feed-
back disconnection (not latched)
D97IN756A
PGND
L5991
OPTIONAL
VREF
SGND
DIS
ISEN
I
4
14
13
1211 RSENSE
R2
R1Ipk
Ipk max ≅2.5
RSENSE 1- R2
R1
•
Figure 44. Device shutdown on overcurrent
D97IN757
PGND
L5991
OUT
SGND
ISEN
Lp
R
FF
R
V
IN
R
FF
= 6·10
6
R·Lp
RSENSE
RSENSE
13
10
1211
80 ÷ 400V
DC
Figure 45. Constant power in pulse-by-pulse current limitation (flyback discontinuous)
L5991
DC
10K
COMP
3
612 13
SGND ISEN
D97IN758A
Figur e 46. Volta ge mo de operati on.
L5991
D98IN905
SGND
DIS
VCC
RSTART
PGND
8
1412 11
VZ
2.2K
L5991
D97IN754
SGND
DIS
V
CC
R
START
PGND
8
1412 11
L5991 - L5991A
19/23
L5991
4
312 11
VREF
SGND PGND
10KΩR25.1
R1
4.7K
V
IN
80÷400V
DC
D97IN750B
Figure 47. Device shutdown on mains undervoltage.
L5991
112
SYNC
SGND
1KΩ
5.1V
D97IN753A
Figure 48. Synchronization to flyback pulses (for monitors).
L5991 - L5991A
20/23
DIP16
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
OUTLINE AND
MECHANICAL DATA
L5991 - L5991A
21/23
SO16 Narrow
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45˚ (typ.)
D (1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F (1) 3.8 4 0.150 0.157
G 4.6 5.3 0.181 0.209
L 0.4 1.27 0.016 0.050
M 0.62 0.024
S
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
OUTLINE AND
MECHANICAL DATA
8˚(max.)
L5991 - L5991A
22/23
Information furnis hed is bel ieved to be ac curate and reliabl e. Howe ver, STMi croelect ronics assum es no respo nsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implic ation or o therwise under any patent or patent rights of STMicroelectronics. Specif ication mentioned in this publication are
subje ct to change w ithout notic e. This public ation supers edes and repl aces all info rmation previous ly sup plied. STMic roelec tronic s product s
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics – Printed in Italy – All Rights Reserved
STMi croelectronics GROUP OF COMPANIES
Australia - Brazil - China - Fi nland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
L5991 - L5991A
23/23
