This is information on a product in full production.
February 2016 DocID023364 Rev 4 1/38
VND5T100LAJ-E
VND5T100LAS-E
Double channel high-side driver with analog current sense
for 24 V automotive applications
Datasheet
-
production data
Features
•General
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– Compliant with European directive
2002/95/EC
– Fault reset standby pin (FR_Stby)
– Optimized for LED application
•Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Off-state open-load detection
– Output short to V
CC
detection
– Overload and short to ground latch-off
– Therm al sh utdown latc h-off
– Very low current sense leakage
•Protection
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Therm al sh utdow n
– Electros tatic disc harge protection
Application
All types of resistive, inductive and capacitive
loads
Description
The VND5T100LAJ-E and VND5T100LAS-E are
monolithic devices made using
STMicroelectronics
®
VIPower
®
technology,
intended for driving resistive or inductive loads
with one side connected to ground. Active V
CC
pin voltage clamp protects the devices against
low energy spikes.
These devices integrate an analog current sense
which delivers a current proportional to the load
current.
Fault conditions such as overload,
overtemperature or short to V
CC
are reported via
the current sense pin.
Output current limitation protects the devices in
overload condition. The devices latch off in case
of overload or thermal shutdown.
The devices are reset by a low level pass on the
fault reset standby pin.
A permanent low level on the inputs and fault
reset standby pin disables all outputs and sets the
devices in standby mode.
Max transient supply voltage V
CC
58 V
Operati ng vol tage range V
CC
8 to 36 V
Typ on-state resistance (per ch.) R
ON
100 mΩ
Current lim itation (typ) I
LIM
22 A
Off-st a te sup ply current I
S
2 µA
(1)
1. Typical value with all loads connected.
PowerSSO-12
SO-16N
www.st.com
Contents VND5T100LAJ-E, VND5T100LAS-E
2/38 DocID023364 Rev 4
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Elect rical char acteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Maximum demagnetization energy (V
CC
= 24 V) . . . . . . . . . . . . . . . . . . . 23
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 SO-16N thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 ECOPACK
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 PowerSSO-12 mechanical da ta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 SO-16N package i n formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 PowerSSO-12 packing informati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 SO-16N packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DocID023364 Rev 4 3/38
VND5T100LAJ-E, VND5T100LAS-E List of tables
3
List of tables
Table 1. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (V
CC
= 24 V; T
j
= 25 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Current sense (8 V < V
CC
< 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
List of figures VND5T100LAJ-E, VND5T100LAS-E
4/38 DocID023364 Rev 4
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram PowerSSO-12 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Configuration diagram SO16-N (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. T
standby
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. T
reset
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Open-load off-state delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Output stuck to V
CC
detection delay time at FR
STBY
activation . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Delay response time between rising edge of output current and rising edge of
current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Input high level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. On-state resistance vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. On-state resistance vs V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. I
LIMH
vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 26. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 27. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24
Figure 29. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 25
Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 25
Figure 31. SO-16N PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 32. R
thj-amb
vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . 27
Figure 33. SO-16N thermal impedance junction ambient single pulse (one channel on) . . . . . . . . . . 28
Figure 34. Thermal fitting model of a double channel HSD in SO-16N . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 35. PowerSSO-12 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 36. SO-16N package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 37. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 38. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. SO-16N tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 40. SO-16N tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DocID023364 Rev 4 5/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Block diagram and pin description
37
1 Block diagram and pin description
Figure 1. Block diagram
Table 1. Pin function
Name Function
V
CC
Battery connec ti on
OUTn Power output
GND Ground connection
INn Voltage controlled input pin with hysteresis, CMOS compatible. It controls output
switch state
CSn Analog current sense pin, it delivers a current proportional to the load current
FR_Stby In case of latch-off for overtemperature/overcurrent condition, a low pulse on the
FR_Stby pin is needed to reset the channel.
The device enters in standby mode if all inputs and the FR_Stby pin are low.
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DRAFT
Block diagram and pin description VND5T100LAJ-E, VND5T100LAS-E
6/38 DocID023364 Rev 4
Figure 2. Configuration diagram PowerSSO-12 (top view)
Figure 3. Configuration diagram SO16-N (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Current sense N.C. Output Input FR_Stby
Floating Not allowed X
(1)
1. X: do not care.
XXX
To ground Through 10 KΩ
resistor X Not allowed Through
10 KΩ resistor Through
10 KΩ resistor
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DocID023364 Rev 4 7/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Electrical specifications
37
2 Electrical specifications
Fig ure 4. Cu rrent and voltage conventions
2.1 Absolute maximum ratings
Stressing the device above the ratings listed in Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions reported in this section for extended periods may affect device
reliability.
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Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
DC supply voltage 58 V
-V
CC
Reverse DC supply voltage 0.3 V
-I
GND
DC reverse ground pin current 200 mA
I
OUT
DC output current Internally limited A
-I
OUT
Reverse D C output current 20 A
I
IN
DC input current -1 to 10 mA
I
FR_Stby
Fault reset standby DC input current -1 to 1.5 mA
-I
CSENSE
DC reverse CS pin current 200 mA
V
CSENSE
Current sense maximum voltage V
CC
- 58 to
+V
CC
V
DRAFT
Electrical specifications VND5T100LAJ-E, VND5T100LAS-E
8/38 DocID023364 Rev 4
2.2 Thermal data
E
MAX
Maximum switching energy
(L = 1.9 mH; V
bat
= 32 V; T
jstart
= 150°C; I
OUT
= I
limL
(Typ)) 70 mJ
V
ESD
Electrostatic discharge
(Human Body Model: R = 1.5 KΩ; C = 100 pF)
– INPUT
– CURRENT SENSE
– FR_STBY
– OUTPUT
–V
CC
4000
2000
4000
5000
5000
V
V
V
V
V
V
ESD
Charge device model (CDM-AEC-Q100-011) 750 V
T
j
Junction operating temperature -40 to 150 °C
T
stg
Storage temperature -55 to 150 °C
L
Smax
Maximum stray inductance in short circuit
R
L
= 300 mΩ, V
bat
= 32 V, T
jstart
= 150°C, I
OUT
= I
limHmax
40 µH
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 4. Thermal data
Symbol Parameter Maximum value Unit
PowerSSO-12 SO-16N
R
thj-case
Thermal resistance junction-case (with one
chann el ON) 6—°C/W
R
thj-pin
Thermal resistance junction-pin (with one
chann el ON) —26°C/W
R
thj-amb
Thermal resistance junction-ambient See Figure 28 See Fig ure 32 °C/W
DocID023364 Rev 4 9/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Electrical specifications
37
2.3 Electrical characteristics
8 V < V
CC
< 36 V; -40°C < T
j
< 150°C, unless otherwise specified.
.
Table 5.
Powe r secti on
Symbol Parameter Test conditions Min. Typ. Max. U nit
V
CC
Operating supply voltage 8 24 36 V
V
USD
Undervo lt age shut do w n 3.5 5 V
V
USDhyst
Undervo lt age shut do w n
hysteresis 0.5 V
R
ON
On-state resistance
(1)
1. For each channel.
I
OUT
= 1.5 A; T
j
= 25°C 100 mΩ
I
OUT
= 1.5 A; T
j
= 150°C 200
V
clamp
Clamp vo lt ag e I
S
= 20 mA 58 64 70 V
I
S
Supply cu rrent
Off-state: V
CC
= 24 V; T
j
= 25°C;
V
IN
= V
OUT
= V
SENSE
= 0 V 2
(2)
2. PowerMos leakage included
5
(2)
µA
On-state: V
CC
= 24 V; V
IN
= 5 V;
I
OUT
= 0 A 4.2 6 mA
I
L(off)
Off-state output current
V
IN
= V
OUT
= 0 V; V
CC
= 24 V;
T
j
= 25°C 00.01 3 µA
V
IN
= V
OUT
= 0 V; V
CC
= 24 V;
T
j
= 125°C 05
V
F
Output - V
CC
diode voltage -I
OUT
= 1.5 A; T
j
= 150°C 0.7 V
Table 6. Switching (V
CC
= 24 V; T
j
= 25 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
Turn-on delay time R
L
= 16 Ω 27 µs
t
d(off)
Turn-off delay time R
L
= 16 Ω 38 µs
dV
OUT
/dt
(on)
Turn-on voltage slope R
L
= 16 Ω 1V/µs
dV
OUT
/dt
(off)
Turn-off voltage slope R
L
= 16 Ω 0.65 V/µs
W
ON
Switching energy losses
during t
won
R
L
= 16 Ω 0.23 mJ
W
OFF
Switching energy losses
during t
woff
R
L
= 16 Ω 0.26 mJ
Table 7. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level voltage 0.9 V
I
IL
Low level input cu rrent V
IN
= 0.9 V 1 µA
V
IH
Input hi gh level voltage 2.1 V
DRAFT
Electrical specifications VND5T100LAJ-E, VND5T100LAS-E
10/38 DocID023364 Rev 4
Figure 5. T
standby
defini ti on
I
IH
High level input current V
IN
= 2.1 V 10 µA
V
I(hyst)
Input hysteresis voltage 0.25 V
V
ICL
Input cl amp voltage I
IN
= 1 mA 5.5 7 V
I
IN
= -1 mA -0.7 V
V
FR_Stby_L
Fault_reset_standby low le ve l
voltage 0.9 V
I
FR_Stby_L
Low level fault_re set_s t andby
current V
FR_Stby
= 0.9 V 1 µA
V
FR_Stby_H
Fault_res et_ standb y hig h
level voltage 2.1 V
I
FR_Stby_H
High level fault_reset_standby
current V
FR_Stby
= 2.1 V 10 µA
V
FR_Stby (hyst)
Fault_reset_standby
hysteresis voltage 0.25 V
V
FR_Stby_CL
Fault_reset_standby clamp
voltage
I
FR_Stby
= 15 mA
(t < 10 ms) 11 15 V
I
FR_Stby
= -1 mA -0.7 V
t
reset
Overload latch-off reset time See Figure 5 224µs
t
stby
Standby delay See Figure 6 120 1200 µs
Table 7. Logic inputs (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
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DocID023364 Rev 4 11/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Electrical specifications
37
Figure 6. T
reset
definition
Table 8. Protections and diagnostic s
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
DC short circuit current V
CC
= 24 V 16 22 30 A
5 V < V
CC
< 36 V 30 A
I
limL
Short circuit current
during ther mal cyclin g V
CC
= 24 V;
T
R
< T
j
< T
TSD
6A
T
TSD
Shut down tem pe rature 150 175 200 °C
T
R
Reset temperature T
RS
+ 1 T
RS
+ 5 °C
T
RS
Thermal reset of status 135 °C
T
HYST
Thermal hysteresis
(T
TSD
- T
R
)7°C
V
DEMAG
Turn-of f outp ut vol t ag e
clamp I
OUT
= 1.5 A; V
IN
= 0;
L = 6 mH V
CC
- 58 V
CC
- 64 V
CC
- 70 V
V
ON
Output voltage drop
limitation I
OUT
= 50 mA;
T
j
= -40°C to 150°C 25 mV
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Electrical specifications VND5T100LAJ-E, VND5T100LAS-E
12/38 DocID023364 Rev 4
Table 9. Current sense (8 V < V
CC
< 36 V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
OL
I
OUT
/I
SENSE
I
OUT
= 12 mA; V
SENSE
= 0.5 V;
T
j
= -40°C to 150°C 833
K
LED
I
OUT
/I
SENSE
I
OUT
= 50 mA; V
SENSE
= 0.5 V;
T
j
= -40°C to 150°C 1328 2190 3332
dK
LED
/K
LED(TOT)(1)
Current sense ratio
drift
I
OUT
= 12 mA to 25 mA;
I
CAL
= 18 mA; V
SENSE
= 0.5 V;
T
j
= -40°C to 150°C -30 30 %
K
0
I
OUT
/I
SENSE
I
OUT
= 100 mA; V
SENSE
= 0.5 V;
T
j
= -40°C to 150°C 1170 1950 2730
dK
0
/K
0(1)
Current sense ratio
drift I
OUT
= 100 mA; V
SENSE
= 0.5 V;
T
j
= -40°C to 150°C -18 18 %
K
1
I
OUT
/I
SENSE
I
OUT
= 0.4 A; V
SENSE
= 1 V ;
T
j
= -40°C to 150°C 1259 1740 2191
dK
1
/K
1(1)
Current sense ratio
drift I
OUT
= 0.4 A; V
SENSE
= 1 V ;
T
j
= -40°C to 150°C -15 15 %
K
2
I
OUT
/I
SENSE
I
OUT
= 0.8 A; V
SENSE
= 2 V ;
T
j
= -40°C to 150°C 1372 1730 2058
dK
2
/K
2(1)
Current sense ratio
drift I
OUT
= 0.8 A; V
SENSE
= 2 V ;
T
j
= -40°C to 150°C -12 12 %
K
3
I
OUT
/I
SENSE
I
OUT
= 1.6 A; V
SENSE
= 2 V ;
T
j
= -40°C to 150°C 1509 1720 1921
dK
3
/K
3(1)
Current sense ratio
drift I
OUT
= 1.6 A; V
SENSE
= 2 V ;
T
j
= -40°C to 150°C -8 8 %
K
4
I
OUT
/I
SENSE
I
OUT
= 6 A; V
SENSE
= 4 V;
T
j
= -40°C to 150°C 1646 1720 1784
dK
4
/K
4(1)
Current sense ratio
drift I
OUT
= 6 A; V
SENSE
= 4 V;
T
j
= -40°C to 150°C -4 4 %
I
SENSE0
Analog sense
leakage current
I
OUT
= 0 A; V
SENSE
= 0 V;
V
IN
= 0 V; T
j
= -40 °C to 150 °C 01µA
I
OUT
= 0 A; V
SENSE
= 0 V;
V
IN
= 5 V; T
j
= -40 °C to 150 °C 02µA
V
SENSE
Max analog sense
output voltage I
OUT
= 6 A; R
SENSE
= 3.9 KΩ5V
V
SENSEH
Analog sense
output voltage in
fault condition
(2)
V
CC
= 24 V; R
SENSE
= 3.9 KΩ7.5 8.5 9.5 V
I
SENSEH
Analog sense
output current in
fault condition
(2)
V
CC
= 24 V; V
SENSE
= 5 V 4.9 9 12 mA
t
DSENSE2H
Delay response
time from rising
edge of INPUT pin
V
SENSE
< 4 V ;
0.07 A < I
OUT
< 6 A;
I
SENSE
= 90 % of I
SENSE
max
(see Figure 7)
100 200 µs
DocID023364 Rev 4 13/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Electrical specifications
37
Figure 7. Current sense delay characteristics
Δt
DSEN
SE
2H
Delay response
time between
rising edge of
output current and
rising edge of
current se nse
V
SENSE
< 4 V;
I
SENSE
= 90 % of I
SENSEMAX
;
I
OUT
= 90 % of I
OUTMAX
;
I
OUTMAX
= 1.5 A (see Figure 12)
150 µs
t
DSENSE2L
Delay response
time from falling
edge of INPUT pin
V
SENSE
< 4 V ;
0.07 A < I
OUT
< 6 A;
I
SENSE
= 10 % of I
SENSE
max
(see Figure 7)
520µs
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open-load in OFF-state condition.
Table 10.
Open-load detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
OL
Open-load off-state
voltage detection
threshold
V
IN
= 0 V; 8 V < V
CC
< 36 V;
F
R_STBY
= 5 V 2—4V
t
DSTKON
Output short circuit to
V
CC
detection delay at
turn off
See Figure 7;
F
R_STBY
= 5 V 180 — 1800 µs
t
DFRSTK_ON
Output short circuit to
V
CC
detection delay at
FRSTBY activation
See Figure 10;
Input
1,2
= low —50µs
I
L(off2)
Off-state o utput current
at V
OUT
= 4V
V
IN
= 0 V ; V
SENSE
= 0 V ;
V
OUT
rising from 0 V to 4 V;
F
R_STBY
= 5 V -120 — 0 µA
t
d_vol
Delay response from
output rising edge to
V
SENSE
rising edge in
open-load
V
OUT
= 4 V; V
IN
= 0 V;
V
SENSE
= 90 % of V
SENSEH
;
R
SENSE
= 3.9 KΩ;
F
R_STBY
= 5 V
—20µs
Table 9. Current sense (8 V < V
CC
< 36 V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
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Electrical specifications VND5T100LAJ-E, VND5T100LAS-E
14/38 DocID023364 Rev 4
Figure 8. Open-load off-state dela y timing
Figure 9. Switching characteristics
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DocID023364 Rev 4 15/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Electrical specifications
37
Figure 10. Output stuck to V
CC
detection delay time at FR
STBY
activation
Figure 11. Delay response time be tween ris ing edge of output cur rent and risi ng edge
of current sense
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Electrical specifications VND5T100LAJ-E, VND5T100LAS-E
16/38 DocID023364 Rev 4
Figure 12. Output voltage drop limitation
Figure 13. Device behavior in overload condition
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DocID023364 Rev 4 17/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Electrical specifications
37
Table 11. Truth table
Conditions Fault reset standby Input Output Sense
Standby L L L 0
Normal operati on X
XL
HL
H0
Nominal
Overload X
XL
HL
H0
> Nominal
Overtemperature / short to ground X
L
H
L
H
H
L
Cycling
Latched
0
V
SENSEH
V
SENSEH
Undervoltage X X L 0
Short to V
BAT
L
H
X
L
L
H
H
H
H
0
V
SENSEH
< Nominal
Open-load off-state (with pull-up) L
H
X
L
L
H
H
H
H
0
V
SENSEH
0
Negative output voltage clamp X L Negative 0
DRAFT
Electrical specifications VND5T100LAJ-E, VND5T100LAS-E
18/38 DocID023364 Rev 4
Table 12. Electrical transient requirements (p art 1)
ISO 7637-2:
2004(E)
Test pulse
Test levels
(1)
Number of
pulses or test
times
Burst cycle /pul se
repetition time Delays and
impedance
III IV
1 - 450 V - 600 V 5000 pulses 0.5 s 5 s 1 ms, 50 Ω
2a + 37 V + 50 V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω
3a - 150 V - 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b + 150 V + 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 - 12 V - 16 V 1 pulse 100 ms, 0.01
Ω
5b
(2)
+ 123 V + 174 V 1 pulse 350 ms, 1
Ω
Table 13. Electrical transient requirements (p art 2)
ISO 7637-2:
2004(E)
Test pulse
Test level results
III IV
1C C
2a C C
3a C C
3b
(1)
1. Without capacitor between V
CC
and GND.
EE
3b
(2)
2. With 10 nF between V
CC
and GND.
CC
4C C
5b
(3)
3. External load dump clamp, 58 V maximum, referred to ground.
CC
Table 14. Electrical transient requirements (p art 3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device are not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the
DocID023364 Rev 4 19/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Electrical specifications
37
2.4 Electrical characteristics curves
Figure 14. Off-state output curr ent Figure 15. High level input current
Figure 16. Input clamp voltage Figure 17. Input high level volt age
Figure 18. Input low level voltage Figure 19. Input hysteresis voltage
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Electrical specifications VND5T100LAJ-E, VND5T100LAS-E
20/38 DocID023364 Rev 4
Figure 20. On-state resistance vs T
case
Figure 21. On-state resistance vs V
CC
Figure 22. I
LIMH
vs T
case
Figure 23. Turn-on voltage slope
Figure 24. Turn-off voltage slope
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DocID023364 Rev 4 21/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Application information
37
3 Application information
Figure 25. Application schematic
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (R
GND
only)
This solution can be used with any type of load.
The following is an indication on how to select the R
GND
resistor.
1. R
GND
≤ 600 mV / (I
S(on)max
).
2. R
GND
≥ (−V
CC
) / (-I
GND
)
where -I
GND
is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in R
GND
(when V
CC
< 0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/ R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND
produces a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output
values. This shift varies depending on how many devices are ON in case of several high
side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).
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DRAFT
Application information VND5T100LAJ-E, VND5T100LAS-E
22/38 DocID023364 Rev 4
3.1.2 Solution 2: diode (D
GND
) in the ground line
A resistor (R
GND
= 4.7 kΩ) should be inserted in parallel to D
GND
if the devi ce drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values, if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
D
ld
is necessary (V oltage Transient Suppressor) if the load dump peak voltage exceeds to
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line
that are greater than the ones shown in the ISO T/R 7637/2 table.
3.3 MCU I/Os pro te c tion
If a ground protection network is used and negative transient are present on the V
CC
line,
the control pins are pulled negative. ST suggests that a resistor (R
prot
) be inserted in line to
prevent the microcontroller I/O pins from latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
CCpeak
/I
latchup
≤ R
prot
≤ (V
OHμC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= -600 V and I
latchup
≥ 20 mA; V
OHμC
≥ 4.5 V
30 kΩ ≤ R
prot
≤ 180 kΩ.
Recommended R
prot
value is 60 kΩ.
DocID023364 Rev 4 23/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Application information
37
3.4 Maximum demagnetization energy (V
CC
= 24 V)
Figure 26. Maximum turn-off current versus inductance
1. Values are generated with R
L
=0 Ω.
In case of repetitive pulses, T
jstart
(at the beginning of each demagnetization) of every pulse must not
exceed the temperature specified above for curves A and B.
C: T
jstart
= 125°C repetitive pulse
A: T
jstart
= 150°C single pulse
B: T
jstart
= 100°C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
V
IN
, I
L
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B
C
DRAFT
Package and PCB thermal data VND5T100LAJ-E, VND5T100LAS-E
24/38 DocID023364 Rev 4
4 Package and PCB thermal data
4.1 PowerSSO-12 thermal data
Figure 27. PowerSSO-12 PC board
1. Layout condition of R
th
and Z
th
measurements (Board finish thickness 1.6 mm +/- 10 %; Board double
layer; Board dimension 77 mm x 86 mm; Board Material FR4; Cu thickness 0.070 mm (front and back
side); Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias
0.025 mm; Footprint dimension 4.1 mm x 6.5 mm)
Figure 28.
R
thj-amb
vs PCB copper area in open box free air condition (one channel ON)
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40
45
50
55
60
65
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DocID023364 Rev 4 25/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Package and PCB thermal data
37
Figure 29. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel ON)
Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-12
1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Equation 1: pulse calculation formula
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THδ
R
TH
δZ
THtp
1δ–()+⋅=
where
δt
p
T⁄=
DRAFT
Package and PCB thermal data VND5T100LAJ-E, VND5T100LAS-E
26/38 DocID023364 Rev 4
Table 15. Thermal para meters
Area/island (cm
2
)Footprint28
R1 = R7 (°C/W) 0.8
R2 = R8 (°C/W) 1.5
R3 (°C/W) 3
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1 = C7 (W.s/°C) 0.0008
C2 = C8 (W.s/°C) 0.005
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
DocID023364 Rev 4 27/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Package and PCB thermal data
37
4.2 SO-16N thermal data
Figure 31. SO-16N PC board
1. Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10%; Board double
layer; Board dimension 129 x 60; Board Material FR4; Cu thickness 0.070mm (front and back side),
Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025
mm).
Figure 32. R
thj-amb
vs PCB copper area in open box free air condition (one channel
ON)
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DRAFT
Package and PCB thermal data VND5T100LAJ-E, VND5T100LAS-E
28/38 DocID023364 Rev 4
Figure 33. SO-16N thermal impe dance junction ambien t single pulse (one channel on)
Figure 34. Thermal fitting model of a double channel HSD in SO -16N
Equation 2:
pulse calculation formula
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Z
THδ
R
TH
δZ
THtp
1δ–()+⋅=
where
δt
p
T⁄=
DocID023364 Rev 4 29/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Package and PCB thermal data
37
Table 16. Thermal para meters
Area/island (cm
2
)Footprint28
R1 = R7 (°C/W) 0.8
R2 = R8(°C/W) 3
R3 (°C/W) 6
R4 (°C/W) 10
R5 (°C/W) 20 14 12
R6 (°C/W) 27 23 14
C1 = C7(W.s/°C) 0.0005
C2 = C8 (W.s/°C) 0.005
C3 (W.s/°C) 0.015
C4 (W.s/°C) 0.1
C5 (W.s/°C) 0.3 0.5 0.5
C6 (W.s/°C) 2.5 5 7
DRAFT
Package and packing information VND5T100LAJ-E, VND5T100LAS-E
30/38 DocID023364 Rev 4
5 Package and packing information
5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
5.2 PowerSSO-12 mechanical data
Figure 35. PowerSSO-12 package dimensions
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DocID023364 Rev 4 31/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Package and packing information
37
Table 17. PowerSSO-12 mechanical data
Symbol Millimeters
Min. Typ. Max.
A 1.250 1.700
A1 0.000 0.100
A2 1.100 1.600
B 0.230 0.410
C 0.190 0.250
D 4.800 5.000
E 3.800 4.000
e 0.800
H 5.800 6.200
h 0.250 0.550
L 0.400 1.270
k0° 8°
X 1.900 2.500
Y 3.600 4.200
ddd 0.100
DRAFT
Package and packing information VND5T100LAJ-E, VND5T100LAS-E
32/38 DocID023364 Rev 4
5.3 SO-16N package information
Figure 36. SO-16N package dimensions
("1($'5
DocID023364 Rev 4 33/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Package and packing information
37
Table 18. SO-16N mechanical data
Symbol Millimeters
Min. Typ. Max.
A1.75
A1 0.10 0.25
A2 1.25
b0.31 0.51
c 017 0.25
D 9.80 9.90 10.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e1.27
h0.25 0.50
L0.40 1.27
k0° 8°
ccc 0.10
DRAFT
Packing information VND5T100LAJ-E, VND5T100LAS-E
34/38 DocID023364 Rev 4
6 Packing information
6.1 PowerSSO-12 packing infor mation
Figure 37. PowerSSO-12 tube shipment (no suffix)
Figure 38. PowerSSO-12 tape and reel shipment (suffix “TR”)
B
A
C
GAPGCFT000123
All dimensions are in mm.
Base q.ty 100
Bulk q.ty 2000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
Base q.ty 2500
Bulk q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (m ax) 18.4
Reel dimensions
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape hole spacing P0 (± 0.1) 4
Comp one nt spac in g P 8
Hole diameter D (± 0.05) 1.5
Hole diameter D1 (min) 1.5
Hole position F (± 0.1) 5.5
Compartment depth K (max) 4.5
Hole spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm mi n
Empty components pockets
saled with cover tape.
User direction of feed
DocID023364 Rev 4 35/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Packing information
37
6.2 SO-16N packing information
Figure 39. SO-16N tube shipment (no suffix)
Figure 40. SO-16N tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base q.ty 50
Bulk q.ty 1000
Tube length (± 0.5) 532
A3.2
B6
C (± 0.1) 0.6
C
B
A
.
REEL DIMENSIONS
All dimensions are in mm.
Base q.ty 1000
Bulk q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max ) 22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
All dimensions are in mm.
Tape width W 16
Tape hole spacing P0 (± 0.1) 4
Compon en t spa cin g P 8
Hole diameter D (± 0.1/-0) 1.5
Hole diameter D1 (min) 1.5
Hole position F ( ± 0.05) 7.5
Compar tm en t de pth K (max) 6.5
Hole spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty component s poc kets
saled with cover tape.
User direction of feed
DRAFT
Order code VND5T100LAJ-E, VND5T100LAS-E
36/38 DocID023364 Rev 4
7 Order code
Table 19. Device summary
Package Order codes
Tube Tape and reel
PowerSSO-12 VND5T100LAJ-E VND5T100LAJTR-E
SO-16N VND5T100LAS-E VND5T100LASTR-E
DocID023364 Rev 4 37/38
DRAFT
VND5T100LAJ-E, VND5T100LAS-E Revision history
37
8 Revision history
Table 20. Document revision history
Date Revision Changes
25-Jun-2 012 1 Initial rele as e.
18-Sep-2013 2 Updated disclaimer.
30-Apr-2014 3 Added SO-16N package and related details.
08-Feb-2016 4
Tabl e 4: Therm al data:
–R
thj-case
: updated values
–R
thj-pin
: added row
Updated Section 5.2: PowerSSO-12 mechanical data and
Section 5.3: SO-16N package information
DRAFT
VND5T100LAJ-E, VND5T100LAS-E
38/38 DocID023364 Rev 4
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