Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
1
Introduction
Multilayer Surface Mount Ceramic Capacitors are constructed by screen printing alter native layers of internal metallic
electrodes onto ceramic dielectric materials and fir ing into a concrete monolithic body, then completed by application of
metal end terminations which are fired to assure per manent bonding with the individual inter nal electrodes.
Multilayer ceramic capacitors have various features such as large capacitance values in small sizes and excellent high
frequency characteristics.
Moreover, chip capacitors can be used on surface mount assembly equipment. Our fully integrated manufacturing and
total quality control systems ensure unprecedented high standards of quality and reliability.
Chip Capacitor Selection
Selection of the most suitable capacitor for any application is based on the following:
Dielectric T ype
The choice of dielectric is largely deter mined by the temperature stability required.
COG (NPO)
Capacitance change with temperature is 0-30ppm/°C which is less than -0.3%°C from -55°C to +125°C .Typical capacitance
change with life is less than -0.1% for NPOs, one-fifth that shown by most other dielectrics. NPO formulations show no aging
characteristics.
X7R
Its temperature var iation of capacitance is within ±15% from -55°C to +125°C.This capacitance change in non-linear.
Z5U
Despite their capacitance instability, Z5U formulations are very popular because of their small size, low ESL, low ESR and
excellent frequency response. These features are particularly important for decoupling application where only a minimum
capacitance value is required.
Y5V
Y5V formulations are for general purpose use in a limited temperature range.They have a wide temperature characteristic
of +22% - 82% capacitance change over the operating temperature range of -30°C to +85°C.Y5Vs high dielectric constant
allows the manufacture of very high capacitance value (up to 22MF) in small physical sizes.
Capacitance V alue & T olerance
Determined by circuit requirements. Note that chip pr ices decrease with lower capacitance value and looser tolerance.
Voltage
Determined by circuit requirements.Units are designed to exceed the withstanding v oltage specification, i.e ., the user need
not incor porate an additional safety margin.
Capacitor Size
Select the smallest unit permitted by the circuit constraints that provides the required capacitance and voltage rating.
Smaller units are generally less expensive : 0805 is the most economical size.
Capacitor T ermination
Termination choice is largely determined b y the chip attachment method.Silver-palladium is adequate f or most applications
involving soldering or solder reflow.
Nickel barrier is standard and recommended for units exposed to repeated solder cycles, to minimize leaching of the
termination.
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
2
Construction Solder (SN/PB) plated outer layer; typical thickness 0.003mm to 0.05 mm
90% solder, 10% lead.
Nickel Barrier Layer (50 Micro-inches Electroplated Nickel min.)
Ag Layer
Inner
Electrodes
Example
Size Code Dielectric Capacitance (pF) Capacitance Voltage Termination Packaging Designates
Tolerance Code EIA Marked
(EIA Code) Parts
GMC21 CG 102 J50 N T M
CG (COG)(NPO)
X7R
Z5U
Y5V
Capacitance values are represented in 3 digits,
and expressed in pF. The first two digits are
significant, and the third is the number of zeros.
The letter “R” is used as a decimal point.
0R5 0.5pF
5R0 5pF
100 10pF
101 100pF
B ±0.1pF for ≤10pF
C ±0.25pF for ≤10pF
D ±0.5pF for ≤10pF
F ±1% for ≤10pF
G±2%
H±3%
J±5%
K ±10%
M ±20%
Z -20%~+80%
16 16 DC
25 25 DC
50 50 DC
100 100 DC
200 200 DC
N Nickel Barr ier
T Card Board Taping
E Embossed Taping
0805 to 2225
*NOTE:Cal-Chip is phasing out mar ked capacitors as it is not cost effective. Our engineers also believe it
weakens the durability of the component over its life due to the laser etching marking techinque used.
Type 0402 0603
Length (L1) mm 1.0±0.05 1.6±0.2
inches 0.04±0.002 0.063±0.008
Width (W) mm 0.5±0.05 0.8±0.2
inches 0.02±0.002 0.031±0.008
Thickness (H) mm 0.5±0.1 0.8±0.2
inches 0.02±0.004 0.031±0.008
Ter mination Band Min Max Min Max
(L2& L3) mm 0.1 0.35 0.1 0.4
inches 0.004 0.014 0.004 0.015
Band Gap (L4) mm 0.3 0.6
(Min) inches 0.012 0.015
Dielectric COG X7R Y5V COG X7R Y5V
Rated Voltage d.c. 25 50 16 25 50 25 50 25 50 100 10 16 25 50 16 25 50
Cap.Range Code Minimum and Maximum capacitance values available
0.5pF 0p5
1.0 1p0
1.2 1p2
1.5 1p5
1.8 1p8
2.2 2p2
2.7 2p7
3.3 3p3
3.9 3p9
4.7 4p7
5.6 5p6
6.8 6p8
8.2 8p2
10 100
12 120
15 150
18 180
22 220
27 270
33 330
39 390
47 470
56 560
68 630
82 820
100 101
120 121
150 151
180 181
220 221
270 271
330 331
390 391
470 471
560 561
680 681
820 821
1.0nF 102
1.2 122
1.5 152
1.8 182
2.2 222
2.7 272
3.3 332
3.9 392
4.7 472
5.6 562
6.8 682
8.2 822
10 103
12 123
15 153
18 183
22 223
27 273
33 333
39 393
47 473
56 563
68 683
82 823
100 104
150 154
220 224
270 274
330 334
390 394
470 474
560 564
680 684
820 824
1.0µF 105
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - Size & Capacitance Table - COG/X7R/Y5V 0402/0603
GMC04 GMC10
3
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - 50/63, 100, 200V - Size & Capacitance Table - Ultra Stable Dielectric COG
CCE Part Number GMC21 GMC29 GMC31 GMC32 GMC43 GMC45 GMC55 GMC57
4
Type 0805 0907 1206 1210 1812 1825 2220 2225
Dimensions
Length (L1) mm 2.0±.03 2.3±0.3 3.2±0.3 3.2±0.3 4.5±0.35 4.5±0.35 5.7±0.4 5.7±0.4
inches 0.08±0.012 0.09±0.012 0.125±0.012 0.125±0.012 0.18±0.014 0.18±0.014 0.225±0.016 0.225±0.016
Width (W) mm 1.25±0.02 1.8±0.3 1.6±0.2 2.5±0.3 3.2±0.3 6.3±0.4 5.0±0.4 6.3±0.4
inches 0.05±0.008 0.071±0.012 0.063±0.008 0.10±0.012 0.125±0.012 0.25±0.016 0.197±0.016 0.25±0.016
Thickness (H) mm 1.3 1.3 1.6 1.8 1.8 1.8 1.8 1.8
inches 0.051 0.051 0.063 0.07 0.07 0.07 0.07 0.07
Ter mination Band Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
(L2& L3) mm 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75
inches 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03
Band Gap (L4) mm 0.5 0.5 1.4 1.4 2.2 2.2 2.9 2.9
(Min) inches 0.019 0.019 0.055 0.055 0.087 0.087 0.114 0.114
Related Voltage d.c.
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
Cap.Range Code Minimum and Maximum capacitance values available
0.5pF 0p5
1.0 1p0
1.2 1p2
1.5 1p5
1.8 1p8
2.2 2p2
2.7 2p7
3.3 3p3
3.9 3p9
4.7 4p7
5.6 5p6
6.8 6p8
8.2 8p2
10 100
12 120
15 150
18 180
22 220
27 270
33 330
39 390
47 470
56 560
68 630
85 820
100 101
120 121
150 151
180 181
220 221
270 271
330 331
390 391
470 471
560 561
680 681
820 821
1.0nF 102
1.2 122
1.5 152
1.8 182
2.2 222
2.7 272
3.3 332
3.9 392
4.7 472
5.6 562
6.8 682
8.2 822
10 103
12 123
15 153
18 183
22 223
27 273
33 333
39 393
47 473
56 563
68 683
82 823
100 104
Notes: 1. Capacitance values to the E24 range also available.
2. Higher capacitance values may be available with a corresponding increase in thickness.
3. Sizes 1005 and 1808 are available as a special requirement.
4. Chips to a specified thickness can be supplied as a special requirement.
Type 0805 0907 1206 1210 1812 1825 2220 2225
Dimensions
Length (L1) mm 2.0±0.3 2.3±0.3 3.2±0.3 3.2±0.3 4.5±0.35 4.5±0.35 5.7±0.4 5.7±0.4
inches 0.08±0.012 0.09±0.012 0.125±0.012 0.125±0.012 0.18±0.014 0.18±0.014 0.225±0.016 0.225±0.016
Width (W) mm 1.25±0.2 1.8±0.3 1.6±0.2 2.5±0.3 3.2±0.3 6.3±0.4 5.0±0.4 6.3±0.4
inches 0.05±0.008 0.071±0.012 0.063±0.008 0.10±0.012 0.125±0.012 0.25±0.016 0.197±0.016 0.25±0.016
Thickness (H) mm 1.3 1.3 1.6 1.8 1.8 1.8 1.8 1.8
inches 0.051 0.051 0.063 0.07 0.07 0.07 0.07 0.07
Ter mination Band Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
(L2& L3) mm 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75
inches 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03
Band Gap (L4) mm 0.5 0.5 1.4 1.4 2.2 2.2 2.9 2.9
(Min) inches 0.019 0.019 0.055 0.055 0.087 0.087 0.114 0.114
Related Voltage d.c.
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
Cap.Range Code Minimum and Maximum capacitance values available
100pF 101
120 121
150 151
180 181
220 221
270 271
330 331
390 391
470 471
560 561
680 681
820 821
1.0nF 102
1.2 122
1.5 152
1.8 182
2.2 222
2.7 272
3.3 332
3.9 392
4.7 472
5.6 562
6.8 682
8.2 822
10 103
12 123
15 153
18 183
22 223
27 273
33 333
39 393
47 473
56 563
68 683
82 823
100 104
120 124
150 154
180 184
220 224
270 274
330 334
390 394
470 474
560 564
680 684
820 824
1.0µF 105
1.2 125
1.5 155
1.8 185
2.2 225
2.7 227
3.3 335
3.9 395
4.7 475
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - 50/63, 100, 200V - Size & Capacitance Table - Stable Dielectric X7R
5
Notes: 1. Higher capacitance values may be available with a corresponding increase in thickness.
2. Sizes 1005 and 1808 are available as a special requirement.
3. Chips to a specified thickness can be supplied as a special requirement.
6
Type 0805 0907 1206 1210 1812 1825 2220 2225
Dimensions
Length (L1) mm 2.0±0.3 2.3±0.3 3.2±0.3 3.2±0.3 4.5±0.35 4.5±0.35 5.7±0.4 5.7±0.4
inches 0.08±0.012 0.09±0.012 0.125±0.012 0.125±0.012 0.18±0.014 0.18±0.014 0.225±0.016 0.225±0.016
Width (W) mm 1.25±0.2 1.8±0.3 1.6±0.2 2.5±0.3 3.2±0.3 6.3±0.4 5.0±0.4 6.3±0.4
inches 0.05±0.008 0.071±0.012 0.063±0.008 0.10±0.012 0.125±0.012 0.25±0.016 0.197±0.016 0.25±0.016
Thickness (H) mm 1.3 1.3 1.6 1.8 1.8 1.8 1.8 1.8
inches 0.051 0.051 0.063 0.07 0.07 0.07 0.07 0.07
Ter mination Band Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
(L2& L3) mm 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75
inches 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03
Band Gap (L4) mm 0.5 0.5 1.4 1.4 2.2 2.2 2.9 2.9
(Min) inches 0.019 0.019 0.055 0.055 0.087 0.087 0.114 0.114
Related Voltage d.c.
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
50 63
100 200
Cap.Range Code Minimum and Maximum capacitance values available
1.0nF 102
1.5 152
2.2 222
3.3 332
4.7 472
6.8 682
10 103
15 153
22 223
33 333
39 393
47 473
56 563
68 683
100 104
150 154
220 224
330 334
470 474
680 684
1.0µF 105
1.5 155
2.2 225
3.3 335
4.7 475
5.6 565
6.8 685
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - 50/63, 100, 200V - Size & Capacitance Table - Stable Dielectric Z5U
CCE Part Number GMC21 GMC29 GMC31 GMC32 GMC43 GMC45 GMC55 GMC57
Notes: 1. Capacitance values to the E12 range also available.
2. Higher capacitance values may be available with a corresponding increase in thickness.
3. Sizes 1005 and 1808 are available as a special requirement.
4. Chips to a specified thickness can be supplied as a special requirement.
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - Size & Capacitance Table - Ultra Stable Dielectric 16 & 25V
COG Dielectric GMC21 GMC31 GMC32 GMC43 GMC55 GMC57
7
Type 0805 1206 1210 1812 2220 2225
Dimensions
Length (L1) mm 2.0±0.3 3.2±0.3 3.2±0.3 4.5±0.35 5.7±0.4 5.7±0.4
inches 0.08±0.012 0.125±0.012 0.125±0.012 0.18±0.014 0.225±0.016 0.225±0.016
Width (W) mm 1.25±0.2 1.6±0.2 2.5±0.3 3.2±0.3 5.0±0.4 6.3±0.4
inches 0.05±0.008 0.063±0.008 0.10±0.012 0.125±0.012 0.197±0.016 0.25±0.016
Thickness (H) mm 1.3 1.6 1.8 1.8 1.8 1.8
inches 0.051 0.063 0.07 0.07 0.07 0.07
Ter mination Band Min Max Min Max Min Max Min Max Min Max Min Max
(L2&L3) mm 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75
inches 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03
Band Gap (L4) mm 0.5 1.4 1.4 2.2 2.9 2.9
(Min) inches 0.019 0.055 0.055 0.087 0.114 0.114
Rated Voltage d.c. 16 25 16 25 16 25 16 25 16 25 16 25
Cap. Range Code Minimum and Maximum capacitance values available
0.5pF 0p5
1.0 1p0
1.2 1p2
1.5 1p5
1.8 1p8
2.2 2p2
2.7 2p7
3.3 3p3
3.9 3p9
4.7 4p7
5.6 5p6
6.8 6p8
8.2 8p2
10 100
12 120
15 150
18 180
22 220
27 270
33 330
39 390
47 470
56 560
68 630
85 820
100 101
120 121
150 151
180 181
220 221
270 271
330 331
390 391
470 471
560 561
680 681
820 821
1.0nF 102
1.2 122
1.5 152
1.8 182
2.2 222
2.7 272
3.3 332
3.9 392
4.7 472
5.6 562
6.8 682
8.2 822
10 103
12 123
15 153
18 183
22 223
27 273
33 333
39 393
47 473
56 563
68 683
82 823
100 104
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - Size & Capacitance Table - Stable Dielectric 10, 16 & 25V
X7R Dielectric GMC21 GMC31 GMC32 GMC43 GMC45 GMC55 GMC57
8
Type 0805 1206 1210 1812 1825 2220 2225
Dimensions
Length (L1) mm 2.0±0.3 3.2±0.3 3.2±0.3 4.5±0.35 4.5±0.35 5.7±0.4 5.7±0.4
inches 0.08±0.012 0.125±0.012 0.125±0.012 0.18±0.014 0.18±0.014 0.225±0.016 0.225±0.016
Width (W) mm 1.25±0.2 1.6±0.2 2.5±0.3 3.2±0.3 6.3±0.4 5.0±0.4 6.3±0.4
inches 0.05±0.008 0.063±0.008 0.10±0.012 0.125±0.012 0.025±0.016 0.197±0.016 0.25±0.016
Thickness (H) mm 1.3 1.6 1.8 1.8 1.8 1.8 1.8
inches 0.051 0.063 0.07 0.07 0.07 0.07 0.07
Termination Band Min Max Min Max Min Max Min Max Min Max Min Max Min Max
(L2&L3) mm 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75
inches 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03
Band Gap (L4) mm 0.5 1.4 1.4 2.2 2.2 2.9 2.9
(Min) inches 0.019 0.055 0.055 0.087 0.087 0.114 0.114
Rated Voltage d.c 10 16 25 10 16 25 16 25 16 25 16 25 16 25 16 25
Cap. Range Code Minimum and Maximum capacitance values available
100pF 101
120 121
150 151
180 181
220 221
270 271
330 331
390 391
470 471
560 561
680 681
820 821
1.0nF 102
1.2 122
1.5 152
1.8 182
2.2 222
2.7 272
3.3 332
3.9 392
4.7 472
5.6 562
6.8 682
8.2 822
10 103
12 123
15 153
18 183
22 223
27 273
33 333
39 393
47 473
56 563
68 683
82 823
100 104
120 124
150 154
180 184
220 224
270 274
330 334
390 394
470 474
560 564
680 684
820 824
1.0µF 105
1.2 125
1.5 155
1.8 185
2.2 225
2.7 275
3.3 335
3.9 395
4.7 475
5.6 565
6.8 685
8.2 825
10 106
15 156
22 226
Type 0805 1206 1210 1812 1825 2220 2225
Dimensions
Length (L1) mm 2.0±0.3 3.2±0.3 3.2±0.3 4.5±0.35 4.5±0.35 5.7±0.4 5.7±0.4
inches 0.08±0.012 0.125±0.012 0.125±0.012 0.18±0.014 0.18±0.014 0.225±0.016 0.225±0.016
Width (W) mm 1.25±0.2 1.6±0.2 2.5±0.3 3.2±0.3 6.3±0.4 5.0±0.4 6.3±0.4
inches 0.05±0.008 0.063±0.008 0.10±0.012 0.125±0.012 0.25±0.016 0.197±0.016 0.25±0.016
Thickness (H) mm 1.3 1.6 1.8 1.8 1.8 1.8 1.8
inches 0.051 0.063 0.07 0.07 0.07 0.07 0.07
Termination Band Min Max Min Max Min Max Min Max Min Max Min Max Min Max
(L2&L3) mm 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75
inches 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03
Band Gap (L4) mm 0.5 1.4 1.4 2.2 2.2 2.9 2.9
(Min) inches 0.019 0.055 0.055 0.087 0.087 0.114 0.114
Rated Voltage d.c 16 25 10 16 25 16 25 16 25 16 25 16 25 16 25
Cap. Range Code Minimum and Maximum capacitance values available
1.0nF 102
1.5 152
2.2 222
3.3 332
4.7 472
6.8 682
10 103
15 153
22 223
33 333
47 473
68 683
100 104
150 154
220 224
330 334
470 474
680 684
1.0µF 105
1.5 155
2.2 225
3.3 335
4.7 475
6.8 685
10 106
15 156
22 226
27 276
33 336
39 396
47 476
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - Size & Capacitance Table - General Purpose Dielectric 10, 16 & 25V
Z5U/Y5V Dielectric GMC21 GMC31 GMC32 GMC43 GMC45 GMC55 GMC57
9
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
10
COG Dielectric
Ultra stable class I dielectr ic: linear temperature coefficient, low loss, negligible change of electrical
proper ties with time, voltage and frequency.
X7R Dielectric
Stable class 11 dielectric (EIA X7R)
Temperature
Operating Temperature Voltage Dissipation Insulation Dielectric Test
Temperature Coefficient Coefficient Factor Resistance withstanding Aging Rate Parameters
Range (∆cMax @ Voltage
VDCW)
-55°C 0±30ppm°C 0±30ppm/°C 0. 1% Max, •25°C, VDCW:: 2.5 X VDCW 0% per •C≤51000pF
to 0.02% Typical >100GΩF or decade hour f=1MHz
+125°C 1000ΩF, V=1.0Vrms
whichever is less ±0.2Vrms
•125°C , VDCW: T=25°C
>10GΩF or •C>1000pF
100ΩF f=1KHz
whichever is less V=1.0Vrms
±0.2Vrms
T=25°C
Temperature
Operating Temperature Voltage Dissipation Insulation Dielectric Test
Temperature Coefficient Coefficient Factor Resistance withstanding Aging Rate Parameters
Range (∆cMax @ Voltage
VDCW)
55°C ±15% X7R 2.5%Max, •25°C,VDCW:: 2.5 X VDCW <2% per 1KHz,
to Not Applicable 1.8% Typical >100GΩFor decade hour 1.OVrms
+125°C 1000ΩF, ±0.2Vrms
whichever is less 25°C
•125°C , VDCW:
>10GΩF or
100ΩF
whichever is less
TEMPERATURE COEFFICIENT
%∆C
0.4
0.0
0.4
-55 - 15 25 65 85 125
0. ± 30pp /*C envelope
typical T.C
Temperature, ˚C
VOLTAGE COEFFICIENT
%∆C
0.2
0.1
0.0
- 0.1
- 0.2
050
100 150 200
Bias Voltage(VDC)
INSULATION RESISTANCE VS TEMP
IR( ΩF)
10K
1K
0.1K 25 50 75 100 125
Temperature, ˚C
Typical I.R
Minimum I.R.
CAPACITANCE VS FREQUENCY
%∆C
0.2
0.1
0.0
- 0.1
- 0.2
10 2103104105106
Frequency, Hz
TEMPERATURE COEFFICIENT
%∆C
15
10
5
0
- 5
- 10
- 15
- 55 -15 25 65 85 125
Temperature ˚C
Permissible TC
Typical TC
VOLTAGE COEFFICIENT
%∆C
5
0
- 5
- 10
- 15
- 20
025
50 75 100
Bias Voltage(VDC)
INSULATION RESISTANCE VS TEMP
IR( Ω F)
10K
1K
0.1K 25 50 75 100 125
Temperature ˚C
Typical I.R.
Minimum I.R.
AGING RATE
%∆C
0
- 5
- 10
- 15
0.1 1.0 10 10 2103104105
Time After Last Curie Point(Hours)
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - Z5U (Y5V) Dielectric
11
High capacitance per unit volume: general pur pose product
Temperature ° C Bias Voltage (VDC) Time after last Curie Point (hours) Test Voltage (Vms)
Packaging (Taping)
(Reel T ype-Size)
Carrier T ape (Standard)
•To peel off the cov er tape by the method sho wn in the right
figure apply a peel-off force of 20 gf - 60 gf (card board);
35 gf - 75 gf (plastic tape).
•The cover tape should not touch the top or bottom of the
chip.
•If the cover tape has been peeled off it may be difficult to
remove the chip due to punch-hole clearance, dirt, and
debris. Make sure therefore that no paper waste will
adhere to and block the absor ption nozzle.
•If the cover tape has been peeled off from the top, stick it
back on with a suitable adhesive.
•Follow the illustration for the star t and end of the winding
operation.
Operating Temperature Dissipation Insulation Dielectric Test
Temperature Coefficient Factor Resistance withstanding Aging Rate Parameters
Range Voltage
-30°C +22% 3.0% Max, 10GΩor 100ΩF 2.5 X VDCW 3.0% per 1KHz,
to -82% 2.0% Typical whichever is decade hour 0.5 Vr ms
+85°C less, 25°C
25°C, VDCW
Standard Reel Unit:mm
ABCDEWtR
Ø178 Ø50 Ø13.0 Ø21.0 2.0 14.9 0.8 1.0
±2.0 min. ±0.5 ±0.8 ±0.5 ±1.5 ±0.2
ABCDEWtR
Ø250 Ø50 Ø13.0 Ø21.0 2.0 10.0 0.8 1.0
±2.0 min. ±0.5 ±0.8 ±0.5 ±1.5 ±0.2
10000 units per reel OPTIONAL Unit:mm
TEMPERATURE COEFFICIENT
%∆C
0
- 20
- 40
- 60
- 90 - 30 25 40 55 70 85
DC VOLTAGE COEFFICIENT
%∆C
0
- 20
- 40
- 60
- 80
025 50 75 100
AGING RATE
%∆C
0
- 5
- 10
- 15
0.1 1.0 10 10 2103104105
AC VOLTAGE COEFFICIENT
%∆C
5.0
4.0
3.0
2.0
1.0
0.0
0 0.1 0.5 10
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
12
Type B F P1P0t1Mounting Quantity
AW E P2D0t2Hole per Reel
0402 0.7±0.2 1.3±0.2 2.0±0.05 10000
0603 1.1±0.2 1.9±0.2 Angular 4000
0805 1.65±0.2 2.4±0.2 8.0±0.3 3.5±0.05 1.75±0.1 4.0±0.1 2.0±0.05 4.0±0.1 Ø1.5+0.1 1.1 max 1.4 max Punch Hole 4000 to 5000*
-0
1206 2.0±0.2 3.6±0.2 4000 to 5000*
Type A B W F E P1P2P0D0t1t2Mounting Quantity
Hole per Reel
0805 1.45±0.2 2.3±0.2 Angular 2000 to 5000*
1206 2.0±0.2 3.6±0.2 8.0±0.3 3.5±0.05 1.75±0.1 4.0±0.1 2.0±0.05 4.0±0.1 Ø1.5+0.1 0.6max 2.5 max Embossed 2000 to 5000*
-0
1210 2.9±0.2 3.6±0.2 Hole 2000 to 4000*
Type A B W F E P1P2P0D0t1t2Mounting Quantity
Hole per Reel
1812 3.6±0.2 4.9±0.2 Angular 1000
1825 6.8±0.3 4.9±0.2 12.0±0.3 5.5±0.05 1.75±0.1 8.0±0.1 2.0±0.05 4.0±0.1 Ø1.5±0. Embossed 1000
2220 5.5±0.3 6.2±0.3 1 0.6 max. 6.5 max. Hole 1000
2225 6.8±0.3 6.2±0.3 1000
• Cardboard carrier tape for 0402, 0603 type and 0805/1206 type Unit: mm
*Dependent on chip thickness
• Embossed plastic carrier tape for 0805/1206 type and 1210 type Unit: mm
*Dependent on chip thickness
• Embossed plastic carrier tape for 1812,1825, 2220 and 2225 type Unit: mm
*Dependent on chip thickness
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors - All Dielectrics
13
Tape and Reel Packing Quantities
The tape and reel packing quantities apply to voltages up to 200V rating only.
The 0402 and 0603 size chips have similar width and thickness dimensions.
Chip Size 178 mm (7") Reel 330 mm (13") Reel
0402 10,000 N/A
0603 4,000 16,000
0805 4,000 12,000
0907 3,000 12,000
1206 4,000 15,000
1210 2,000, 4,000 8,000
1812 1,000 4,000
1825 1,000 4,000
2220 1,000 4,000
2225 1,000 4,000
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Multilayer Ceramic Chip Capacitors
14
•Bulk case packaging can reduce the stock space and transpor tation costs.
•The bulk feeding system can increase the productivity.
•It can eliminate the components loss.
•Structure and Dimension
•Quantity
BULK CASE
Symbol A B T C D E
Dimension 6.8±0.1 8.8±0.1 12±0.1 1.5+0.1, 2+0, 4.7±0.1
-0 -0.1
Symbol F W G H L I
Dimension 31.5+0.2, 36+0. 19±0.35 7±0.35 110±0.7 5±0.35
-0 -0.2
Size 04(0402) 10(0603) 21(0805)
T≤0.85mm T≥1.0mm
Quantity 80,000 15,000 10,000 5,000
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Multilayer Ceramic Chip Capacitors
15
Item Specification Test Method
Capacitance Within tolerance shown •Class (1)
by part number code C<1000pF:1MHz±10%,
0.5 to 5Vrms
Dissipation Factor •Class (I) C≥1000pF:1KHz±10%,
(tanδ
δor Q) C<30pF:Q≥400+20xC C<1000pF:1K1.0±0.2Vrms
C≥30pF:Q≥1000
•Class (II) •Class (II)
B:DF≤2.5% 1KHz±10%, 1.0±0.2Vrms
F:DF≤5.0%
Insulation C≤10,000pF:IR≥100GΩApply rated voltage for 60
Resistance(IR) C>10,000pF:IR≥500/C seconds at room temperature
and normal humidity.
(70% RH max)
Dielectric There shall be no evidence Apply 3 x rated voltage (Class I)
Withstanding of damage or flash over or 2.5 x rated voltage (Class II) to
Voltage during the test both terminations for 5
seconds. Charge and discharge
current are less than 50mA.
Termination No mechanical damage
Adherence
Care shall be taken to avoid
thermal shock. 500g of steady
pull is applied in direction of arrow
for 1 minute.
Bend Strength No mechanical damage After soldering capacitor on the
glass-epoxy PWB, 2 mm of vend-
ing shall be applied for 10 seconds
as shown by drawing.
Life T est •Class (I) Applied 2 x rated voltage at
(High Temperature No more than ±3% or ±0.3pF maximum operating temperature
Loading T est) ∆Cwhichever is less for 1000 hours.The surge current
•Class (II) shall not exceed 50mA after above
B:±10% max testing condition, test samples
F:±30% max shall be kept in room temperature
•Class (I) for 24 hours (Class I) or
C<10pF:Q>200+10xC 48 hours (Class II),
Q10≤C<30pF:Q≥275+5/2xC and then shall be measured.
or C≥30pF:Q≥350
DF •Class (II)
B:DF≤5.0%
F:DF≤7.5%
1000MΩor 50ΩF, min
IR whichever is less
RELIABILITY AND TEST
CONDITIONS
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
16
Item Specification Test Method
Moisture T est •Class (I)
No more than ±5%
or ±0.5pF The capacitors shall be subjected
∆C whichever is larger to 40°C, 90-95%RH for 500 hours.
•Class (II)
B:±l0% After above testing condition, samples
F:±30% shall be kept in room temperature for
•Class (I) 24 hours (Class I) or 48 hours (Class II),
C<10pF:Q>200+10xC and then shall be measured.
Q10≤C<30pF:Q≥275+5/2xC
or C≥30pF:Q≥350
DF •Class (II)
B:DF≤5.0%
F:DF≤7.5%
IR 1000MΩor 50ΩF,
whichever is less
Moisture •Class (I)
Resistance No more than ±7.5%
Test or ±0.75pF
∆C whichever is larger Apply rated voltage at 40°C,
•Class (II) 90-95%RH for 500 hours.
B:±10%
F:±30% The surge current shall not exceed
•Class (I) 50mA. After testing with above condition,
Q C<30pF:Q>100+100/3xC samples shall be kept in room tempera-
or C≥30pF:Q≥200 ture for 24 hours (Class 1) or 48 hours
DF • Class (II) (Class 11), and then shall be measured.
B:DF≤5.0%
F:DF≤7.5%
IR 500MΩor 25ΩF, min
whichever is less
•Class (I) Perform 5 cycles as follow:
Temperature No more than ±2.5% 1. Room temperature. Dwell for 15 minutes.
Cycle or ±0.25pF 2. Minimum operating temperature, dwell for
∆C whichever is larger 30 minutes.
•Class (II) 3. Room temperature, dwell for 30 minutes.
B:±5% 4. Maximum operating temperature, dwell for
F:±20% 30 minutes.
Q To satisfy the specified After above testing condition, samples shall
or initial value. be kept in room temperature for 24 hours
DF (Class I) or 48 hours (Class II), and then shall
IR To satisfy the specified be measured.
initial value.
Solderability Ter mination area shall be at The capacitors are completely
least 95% covered with a new immersed during 4±0.5 seconds
solder coating.There shall be no in the molten solder with a
crack and ceramic exposure of temperature of 230±5°C
terminated surface by melting. *Solder: Sn 63.
Resistance to •Class (I)
Solder Heat Test No more than ±2.5% Immerse into molten solder at
or ±0.25pF 270±5°C for 3±0.5 seconds.
∆C whichever is larger Preheat before immersion.
•Class (II) 1. 80~100°C for 2 minutes.
B:±5% 2.150~180°C for 2 minutes.
F.:±20% 3. 270±5°C for 3±0.5 seconds.
QTo satisfy the specified The capacitance, measurement
or initial value. shall be made after sample
DF. keeping at room temperature for
IR To satisfy the specified 24 hours.
initial value.
RELIABILITY AND TEST
CONDITIONS
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
17
1. Temperature / Humidity Control
Since dew condensation may occur by the differences in temperature when
the products are take out of storage, it is impor tant to maintain a temperature-
controlled environment.
2. Design of Solder Land Pattern
When designing printed circuit boards, the shape and size of the solder lands
must allow for the proper amount of solder on the capacitor.The amount of solder
at the end terminations has a direct effect on the probability that the chip will
crack. The greater amount of solder, the larger amount of stress on the chip, and
the more likely that it will break. Use the following illustrations as guidelines for
proper solder land design.
Recommendation of solder land shape and size.
3. Adhesives
MLCCs generally require the use of an adhesive to adhere the chips to the circuit
board prior to wave soldering.
3-1. Requirements for Adhesives
- They must have enough adhesion so that the chips will not fall off or move
during the handling of the circuit board.
- They must maintain their adhesive strength when exposed to solder ing
temperatures.
- They should not spread or run when applied to the circuit board.
- They should have a long pot life.
- They should harden quickly.
- They should not corrode the circuit board or chip material.
- They should be a good insulator.
- They should be non-toxic, and not produce harmful gases, nor be harmful
when touched.
3-2. Application Method
It is impor tant to use the proper amount of adhesive.Too little will cause poor
adhesion to the circuit board, and too much may strain the conductor patter n,
thereby causing defective soldering.The following illustrations show the proper
quantity of adhesive. (Unit: mm)
3-3. Adhesive Hardening Characteristics
To prevent oxidation of the ter minations, the adhesive must harden at 160°C
or less, within 2 minutes or less.
APPLICATION MANUAL FOR
SURFACE MOUNTING
Type 21 31
a 0.2 min 0.2 min
b 70~100µm 70~100µm
c>0 >0
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
18
4. Mounting
4-1. Mounting Head Pressure
Excessive pressure will cause chip capacitors to crack.The pressure between
nozzle and chip capacitor will be 300g maximum during mounting.
4-2. Bending Stress
Bending of printed circuit board by mounting head when double-sided circuit
boards are used, chip capacitors first are mounted and soldered onto one side of
the board.When the capacitors are mounted onto the other side, it is important
to suppor t the board as shown in the illustration . If the circuit board is not
suppor ted, it may bend, causing the already installed capacitors to crack.
5. Flux
Although highly activated flux gives better solderability, substances which increase
activity may also degrade the insulation of the chip capacitors.To avoid such
degradation, it is recommended that a mildly activated rosin flux (less than 0.2%
chlorine) be used.
6. Soldering
Since a multilayer chip ceramic capacitor comes into direct contact with melted
solder during solder ing, it is exposed to potentially damaging mechanical stress
caused by the sudden temperature change.The capacitor may also be subject to
silver migration, and to contamination by the flux. Because of these factors, soldering
technique is critical.
6-1. Soldering Methods
6-2. Soldering Profile
To avoid the crack problem by sudden temperature change, follow the tempera-
ture profile in the adjacent graph.
Method Classification
Mass • IR/Convection
Reflow reflow • VPS (Vapor phase)
Soldering Selective • Hot air/gas
reflow • Laser
Flow Dual W ave
Soldering
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
19
6-3. Manual Soldering
Manual Soldering can pose a great risk of creating ther mal cracks in chip capacitors.
The hot soldering iron tip comes into direct contact with the end ter minations,
and operator’s carelessness may cause the tip of the solder ing iron to come
into direct contact with the ceramic body of the capacitor.Therefore the soldering
iron must be handled carefully, and close attention must be paid to the selection
of the soldering iron tip and to temperature control of the tip.
6-4. Amount of Solder
Too much Cracks tend to occur
solder due to large stress
Amount of Maximum amount of solder
solder is Minimum amount of solder
adequate
Not enough Weak holding force may
solder cause bad connections or
detaching of the capacitor
6-5. Cooling
Natural cooling using air is recommended. If the chips are dipped into solvent for
cleaning, the temperature difference (∆T) must be less than 100°C.
6-6. Cleaning
If rosin flux is used, cleaning usually is unnecessar y. When strongly activated flux
is used, chlorine in the flux may dissolve into some types of cleaning fluids, there-
by affecting the chip capacitors.This means that the cleaning fluid must be care-
fully selected, and should always be new.
7. Notes for Separating Multiple, Shared PC Boards
A multi-PC board is separated into many individual circuit boards after solder ing has
been completed. If the board is bent or distor ted at the time of separation, cracks
may occur in the chip capacitors. Carefully choose a separation method that
minimizes the bending of the circuit board.
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
20
Recommended Pad Dimensions
*These sizes are recommended for use with IR and vapor phase soldering only.
NOTICE: Specifications are subject to change without notice. Contact your nearest Cal-Chip Sales Office for the latest specifications. All
statements, infor mation and data given herein are believed to be accurate and reliable, but are presented without guarantee, warranty, or
responsibility of any kind, expressed or implied. Statements or suggestions concer ning possible use of our products are made without rep-
resentation or warranty that any such use is free of patent infr ingement and are not recommendations to infringe any patent.The user
should not assume that all safety measures are indicated or that other measures may not be required. Specifications are typical and may
not apply to all applications.
Dimensions (inches)
Chip Size L W S T
0402* 0.021 0.022 0.017 0.059
0603* 0.035 0.030 0.030 0.100
0805 0.040 0.050 0.040 0.120
0907 0.040 0.070 0.050 0.130
1206 0.040 0.065 0.080 0.160
1210 0.040 0.100 0.080 0.160
1812* 0.050 0.120 0.130 0.230
1825* 0.050 0.250 0.130 0.230
2220 0.050 0.250 0.130 0.230
2225* 0.050 0.250 0.170 0.270
3640* 0.060 0.400 0.300 0.420
APPLICATION INFORMATION ON SOLDER PAD DESIGN
FOR SURFACE MOUNT CHIP CAPACITOR
T
(TOTAL LENGTH)
(WIDTH)
W
LSL
(LENGTH) (LENGTH)
(SEPARATION)
Letter 0123 4 5
a2.5
b3.5
d4.0
e4.5
f5.0
m6.0
n7.0
t8.0
y9.0
x1.0 x10 x100 x1000 x10,000 x100,000
Cal-Chip EElleeccttrroonniiccss,, IInnccoorrppoorraatteeddGMC SERIES
Multilayer Ceramic Chip Capacitors
21
Marking
Proposed EIA Standard:
Two Position Marking:*
Alpha: 1st position significant figures of capacitance in pF
Numerical: 2nd position decimal multiplier of capacitance
NOTE: ¥ 0402, 0603, 0907 available unmarked only.
CAPACITANCE
CHIP MARKING IDENTIFICATION SYSTEM
Letter 0123 4 5
A1.0 10 100 1000 10,000 100,000
B1.1 11 110 1100 11,000 110,000
C1.2 12 120 1200 12,000 120,000
D1.3 13 130 1300 13,000 130,000
E1.5 15 150 1500 15,000 150,000
F1.6 16 160 1600 16,000 160,000
G1.8 18 180 1800 18,000 180,000
H2.0 20 200 2000 20,000 200,000
J2.2 22 220 2200 22,000 220,000
K2.4 24 240 2400 24,000 240,000
L2.7 27 270 2700 27,000 270,000
M3.0 30 300 3000 30,000 300,000
N3.3 33 330 3300 33,000 330,000
P3.6 36 360 3600 36,000 360,000
Q3.9 39 390 3900 39,000 390,000
R4.3 43 430 4300 43,000 430,000
S4.7 47 470 4700 47,000 470,000
T5.1 51 510 5100 51,000 510,000
U5.6 56 560 5600 56,000 560,000
V6.2 62 620 6200 62,000 620,000
W6.8 68 680 6800 68,000 680,000
X7.5 75 750 7500 75,000 750,000
Y8.2 82 820 8200 82,000 820,000
Z9.1 91 910 9100 91,000 910,000
