CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N05 Technical Manual S1C60N05 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2004, All rights reserved. Revisions and Additions for this manual Chapter Section Appendices Appendix B Appendix C Page 90 93 Item A/D converter error factors Ratings External dimension Contents Figure B.4 and the explanation were added. The table was revised. The figure was revised. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q : TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP Model number Model name C: microcomputer, digital products Product classification S1: semiconductor Development tools S5U1 C 60R08 D1 1 00 Packing specifications 00: standard packing Version 1: Version 1 Tool type Hx : ICE Ex : EVA board Px : Peripheral board Wx : Flash ROM writer for the microcomputer Xx : ROM writer peripheral board Cx Ax Dx Qx : C compiler package : Assembler package : Utility tool by the model : Soft simulator Corresponding model number 60R08: for S1C60R08 Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products S1C60/62 Family CONTENTS CONTENTS CHAPTER 1 CHAPTER 2 INTRODUCTION ................................................................ 1 1.1 Configuration .................................................................... 1 1.2 Features ........................................................................... 2 1.3 Block Diagram .................................................................. 3 1.4 Pin Layout Diagram .......................................................... 4 1.5 Pin Description ................................................................. 5 POWER SUPPLY AND INITIAL RESET ................................. 6 2.1 Power Supply ................................................................... 6 2.2 Initial Reset ....................................................................... 8 Oscillation detection circuit ....................................... Reset pin (RESET) ..................................................... Simultaneous high input to input ports (K00-K03) .... Internal register following initialization ..................... 2.3 CHAPTER 3 CHAPTER 4 9 9 9 10 Test Pin (TEST) ............................................................... 10 CPU, ROM, RAM ............................................................. 11 3.1 CPU ................................................................................. 11 3.2 ROM ................................................................................ 12 3.3 RAM ................................................................................ 12 PERIPHERAL CIRCUITS AND OPERATION ....................... 13 4.1 Memory Map ................................................................... 13 4.2 Oscillation Circuit ............................................................. 16 Crystal oscillation circuit .......................................... 16 CR oscillation circuit ................................................ 17 S1C60N05 TECHNICAL MANUAL EPSON i CONTENTS 4.3 Input Ports (K00-K03) ..................................................... 18 Configuration of input ports ..................................... Input comparison registers and interrupt function ... Mask option ............................................................. Control of input ports ............................................... 4.4 18 19 20 20 Output Ports (R00-R03) .................................................. 22 Configuration of output ports ................................... 22 Mask option ............................................................. 23 Control of output ports ............................................. 25 4.5 I/O Ports (P00-P03) ........................................................ 28 Configuration of I/O ports ........................................ I/O control register and I/O mode ............................ Mask option ............................................................. Control of I/O ports ................................................. 4.6 LCD Driver (COM0-COM3, SEG0-SEG19) ................... 31 Configuration of LCD driver ...................................... Cadence adjustment of oscillation frequency ............ Mask option (segment allocation) .............................. Control of LCD driver ............................................... 4.7 28 28 29 29 31 37 38 40 Clock Timer ..................................................................... 41 Configuration of clock timer ..................................... 41 Interrupt function .................................................... 42 Control of clock timer ............................................... 43 4.8 A/D Converter .................................................................. 45 Configuration of A/D converter ................................ Operation of A/D converter ...................................... Interrupt function .................................................... Usage example of the A/D converter ......................... Control of A/D converter .......................................... 4.9 45 46 51 51 53 Heavy Load Protection Function ..................................... 57 Operation of heavy load protection function ............. 57 Control of heavy load protection function ................. 58 4.10 Interrupt and HALT .......................................................... 59 Interrupt factors ....................................................... Specific masks and factor flags for interrupt ............. Interrupt vectors ...................................................... Control of interrupt .................................................. ii EPSON 60 61 61 62 S1C60N05 TECHNICAL MANUAL CONTENTS CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM ............................. 63 CHAPTER 6 ELECTRICAL CHARACTERISTICS ..................................... 65 CHAPTER 7 CHAPTER 8 CHAPTER 9 6.1 Absolute Maximum Rating .............................................. 65 6.2 Recommended Operating Conditions ............................. 66 6.3 DC Characteristics .......................................................... 67 6.4 Analog Circuit Characteristics and Power Current Consumption .................................... 69 6.5 Oscillation Characteristics ............................................... 73 PACKAGE ....................................................................... 75 7.1 Plastic Package ............................................................... 75 7.2 Ceramic Package for Test Samples ................................ 76 PAD LAYOUT ................................................................... 77 8.1 Diagram of Pad Layout .................................................... 77 8.2 Pad Coordinates .............................................................. 78 PRECAUTIONS ON MOUNTING ...................................... 79 Oscillation circuit ..................................................... 79 Reset circuit .................................................................... Power supply circuit ................................................. Arrangement of signal lines ............................................. Precautions for visible radiation (when bare chip is mounted) ................................................................. Appendices 79 79 80 80 TECHNICAL INFORMATION ............................................ 81 Appendix A Design Steps for Designing Thermometer ...................... 81 Thermometer design steps ........................................ How to obtain capacitor value and oscillation frequency .. Setting up counter initial value ................................ Computation method of displayed temperature by linear approximation ........................................... S1C60N05 TECHNICAL MANUAL EPSON 81 83 84 85 iii CONTENTS Appendix B Error Factors ................................................................... 87 Thermistor resistance dispersion .............................. A/D converter error factors ...................................... Error by floating capacity ......................................... Software error .......................................................... Appendix C iv 87 87 91 91 AT Thermistor .................................................................. 92 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION Each member of the S1C60N05 Series of single chip microcomputers feature a 4-bit S1C6200B core CPU, 1,536 words of ROM (12 bits per word), 80 words of RAM (4 bits per word), an LCD driver, 4 bits for input ports (K00-K03), 4 bits for output ports (R00-R03), one 4-bit I/O port (P00- P03), clock timer and A/D converter. Because of their low voltage operation and low power consumption, the S1C60N05 Series are ideal for a wide range of applications. 1.1 Configuration The S1C60N05 Series are configured as follows, depending on the supply voltage. Table 1.1.1 Configuration of the S1C60N05 Series S1C60N05 TECHNICAL MANUAL Model Supply voltage Oscillation circuits S1C60N05 1.8-3.5 V Crystal or CR S1C60L05 1.2-2.0 V Crystal or CR EPSON 1 CHAPTER 1: INTRODUCTION 1.2 Features Core CPU S1C6200B Built-in oscillation circuit Crystal or CR oscillation circuit, 32,768 Hz (typ.) Instruction set 100 instructions ROM capacity 1,536 words x 12 bits RAM capacity (data RAM) 80 words x 4 bits Input port 4 bits (Supplementary pull-down resistors may be used) Output port 4 bits (Piezo buzzer and programmable frequency output can be driven directry by mask option) Input/output port 4 bits LCD driver 20 segments x 4 common duty (or 3 and 2 common duty) Timer Clock timer A/D converter CR oscillation type A/D converter built-in (2 channels) Interrupts: External interrupt Input port interrupt Internal interrupt Timer interrupt A/D converter interrupt 1 system 1 system 1 system Supply voltage 1.5 V (1.2-2.0 V) S1C60L05 (During A/D conversion) 3.0 V (1.8-3.5 V) S1C60N05 Current consumption (typ.) 0.8 A (Crystal oscillation CLK = 32,768 Hz, when halted) 1.5 A (Crystal oscillation CLK = 32,768 Hz, when executing) Supply form QFP6-60pin (plastic) or chip 2 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION ROM 1,536 words x 12 bits RESET OSC1 OSC2 1.3 Block Diagram OSC System Reset Control Core CPU S1C6200B RAM 80 words x 4 bits COM0-3 Interrupt Generator LCD Driver SEG0-19 VDD VL1-3 CA-CB VS1 VSS Power Controller ADOUT RS TH1 TH2 CS A/D Converter Input Port Test Port K00-03 I/O Port P00-03 Output Port R00-03 TEST Timer Fig. 1.3.1 Block diagram S1C60N05 TECHNICAL MANUAL EPSON 3 CHAPTER 1: INTRODUCTION 1.4 Pin Layout Diagram QFP6-60pin 45 31 30 46 INDEX 16 60 1 15 Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 N.C. 16 N.C. 31 TEST 46 VL3 2 N.C. 17 ADOUT 32 RESET 47 VL2 3 K00 18 SEG0 33 SEG12 48 VL1 4 K01 19 SEG1 34 SEG13 49 CA 5 K02 20 SEG2 35 SEG14 50 CB 6 K03 21 SEG3 36 SEG15 51 VSS 7 R00 22 SEG4 37 SEG16 52 VDD 8 R01 23 SEG5 38 SEG17 53 OSC1 9 R02 24 SEG6 39 SEG18 54 OSC2 10 R03 25 SEG7 40 SEG19 55 VS1 11 RS 26 SEG8 41 COM0 56 P00 12 TH1 27 SEG9 42 COM1 57 P01 13 TH2 28 SEG10 43 COM2 58 P02 14 CS 29 SEG11 44 COM3 59 P03 15 N.C. 30 N.C. 45 N.C. 60 N.C. N.C. = No connection Fig. 1.4.1 Pin assignment 4 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION 1.5 Pin Description Table 1.5.1 Pin description Terminal name Pin No. Input/Output Function VDD 52 (I) Power source (+) terminal VSS 51 (I) Power source (-) terminal VS1 55 O Oscillation and internal logic system regulated voltage output terminal VL1 48 O LCD system regulated voltage output terminal VL2 47 O LCD system booster output terminal VL3 46 O LCD system booster output terminal 49, 50 - Booster capacitor connecting terminal CA, CB OSC1 53 I Crystal or CR oscillation input terminal OSC2 54 O Crystal or CR oscillation output terminal K00-K03 3-6 I Input terminal P00-P03 56-59 I/O R00-R03 7-10 O Output terminal SEG0-19 18-29 O LCD segment output terminal 33-40 COM0-3 I/O terminal (convertible to DC output terminal by mask option) 41-44 O LCD common output terminal CS 14 I A/D converter CR oscillation input terminal RS 11 O A/D converter CR oscillation output terminal 12, 13 O A/D converter CR oscillation output terminal ADOUT 17 O A/D converter oscillation frequency output terminal RESET 32 I Initial setting input terminal TEST 31 I Test input terminal TH1, TH2 S1C60N05 TECHNICAL MANUAL EPSON 5 CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (*1) supplied to VDD through VSS, the S1C60N05 Series generate the necessary internal voltages with the regulated voltage circuit (<VS1> for oscillators and internal circuit) and the voltage booster/ reducer (<VL2, VL3 or VL1, VL3> for LCDs). When the S1C60N05 LCD power is selected for 4.5 V LCD panel by mask option, the S1C60N05 short-circuits between <VL2> and <VSS> in internally, and the voltage booster/ reducer generates <VL1> and <VL3>. When 3.0 V LCD panel is selected, the S1C60N05 short-circuits between <VL3> and <VSS>, and the voltage reducer generates <VL1> and <VL2>. The S1C60L05 short-circuits between <VL1> and <VSS>, and the voltage booster generates <VL2> and <VL3>. The voltage <VS1> for the internal circuit that is generated by the regulated voltage circuit is -1.2 V (VDD standard). Figure 2.1.1 shows the power supply configuration of the S1C60N05 Series in each condition. *1 Supply voltage: Note - 6 S1C60N05 .... 3.0 V S1C60L05 .... 1.5 V External loads cannot be driven by the output voltage of the regulated voltage circuit and the voltage booster/reducer. See Chapter 6, "ELECTRICAL CHARACTERISTICS", for voltage values. EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET * S1C60N05 4.5 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA C2 C3 C4 C1 3V CB VSS Note: VL2 is shorted to VSS inside the IC. 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/2 bias VDD VS1 VL1 VL2 VL3 CA C2 C3 C4 C1 3V CB VSS C2 C3 C1 3V CB VSS Note: VL3 is shorted to VSS inside the IC. * S1C60L05 4.5 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/2 bias VDD VS1 VL1 VL2 VL3 CA C2 C3 C4 1.5 V C1 CB VSS C2 C3 C1 1.5 V CB VSS Note: VL1 is shorted to VSS inside the IC. Fig. 2.1.1 External element configuration of power system S1C60N05 TECHNICAL MANUAL EPSON 7 CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C60N05 Series circuits, an initial reset must be executed. There are three ways of doing this. (1) Initial reset by the oscillation detection circuit (Note) (2) External initial reset via the RESET pin (3) External initial reset by simultaneous high input to pins K00-K03 (depending on mask option) Figure 2.2.1 shows the configuration of the initial reset circuit. OSC1 OSC1 OSC2 Oscillation circuit Oscillation detection circuit K00 Vss Noise rejection circuit K01 Initial reset Noise rejection circuit K02 K03 RESET Fig. 2.2.1 Configuration of Vss initial reset circuit Note Since the circuit may sometimes not operate normally with the initial resetting by the oscillation detection circuit indicated in number (1), depending on the method of making the power, you should utilize one of the initial resetting methods mentioned in numbers (2) and (3). 8 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET Oscillation detection When the oscillation circuit has been stopped until the oscillation circuit begins to oscillate when the power is circuit turned on or for any other reason, the oscillation detection circuit will output an initial reset signal, but since the circuit may sometimes not operate normally with the initial resetting due to the oscillation detection circuit, depending on the method of making the power, you should utilize one of the initial resetting methods indicated hereafter. Reset pin (RESET) An initial reset can be invoked externally by making the reset pin high. This high level must be maintained for at least 5 ms (when oscillating frequency, fosc = 32 kHz), because the initial reset circuit contains a noise rejection circuit. When the reset pin goes low the CPU begins to operate. Simultaneous high input to input ports (K00-K03) Another way of invoking an initial reset externally is to input a high signal simultaneously to the input ports (K00-K03) selected with the mask option. The specified input port pins must be kept high for at least 4 sec (when oscillating frequency fosc = 32 kHz), because of the noise rejection circuit. Table 2.2.1 shows the combinations of input ports (K00- K03) that can be selected with the mask option. Table 2.2.1 Input port combinations A B C D Not used K00*K01 K00*K01*K02 K00*K01*K02*K03 When, for instance, mask option D (K00*K01*K02*K03) is selected, an initial reset is executed when the signals input to the four ports K00-K03 are all high at the same time. If you use this function, make sure that the specified ports do not go high at the same time during normal operation. S1C60N05 TECHNICAL MANUAL EPSON 9 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Internal register following initialization An initial reset initializes the CPU as shown in the table below. Table 2.2.2 Initial values CPU Core Name Signal Number of bits Setting value Program counter step Program counter page New page pointer Stack pointer Index register X Index register Y Register pointer General register A General register B Interrupt flag Decimal flag Zero flag Carry flag PCS PCP NPP SP X Y RP A B I D Z C 8 4 4 8 8 8 4 4 4 1 1 1 1 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral circuits Name Number of bits Setting value 80 x 4 20 x 4 - Undefined Undefined *1 RAM Display memory Other peripheral circuit *1: See Section 4.1, "Memory Map" 2.3 Test Pin (TEST) This pin is used when IC is inspected for shipment. During normal operation connect it to VSS. 10 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N05 Series employs the S1C6200B core CPU, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the S1C6200B. Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B. Note the following points with regard to the S1C60N05 Series: (1) The SLEEP operation is not provided, so the SLP instruction cannot be used. (2) Because the ROM capacity is 1,536 words, 12 bits per word, bank bits are unnecessary, and PCB and NBP are not used. (3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is invalid. PUSH POP LD LD S1C60N05 TECHNICAL MANUAL XP XP XP,r r,XP EPSON PUSH POP LD LD YP YP YP,r r,YP 11 CHAPTER 3: CPU, ROM, RAM 3.2 ROM The built-in ROM, a mask ROM for the program, has a capacity of 1,536 x 12-bit steps. The program area is 6 pages (0-5), each consisting of 256 steps (00H-FFH). After an initial reset, the program start address is page 1, step 00H. The interrupt vector is allocated to page l, steps 01H- 07H. Bank 0 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 4 page 5 page 07H step 08H step Program area FFH step Fig. 3.2.1 12 bits ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 80 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H-00FH is the memory area pointed by the register pointer (RP). 12 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N05 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C60N05 Series has an address space of 137 words, of which 32 words are allocated to display memory and 25 words, to I/O memory. Figure 4.1.1 show the overall memory map for the S1C60N05 Series, and Tables 4.1.1(a) and (b), the memory maps for the peripheral circuits (I/O space). Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 RAM area (000H-04FH) 80 words x 4 bits (R/W) 3 4 5 6 0 7 8 Display memory area (090H-0AFH) 32 words x 4 bits (Write only) 9 A B C D E F I/O memory area Table 4.1.1(a), (b) Fig. 4.1.1 Unused area Memory map Note Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C60N05 TECHNICAL MANUAL EPSON 13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(a) I/O memory map Address D3 Register D2 D1 D0 K03 K02 K01 K00 TM1 TM0 TC1 TC0 TC5 TC4 TC9 TC8 TC13 TC12 EIK01 EIK00 0E0H R TM3 TM2 0E3H R TC3 TC2 0E4H R/W TC7 TC6 0E5H R/W TC11 TC10 0E6H R/W TC15 TC14 0E7H R/W EIK03 EIK02 0E8H R/W 0 EIT2 EIT8 EIT32 0EBH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 IK0 0EDH R 0 IT2 IT8 0EFH R *1 *2 *3 *4 *5 *6 14 IT32 Name K03 K02 K01 K00 TM3 TM2 TM1 TM0 TC3 TC2 TC1 TC0 TC7 TC6 TC5 TC4 TC11 TC10 TC9 TC8 TC15 TC14 TC13 TC12 EIK03 EIK02 EIK01 EIK00 0 EIT2 EIT8 EIT32 0 0 0 EIAD 0 0 0 IK0 0 IT2 IT8 IT32 Init *1 - *2 - *2 - *2 - *2 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 0 0 0 0 Comment 1 High High High High High High High High 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 Low Low Low Low Low Low Low Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mask Mask Mask Mask Input port data K03 Input port data K02 Input port data K01 Input port data K00 Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz Up/down counter data TC3 Up/down counter data TC2 Up/down counter data TC1 Up/down counter data TC0 (LSB) Up/down counter data TC7 Up/down counter data TC6 Up/down counter data TC5 Up/down counter data TC4 Up/down counter data TC11 Up/down counter data TC10 Up/down counter data TC9 Up/down counter data TC8 Up/down counter data TC15 (MSB) Up/down counter data TC14 Up/down counter data TC13 Up/down counter data TC12 Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz *5 0 0 0 *5 *5 *5 0 Enable Mask Interrupt mask register (A/D) *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) 0 0 0 Yes Yes Yes No No No Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *5 *4 *4 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(b) I/O memory map Address D3 0 Register D2 D1 0 0F0H CHTH 0 0F1H R/W R03 R02 P03 P02 0F3H 0F4H C3 C2 0F5H C7 C6 0F6H C11 C10 0F7H C15 C14 0F8H 0 0 0F9H R HLMOD 0 0FAH R/W CSDC 0 0FBH R/W 0 0 0FCH R XBZR 0 0FDH R/W R 0 0 0FEH R S1C60N05 TECHNICAL MANUAL D0 Name 0 0 IAD 0 0 R IAD CHTH 0 ADRUN 0 0 R/W R ADRUN R03 R00 R01 R02 BUZZER FOUT R01 BUZZER R/W R00 FOUT P03 P00 P01 P02 P01 R/W P00 C3 C0 C1 C2 C1 R/W C0 C7 C4 C5 C6 C5 R/W C4 C11 C8 C9 C10 C9 R/W C8 C15 C12 C13 C14 C13 R/W C12 0 0 TMRST 0 0 W TMRST HLMOD 0 0 0 0 R 0 CSDC 0 0 0 0 R 0 0 0 IOC 0 0 R/W IOC XBZR XFOUT1 XFOUT0 0 XFOUT1 R/W XFOUT0 0 0 ADCLK 0 0 R/W ADCLK Init *1 1 0 Comment *5 *5 *5 Yes TH2 0 0 No TH1 Interrupt factor flag (A/D) A/D channel selection *4 *5 *5 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - - - - - *2 *2 *2 *2 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 Start High High High On High On High High High High 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Stop Low Low Low Off Low Off Low Low Low Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A/D conversion Start/Stop Output port data R03 Output port data R02 Output port data R01 Buzzer On/Off control register Output port data R00 Frequency output control register I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 Up-counter data C3 Up-counter data C2 Up-counter data C1 Up-counter data C0 (LSB) Up-counter data C7 Up-counter data C6 Up-counter data C5 Up-counter data C4 Up-counter data C11 Up-counter data C10 Up-counter data C9 Up-counter data C8 Up-counter data C15 (MSB) Up-counter data C14 Up-counter data C13 Up-counter data C12 *5 *5 *5 Reset 0 Reset Heavy - Normal Clock timer reset Heavy load protection mode register *5 *5 *5 *5 0 Static Dynamic LCD drive switch *5 *5 *5 *5 *5 *5 0 0 Out 2 kHz In 4 kHz I/O port I/O control register Buzzer frequency control *5 FOUT frequency control FOUT frequency control 0 0 *6 *6 *5 *5 *5 0 EPSON 65 kHz 32 kHz A/D clock selection 65 kHz/32 kHz 15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.2 Oscillation Circuit The S1C60N05 Series has a built-in oscillation circuit. For the oscillation circuit, eiter crystal oscillation or CR oscillation may be selected by a mask option. Crystal oscillation circuit The crystal oscillation circuit generates the operating clock for the CPU and peripheral circuit on connection to an external crystal oscillator (typ. 32.768 kHz) and trimmer capacitor (5-25 pF). Figure 4.2.1 is the block diagram of the crystal oscillation circuit. V DD CG OSC2 Fig. 4.2.1 RD To CPU and peripheral circuits Rf X'tal OSC1 V DD CD The S1C60N05 Series Crystal oscillation circuit As Figure 4.2.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) between the OSC1 and OSC2 pins and the trimmer capacitor (CG) between the OSC1 and VDD pins. 16 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) CR oscillation circuit For the S1C60N05 Series, CR oscillation circuit (typ. 65 kHz) may be selected by a mask option. Figure 4.2.2 is the block diagram of the CR oscillation circuit. OSC1 To CPU and peripheral circuits RCR OSC2 Fig. 4.2.2 CR oscillation circuit C The S1C60N05 Series As Figure 4.2.2 indicates, the CR oscillation circuit can be configured simply by connecting the register (RCR) between pins OSC1 and OSC2 since capacity (C) is built-in. See Chapter 6, "ELECTRICAL CHARACTERISTICS" for RCR value. S1C60N05 TECHNICAL MANUAL EPSON 17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3 Input Ports (K00-K03) Configuration of input ports The S1C60N05 Series has a general-purpose input (4 bits). Each of the input port pins (K00-K03) has an internal pulldown resistance. The pull-down resistance can be selected for each bit with the mask option. Figure 4.3.1 shows the configuration of input port. Interrupt request K0x Data bus VDD Address VSS Fig. 4.3.1 Configuration of input port Mask option Selecting "pull-down resistance enabled" with the mask option allows input from a push button, key matrix, and so forth. When "pull-down resistance disabled" is selected, the port can be used for slide switch input and interfacing with other LSIs. 18 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Input comparison registers and interrupt function All four input port bits (K00-K03) provide the interrupt function. The conditions for issuing an interrupt can be set by the software for the four bits. Also, whether to mask the interrupt function can be selected individually for all four bits by the software. Figure 4.3.2 shows the configuration of K00-K03. K0x One for each pin series Data bus Address Noise rejector Interrupt factor flag (IK) Interrupt request Address Mask option (K00-K03) Interrupt mask register (EIK) Address Fig. 4.3.2 Input interrupt circuit configuration (K00-K03) The interrupt mask registers (EIK00-EIK03) enable the interrupt mask to be selected individually for K00-K03. An interrupt occurs when the input value which are not masked change and the interrupt factor flag (IK0) is set to "1". S1C60N05 TECHNICAL MANUAL EPSON 19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) The contents that can be selected with the input port mask option are as follows: Mask option (1) An internal pull-down resistance can be selected for each of the four bits of the input ports (K00-K03). Having selected "pull-down resistance disabled", take care that the input does not float. Select "pull-down resistance enabled" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring through noise. The mask option enables selection of the noise rejection circuit for each separate pin series. When "use" is selected, a maximum delay of 0.5 ms (fosc = 32 kHz) occurs from the time an interrupt condition is established until the interrupt factor flag (IK) is set to "1". Control of input ports Table 4.3.1 list the input port control bits and their addresses. Table 4.3.1 Input port control bits Address D3 Register D2 D1 D0 K03 K02 K01 K00 EIK01 EIK00 0E0H R EIK03 EIK02 0E8H R/W 0 0 0 0EDH R *1 *2 *3 *4 *5 *6 20 IK0 Name K03 K02 K01 K00 EIK03 EIK02 EIK01 EIK00 0 0 0 IK0 Init *1 - *2 - *2 - *2 - *2 0 0 0 0 1 High High High High Enable Enable Enable Enable 0 Low Low Low Low Mask Mask Mask Mask Comment Input port data K03 Input port data K02 Input port data K01 Input port data K00 Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K00-K03 Input port data (0E0H) The input data of the input port pins can be read with these registers. When "1" is read: When "0" is read: Writing: High level Low level Invalid The value read is "1" when the pin voltage of the four bits of the input ports (K00-K03) goes high (VDD), and "0" when the voltage goes low (VSS). These bits are reading, so writing cannot be done. EIK00-EIK03 Interrupt mask registers (0E8H) Masking the interrupt of the input port pins can be done with these registers. When "1" is written: When "0" is written: Reading: Enable Mask Valid With these registers, masking of the input port bits can be done for each of the four bits. After an initial reset, these registers are all set to "0". IK0 Interrupt factor flags (0EDH D0) These flags indicate the occurrence of an input interrupt. When "1" is read: When "0" is read: Interrupt has occurred Interrupt has not occurred Writing: Invalid The interrupt factor flag IK0 is associated with K00-K03, respectively. From the status of these flags, the software can decide whether an input interrupt has occurred. These flags are reset when the software has read them. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. After an initial reset, these flags are set to "0". S1C60N05 TECHNICAL MANUAL EPSON 21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.4 Output Ports (R00-R03) Configuration of output ports The S1C60N05 Series has 4 bits for general output ports (R00-R03). Output specifications of the output ports can be selected individually with the mask option. Three kinds of output specifications are available: complementary output and Pch open drain output. Also, the mask option enables the output ports R00 and R01 to be used as special output ports. Figure 4.4.1 shows the configuration of the output ports. Data bus VDD Register R0x Complementary Pch open drain Address VSS Fig. 4.4.1 Configuration of output ports 22 Mask option EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) The mask option enables the following output port selection. Mask option (1) Output specifications of output ports The output specifications for the output ports (R00-R03) may be either complementary output or Pch open drain output for each of the four bits. However, even when Pch open drain output is selected, a voltage exceeding the source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for output ports R00 and R01, as shown in Table 4.4.1. Figure 4.4.2 shows the structure of output ports R00-R03. Data bus Table 4.4.1 Special output Pin name When special output is selected R00 FOUT or BUZZER R01 BUZZER Register (R03) R03 Register (R02) R02 BUZZER Register (R01) R01 BUZZER Register (R00) Fig. 4.4.2 Structure of output port R00-R03 S1C60N05 TECHNICAL MANUAL R00 FOUT Address (0F3H) Mask option EPSON 23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) FOUT (R00) When output port R00 is set for FOUT output, this port will generate fosc (CPU operating clock frequency) or clock frequency divided into fosc. Clock frequency may be selected individually for F1-F4, from among 5 types by mask option; one among F1-F4 is selected by software and used. The types of frequency which may be selected are shown in Table 4.4.2. Table 4.4.2 FOUT clock frequency Clock frequency (Hz) Setting value fosc = 32,768 F1 F2 F3 F4 (D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1) 1 256 (fosc/128) 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 2 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 3 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 4 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 5 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 32,768 (fosc/1) (D1, D0) = (XFOUT1, XFOUT0) Note A hazard may occur when the FOUT signal is turned on or off. BUZZER, BUZZER Output ports R01 and R00 may be set to BUZZER output (R01, R00) and BUZZER output (BUZZER reverse output), respectively, allowing for direct driving of the piezo-electric buzzer. BUZZER output (R00) may only be set if R01 is set to BUZZER output. In such case, whether ON/OFF of the BUZZER output is done through R00 register or is controlled through R01 simultaneously with BUZZER output is also selected by mask option. The frequency of buzzer output may be selected by software to be either 2 kHz or 4 kHz. Note A hazard may occur when the BUZZER signal is turned on or off. 24 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Control of output ports Table 4.4.3 lists the output port control bits and their addresses. Table 4.4.3 Control bits of output ports Address D3 R03 0F3H XBZR 0FDH R/W *1 *2 *3 *4 *5 *6 Register D2 D1 D0 Name R03 R00 R01 R02 R02 BUZZER FOUT R01 BUZZER R/W R00 FOUT XBZR 0 XFOUT1 XFOUT0 0 XFOUT1 R R/W XFOUT0 Init *1 0 0 0 0 0 0 0 1 High High High On High On 2 kHz 0 Low Low Low Off Low Off 4 kHz Comment Output port data R03 Output port data R02 Output port data R01 Buzzer On/Off control register Output port data R00 Frequency output control register Buzzer frequency control *5 0 0 FOUT frequency control FOUT frequency control *6 *6 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual R00-R03 Output port data (0F3H) Sets the output data for the output ports. When "1" is written: When "0" is written: Reading: High output Low output Valid The output port pins output the data written to the corresponding registers (R00-R03) without changing it. When "1" is written to the register, the output port pin goes high (VDD), and when "0" is written, the output port pin goes low (VSS). After an initial reset, all registers are set to "0". S1C60N05 TECHNICAL MANUAL EPSON 25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00 (when FOUT Special output port data (0F3H D0) is selected) Controls the FOUT (clock) output. When "1" is written: When "0" is written: Reading: Clock output Low level (DC) output Valid FOUT output can be controlled by writing data to R00. After an initial reset, this register is set to "0". Figure 4.4.3 shows the output waveform for FOUT output. R00 register Fig. 4.4.3 FOUT output waveform 0 1 FOUT output waveform XFOUT0, XFOUT1 FOUT frequency control (0FDH D0, 0FDH D1) Selects the output frequency when R00 port is set for FOUT output. Table 4.4.4 FOUT frequency selection XFOUT1 XFOUT0 Frequency selection 0 0 F1 0 1 F2 1 0 F3 1 1 F4 After an initial reset, these registers are set to "0". 26 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00, R01 (when BUZZER Special output port data (0F3H D0, 0F3H D1) and BUZZER Controls the buzzer output. is selected) When "1" is written: Buzzer output When "0" is written: Low level (DC) output Reading: Valid BUZZER and BUZZER output can be controlled by writing data to R00 and R01. When BUZZER output by R01 register control is selected by mask option, BUZZER output and BUZZER output can be controlled simultaneously by writing data to R01 register. After an initial reset, these registers are set to "0". Figure 4.4.4 shows the output waveform for buzzer output. R01 (R00) register 0 1 BUZZER output waveform Fig. 4.4.4 Buzzer output waveform BUZZER output waveform XBZR Buzzer frequency control (0FDH D3) Selects the frequency of the buzzer signal. When "1" is written: When "0" is written: Reading: 2 kHz 4 kHz Valid When R00 and R01 port is set to buzzer output, the frequency of the buzzer signal can be selected by this register. When "1" is written to this register, the frequency is set in 2 kHz, and in 4 kHz when "0" is written. After an initial reset, this register is set to "0". S1C60N05 TECHNICAL MANUAL EPSON 27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.5 I/O Ports (P00-P03) The S1C60N05 Series has a 4-bit general-purpose I/O port. Figure 4.5.1 shows the configuration of the I/O port. The four bits of the I/O port P00-P03 can be set to either input mode or output mode. The mode can be set by writing data to the I/O control register (IOC). Data bus Configuration of I/O ports Input control Register P0x Address Fig. 4.5.1 Configuration of I/O port I/O control register and I/O mode Address I/O control register (IOC) VSS Input or output mode can be set for the four bits of I/O port P00-P03 by writing data into I/O control register IOC. To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, its impedance becomes high and it works as an input port. However, the input line is pulled down when input data is read. The output mode is set when "1" is written to the I/O control register (IOC). When an I/O port set to output mode works as an output port, it outputs a high signal (VDD) when the port output data is "1", and a low signal (VSS) when the port output data is "0". After an initial reset, the I/O control register is set to "0", and the I/O port enters the input mode. 28 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Mask option The output specification during output mode (IOC = "1") of the I/O port can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of the I/O port. However, when Pch open drain output has been selected, voltage in excess of the supply voltage must not be applied to the port. Control of I/O ports Table 4.5.1 lists the I/O port control bits and their addresses. Table 4.5.1 I/O port control bits Address D3 Register D2 D1 D0 P03 P02 P01 P00 0 IOC 0F4H R/W 0 0 0FCH R *1 *2 *3 *4 *5 *6 R/W Name P03 P02 P01 P00 0 0 0 IOC Init *1 - *2 - *2 - *2 - *2 1 High High High High 0 Low Low Low Low Comment I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 *5 *5 *5 0 Out In I/O port I/O control register Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual P00-P03 I/O port data (0F4H) I/O port data can be read and output data can be written through the port. * When writing data When "1" is written: When "0" is written: High level Low level When an I/O port is set to the output mode, the written data is output from the I/O port pin unchanged. When "1" is written as the port data, the port pin goes high (VDD), and when "0" is written, the level goes low (VSS). Port data can also be written in the input mode. S1C60N05 TECHNICAL MANUAL EPSON 29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) * When reading data When "1" is read: When "0" is read: High level Low level The pin voltage level of the I/O port is read. When the I/ O port is in the input mode the voltage level being input to the port pin can be read; in the output mode the output voltage level can be read. When the pin voltage is high (VDD) the port data read is "1", and when the pin voltage is low (VSS) the data is "0". Also, the built-in pulldown resistance functions during reading, so the I/O port pin is pulled down. Note - - When the I/O port is set to the output mode and a low-impedance load is connected to the port pin, the data written to the register may differ from the data read. When the I/O port is set to the input mode and a low-level voltage (Vss) is input by the built-in pull-down resistance, an erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistance load is greater than the read-out time. When the input data is being read, the time that the input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the pins must settle within 0.5 cycles. If this condition cannot be met, some measure must be devised, such as arranging a pull-down resistance externally, or performing multiple read-outs. IOC I/O control register (0FCH D0) The input or output I/O port mode can be set with this register. When "1" is written: When "0" is written: Reading: Output mode Input mode Valid The input or output mode of the I/O port is set in units of four bits. For instance, IOC sets the mode for P00-P03. Writing "1" to the I/O control register makes the I/O port enter the output mode, and writing "0", the input mode. After an initial reset, the IOC register is set to "0", so the I/O port is in the input mode. 30 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6 LCD Driver (COM0-COM3, SEG0-SEG19) Configuration of LCD The S1C60N05 Series has four common pins and 20 (SEG0- SEG19) segment pins, so that an LCD with a maximum of driver 80 (20 x 4) segments can be driven. The power for driving the LCD is generated by the CPU internal circuit, so there is no need to supply power externally. The driving method is 1/4 duty (or 1/3, 1/2 duty by mask option) dynamic drive, adopting the four types of potential (1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias dynamic drive that uses three types of potential, VDD, VL1 = VL2 and VL3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). 1/2 bias drive is effective when the LCD system regulated voltage circuit is not used. The VL1 terminal and the VL2 terminal should be connected outside of the IC. The frame frequency is 32 Hz for 1/4 duty and 1/2 duty, and 42.7 Hz for 1/3 duty (in the case of fosc = 32.768 kHz). Figure 4.6.1 shows the drive waveform for 1/4 duty (1/3 bias), Figure 4.6.2 shows the drive waveform for 1/3 duty (1/3 bias), Figure 4.6.3 shows the drive waveform for 1/2 duty (1/3 bias), Figure 4.6.4 shows the drive waveform for 1/4 duty (1/2 bias), Figure 4.6.5 shows the drive waveform for 1/3 duty (1/2 bias) and Figure 4.6.6 shows the drive waveform for 1/2 duty (1/2 bias). Note fosc indicates the oscillation frequency of the oscillation circuit. S1C60N05 TECHNICAL MANUAL EPSON 31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 -VDD -VL1 -VL2 -VL3 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0-19 COM2 Not lit Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0-19 Fig. 4.6.1 Drive waveform for Frame frequency 1/4 duty (1/3 bias) 32 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 -VDD -VL1 -VL2 -VL3 LCD lighting status COM0 COM1 COM2 COM1 SEG0-19 COM2 Not lit Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0-19 Fig. 4.6.2 Drive waveform for Frame frequency 1/3 duty (1/3 bias) S1C60N05 TECHNICAL MANUAL EPSON 33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1 -VL2 -VL3 COM0 LCD lighting status COM0 COM1 SEG0-19 COM1 Not lit COM2 Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0-19 Fig. 4.6.3 Frame frequency Drive waveform for 1/2 duty (1/3 bias) 34 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0-19 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0-19 Fig. 4.6.4 Drive waveform for Frame frequency 1/4 duty (1/2 bias) S1C60N05 TECHNICAL MANUAL EPSON 35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0-19 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0-19 Fig. 4.6.5 Drive waveform for Frame frequency 1/3 duty (1/2 bias) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 SEG0-19 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0-19 Fig. 4.6.6 Drive waveform for 1/2 duty (1/2 bias) 36 Frame frequency EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Cadence adjustment of oscillation frequency In the S1C60N05 Series, the LCD drive duty can be set to 1/1 duty by software. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the OSC circuit. The procedure to set to 1/1 duty drive is as follows: Write "1" to the CSDC register at address "0FBH D3". Write the same value to all registers corresponding to COMs 0 through 3 of the display memory. The frame frequency is 32 Hz (fOSC1/1,024, when fOSC1 = 32.768 kHz). Note - - Even when l/3 or 1/2 duty is selected by the mask option, the display data corresponding to all COM are valid during 1/1 duty driving. Hence, for 1/1 duty drive, set the same value for all display memory corresponding to COMs 0 through 3. For cadence adjustment, set the display data corresponding to COMs 0 through 3, so that all the LCD segments go on. Figure 4.6.7 shows the 1/1 duty drive waveform (1/3 bias). Figure 4.6.8 shows the 1/1 duty drive waveform (1/2 bias). LCD lighting status -VDD -VL1 -VL2 -VL3 COM 0-3 COM0 COM1 COM2 COM3 Frame frequency SEG0-19 Not lit Lit -VDD -VL1 -VL2 -VL3 SEG 0-19 Fig. 4.6.7 1/1 duty drive waveform -VDD -VL1 -VL2 -VL3 (1/3 bias) LCD lighting status -VDD -VL1, VL2 -VL3 COM 0-3 SEG0-19 Not lit Lit Frame frequency -VDD -VL1, VL2 -VL3 SEG 0-19 -VDD -VL1, VL2 -VL3 Fig. 4.6.8 1/1 duty drive waveform (1/2 bias) S1C60N05 TECHNICAL MANUAL COM0 COM1 COM2 COM3 EPSON 37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (1) Segment allocation Mask option (segment allocation) As shown in Figure 4.l.1, the S1C60N05 Series display data is decided by the display data written to the display memory (write-only) at address "090H-0AFH". The address and bits of the display memory can be made to correspond to the segment pins (SEG0-SEG19) in any combination through mask option. This simplifies design by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.6.9 shows an example of the relationship between the LCD segments (on the panel) and the display memory in the case of 1/3 duty. Address Common 0 Common 1 Common 2 9A, D0 9B, D1 9B, D0 (a) (f) (e) SEG11 9A, D1 9B, D2 9A, D3 (b) (g) (d) SEG12 9D, D1 9A, D2 9B, D3 (f') (c) (p) Data D3 D2 D1 D0 09AH d c b a 09BH p g f e 09CH d' c' b' a' 09DH p' g' f' e' SEG10 Display data memory allocation Pin address allocation a a' b f g' g e c c' e' p d SEG10 b' f' SEG11 p' d' SEG12 Common 0 Common 1 Fig. 4.6.9 Segment allocation 38 Common 2 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (2) Drive duty According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty. Table 4.6.1 shows the differences in the number of segments according to the selected duty. Table 4.6.1 Differences according to selected duty Duty Pins used in common Maximum number of segments Frame frequency (when fosc = 32 kHz) 1/4 1/3 1/2 COM0-3 COM0-2 COM0-1 80 (20 x 4) 60 (20 x 3) 40 (20 x 2) 32 Hz 42.7 Hz 32 Hz (3) Output specification The segment pins (SEG0-SEG19) are selected by mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment pin is output. When DC output is selected, either complementary output or Pch open drain output can be selected for each pin by mask option. Note The pin pairs are the combination of SEG (2*n) and SEG (2*n + 1) (where n is an integer from 0 to 9). (4) Drive bias For the drive bias of the S1C60N05 or the S1C60L05, either 1/3 bias or 1/2 bias can be selected by the mask option. S1C60N05 TECHNICAL MANUAL EPSON 39 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Table 4.6.2 shows the control bits of the LCD driver and their addresses. Figure 4.6.10 shows the display memory map. Control of LCD driver Table 4.6.2 Control bits of LCD driver Address Register D2 D1 D3 CSDC 0 D0 0 0 0FBH R/W *1 *2 *3 *4 *5 *6 Init *1 0 Name CSDC 0 0 0 R 1 Static 0 Dynamic Comment LCD drive switch *5 *5 *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual Address 0 1 2 3 4 5 6 7 8 9 A B C D E F Fig. 4.6.10 Display memory map 090 Display memory (Write only) 32 words x 4 bits 0A0 CSDC LCD drive switch (0FBH D3) The LCD drive format can be selected with this switch. When "1" is written: When "0" is written: Reading: Static drive Dynamic drive Valid After an initial reset, dynamic drive (CSDC = "0") is selected. Display memory (090H-0AFH) The LCD segments are turned on or off according to this data. When "1" is written: When "0" is written: Reading: On Off Invalid By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be turned on or off. After an initial reset, the contents of the display memory are undefined. 40 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.7 Clock Timer Configuration of clock timer The S1C60N05 Series has a built-in clock timer driven by the source oscillator. The clock timer is configured as a seven-bit binary counter that serves as a frequency divider taking a 256 Hz source clock from a prescaler. The four high-order bits (16 Hz-2 Hz) can be read by the software. Figure 4.7.1 is the block diagram of the clock timer. Data bus OSC 256 Hz (oscillation circuit) 128 Hz-32 Hz 16 Hz-2 Hz 32 Hz, 8 Hz, 2 Hz Fig. 4.7.1 Block diagram of Clock timer reset signal clock timer Interrupt control Interrupt request Normally, this clock timer is used for all kinds of timing purpose, such as clocks. S1C60N05 TECHNICAL MANUAL EPSON 41 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) The clock timer can interrupt on the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The software can mask any of these interrupt signals. Figure 4.7.2 is the timing chart of the clock timer. Interrupt function Address 0E3H Register Frequency bits D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz Clock timer timing chart Occurrence of 32 Hz interrupt request Occurrence of 8 Hz interrupt request Occurrence of 2 Hz interrupt request Fig. 4.7.2 Timing chart of the clock timer As shown in Figure 4.7.2, an interrupt is generated on the falling edge of the 32 Hz, 8 Hz, and 2 Hz frequencies. When this happens, the corresponding interrupt event flag (IT32, IT8, IT2) is set to "1". Masking the separate interrupts can be done with the interrupt mask register (EIT32, EIT8, EIT2). However, regardless of the interrupt mask register setting, the interrupt event flags will be set to "1" on the falling edge of their corresponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to "1"). Note Write to the interrupt mask register (EIT32, EIT8, EIT2) only in the DI status (interrupt flag = "0"). Otherwise, it causes malfunction. 42 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Table 4.7.1 shows the clock timer control bits and their addresses. Control of clock timer Table 4.7.1 Control bits of clock timer Address D3 Register D2 D1 D0 TM3 TM2 TM1 TM0 EIT8 EIT32 0E3H R 0 EIT2 0EBH R 0 R/W IT2 IT8 IT32 0EFH R 0 0 0 TMRST 0F9H R *1 *2 *3 *4 *5 *6 W Name TM3 TM2 TM1 TM0 0 EIT2 EIT8 EIT32 0 IT2 IT8 IT32 0 0 0 TMRST Init *1 - *3 - *3 - *3 - *3 Comment 1 High High High High 0 Low Low Low Low Clock timer data 2 Hz Clock timer data 4 Hz Clock timer data 8 Hz Clock timer data 16 Hz 0 0 0 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz 0 0 0 Yes Yes Yes No No No *5 *5 Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *4 *4 *5 *5 *5 Reset Reset - Clock timer reset *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual TM0-TM3 Timer data (0E3H) The l6 Hz to 2 Hz timer data of the clock timer can be read from this register. These four bits are read-only, and write operations are invalid. After an initial reset, the timer data is initialized to "0H". EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0-D2) These registers are used to mask the clock timer interrupt. When "1" is written: When "0" is written: Reading: Enabled Masked Valid The interrupt mask register bits (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz). After an initial reset, these registers are all set to "0". S1C60N05 TECHNICAL MANUAL EPSON 43 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) IT32, IT8, IT2 Interrupt factor flags (0EFH D0-D2) These flags indicate the status of the clock timer interrupt. When "1" is read: When "0" is read: Writing: Interrupt has occurred Interrupt has not occurred Invalid The interrupt factor flags (IT32, IT8, IT2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can determine from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" on the falling edge of the signal. These flags can be reset when the register is read by the software. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. After an initial reset, these flags are set to "0". TMRST Clock timer reset (0F9H D0) This bit resets the clock timer. When "1" is written: When "0" is written: Reading: Clock timer reset No operation Always "0" The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" when read. 44 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) 4.8 A/D Converter Configuration of A/D The S1C60N05 Series has a CR oscillation type A/D converter with two input channels. This A/D converter is converter equipped with two CR oscillation circuit systems and a counter that measures their oscillation frequency. Counted values represent connected resistance values converted into digital values. Connect a reference resistance that does not change oscillation frequency according to temperature between the RS and CS terminals and a sensor that does change resistance values according to temperature between the TH and CS terminals. Then, oscillate them alternately. The difference in the counted value can be evaluated as the difference between the respective oscillation frequencies. Therefore, various sensor circuit such as a temperaturemeasuring circuit using a thermistor can be easily created, for example. The configuration of the A/D converter is shown in Figure 4.8.1. OSC1 clock Up/down counter 32 kHz or 65 kHz Multiplying circuit ADCLK TC15 TC11 -TC12 -TC8 Up/Down control TC7 -TC4 TC3 -TC0 Start/Stop control Data bus IAD ADRUN C15 -C12 Start/Stop C11 -C8 C7 -C4 EIAD Interrupt controller C3 -C0 Interrupt request Up-counter Start/Stop control Controller VSS ADOUT Tr3 VSS CAD Fig. 4.8.1 Configuration of CS RS Tr2 TH1 VDD Tr4 VDD TH2 RS TH1 TH2 A/D converter S1C60N05 TECHNICAL MANUAL Tr1 EPSON 45 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Connect a reference resistance that only slightly changes resistance values according to environmental conditions between the oscillating I/O terminals RS and CS. Connect a sensor that changes resistance values between the TH and CS terminals. Furthermore, by connecting a condenser between the CS and VSS, a CR oscillation circuit is completed. Operation of A/D converter This A/D converter performs CR oscillation using one of the two resistances connected to external devices. Their oscillation frequency serves as a clock from which the oscillation frequency is counted. Difference in counted oscillation frequency can be evaluated in terms of the difference between the respective resistance values. Measurement results can be obtained from the changes in resistance values after correcting the difference according to the program. (1) External resistances and condenser Connect a sensor (a variable resistance element such as a thermistor) between the TH1/TH2 and CS terminals. Next, set the reference value of the item to be measured (e.g. reference temperature in the case of temperature measurement) and connect the reference resistance equivalent to the sensor resistance value at the above reference value between the RS and CS terminals. An element that does not change due to temperature or other environmental conditions must be used as the reference resistance. Connect an oscillating condenser that is used for CR oscillation of both the reference resistance and the sensor between the CS and VSS terminals. 46 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) (2) Oscillation circuit The CR oscillation circuit is designed so that either the reference resistance side or the sensor side can be operated independently by the oscillation control circuit. A/D conversion begins when "1" is written in the ADRUN register (0F1H D0). At the same time, the oscillation circuit also turns on. At first, the circuit of the reference resistance side (RS) is operated by the oscillation control circuit. Then, the circuit of the sensor side (TH1 or TH2) turns on when counting by the oscillation clock of the reference resistance is terminated. TH1 or TH2 is controlled by the CHTH register (0F1H D3). Each circuit performs the same oscillating operation as follows (in this example, CHTH = "0", TH1 is selected): The Tr1 (Tr2) turns on first, and the condenser connected between the CS and VSS terminals is charged through the reference resistance (sensor). If the voltage level of the CS terminal decreases, the Tr1 (Tr2) turns off and the Tr3 turns on. As a result, the condenser becomes discharged, and oscillation is performed according to CR time constant. The time constant changes as the sensor resistance value fluctuates, producing a difference from the oscillation frequency of the reference resistance. Oscillation waveforms are shaped by the Schmitt trigger and transmitted to counter. The clock transmitted to the counter is also output from the ADOUT terminal. As a result, oscillation frequency can be identified by the oscilloscope. Since this monitor has no effect on oscillation frequency, it can be used to adjust CR oscillation frequency. Oscillation waveforms and waveforms output from the ADOUT terminal are shown in Figure 4.8.2. VDD CS terminal Fig. 4.8.2 Oscillation waveforms S1C60N05 TECHNICAL MANUAL VSS VDD ADOUT VSS EPSON 47 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) (3) Counter The A/D converter incorporates two types of 16-bit counters. One is the up-counter C0-C15 that counts the aforementioned oscillation clock, and the other is up/ down counter TC0-TC15 that counts the internal clock for reference counting. Each counter permits reading and writing on a 4-bit basis. The input unit of the up/down counter TC0-TC15 incorporates a multiplying circuit so that either the OSC1 clock (Typ. 32.768 kHz) or its multiplication clock (Typ. 65.536 kHz) can be selected as an input clock. When A/D conversion is initiated by the ADRUN register, oscillation by the reference resistance begins first, and the up-counter C0-C15 starts counting up according to the oscillation clock. At the same time, the up/down counter TC0-TC15 starts counting up. Timing in starting oscillation and starting counting up are shown in Figure 4.8.3. The up-counter becomes ENABLE at the falling edge of the first clock after CR oscillation is initiated and starts counting up from the falling edge of the next clock. The up/down counter becomes ENABLE at the falling edge of the internal clock which is input immediately after the first CR oscillation clock has fallen. Then, it starts counting up from the falling edge of the next internal clock. ADRUN register CS terminal ADOUT Up-counter enable Start Up-counter (C0) Clock (Up/down counter) Fig. 4.8.3 Counting up start timing Up/down counter enable Start Up/down counter (TC0) If the up-counter C0-C15 becomes "0000H" due to overflow, the sensor side of the oscillation circuit turns on, and the up-counter starts counting up according to the oscillation clock on the sensor side. 48 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) The up/down counter TC0-TC15 shifts to the countingdown mode at this point and starts counting down from the value measured as a result of oscillation by the reference resistance. Timing in starting counting when oscillation is switched, is same as Figure 4.8.3. When the up/down counter TC0-TC15 has counted down to "0000H", the counting operation of both counters and CR oscillation stops, and an interrupt occurs. At the same time, the ADRUN register is set to "0", and the A/D converter circuit stops operation completely. The sensor is oscillated for the same period of time as the reference resistance is oscillated after the up/down counter TC0-TC15 is set to "0000H" prior to A/D conversion. Therefore, the difference in oscillation frequency can be measured from the values counted by the up-counter C0-C15. Since the reference resistance is oscillated until the upcounter C0-C15 overflows, an appropriate initial value needs to be set before A/D conversion is started. If a smaller initial value is set, a longer counting period is possible, thereby ensuring more accurate detection. Likewise, if the input clock of the up/down counter TC0- TC15 is set at 65 kHz, the degree of precision is reduced. However, since CR oscillation frequency is normally set lower than the clock frequency of the up/down counter TC0-TC15 to ensure accurate measurement, the up/ down counter TC0-TC15 may overflow while counting the oscillation frequency of the reference resistance. If an overflow occurs, CR oscillation and A/D conversion is terminated immediately. Also in such cases, the up/ down counter indicates "0000H", and interrupt occurs. However, it is impossible to judge whether the interrupt has occurred due to an overflow or normal termination. Note that correct measurement is impossible if an overflow occurs. The initial value to be set depends on the measurable range by the sensor or where to set the reference resistance value within that range. The initial value must be set taking the above into consideration. S1C60N05 TECHNICAL MANUAL EPSON 49 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Convert the initial value into a complement (value subtracted from 0000H) before setting it on the up-counter C0-C15. Since the data output from the up-counter C0- C15 after A/D conversion matches data detected by the sensor, process the difference between that value and the initial value before it is converted into a complement according to the program and calculate the target value. The above operations are shown in Figure 4.8.4. Setting by software Up/down counter (TC0-TC15) Up-counter (C0-C15) (1) Set the initial value (0000H-n) (0000H-n) (2) Start A/D conversion (Set "1" on the ADRUN) Count up 0000H 0000H Set the complement of the initial value n on the up-counter Set "0000H" on the up /down counter Count up FFFFH : 0 x 0 x Count up Count down : 0001H m 0000H (3) Read the up-counter and process the m-n value acoording to the program Oscillation by reference resistance Switch CR oscillation when the up-counter overflows and shift the up/down counter to the counting-down mode Oscillation by sensor When the value of the up/down counter reaches 0000H, oscillation and conting stops, and an interruption occurs. Fig. 4.8.4 Sequence of A/D conversion Note - 50 Before setting "1" to ADRUN, an input channel must be selected from TH1 and TH2 (TH1 by default). - Set the initial value of the up-counter C0-C15 taking into account the measurable range and the overflow of the up/down counter TC0-TC15. - If the up/down counter TC0-TC15 is measured after A/D conversion, it may not indicate "0000H". This is not due to incorrect timing in terminating A/D conversion but because the counting down clock is input after the control signal is output to the up-counter to terminate counting. EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Interrupt function The A/D converter has a function which allows interrupt to occur after A/D conversion. When the up/down counter TC0-TC15 is counted down to "0000H", both counters stop counting. The interrupt factor flag IAD is set to "1" at the falling edge of the next clock. If the up/down counter TC0-TC15 overflow during countingup operation, the interrupt factor flag is set to "1" at the rising edge of the clock immediately after the counter reaches "0000H". This interrupt factor allows masking by the interrupt mask register EIAD. If the EIAD is set at "1", an interrupt occurs in the CPU. If the EIAD is set at "0", the interrupt factor flag is set to "1". However, no interrupt will occur in the CPU. The interrupt factor flag is reset to "0" by a reading operation. Timing of interrupt by the A/D converter is shown in Figure 4.8.5. ADRUN register ADOUT Up-counter data n n+1 n+2 FFFE FFFF 0 1 2 m-1 m Up/down counter clock Up/down counter data 0 1 2 3 x-3 x-2 x-1 x x-1 x-2 x-3 3 2 1 0 Interrupt Oscillation with reference resistor Fig. 4.8.5 Oscillation with sensor Timing of A/D converter interrupt Usage example of the A/D converter Temperature measurement is possible with the A/D converter in which a thermistor is used as a sensor. Elements to be connected and counter setting in the case of temperature measurement are as follows: Example: S1C60N05 TECHNICAL MANUAL Temperature measurement at -20C to 70C Reference resistance ....... 49.8 k Thermistor ...................... 50 k Oscillating condenser ...... 2,200 pF EPSON 51 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) When the above elements are connected, the oscillation frequency of the reference resistance becomes about 10 kHz, and the oscillation frequency of the thermistor varies within the range of about 1 kHz to 50 kHz at -20C to 70C. Reference resistance is adjusted to the thermistor resistance value at 25C. In addition, Figure 4.8.6 indicates the resistance and oscillation frequency ratio TYP at the time of A/D conversion. 5.0 Oscillation frequency ratio Resistance and oscillation frequency ratio of A/D conversion circuit For 50 k , set the oscillation frequency to 1. 1.0 0.1 10 k 50 k Fig. 4.8.6 Resistance and oscillation 100 k Resistance value 500 k ( ) frequency ratio 52 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) Table 4.8.2 shows the A/D converter control bits and their addresses. Control of A/D converter Table 4.8.2 Control bits of clock timer Address D3 Register D2 D1 D0 TC3 TC2 TC1 TC0 TC5 TC4 TC9 TC8 TC13 TC12 C1 C0 C5 C4 C9 C8 C13 C12 0 ADRUN 0E4H R/W TC7 TC6 0E5H R/W TC11 TC10 0E6H R/W TC15 TC14 0E7H R/W C3 C2 0F5H R/W C7 C6 0F6H R/W C11 C10 0F7H R/W C15 C14 0F8H R/W CHTH 0 0F1H R/W 0 R/W R 0 0 ADCLK 0FEH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 0F0H R IAD Name TC3 TC2 TC1 TC0 TC7 TC6 TC5 TC4 TC11 TC10 TC9 TC8 TC15 TC14 TC13 TC12 C3 C2 C1 C0 C7 C6 C5 C4 C11 C10 C9 C8 C15 C14 C13 C12 CHTH 0 0 ADRUN 0 0 0 ADCLK 0 0 0 EIAD 0 0 0 IAD *1 Initial value following initial reset *2 Not set in the circuit *3 Undefined S1C60N05 TECHNICAL MANUAL Init *1 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 - *3 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TH1 Comment Up/down counter data TC3 Up/down counter data TC2 Up/down counter data TC1 Up/down counter data TC0 (LSB) Up/down counter data TC7 Up/down counter data TC6 Up/down counter data TC5 Up/down counter data TC4 Up/down counter data TC11 Up/down counter data TC10 Up/down counter data TC9 Up/down counter data TC8 Up/down counter data TC15 (MSB) Up/down counter data TC14 Up/down counter data TC13 Up/down counter data TC12 Up-counter data C3 Up-counter data C2 Up-counter data C1 Up-counter data C0 (LSB) Up-counter data C7 Up-counter data C6 Up-counter data C5 Up-counter data C4 Up-counter data C11 Up-counter data C10 Up-counter data C9 Up-counter data C8 Up-counter data C15 (MSB) Up-counter data C14 Up-counter data C13 Up-counter data C12 A/D channel selection *5 *5 Start 0 Stop A/D conversion Start/Stop *5 *5 *5 65 kHz 0 32 kHz A/D clock selection 65 kHz/32 kHz *5 *5 *5 Enable 0 Mask Interrupt mask register (A/D) *5 *5 *5 Yes 0 No Interrupt factor flag (A/D) *4 *4 Reset (0) immediately after being read *5 Always "0" when being read *6 Refer to main manual EPSON 53 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) TC0-TC15 Up/down counter (0E4H-0E7H) Writing and reading is possible on a 4-bit basis by the up/ down counter that is used to adjust the CR oscillation time between the reference resistance and the variable resistance elements. The up/down counter counts up during oscillation of the reference resistance and counts down from the value it reached when counting up to "0000H" during oscillation of the sensor. "0000H" needs to be entered in the counter prior to A/D conversion in order to adjust the counting time of both counts. After an initial reset, data in this counter become indefinite. C0-C15 Up-counter (0F5H-0F8H) This counter counts up according to the CR oscillation clock. It permits writing and reading on a 4-bit basis. The complement of the number of clocks to be counted by the oscillation of the reference resistance, must be entered in this counter prior to A/D conversion. If A/D conversion is initiated, the counter counts up from the set initial value, first according to the oscillation clock of the reference resistance. When the counter reaches "0000H" due to overflow, the oscillation of the reference resistance stops, and the sensor starts oscillating. The counter continues counting according to the sensor oscillation clock. Counting time during the oscillation of the reference resistance is calculated by the up/down counter TC0-TC15. Upcounter C0-C15 stops counting when the same period of time elapses. Difference from the reference resistance can be evaluated from the value indicated by the counter when it stops. Calculate the target value by processing the above difference according to the program. Measurable range and the overflow of the up/down counter TC0-TC15 must be taken into account when setting an initial value to be entered prior to A/D conversion. After an initial reset, data in this counter become indefinite. 54 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) ADCLK Input clock selection (0FEH D0) Select the input clock of the up/down counter TC0-TC15. When "1" is written: When "0" is written: Reading: 65 kHz 32 kHz Valid Select the output clock of the multiplying circuit for the counting operation of the up/down counter TC0-TC15. When "1" is written in the ADCLK, 65 kHz, a multitude of the OSC1 clock is selected. When "0" is written, the OSC1 clock is selected at 32 kHz. If 65 kHz is selected, A/D conversion becomes more accurate. However, the initial value must be set on the upcounter C0-C15 so that the up/down counter TC0-TC15 will not overflow while CR oscillation is being counted. After an initial reset, ADCLK is set to "0". ADRUN A/D conversion START/STOP (0F1H D0) Start A/D conversion. When "1" is written: When "0" is written: Reading: A/D conversion starts A/D conversion stops Valid When "1" is written in the ADRUN, A/D conversion begins. The register remains at "1" during A/D conversion and is set to "0" when A/D conversion is terminated. When "0" is written in the ADRUN during A/D conversion, A/D conversion is paused. ADRUN is set to "0" at initial reset, when the up/down counter overflows or when measurement is finished. CHTH A/D channel selection (0F1H D3) Select an A/D converter channel. When "1" is written: When "0" is written: Reading: TH2 is selected TH1 is selected Valid Before running the A/D converter, either TH1 or TH2 must be selected as an input channel. After an initial reset, CHTH is set to "0". S1C60N05 TECHNICAL MANUAL EPSON 55 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter) EIAD Interrupt mask register (0ECH D0) Select whether to mask interrupt with the A/D converter. When "1" is written: When "0" is written: Reading: Enable Mask Valid The A/D converter interrupt is permitted when "1" is written in the EIAD. When "0" is written, interrupt is masked. After an initial reset, this register is set to "0". IAD Interrupt factor flag (0F0H D0) This flag indicates interrupt caused by the A/D converter. When "1" is read: When "0" is read: Writing: Interrupt has occurred Interrupt has not occurred Invalid IAD is set to "1" when A/D conversion is terminated (when the up/down counter counted up or down to "0000H"). From the status of this flag, the software can decide whether an A/D converter interrupt has occurred. This flag is reset when the software has read it. Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. After an initial reset, this flag is set to "0". 56 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function) 4.9 Heavy Load Protection Function Operation of heavy load protection function The S1C60N05 Series has a heavy load protection function for when the battery load becomes heavy and the supply voltage drops, such as when an external buzzer sounds or an external lamp lights. This function works in the heavy load protection mode. The normal mode changes to the heavy load protection mode in the following case: * When the software changes the mode to the heavy load protection mode (HLMOD = "1") In the heavy load protection mode, the internally regulated voltage is switched to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless necessary, do not select the heavy load protection mode with the software. S1C60N05 TECHNICAL MANUAL EPSON 57 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function) Table 4.9.1 shows the control bits and their addresses for the heavy load protection function. Control of heavy load protection function Table 4.9.1 Control bits for heavy load protection function Address D3 HLMOD Register D2 D1 0 0 0FAH R/W *1 *2 *3 *4 *5 *6 R D0 0 Init *1 0 Name HLMOD 0 0 0 1 Heavy 0 Normal Comment Heavy load protection mode register *5 *5 *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual HLMOD Heavy load protection mode on/off (0FAH D3) When "1" is written: When "0" is written: Reading: Heavy load protection mode on Heavy load protection mode off Valid When HLMOD is set to "1", the IC enters the heavy load protection mode. In the heavy load protection mode, the consumed current becomes larger. Unless necessary, do not select the heavy load protection mode with the software. 58 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.10 Interrupt and HALT The S1C60N05 Series provides the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input interrupt (one) Timer interrupt (one) A/D converter interrupt (one) To enable interrupts, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask registers must be set to "1" (enable). When an interrupt occurs, the interrupt flag is automatically reset to "0" (DI) and interrupts after that are inhibited. When a HALT instruction is input, the CPU operating clock stops and the CPU enters the halt state. The CPU is reactivated from the halt state when an interrupt request occurs. Figure 4.10.1 shows the configuration of the interrupt circuit. Interrupt vector (MSB) K00 : EIK00 : K01 (LSB) Program counter of CPU (three low-order bits) EIK01 IK0 INT (Interrupt request) K02 EIK02 Interrupt flag K03 EIK03 IAD EIAD IT2 Interrupt factor flag EIT2 IT8 Interrupt mask register EIT8 IT32 EIT32 Fig. 4.10.1 Configuration of interrupt circuit S1C60N05 TECHNICAL MANUAL EPSON 59 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.10.1 shows the factors that generate interrupt requests. Interrupt factors The interrupt factor flags are set to "1" depending on the corresponding interrupt factors. The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to "1". * The corresponding mask register is "1" (enabled) * The interrupt flag is "1" (EI) The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read. After an initial reset, the interrupt factor flags are reset to "0". Note Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. Table 4.10.1 Interrupt factors Interrupt factor Colck timer 2 Hz falling edge IT2 (0EFH D2) Colck timer 8 Hz falling edge IT8 (0EFH D1) Colck timer 32 Hz falling edge IT32 (0EFH D0) IAD (0F0H D0) IK0 (0EDH D0) A/D converter A/D conversion completion Input data (K00-K03) Rising edge 60 Interrupt factor flag EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Specific masks and factor flags for interrupt Table 4.10.2 Interrupt mask registers and interrupt factor flags The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt enabled) when "1" is written to them, and masked (interrupt disabled) when "0" is written to them. After an initial reset, the interrupt mask register is set to "0". Table 4.10.2 shows the correspondence between interrupt mask registers and interrupt factor flags. Interrupt mask register Interrupt factor flag EIT2 (0EBH D2) IT2 (0EFH D2) EIT8 (0EBH D1) IT8 (0EFH D1) EIT32 (0EBH D0) IT32 (0EFH D0) EIAD (0ECH D0) IAD (0F0H D0) EIK03* (0E8H D3) EIK02* (0E8H D2) EIK01* (0E8H D1) IK0 (0EDH D0) EIK00* (0E8H D0) * There is an interrupt mask register for each input port pin. When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is suspended, interrupt processing is executed in the following order: Interrupt vectors The address data (value of the program counter) of the program step to be executed next is saved on the stack (RAM). The interrupt request causes the value of the interrupt vector (page 1, 01H-07H) to be loaded into the program counter. The program at the specified address is executed (execution of interrupt processing routine). Note The processing in steps 1 and 2, above, takes 12 cycles of the CPU system clock. S1C60N05 TECHNICAL MANUAL EPSON 61 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.10.3 shows the interrupt control bits and their addresses. Control of interrupt Table 4.10.3 Interrupt control bits Address D3 EIK03 Register D2 D1 EIK02 EIK01 D0 EIK00 0E8H R/W 0 EIT2 EIT8 EIT32 0EBH R 0 R/W 0 0 EIAD 0ECH R 0 R/W 0 0 IK0 0EDH R 0 IT2 IT8 IT32 0EFH R 0 0 0 0F0H R *1 *2 *3 *4 *5 *6 IAD Name EIK03 EIK02 EIK01 EIK00 0 EIT2 EIT8 EIT32 0 0 0 EIAD 0 0 0 IK0 0 IT2 IT8 IT32 0 0 0 IAD Init *1 0 0 0 0 Comment 1 Enable Enable Enable Enable 0 Mask Mask Mask Mask Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 Enable Enable Enable Mask Mask Mask Interrupt mask register (clock timer) 2 Hz Interrupt mask register (clock timer) 8 Hz Interrupt mask register (clock timer) 32 Hz *5 0 0 0 *5 *5 *5 0 Enable Mask Interrupt mask register (A/D) *5 *5 *5 0 Yes No Interrupt factor flag (K00-K03) 0 0 0 Yes Yes Yes No No No Interrupt factor flag (clock timer) 2 Hz Interrupt factor flag (clock timer) 8 Hz Interrupt factor flag (clock timer) 32 Hz *4 *5 *4 *4 *4 *5 *5 *5 0 Yes No Interrupt factor flag (A/D) *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always "0" when being read Refer to main manual EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0-D2) IT32, IT8, IT2 Interrupt factor flags (0EFH D0-D2) See 4.7, "Clock Timer". EIAD Interrupt mask register (0ECH D0) IAD Interrupt factor flag (0F0H D0) See 4.8, "A/D Converter". EIK00-EIK03 Interrupt mask registers (0E8H) IK0 Interrupt factor flag (0EDH D0) See 4.3, "Input Ports". 62 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM (1) Piezo Buzzer Single Terminal Driving I COM3 K00 COM0 SEG0 SEG19 LCD PANEL CA CB VL1 K03 I/O VDD P03 OSC1 S1C60N05/60L05 [The potential of the substrate (back of the chip) is VDD.] CG OSC2 VS1 X'tal C2 RESET R00 R02 R03 TEST 1.5 V or 3.0 V Cp R01 CS TH2 TH1 RS Vss Piezo Buzzer RS TH1 TH2 CAD S1C60N05 TECHNICAL MANUAL Capacitors (C3 and C4) are connected. Connection dependingon power supply and LCD panel specification. Please refer to page 7. VL2 VL3 P00 O C1 Coil X'tal Crystal oscillator 32,768 Hz CG Trimmer capacitor 5-25 pF C1 , C 2 , C 3 , C4 Capacitor 0.1 F Cp Capacitor 3.3 F TH1, TH2 Thermistor 50 k RS Resistor 49.8 k CAD Capacitor 2,200 pF EPSON CI(MAX) = 35 k 63 CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM (2) Piezo Buzzer Direct Driving COM3 K00 I COM0 SEG0 SEG19 LCD PANEL CA CB VL1 K03 Capacitors (C3 and C4) are connected. Connection dependingon power supply and LCD panel specification. Please refer to page 7. VL2 P00 VL3 VDD I/O P03 CG OSC1 S1C60N05/60L05 [The potential of the substrate (back of the chip) is VDD.] O C1 X'tal OSC2 VS1 C2 RESET R02 R03 TEST 1.5 V or 3.0 V Cp RS TH1 TH2 R1 R2 Piezo Buzzer CAD 64 R00 R01 CS TH2 TH1 RS Vss X'tal Crystal oscillator 32,768 Hz CG Trimmer capacitor 5-25 pF C1 , C 2 , C 3 , C 4 Capacitor 0.1 F Cp Capacitor 3.3 F TH1, TH2 Thermistor 50 k RS Resistor 49.8 k R1 , R 2 Resistor 100 CAD Capacitor 2,200 pF EPSON CI(MAX) = 35 k S1C60N05 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating S1C60N05 (VDD=0V) Item Symbol Rated value Unit Power voltage VSS -5.0 to 0.5 V Input voltage (1) VI Vss-0.3 to 0.5 V Input voltage (2) VIOSC Vss-0.3 to 0.5 V Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Tsol 260C, 10sec (lead section) - PD 250 mW Soldering temperature / Time Allowable dissipation *1 *1 In case of QFP6-60 pin plastic package S1C60L05 (VDD=0V) Item Symbol Rated value Unit Power voltage VSS -5.0 to 0.5 V Input voltage (1) VI Vss-0.3 to 0.5 V Input voltage (2) VIOSC Vss-0.3 to 0.5 V Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Tsol 260C, 10sec (lead section) - PD 250 mW Soldering temperature / Time Allowable dissipation *1 *1 In case of QFP6-60 pin plastic package S1C60N05 TECHNICAL MANUAL EPSON 65 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.2 Recommended Operating Conditions S1C60N05 Item Power voltage Oscillation frequency Booster capacitor Capacitor between VDD and VS1 Symbol Condition VSS VDD=0V fOSC1 Crystal oscillation fOSC2 CR oscillation, R=420k C1 C2 Min -3.5 Symbol Condition VSS VDD=0V *1 fOSC1 Crystal oscillation fOSC2 CR oscillation, R=420k C1 C2 Min -2.0 Typ -3.0 32,768 65 0.1 0.1 (Ta=-20 to 70C) Max Unit -1.8 V Hz 80 kHz F F S1C60L05 Item Power voltage Oscillation frequency Booster capacitor Capacitor between VDD and VS1 0.1 0.1 Typ -1.5 32,768 65 (Ta=-20 to 70C) Max Unit -1.2 V Hz 80 kHz F F *1 When there is no software control during CR oscillation or crystal oscillation. 66 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics S1C60N05 Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F Item Symbol Condition High level input voltage (1) VIH1 K00-K03, P00-P03 High level input voltage (2) VIH2 RESET, TEST Low level input voltage (1) K00-K03, P00-P03 VIL1 Low level input voltage (2) RESET, TEST VIL2 High level input current (1) K00-K03, P00-P03 IIH1 VIH1=0V Without pull down resistor High level input current (2) K00-K03 IIH2 VIH2=0V With pull down resistor High level input current (3) P00-P03 IIH3 VIH3=0V RESET, TEST With pull down resistor Low level input current K00-K03, P00-P03 VIL=VSS IIL RESET, TEST High level output current (1) IOH1 VOH1=0.1*VSS R02, R03, P00-P03 High level output current (2) IOH2 VOH2=0.1*VSS R00, R01 (built-in protection resistance) High level output current (3) IOH3 VOH3=-1.0V ADOUT Low level output current (1) IOL1 VOL1=0.9*VSS R02, R03, P00-P03 Low level output current (2) IOL2 VOL2=0.9*VSS R00, R01 (built-in protection resistance) Low level output current (3) IOL3 VOL3=-2.0V ADOUT Common output current COM0-COM3 IOH4 VOH4=-0.05V IOL4 VOL4=VL3+0.05V Segment output current SEG0-SEG19 IOH5 VOH5=-0.05V (during LCD output) IOL5 VOL5=VL3+0.05V Segment output current SEG0-SEG19 IOH6 VOH6=0.1*VSS (during DC output) IOL6 VOL6=0.9*VSS S1C60N05 TECHNICAL MANUAL EPSON Max Min Typ Unit 0 0.2*VSS V 0 0.15*VSS V 0.8*VSS VSS V VSS 0.85*VSS V A 0 0.5 10 40 A 30 100 A -0.5 0 A -1.0 -1.0 mA mA -1.0 mA mA mA 3.0 3.0 3.0 -3 3 -3 3 -300 300 mA A A A A A A 67 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60L05 Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F Item Symbol Condition High level input voltage (1) VIH1 K00-K03, P00-P03 High level input voltage (2) VIH2 RESET, TEST Low level input voltage (1) K00-K03, P00-P03 VIL1 Low level input voltage (2) RESET, TEST VIL2 High level input current (1) K00-K03, P00-P03 IIH1 VIH1=0V Without pull down resistor High level input current (2) K00-K03 IIH2 VIH2=0V With pull down resistor High level input current (3) P00-P03 IIH3 VIH3=0V RESET, TEST With pull down resistor Low level input current K00-K03, P00-P03 VIL=VSS IIL RESET, TEST High level output current (1) IOH1 VOH1=0.1*VSS R02, R03, P00-P03 High level output current (2) IOH2 VOH2=0.1*VSS R00, R01 (built-in protection resistance) High level output current (3) IOH3 VOH3=-0.5V ADOUT Low level output current (1) IOL1 VOL1=0.9*VSS R02, R03, P00-P03 Low level output current (2) IOL2 VOL2=0.9*VSS R00, R01 (built-in protection resistance) Low level output current (3) IOL3 VOL3=-1.0V ADOUT Common output current COM0-COM3 IOH4 VOH4=-0.05V IOL4 VOL4=VL3+0.05V Segment output current SEG0-SEG19 IOH5 VOH5=-0.05V (during LCD output) IOL5 VOL5=VL3+0.05V Segment output current SEG0-SEG19 IOH6 VOH6=0.1*VSS (during DC output) IOL6 VOL6=0.9*VSS 68 EPSON Max Min Typ Unit 0 0.2*VSS V 0 0.15*VSS V 0.8*VSS VSS V VSS 0.85*VSS V A 0 0.5 5 20 A 9.0 100 A -0.5 0 A -200 -200 A A -200 A A A 700 700 700 -3 3 -3 3 -100 130 A A A A A A A S1C60N05 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Analog Circuit Characteristics and Power Current Consumption S1C60N05 (Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F (During A/D conversion: RS=49.8 k, TH=50 k, CAD=2,200 pF) Item Internal voltage Power current consumption Min Symbol Condition VL1 Connect 1M load resistor between VDD and VL1 1/2*VL2 (without panel load) -0.1 Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 3/2*VL2 VL3 (without panel load) -0.1 IOP During HALT During execution Without panel load During A/D conversion (HALT) Typ VSS Max Unit 1/2*VL2 V x 0.9 V 3/2*VL2 V x 0.9 1.4 0.8 A 5.0 1.5 A 40 30 A S1C60N05 (Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F (During A/D conversion: RS=49.8 k, TH=50 k, CAD=2,200 pF) Item Internal voltage Power current consumption Symbol Min Condition VL1 Connect 1M load resistor between VDD and VL1 1/2*VL2 (without panel load) -0.1 Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 3/2*VL2 VL3 (without panel load) -0.1 IOP During HALT During execution Without panel load During A/D conversion (HALT) S1C60N05 TECHNICAL MANUAL EPSON Typ VSS Max Unit 1/2*VL2 V x 0.85 V 3/2*VL2 V x 0.85 5.5 2.0 A 10.0 5.5 A 41.5 31 A 69 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60L05 (Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F (During A/D conversion: RS=49.8 k, TH=50 k, CAD=2,200 pF) Item Internal voltage Power current consumption Symbol Min Condition VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 2*VL1 VL2 (without panel load) -0.1 Connect 1M load resistor between VDD and VL3 3*VL1 VL3 (without panel load) -0.1 IOP During HALT During execution Without panel load During A/D conversion (HALT) Typ VSS 0.8 1.5 30 Max Unit V 2*VL1 x 0.9 3*VL1 x 0.9 1.4 5.0 40 V V A A A S1C60L05 (Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F (During A/D conversion: RS=49.8 k, TH=50 k, CAD=2,200 pF) Item Internal voltage Power current consumption 70 Symbol Min Condition VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 2*VL1 VL2 (without panel load) -0.1 Connect 1M load resistor between VDD and VL3 3*VL1 VL3 (without panel load) -0.1 IOP During HALT During execution Without panel load During A/D conversion (HALT) EPSON Typ VSS Max Unit V 2*VL1 V x 0.85 3*VL1 V x 0.85 2.0 5.5 31 5.5 10.0 41.5 A A A S1C60N05 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60N05 (CR, Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F, Recommended external resistance for CR oscillation = 420 k (During A/D conversion: RS=49.8 k, TH=50 k, CAD=2,200 pF) Item Internal voltage Power current consumption Symbol Condition Min VL1 Connect 1M load resistor between VDD and VL1 1/2*VL2 (without panel load) -0.1 Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 3/2*VL2 VL3 (without panel load) -0.1 IOP During HALT During execution Without panel load During A/D conversion (HALT) Typ VSS Max Unit 1/2*VL2 V x 0.9 V 3/2*VL2 V x 0.9 15.0 8.0 A 15.0 20.0 A 52.5 37 A S1C60N05 (CR, Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F, Recommended external resistance for CR oscillation = 420 k (During A/D conversion: RS=49.8 k, TH=50 k, CAD=2,200 pF) Item Internal voltage Power current consumption Symbol Condition Min VL1 Connect 1M load resistor between VDD and VL1 1/2*VL2 (without panel load) -0.1 Connect 1M load resistor between VDD and VL2 VL2 (without panel load) Connect 1M load resistor between VDD and VL3 3/2*VL2 VL3 (without panel load) -0.1 IOP During HALT During execution Without panel load During A/D conversion (HALT) S1C60N05 TECHNICAL MANUAL EPSON Typ VSS Max Unit 1/2*VL2 V x 0.85 V 3/2*VL2 V x 0.85 16.0 30.0 A 30.0 40.0 A 57.5 45 A 71 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60L05 (CR, Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F, Recommended external resistance for CR oscillation = 420 k (During A/D conversion: RS=49.8 k, TH=50 k, CAD=2,200 pF) Item Internal voltage Power current consumption Symbol Condition Min VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 2*VL1 VL2 (without panel load) -0.1 Connect 1M load resistor between VDD and VL3 3*VL1 VL3 (without panel load) -0.1 IOP During HALT During execution Without panel load During A/D conversion (HALT) Typ VSS 8.0 15.0 37 Max Unit V 2*VL1 x 0.9 3*VL1 x 0.9 15.0 20.0 52.5 V V A A A S1C60L05 (CR, Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=0.1 F, Recommended external resistance for CR oscillation = 420 k (During A/D conversion: RS=49.8 k, TH=50 k, CAD=2,200 pF) Item Internal voltage Power current consumption 72 Symbol Condition Min VL1 Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 2*VL1 VL2 (without panel load) -0.1 Connect 1M load resistor between VDD and VL3 3*VL1 VL3 (without panel load) -0.1 IOP During HALT During execution Without panel load During A/D conversion (HALT) EPSON Typ VSS Max Unit V 2*VL1 V x 0.85 3*VL1 V x 0.85 16.0 30.0 45 30.0 40.0 57.5 A A A S1C60N05 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.5 Oscillation Characteristics Oscillation characteristics will vary according to different conditions (components used, board pattern, etc.). Use the following characteristics are as reference values. S1C60N05 Unless otherwise specified VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25C Symbol Vsta (Vss) Vstp Oscillation stop voltage (Vss) CD Built-in capacity (drain) Frequency voltage deviation f/V f/IC Frequency IC deviation Frequency adjustment range f/CG Higher harmonic oscillation Vhho start voltage (Vss) Allowable leak resistance Rleak Item Oscillation start voltage tsta5sec Condition Min -1.8 tstp10sec -1.8 Typ 5 10 -10 40 -3.6 Between OSC1 and VDD, and between VSS and OSC1 Unit V V 20 Including the parasitic capacity inside the IC Vss=-1.8 to -3.5V CG=5-25pF CG=5pF Max pF ppm ppm ppm V M 200 S1C60L05 Unless otherwise specified VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25C Symbol Vsta (Vss) Vstp Oscillation stop voltage (Vss) CD Built-in capacity (drain) Frequency voltage deviation f/V Frequency IC deviation f/IC Frequency adjustment range f/CG Higher harmonic oscillation Vhho start voltage (Vss) Allowable leak resistance Rleak Item Oscillation start voltage tsta5sec Condition Min -1.2 tstp10sec -1.2 Max -10 40 5 10 -2.0 Between OSC1 and VDD, and between VSS and OSC1 Unit V V 20 Including the parasitic capacity inside the IC Vss=-1.2 to -2.0V (-0.9) *1 CG=5-25pF CG=5pF Typ 200 pF ppm ppm ppm V M *1 Items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. S1C60N05 TECHNICAL MANUAL EPSON 73 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60N05 (CR) Unless otherwise specified VDD=0 V, VSS=-3.0 V, RCR=480 k, Ta=25C Symbol Item Condition Min fosc Oscillation frequency dispersion -20 Vsta Oscillation start voltage -1.8 Oscillation start time tsta Vss=-1.8 to -3.5V Oscillation stop voltage Vstp -1.8 Typ 65kHz Max 20 Unit % V ms V Max 20 Unit % V ms V 3 S1C60L05 (CR) Unless otherwise specified VDD=0 V, VSS=-1.5 V, RCR=480 k, Ta=25C Symbol Item Condition Min fosc Oscillation frequency dispersion -20 Vsta Oscillation start voltage -1.2 Oscillation start time tsta Vss=-1.2 to -2.0V Oscillation stop voltage Vstp -1.2 74 EPSON Typ 65kHz 3 S1C60N05 TECHNICAL MANUAL CHAPTER 7: PACKAGE CHAPTER 7 PACKAGE 7.1 Plastic Package QFP6-60pin (Unit: mm) 17.60.4 140.2 45 31 140.2 INDEX 16 60 1 15 0.350.1 0.1 2.70.1 0.8 3.1max 17.60.4 30 46 0.150.05 0 10 0.850.2 1.8 S1C60N05 TECHNICAL MANUAL EPSON 75 CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples DIP-64pin (Unit: mm) 81.3 PIN NO. 1 2 23.1 34 33 22.8 64 63 31 32 INDEX MARK 2.54 78.7 76 No. 1 2 3 4 5 Pin name N.C. SEG17 SEG18 SEG19 COM0 No. 17 18 19 20 21 6 7 8 9 10 11 12 13 14 15 16 COM1 COM2 COM3 N.C. VL3 22 23 24 25 26 27 28 29 30 31 32 R01 VL2 VL1 CA CB VSS VDD EPSON Pin name OSC1 OSC2 VS1 P00 P01 P02 P03 N.C. N.C. N.C. K00 K01 K02 K03 R00 No. 33 34 35 36 37 Pin name R02 R03 RS TH1 TH2 No. 49 50 51 52 53 Pin name SEG6 SEG7 SEG8 SEG9 SEG10 38 39 40 41 42 43 44 45 46 47 48 CS 54 SEG11 N.C. 55 N.C. N.C. 56 N.C. N.C. 57 TEST ADOUT 58 RESET SEG0 59 SEG12 SEG1 60 SEG13 SEG2 61 SEG14 SEG3 62 SEG15 SEG4 63 SEG16 SEG5 64 N.C. N.C. = No Connection S1C60N05 TECHNICAL MANUAL CHAPTER 8: PAD LAYOUT CHAPTER 8 PAD LAYOUT 8.1 Diagram of Pad Layout 13 12 11 10 9 8 7 6 5 4 3 2 1 52 51 50 49 48 Y (0, 0) X 47 46 45 44 43 42 24 25 26 27 Die No. 53 2.58 mm 14 15 16 17 18 19 20 21 22 23 28 29 30 31 32 33 34 35 36 37 38 39 40 41 2.95 mm S1C60N05 TECHNICAL MANUAL EPSON 77 CHAPTER 8: PAD LAYOUT 8.2 Pad Coordinates Pad No. Pad name X Y Pad No. Pad name X Y 1 ADOUT 644 1,121 28 VL3 -1,259 -1,121 2 SEG0 511 1,121 29 VL2 -1,129 -1,121 3 SEG1 381 1,121 30 VL1 -998 -1,121 4 SEG2 251 1,121 31 CA -868 -1,121 5 SEG3 121 1,121 32 CB -737 -1,121 6 SEG4 -9 1,121 33 VSS -81 -1,121 7 SEG5 -139 1,121 34 VDD 50 -1,121 8 SEG6 -269 1,121 35 OSC1 185 -1,121 9 SEG7 -399 1,121 36 OSC2 337 -1,121 10 SEG8 -529 1,121 37 VS1 490 -1,121 11 SEG9 -659 1,121 38 P00 863 -1,121 12 SEG10 -789 1,121 39 P01 993 -1,121 13 SEG11 -919 1,121 40 P02 1,123 -1,121 14 TEST -1,306 987 41 P03 1,253 -1,121 15 RESET -1,306 854 42 K00 1,306 -665 16 SEG12 -1,306 724 43 K01 1,306 -535 17 SEG13 -1,306 597 44 K02 1,306 -404 18 SEG14 -1,306 464 45 K03 1,306 -274 19 SEG15 -1,306 334 46 R00 1,306 -49 20 SEG16 -1,306 204 47 R01 1,306 81 21 SEG17 -1,306 74 48 R02 1,306 310 22 SEG18 -1,306 -56 49 R03 1,306 440 23 SEG19 -1,306 -186 50 RS 1,306 582 24 COM0 -1,306 -371 51 TH1 1,306 721 25 COM1 -1,306 -509 52 TH2 1,306 857 26 COM2 -1,306 -639 53 CS 1,306 1,038 27 COM3 -1,306 -769 (Unit: m) 78 EPSON S1C60N05 TECHNICAL MANUAL CHAPTER 9: PRECAUTIONS ON MOUNTING CHAPTER 9 PRECAUTIONS ON MOUNTING Oscillation circuit * Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. * Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: (1) Components which are connected to the OSC1 and OSC2 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VDD pattern as large as possible at circumscription of the OSC1 and OSC2 terminals and the components connected to these terminals. Furthermore, do not use this VDD pattern for any purpose other than the oscillation system. Sample VDD pattern OSC2 OSC1 VDD Reset circuit Power supply circuit * In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1 and VSS, please keep enough distance between OSC1 and VSS or other signals on the board pattern. * The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-down resistor is added to the RESET terminal by mask option, take into consideration dispersion of the resistance for setting the constant. * In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. * Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. S1C60N05 TECHNICAL MANUAL EPSON 79 CHAPTER 9: PRECAUTIONS ON MOUNTING (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VS1, VL1-VL3 terminals, such as capacitors and resistors, should be connected in the shortest line. In particular, the VL1-VL3 voltages affect the display quality. Arrangement of signal lines * Do not connect anything to the VL1-VL3 terminals when the LCD driver is not used. * In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. * When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern OSC2 OSC1 VDD Large current signal line High-speed signal line Precautions for visible radiation (when bare chip is mounted) * Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. 80 EPSON S1C60N05 TECHNICAL MANUAL APPENDIX: TECHNICAL INFORMATION Appendices TECHNICAL INFORMATION This chapter presents the information necessary for designing a thermometer using a Seiko Epson S1C60N05 and a Thermistor manufactured by Ishizuka Denshi Inc. Appendix A Design Steps for Designing Thermometer This section describes the design steps for the thermometer using the S1C60N05 and the Thermistor. Thermometer design steps The following shows the design steps: (1) Obtain the external capacitor value and the oscillation frequency. (2) Obtain the initial value that is set to the up-counter of the A/D converter. (3) After A/D conversion, calculate the displayed temperature from the counter value that has been set in the up-counter. Details of these steps are described in later sections. Before designing the thermometer, the measured temperature range, standard temperature, and thermistor to be used have to be determined. Measured temperature range Determine for your application. Standard temperature The standard temperature is the most precise value. Determine the standard temperature as the temperature that you want to be the most precise. Thermistor Select the thermistor considering the measured temperature range and the standard temperature. It also should match the IC. Note that this document assumes the following: Measured temperature range: -30C-70C Standard temperature: 20C Thermistor: Thermistor 103AT (Compatibility with S1C60N05) S1C60N05 TECHNICAL MANUAL EPSON 81 APPENDIX: TECHNICAL INFORMATION The following A/D converter circuit diagram is shown for your reference. OSC1 clock Up/down counter 32 kHz or 65 kHz Multiplying circuit ADCLK TC15 TC11 -TC12 -TC8 Up/Down control TC7 -TC4 TC3 -TC0 Start/Stop control Data bus IAD ADRUN C15 -C12 Start/Stop C11 -C8 C7 -C4 EIAD Interrupt controller C3 -C0 Interrupt request Up-counter Start/Stop control Controller VSS ADOUT Tr3 VSS C External capacitor Tr1 CS RS Tr2 TH1 VDD Tr4 VDD TH2 R1 Standard resistor R2 Thermistor R3 Fig. A.1 A/D converter configuration 82 EPSON S1C60N05 TECHNICAL MANUAL APPENDIX: TECHNICAL INFORMATION How to obtain capacitor value and oscillation frequency Table A.1 Item Standard resistor value (R1) Computation of capacitor for oscillation The standard resistor and the thermistor are oscillated according to S1C60N05 A/D converter principles. It is necessary to determine the value of the external capacitor for the oscillation. This section describes how to determine the standard resistor value, the external capacitor value and the CR oscillation frequency. Description Thermistor resistance value at the standard temperature. The relationship between the frequency, capacitor, and the resistor is as follows: K f= CR f: Oscillation frequency K: CR oscillation frequency coefficient C: Capacitor R: Resistance From the equation above, C can be obtained based on f and K conditions of S1C60N05. If the C value is smaller within the conditions, the precision is higher. Thermistor 103AT usage example At 25C, the 103AT resistance is 10 k. Thus the standard resistance is 10 k. The f and K conditions of S1C60N05 are as follows: f(max) = 85 kHz (limit of IC operation) 1K3 (Oscillation coefficient in S1C60N05) With these conditions, the following equation can be derived: K CR2(TMAX) R2(TMAX): Minimum resistance of Thermistor 85 kHz K=3 is the worst condition, then C 3 = 15,800 (pF) 85x103x2.23x103 As a result, the following is determined: Computation of frequency from the standard resistance If the C value is determined by the above equation, the frequency (fCR1) by the standard resistance can be obtained by the following equation: fCR1 (kHz) = C = 22,000 (pF) (Value for general purpose product) The following is obtained: fCR1 = (1 to 3) = 4.5 to 13.5 (kHz) 22,000x10-12x10x103 K CR1 By the above equations, the capacitor value (22,000 pF) and the oscillation frequency (4.5-13.5 kHz) by the standard resistance are determined. For the details of 103AT, see Appendix C. S1C60N05 TECHNICAL MANUAL EPSON 83 APPENDIX: TECHNICAL INFORMATION The capacitor value and the oscillation frequency by the standard resistance are determined in the previous section. This section describes how to set the initial value of the A/D converter's up counter. For A/D converter principals, see the technical manual for the S1C60N05. Setting up counter initial value fCR1 0 Up counter fCR2 tA 0 Up-down counter Fig. A.2 fx'tal tA CUPS 65535 - CUPI tA fx'tal: fCR1: fCR2: 65535 - CUPI: CUPS: 65535: tA: 65535 65535 Crystal oscillation frequency Standard oscillation frequency Thermistor oscillation frequency Up counter initial value Thermistor count value MAX. counter value Count time fx'tal Figure A.2 shows the relationship between the up counter and the up-down counter. The following conditions should be satisfied: Condition (A): The up-down counter should not overflow during an up-count Condition (B): The up counter should not overflow during a downcount With these conditions, the up counter initial value can be obtained with the following equations: Table A.2 Description Item Thermistor 103AT usage example From the condition (A) the following equation is From fx'tal = 65 kHz, fCR1 = 4.5-13.5 kHz Obtain the up counter initial value derived: 4.5x103 CUPI = ( 1 from the condition )x65535 59571 65535 - CUPI 65x103 65535 > tA*fx'tal = x fx'tal (A) fCR1 13.5x103 )x 65535 50707 CUPI = ( 1 fCR1 65x103 CUPI > ( 1)x 65535 fx'tal Initial value 65535 - 59571 = 5964 ...(a)' Initial value 65535 - CUPI ...(a) From the condition (B) the following equation is fCR1 = 4.5-13.5 kHz, Obtain the up counter initial value derived: fCR2 = 85 kHz (IC operational maximum) from the condition 65535 > CUPS = tAxfCR2(3) 4.5x103 (B) CUPI = ( 1 )x65535 60608 fCR2 85x103 = x(65535 - CUPI) 3 fCR1 13.5x10 CUPI = ( 1 )x65535 53837 fCR1 85x103 CUPI = ( 1 )x65535 fCR2(3) Initial value 65535 - 60608 = 4927 ...(b)' Initial value 65535 - CUPI ...(b) From (a)' and (b)', the initial value should be set less From the above equations (a) and (b) the initial than 4927. Here, it is set to 3000. value can be determined. (Under the conditions, if the initial value is smaller, the precision is higher.) The initial value (3,000) for the up counter is derived from the above equations. 84 EPSON S1C60N05 TECHNICAL MANUAL APPENDIX: TECHNICAL INFORMATION Computation method of displayed temperature by linear approximation The following shows the linear approximation equation to derive the displayed temperature. Displayed temperature (C) = (Count after A/D conversion - Count for minimum in the temperature range) x linear approximation coefficient + minimum value of the temperature range This equation derives the displayed temperature. The following shows the method. First, each value is described. [Count value after A/D conversion] This is the up counter value after an A/D conversion. [Count for the minimum value of the temperature range] [Minimum value of the temperature range] To derive the displayed temperature by the linear approximation, the temperature range must be determined for the linear approximation. In this example, the measured temperature range is -30 to 70C. If the temperature range for the linear approximation is set for every 10C, the temperature range is -30 to -20C, -20 to -10C, and so on. The smallest value of each temperature range segment is the minimum value of the temperature range. The largest value is the maximum value of the temperature range. The count value for the minimum value for the temperature range is expressed by the following equation: fCR2(3) x up counter initial value fCR1 (K/CR2(3)) = x up counter initial value (K/CR1) R1 = x up counter initial value R2(3) A/D converter count value = By substituting R2 (Thermistor resistance), R1 (standard resistance), and the up counter initial value with actual values, the count value for the minimum of the temperature range is obtained. [Linear approximation coefficient] The linear approximation coefficient is the value that shows how many degrees (centigrade) for one count in the temperature range. The linear approximation coefficient is expressed by the following equation: Linear approximation coefficient = Temperature range Count for max. of temperature range - Count for min. of temperature range (As you can see, the temperature range is smaller, the precision is higher.) S1C60N05 TECHNICAL MANUAL EPSON 85 APPENDIX: TECHNICAL INFORMATION The following table shows the various values for every 10C. Table A.3 Linear approximation Temperature 103AT Thermistor coefficient in the specified Count value (C) R2 resistance (k) temperature range -30 111.3 269 0.0575 -20 67.74 443 0.0380 -10 42.45 706 0.0254 0 27.28 1099 0.0175 10 17.96 1670 0.0123 20 12.09 2481 0.00887 30 8.313 3608 0.00650 40 5.828 5147 0.00485 50 4.161 7209 0.00368 60 3.021 9930 0.00283 70 2.229 13459 The following example derives a displayed temperature using the values in the above table. Example: Assume the count value after an A/D conversion is 3200. Then, it is between 3608 and 2481 in the table. As a result the temperature range is 20 to 30C. * The count value for the minimum value of the temperature range: 2481 * The count value for the maximum value of the temperature range: 3608 Then, the linear approximation coefficient of the temperature range is 0.00887. As a result, the displayed temperature is derived as follows: Displayed temperature = (3200 - 2481) x 0.00887 + 20 (C) = 26.377 (C) 86 EPSON S1C60N05 TECHNICAL MANUAL APPENDIX: TECHNICAL INFORMATION Appendix B Error Factors When a temperature is computed using the S1C60N05 A/D converter and the Thermistor, the following error factors should be taken in account: Thermistor resistance dispersion The Thermistor manufacturer should guarantee the precision. A/D converter error factors Error (circuit) by A/D conversion in R1 (standard resistance) and R2 (Thermistor) By the CR oscillation at the standard resistor (R1), the up counter and the up-down counter increment the counter with the timing shown below. ADRUN register CS pin ADOUT output Up counter enable Starts counting Up counter (C0) Clock (Up-down counter) Up-down counter enable Fig. B.1 Starts counting Up-down counter (TC0) After the A/D RUN, the first trailing edge of the CS pin triggers the up counter enable. From the next trailing edge, the up counter starts to count. In addition, the first trailing edge of the clock after the up counter is enabled, the up-down counter is enabled and it starts to count from the next trailing edge. When the up counter value becomes 0, the up counter is disabled. The next trailing edge of the clock disables the up-down counter. If this situation occurs, the error described below will result. Min. 0 Max. Up-down counter - 1 count Stopped: Min 0 Max. Up-down counter - 1 count Started: Total up-down counter - 2 counts The same is true in the CR oscillation by Thermistor R2, and a similar error occurs. Exception: because the up-down counter is down-counted the following counting error occurs: Min. 0 Max. Up-down counter - 1 count Stopped: Min 0 Max. Up-down counter - 1 count Started: Total up-down counter - 2 counts Therefore, as for the error from the circuit, a maximum of 2 count errors results. S1C60N05 TECHNICAL MANUAL EPSON 87 APPENDIX: TECHNICAL INFORMATION The effect of the maximum 2 count error is given below. 2 x 100 --- (1) (fCLK/fCR1) x CUPI1 2 2MAX (%) = x 100 --- (2) (fCLK/fCR2) x CUPS 1MAX (%) = fCLK: Clock frequency (32 kHz/64 kHz) fCR1: CR oscillation frequency by standard resistor CUPI1: Up counter initial value (times) 1MAX:Maximum error (%) at CR oscillation by standard resistor fCR2: CR oscillation frequency by Thermistor CUPS: Thermistor count (times) 2MAX:Maximum error (%) at CR oscillation by Thermistor In addition, the number of counts of the up-down counter should be the same. Then the following equation is true: fCLK fCLK x CUPI1 = x CUPS --- (3) fCR2 fCR1 Then, from (3), assume the up-down counter counts shifted 2 counts, the following equations are true: fCLK fCLK x CUPI1 = x CUPS 2 fCR2 fCR1 CUPS 2 x (fCR2/fCLK) fCR2 = --- (3)' CUPI1 fCR1 (1) is the count error at the CR oscillation by the standard resistor. (2) is the count error at the CR oscillation by Thermistor. The total error is expressed by the equation (3)' with the ratio of fCR1 and fCR2. The segment that represents the error in the equation (3)' is 2 x (fCR2/fCLK). If the values CUPI1 and CUPS are large, this error factor may be ignored. For how to determine the initial value (CUPI1) of the up counter, see the section describing thermometer design steps. CR oscillation constant (K) error The constant, K, is determined by the logic level of the internal Schmidt trigger of the IC. However, in S1C60N05, the Schmidt trigger shares the circuit with the standard resistor and Thermistor. As a result, oscillation is canceled and no error occurs. Error by transistor ON resistance The transistor ON resistance is directly connected to the standard resistor and Thermistor; this may cause an error. See the circuit shown next to Figure B.2 below. In this circuit, the capacitor is charged by Tr1, T2 ON and Tr3 OFF. If the voltage at the CS pin changes to a certain level, the capacitor charge is drained by Tr1, Tr2 OFF and Tr3 ON. As a result, the CR oscillation is generated as in Figure B.3. 88 EPSON S1C60N05 TECHNICAL MANUAL APPENDIX: TECHNICAL INFORMATION VSS ADOUT Tr3 VSS C Tr1 RS CS Tr2 TH1 VDD Tr4 VDD TH2 R1 R2 R3 Fig. B.2 Fig. B.3 t1 t2 At this time, if the ON resistance of Tr1 and Tr2 ON is t1 and the ON resistance of Tr3 is t2, the constance may be effected. The S1C60N05 transistors are standardized to have a maximum of 100 . This standard includes dispersion by temperature characteristics, Pch and Nch. The Evaluation board transistor uses standard ICs and the actual resistance is about 1 k. (This is not guaranteed and should be regarded as just a reference.) The error by ON resistance of this transistor is expressed by the following equations: Up counter count - Actual upcounter count x 100 Up counter count K C(R1 + RTr) CUPI1 x CUPI1 fCR1 R1 = x 100 = { 1} x 100 (R1 + RTr) CUPI1 3 (%) = Up counter count - Actual upcounter count x 100 Up counter count K C(R2 + RTr) CUPS x CUPI1 fCR2 R2 = x 100 = { 1} x 100 (R2 + RTr) CUPS 4 (%) = 3: Error (%) by transistor ON resistance (CR oscillation by standard resistance) 4: Error (%) by transistor ON resistance (CR oscillation by Thermistor) CUPI1: Up counter initial value (times) CUPS: Thermistor count value (times) RTr: Transistor ON resistance () fCR1: Oscillation frequency (Hz) (CR oscillation by standard resistance) fCR2: Oscillation frequency (Hz) (CR oscillation by Thermistor) S1C60N05 TECHNICAL MANUAL EPSON 89 APPENDIX: TECHNICAL INFORMATION Example: Transistor ON resistance error when Thermistor 103AT measures 60C 3 = { 1 - 10 x 103 } x 100 1% (10 x 103 + 100) 4 = { 1 - 3.217 x 103 } x 100 3% (3.217 x 103 + 100) As a result, the following errors occur by directly connecting the transistor ON resistance: 1% at CR oscillation on the standard resistor 3% at CR oscillation on Thermistor The transistor ON resistance effect is smaller if R1 and R2 are larger. (See Equation 3 and 4.) In the high temperature range, the R2 value becomes small and 4 becomes large. This causes precision degradation. Compensation is needed to implement a user's required precision. Figure B.4 shows the A/D converter ON resistance errors (4 - 3) of the Evaluation board and the actual IC when the thermistor 103AT is used. ON resistance errors when thermistor 103AT is used Error 4 - 3 (%) Error by ON resistance (1 k) in the Evaluation board 30 20 Error by ON resistance (100 ) in the actual IC 10 0 -50 -20 0 25 50 70 100 Temperature (C) -10 Fig. B.4 -20 This figure shows the plot of errors when the ON resistance in the Evaluation board is 1 k and that of the actual IC is 100 . As shown in the figure, the Evaluation board's error is larger than the actual IC, therefore, programs evaluated using the Evaluation board may not operate normally in the actual IC. To avoid this problem, it is necessary to reduce the ON resistance error. Choose a thermistor resistance as large as possible to reduce the ON resistance error. At least 10 k (Ta = 25C) of resistance is required. The plot (Figure B.4) is in this case shows a 10 k thermistor resistance that satisfies the minimum resistance condition, note, however, that there is a large error increase in temperature over 60C. 90 EPSON S1C60N05 TECHNICAL MANUAL APPENDIX: TECHNICAL INFORMATION For example, when using a 10 k (Ta = 25C) thermistor for the actual IC, the ON resistance in the Evaluation board can be close to that of the actual IC by connecting 10 thermistors in series to configure a 100 k (Ta = 25C) thermistor and by using a 100 k reference resistance and reducing the capacitance to 1/10. However, ON resistance is so susceptible to source voltage levels and board mount conditions affect the conversion results, therefore, it is impossible to obtain exactly the same results between the Evaluation board and the actual IC even if the methods described above are used. It is necessary to evaluate the A/D conversion using the results of several samples from the final product. Error by floating capacity The floating capacity of the inside of an IC, board, lead of a sensor and others may be an error factor. Floating capacity inside an IC may be several pF and it may be ignored by increasing the capacitor value. Software error In the software, it is normal to convert the counter value to an actual temperature by a linear approximation. In this method, an error may be caused by the linear approximation in the temperature measured range. As shown in Figure B.5 below, if the temperature range measured is 20C to 30C, the weight of 1 count differs between 20C and 29C. (1) (2) Temperature (C) 30 29 20 Fig. B.5 Counts (times) On the slope (1), the linear approximation coefficient in this segment for 1 count is large, and the slope (2) has a smaller coefficient. For example, if this segment (20C to 30C) is calculated by the same linear approximation coefficient, and if the 20C is the reference point, then, at 29C, the linear approximation coefficient becomes the largest and, at 29C, the error is maximum. The error may differ depending on the temperature measured by the software, up counter initial value and Thermistor type. S1C60N05 TECHNICAL MANUAL EPSON 91 APPENDIX: TECHNICAL INFORMATION Appendix C AT Thermistor High precision thermistor Features The AT Thermistor has a high precision thermistor with small resistance and B constant error margin. Using the AT Thermistor as a temperature sensor does not require adjustment between a control circuit and the sensor; and the AT Thermistor provides a temperature precision of 0.3C. As a result, a high precision temperature control and temperature display are possible. * Error margins of resistance and temperature characteristics are very small. * Small age-based change and high reliability * Low price * High durability Usage Air conditioners, fan heaters, FF heaters, refrigerators, water heaters, boiler/kitchen appliances, copiers, printers, facsimiles, automatic vending machines, agricultural equipment, automobiles (for external temperature, internal temperature, air flow sensor), portable thermometers, medical equipment, thermos-type containers, solar heating system, automatic toilet seats, fire alarms, home automation Type number 103 AT - 2 External type High precision AT Thermistor Zero load resistance (25C) 103: 10 k Resistance margin graph Resistance margin (%) 5 4 3 2 1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Ambient temperature (C) 2.5 Temperature margin (C) Temperature precision graph 2.0 1C 1.5 0.7C 1.0 0.5C 0.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Ambient temperature (C) 92 EPSON S1C60N05 TECHNICAL MANUAL APPENDIX: TECHNICAL INFORMATION Comparison between AT type and others Thermistor R25 margin B margin AT type Other type 1% 5% 1% 3% Temperature margine Temperature control (display) for (25C) every 1C 0.3C Circuit adhustment - not required 1.3C Circuit adjystment - required Ratings Type R25 B constant 102AT-1 202AT-1 502AT-1 103AT-1 102AT-2 202AT-2 502AT-2 103AT-2, 3 203AT-2 103AT-4 1 k 1% 2 k 1% 5 k 1% 10 k 1% 1 k 1% 2 k 1% 5 k 1% 10 k 1% 20 k 1% 10 k 1% 3100K 1% 3182K 1% 3324K 1% 3435K 1% 3100K 1% 3182K 1% 3324K 1% 3435K 1% 4013K 1% 3435K 1% Thermal radiation Thermal Maximum power Temperature constant (mW/C) constant (s) (mW) at 25C range (C) Approx. 3 Approx. 75 15 -50 to 90 Approx. 3 Approx. 75 15 -50 to 90 Approx. 3 Approx. 75 15 -50 to 105 Approx. 3 Approx. 75 15 -50 to 105 Approx. 2 Approx. 15 10 -50 to 90 Approx. 2 Approx. 15 10 -50 to 90 Approx. 2 Approx. 15 10 -50 to 110 Approx. 2 Approx. 15 10 -50 to 110 Approx. 2 Approx. 15 10 -50 to 110 Approx. 2 Approx. 10 10 -30 to 90 External dimension (AT-3, 4 in omission) AT-1 AT-2 max.3.5 max.2.4 103AT Thermistor TPE resin Soldered TPE resin covered parallel line 0.18x12 core (0.3SQ) Black 8.51 51 Printed 171.5 max. 5 max. 15 max.4.0 +20 600 -0 Taper cut 0.7 Temperature difference (%) Epoxy resin 0.5 tinned 42 alloy Color code : Black : Red : Yellow : White : No color : 2.540.25 Thermal response Color code Type 102AT-2 202AT-2 502AT-2 103AT-2 203AT-2 Board soldering method Proper usage example 100 95.0 86.5 AT-2 (in the air) 63.2 60 8.5 AT-1 (in the air) 40 Board 20 2.54 0 10 20 30 40 50 60 70 80 90 Time (s) S1C60N05 TECHNICAL MANUAL EPSON 100 Proper soldering conditions: 260C, 10 seconds or less 93 APPENDIX: TECHNICAL INFORMATION Resistance - Temperature characteristics -50 to 29C Temp (C) -50 -49 -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 94 Rmax (k) 344.4 324.7 306.4 289.2 273.2 258.1 244.0 230.8 218.5 206.8 195.9 185.4 175.5 166.2 157.5 149.3 141.6 134.4 127.6 121.2 115.1 109.3 103.8 98.63 93.75 89.15 84.82 80.72 76.85 73.20 69.74 66.42 63.27 60.30 57.49 54.83 52.31 49.93 47.67 45.53 43.50 41.54 39.68 37.91 36.24 34.65 33.14 31.71 30.35 29.06 27.83 26.64 25.51 24.44 23.42 22.45 21.52 20.64 19.80 19.00 18.24 17.51 16.80 16.13 15.50 14.89 14.31 13.75 13.22 12.72 12.23 11.77 11.32 10.90 10.49 10.10 9.732 9.381 9.044 8.721 103AT Rst (k) 329.2 310.7 293.3 277.0 261.8 247.5 234.1 221.6 209.8 198.7 188.4 178.3 168.9 160.1 151.8 144.0 136.6 129.7 123.2 117.1 111.3 105.7 100.4 95.47 90.80 86.39 82.22 78.29 74.58 71.07 67.74 64.54 61.52 58.66 55.95 53.39 50.96 48.66 46.48 44.41 42.45 40.56 38.76 37.05 35.43 33.89 32.43 31.04 29.72 28.47 27.28 26.13 25.03 23.99 22.99 22.05 21.15 20.29 19.48 18.70 17.96 17.24 16.55 15.90 15.28 14.68 14.12 13.57 13.06 12.56 12.09 11.63 11.20 10.78 10.38 10.00 9.632 9.281 8.944 8.622 30 to110C Rmin (k) 314.7 297.2 280.7 265.3 250.8 237.3 224.6 212.7 201.5 191.0 181.1 171.5 162.6 154.2 146.2 138.8 131.8 125.2 118.9 113.1 107.5 102.2 97.16 92.41 87.93 83.70 79.71 75.93 72.36 68.99 65.80 62.72 59.81 57.05 54.44 51.97 49.63 47.42 45.31 43.32 41.43 39.59 37.85 36.20 34.63 33.14 31.73 30.39 29.11 27.89 26.74 25.62 24.55 23.54 22.57 21.66 20.78 19.95 19.15 18.40 17.67 16.97 16.31 15.67 15.06 14.48 13.93 13.40 12.89 12.41 11.95 11.50 11.07 10.66 10.27 9.900 9.533 9.181 8.845 8.523 EPSON Temp (C) 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Rmax (k) 8.412 8.113 7.826 7.551 7.288 7.036 6.793 6.561 6.338 6.124 5.918 5.719 5.527 5.343 5.166 4.996 4.833 4.676 4.525 4.380 4.240 4.104 3.973 3.847 3.726 3.609 3.497 3.389 3.285 3.184 3.088 2.994 2.903 2.816 2.732 2.650 2.572 2.496 2.423 2.353 2.285 2.219 2.155 2.093 2.034 1.976 1.920 1.866 1.814 1.764 1.716 1.668 1.623 1.578 1.536 1.494 4.454 1.415 1.378 1.341 1.306 1.271 1.238 1.206 1.175 1.144 1.115 1.087 1.059 1.032 1.006 0.9812 0.9567 0.9330 0.9100 0.8877 0.8660 0.8456 0.8245 0.8047 103AT Rst (k) 8.313 8.015 7.729 7.455 7.192 6.941 6.699 6.468 6.246 6.033 5.828 5.630 5.439 5.256 5.080 4.912 4.749 4.594 4.444 4.300 4.161 4.026 3.897 3.772 3.652 3.537 3.426 3.319 3.216 3.116 3.021 2.928 2.838 2.752 2.669 2.589 2.512 2.437 2.365 2.296 2.229 2.163 2.101 2.040 1.981 1.924 1.870 1.817 1.766 1.716 1.669 1.622 1.577 1.534 1.492 1.451 1.412 1.374 1.337 1.301 1.266 1.233 1.200 1.169 1.138 1.108 1.080 1.052 1.025 0.9988 0.9735 0.9489 0.9250 0.9018 0.8793 0.8575 0.8364 0.8159 0.7960 0.7767 Rmin (k) 8.215 7.917 7.632 7.359 7.097 6.846 6.606 6.375 6.154 5.942 5.739 5.541 5.352 5.170 4.996 4.828 4.667 4.512 4.364 4.221 4.084 3.950 3.822 3.698 3.579 3.465 3.355 3.249 3.148 3.049 2.955 2.863 2.775 2.690 2.608 2.529 2.452 2.379 2.308 2.240 2.174 2.109 2.047 1.987 1.930 1.874 1.820 1.768 1.718 1.669 1.622 1.577 1.533 1.490 1.449 1.409 1.371 1.333 1.297 1.262 1.228 1.195 1.163 1.132 1.102 1.073 1.045 1.018 0.9918 0.9663 0.9416 0.9175 0.8942 0.8716 0.8496 0.8284 0.8077 0.7877 0.7683 0.7495 S1C60N05 TECHNICAL MANUAL International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 23F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 SHANGHAI BRANCH 7F, High-Tech Bldg., 900, Yishan Road Shanghai 200233, CHINA Phone: 86-21-5423-5577 Fax: 86-21-5423-4677 - SALES OFFICES West 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. Northeast 14F, No. 7, Song Ren Road, Taipei 110 Phone: 02-8786-6688 Fax: 02-8786-6660 301 Edgewater Place, Suite 120 Wakefield, MA 01880, U.S.A. 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EUROPE SEIKO EPSON CORPORATION KOREA OFFICE EPSON EUROPE ELECTRONICS GmbH 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: 02-784-6027 Fax: 02-767-3677 - HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-(0)89-14005-0 No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone: +65-6337-7911 Fax: +65-6334-2716 GUMI OFFICE Fax: +49-(0)89-14005-110 DUSSELDORF BRANCH OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10 UK & IRELAND BRANCH OFFICE Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701 FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Testa, Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 Scotland Design Center Integration House, The Alba Campus Livingston West Lothian, EH54 7EG, SCOTLAND Phone: +44-1506-605040 Fax: +44-1506-605041 6F, Good Morning Securities Bldg. 56 Songjeong-Dong, Gumi-City, 730-090, KOREA Phone: 054-454-6027 Fax: 054-454-6093 SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION ED International Marketing Department 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5117 S1C60N05 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com Document code: 404492803 First issue September, 1998 Printed January, 2004 in Japan M L A