S1C60N05D0A0100 - Seiko Epson Corporation

Technical Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C60N05 Technical Hardware

S1C60N05

NOTICE

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Revisions and Additions for this manual

Section

Appendix B

Appendix C

Page

Item

A/D converter error factors

Ratings

External dimension

Contents

Figure B.4 and the explanation were added.

The table was revised.

The figure was revised.

Chapter

Appendices

S1C60/62 Family

Devices

S1 C 60N01 F 0A01

Packing specifications

 00 : Besides tape & reel

 0A : TCP BL 2 directions

 0B : Tape & reel BACK

 0C: TCP BR 2 directions

 0D: TCP BT 2 directions

 0E : TCP BD 2 directions

 0F : Tape & reel FRONT

 0G: TCP BT 4 directions

 0H: TCP BD 4 directions

 0J : TCP SL 2 directions

 0K : TCP SR 2 directions

 0L : Tape & reel LEFT

 0M: TCP ST 2 directions

 0N: TCP SD 2 directions

 0P : TCP ST 4 directions

 0Q: TCP SD 4 directions

 0R: Tape & reel RIGHT

 99 : Specs not fixed

Specification

Package

 D: die form; F: QFP

Model number

Model name

 C: microcomputer, digital products

Product classification

 S1: semiconductor

Development tools

S5U1 C 60R08 D1 1

Packing specifications

 00: standard packing

Version

 1: Version 1

Tool type

 Hx : ICE

 Ex : EVA board

 Px : Peripheral board

 Wx: Flash ROM writer for the microcomputer

 Xx : ROM writer peripheral board

 Cx : C compiler package

 Ax : Assembler package

 Dx : Utility tool by the model

 Qx : Soft simulator

Corresponding model number

 60R08: for S1C60R08

Tool classification

 C: microcomputer use

Product classification

 S5U1: development tool for semiconductor products

Configuration of product number

S1C60N05 TECHNICAL MANUAL EPSON i

CONTENTS

CHAPTER 1 INTRODUCTION................................................................ 1

1.1 Configuration .................................................................... 1

1.2 Features ........................................................................... 2

1.3 Block Diagram .................................................................. 3

1.4 Pin Layout Diagram.......................................................... 4

1.5 Pin Description ................................................................. 5

CHAPTER 2 POWER SUPPLY AND INITIAL RESET ................................. 6

2.1 Power Supply ................................................................... 6

2.2 Initial Reset....................................................................... 8

Oscillation detection circuit....................................... 9

Reset pin (RESET) ..................................................... 9

Simultaneous high input to input ports (K00–K03) .... 9

Internal register following initialization..................... 10

2.3 Test Pin (TEST)............................................................... 10

CHAPTER 3 CPU, ROM, RAM ............................................................. 11

3.1 CPU................................................................................. 11

3.2 ROM ................................................................................ 12

3.3 RAM ................................................................................ 12

CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ....................... 13

4.1 Memory Map ................................................................... 13

4.2 Oscillation Circuit............................................................. 16

Crystal oscillation circuit.......................................... 16

CR oscillation circuit ................................................ 17

ii EPSON S1C60N05 TECHNICAL MANUAL

CONTENTS

4.3 Input Ports (K00–K03)..................................................... 18

Configuration of input ports ..................................... 18

Input comparison registers and interrupt function ... 19

Mask option ............................................................. 20

Control of input ports............................................... 20

4.4 Output Ports (R00–R03).................................................. 22

Configuration of output ports ................................... 22

Mask option ............................................................. 23

Control of output ports............................................. 25

4.5 I/O Ports (P00–P03) ........................................................ 28

Configuration of I/O ports........................................ 28

I/O control register and I/O mode............................ 28

Mask option ............................................................. 29

Control of I/O ports ................................................. 29

4.6 LCD Driver (COM0–COM3, SEG0–SEG19) ................... 31

Configuration of LCD driver...................................... 31

Cadence adjustment of oscillation frequency ............ 37

Mask option (segment allocation).............................. 38

Control of LCD driver ............................................... 40

4.7 Clock Timer ..................................................................... 41

Configuration of clock timer ..................................... 41

Interrupt function .................................................... 42

Control of clock timer............................................... 43

4.8 A/D Converter.................................................................. 45

Configuration of A/D converter ................................ 45

Operation of A/D converter ...................................... 46

Interrupt function .................................................... 51

Usage example of the A/D converter......................... 51

Control of A/D converter .......................................... 53

4.9 Heavy Load Protection Function ..................................... 57

Operation of heavy load protection function ............. 57

Control of heavy load protection function ................. 58

4.10 Interrupt and HALT.......................................................... 59

Interrupt factors....................................................... 60

Specific masks and factor flags for interrupt............. 61

Interrupt vectors ...................................................... 61

Control of interrupt .................................................. 62

S1C60N05 TECHNICAL MANUAL EPSON iii

CONTENTS

CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM............................. 63

CHAPTER 6 ELECTRICAL CHARACTERISTICS ..................................... 65

6.1 Absolute Maximum Rating .............................................. 65

6.2 Recommended Operating Conditions ............................. 66

6.3 DC Characteristics .......................................................... 67

6.4 Analog Circuit Characteristics

and Power Current Consumption .................................... 69

6.5 Oscillation Characteristics ............................................... 73

CHAPTER 7 PACKAGE ....................................................................... 75

7.1 Plastic Package............................................................... 75

7.2 Ceramic Package for Test Samples................................ 76

CHAPTER 8 PAD LAYOUT ................................................................... 77

8.1 Diagram of Pad Layout.................................................... 77

8.2 Pad Coordinates.............................................................. 78

CHAPTER 9 PRECAUTIONS ON MOUNTING ...................................... 79

Oscillation circuit..................................................... 79

Reset circuit ....................................................................

Power supply circuit................................................. 79

Arrangement of signal lines .............................................

Precautions for visible radiation (when bare chip is

mounted) ................................................................. 80

Appendices TECHNICAL INFORMATION ............................................ 81

Appendix A Design Steps for Designing Thermometer ...................... 81

Thermometer design steps........................................ 81

How to obtain capacitor value and oscillation frequency ..

Setting up counter initial value ................................ 84

Computation method of displayed temperature

by linear approximation ........................................... 85

iv EPSON S1C60N05 TECHNICAL MANUAL

CONTENTS

Appendix B Error Factors ................................................................... 87

Thermistor resistance dispersion.............................. 87

A/D converter error factors ...................................... 87

Error by floating capacity ......................................... 91

Software error .......................................................... 91

Appendix C AT Thermistor.................................................................. 92

S1C60N05 TECHNICAL MANUAL EPSON 1

CHAPTER 1: INTRODUCTION

CHAPTER 1

1.1

Table 1.1.1

Configuration of the

S1C60N05 Series

INTRODUCTION

Each member of the S1C60N05 Series of single chip micro-

computers feature a 4-bit S1C6200B core CPU, 1,536 words

of ROM (12 bits per word), 80 words of RAM (4 bits per

word), an LCD driver, 4 bits for input ports (K00–K03), 4

bits for output ports (R00–R03), one 4-bit I/O port (P00–

P03), clock timer and A/D converter.

Because of their low voltage operation and low power con-

sumption, the S1C60N05 Series are ideal for a wide range of

applications.

Configuration

The S1C60N05 Series are configured as follows, depending

on the supply voltage.

Model Supply voltage Oscillation circuits

1.8–3.5 V

1.2–2.0 V

S1C60N05

S1C60L05

Crystal or CR

2EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 1: INTRODUCTION

Features

S1C6200B

Crystal or CR oscillation circuit, 32,768 Hz (typ.)

100 instructions

1,536 words × 12 bits

80 words × 4 bits

4 bits (Supplementary pull-down resistors may be used)

4 bits (Piezo buzzer and programmable frequency output

can be driven directry by mask option)

4 bits

20 segments × 4 common duty (or 3 and 2 common duty)

Clock timer

CR oscillation type A/D converter built-in (2 channels)

Input port interrupt 1 system

Timer interrupt 1 system

A/D converter interrupt 1 system

1.5 V (1.2–2.0 V) S1C60L05 (During A/D conversion)

3.0 V (1.8–3.5 V) S1C60N05

0.8 µA (Crystal oscillation CLK = 32,768 Hz, when halted)

1.5 µA

(Crystal oscillation CLK = 32,768 Hz, when executing)

QFP6-60pin (plastic) or chip

1.2

Core CPU

Built-in oscillation circuit

Instruction set

ROM capacity

RAM capacity (data RAM)

Input port

Output port

Input/output port

LCD driver

Timer

A/D converter

Interrupts:External interrupt

Internal interrupt

Supply voltage

Current consumption (typ.)

Supply form

S1C60N05 TECHNICAL MANUAL EPSON 3

CHAPTER 1: INTRODUCTION

COM0–3

SEG0–19

K00–03

P00–03

R00–03

OSC1

OSC2

RESET

TEST

Power

Controller

RAM

80 words x 4 bits

OSC System Reset

Control

VDD

VL1–3

CA–CB

VS1

VSS

ADOUT

TH1

TH2

Interrupt

Generator

Input Port

Test Port

LCD Driver

I/O Port

Output Port

Timer

Core CPU S1C6200B

A/D Converter

ROM

1,536 words x 12 bits

1.3

Fig. 1.3.1

Block diagram

Block Diagram

4EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 1: INTRODUCTION

3145

INDEX

151

1.4

QFP6-60pin

Pin No.

Pin name

N.C.

ADOUT

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

N.C.

Pin No.

Pin name

TEST

RESET

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

COM0

COM1

COM2

COM3

N.C.

Pin No.

Pin name

N.C.

K00

K01

K02

K03

R00

R01

R02

R03

TH1

TH2

N.C.

Pin name

OSC1

OSC2

P00

P01

P02

P03

N.C.

Pin Layout Diagram

Fig. 1.4.1

Pin assignment

N.C. = No connection

S1C60N05 TECHNICAL MANUAL EPSON 5

CHAPTER 1: INTRODUCTION

1.5

Table 1.5.1 Pin description

Terminal name

VDD

VSS

VS1

VL1

VL2

VL3

CA, CB

OSC1

OSC2

K00–K03

P00–P03

R00–R03

SEG0–19

COM0–3

TH1, TH2

ADOUT

RESET

TEST

Pin No.

49, 50

3–6

56–59

7–10

18–29

33–40

41–44

12, 13

Input/Output

(I)

–

I/O

Function

Power source (+) terminal

Power source (-) terminal

Oscillation and internal logic system regulated voltage output terminal

LCD system regulated voltage output terminal

LCD system booster output terminal

Booster capacitor connecting terminal

Crystal or CR oscillation input terminal

Crystal or CR oscillation output terminal

Input terminal

I/O terminal

Output terminal

LCD segment output terminal

(convertible to DC output terminal by mask option)

LCD common output terminal

A/D converter CR oscillation input terminal

A/D converter CR oscillation output terminal

A/D converter oscillation frequency output terminal

Initial setting input terminal

Test input terminal

Pin Description

6EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

POWER SUPPLY AND INITIAL RESETCHAPTER 2

2.1

Note

Power Supply

With a single external power supply (*1) supplied to VDD

through VSS, the S1C60N05 Series generate the necessary

internal voltages with the regulated voltage circuit (<VS1> for

oscillators and internal circuit) and the voltage booster/

reducer (<VL2, VL3 or VL1, VL3> for LCDs).

When the S1C60N05 LCD power is selected for 4.5 V LCD

panel by mask option, the S1C60N05 short-circuits between

<VL2> and <VSS> in internally, and the voltage booster/

reducer generates <VL1> and <VL3>. When 3.0 V LCD panel

is selected, the S1C60N05 short-circuits between <VL3> and

<VSS>, and the voltage reducer generates <VL1> and <VL2>.

The S1C60L05 short-circuits between <VL1> and <VSS>, and

the voltage booster generates <VL2> and <VL3>.

The voltage <VS1> for the internal circuit that is generated

by the regulated voltage circuit is -1.2 V (VDD standard).

Figure 2.1.1 shows the power supply configuration of the

S1C60N05 Series in each condition.

*1 Supply voltage: S1C60N05.... 3.0 V

S1C60L05 .... 1.5 V

- External loads cannot be driven by the output voltage of the

regulated voltage circuit and the voltage booster/reducer.

- See Chapter 6, "ELECTRICAL CHARACTERISTICS", for

voltage values.

S1C60N05 TECHNICAL MANUAL EPSON 7

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

• S1C60N05

4.5 V LCD panel

1/4, 1/3, 1/2 duty, 1/3 bias

Note: VL2 is shorted to VSS inside the IC.

3 V LCD panel 3 V LCD panel

1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias

• S1C60L05

4.5 V LCD panel 3 V LCD panel

1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias

Note: VL1 is shorted to VSS inside the IC.

Fig. 2.1.1 External element configuration of power system

Note: VL3 is shorted to VSS inside the IC.

VDD

VS1

VL1

VL2

VL3

VSS

3 V

VDD

VS1

VL1

VL2

VL3

VSS

3 V

VDD

VS1

VL1

VL2

VL3

VSS

3 V

1.5 V

8EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Initial Reset

To initialize the S1C60N05 Series circuits, an initial reset

must be executed. There are three ways of doing this.

(1)Initial reset by the oscillation detection circuit (

Note

)

(2)External initial reset via the RESET pin

(3)External initial reset by simultaneous high input to pins

K00–K03 (depending on mask option)

Figure 2.2.1 shows the configuration of the initial reset

circuit.

2.2

Vss

RESET

K03

K02

K01

K00

OSC2

OSC1

Oscillation

circuit

Vss

Oscillation

detection

circuit Noise

rejection

circuit

Initial

reset

Noise

rejection

circuit

Fig. 2.2.1

Configuration of

initial reset circuit

Since the circuit may sometimes not operate normally with the

initial resetting by the oscillation detection circuit indicated in

number (1), depending on the method of making the power, you

should utilize one of the initial resetting methods mentioned in

numbers (2) and (3).

Note

S1C60N05 TECHNICAL MANUAL EPSON 9

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

When the oscillation circuit has been stopped until the

oscillation circuit begins to oscillate when the power is

turned on or for any other reason, the oscillation detection

circuit will output an initial reset signal, but since the

circuit may sometimes not operate normally with the initial

resetting due to the oscillation detection circuit, depending

on the method of making the power, you should utilize one

of the initial resetting methods indicated hereafter.

An initial reset can be invoked externally by making the

reset pin high. This high level must be maintained for at

least 5 ms (when oscillating frequency, fosc = 32 kHz),

because the initial reset circuit contains a noise rejection

circuit. When the reset pin goes low the CPU begins to

operate.

Another way of invoking an initial reset externally is to input

a high signal simultaneously to the input ports (K00–K03)

selected with the mask option. The specified input port pins

must be kept high for at least 4 sec (when oscillating fre-

quency fosc = 32 kHz), because of the noise rejection circuit.

Table 2.2.1 shows the combinations of input ports (K00–

K03) that can be selected with the mask option.

ANot used

BK00*K01

CK00*K01*K02

DK00*K01*K02*K03

When, for instance, mask option D (K00*K01*K02*K03) is

selected, an initial reset is executed when the signals input

to the four ports K00–K03 are all high at the same time.

If you use this function, make sure that the specified ports

do not go high at the same time during normal operation.

Oscillation detection

circuit

Reset pin (RESET)

Table 2.2.1

Input port combinations

Simultaneous high

input to input ports

(K00–K03)

10 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Internal register fol-

lowing initialization

An initial reset initializes the CPU as shown in the table

below.

CPU Core

Name

Program counter step

Program counter page

New page pointer

Stack pointer

Index register X

Index register Y

General register A

General register B

Interrupt flag

Decimal flag

Zero flag

Carry flag

Signal

PCS

PCP

NPP

Number of bits

Setting value

00H

Undefined

Table 2.2.2

Initial values

2.3

Peripheral circuits

Name

RAM

Display memory

Other peripheral circuit

Number of bits

80 × 4

20 × 4

–

Setting value

Undefined

*1: See Section 4.1, "Memory Map"

Test Pin (TEST)

This pin is used when IC is inspected for shipment.

During normal operation connect it to VSS.

S1C60N05 TECHNICAL MANUAL EPSON 11

CHAPTER 3: CPU, ROM, RAM

CPU, ROM, RAM

CPU

The S1C60N05 Series employs the S1C6200B core CPU, so

that register configuration, instructions, and so forth are

virtually identical to those in other processors in the family

using the S1C6200B. Refer to the "S1C6200/6200A Core

CPU Manual" for details of the S1C6200B.

Note the following points with regard to the S1C60N05

Series:

(1)The SLEEP operation is not provided, so the SLP instruc-

tion cannot be used.

(2)Because the ROM capacity is 1,536 words, 12 bits per

word, bank bits are unnecessary, and PCB and NBP are

not used.

(3)The RAM page is set to 0 only, so the page part (XP, YP)

of the index register that specifies addresses is invalid.

PUSH XP PUSH YP

POP XP POP YP

LD XP,r LD YP,r

LD r,XP LD r,YP

CHAPTER 3

3.1

12 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 3: CPU, ROM, RAM

ROM

The built-in ROM, a mask ROM for the program, has a

capacity of 1,536 × 12-bit steps. The program area is 6

pages (0–5), each consisting of 256 steps (00H–FFH). After

an initial reset, the program start address is page 1, step

00H. The interrupt vector is allocated to page l, steps 01H–

07H.

3.2

RAM

The RAM, a data memory for storing a variety of data, has a

capacity of 80 words, 4-bit words. When programming,

keep the following points in mind:

(1)Part of the data memory is used as stack area when

saving subroutine return addresses and registers, so be

careful not to overlap the data area and stack area.

(2)Subroutine calls and interrupts take up three words on

the stack.

(3)Data memory 000H–00FH is the memory area pointed by

the register pointer (RP).

3.3

Fig. 3.2.1

ROM configuration

00H step

07H step

08H step

FFH step

12 bits

Program start address

Interrupt vector area

Bank 0

Program area

0 page

1 page

2 page

3 page

4 page

5 page

01H step

S1C60N05 TECHNICAL MANUAL EPSON 13

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

PERIPHERAL CIRCUITS AND

OPERATION

Peripheral circuits (timer, I/O, and so on) of the S1C60N05

Series are memory mapped. Thus, all the peripheral circuits

can be controlled by using memory operations to access the

I/O memory. The following sections describe how the pe-

ripheral circuits operate.

CHAPTER 4

Memory Map

The data memory of the S1C60N05 Series has an address

space of 137 words, of which 32 words are allocated to

display memory and 25 words, to I/O memory. Figure 4.1.1

show the overall memory map for the S1C60N05 Series, and

Tables 4.1.1(a) and (b), the memory maps for the peripheral

circuits (I/O space).

4.1

Address

Page High

Low 0123456789ABCDEF

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

RAM area (000H–04FH)

80 words x 4 bits (R/W)

Display memory area (090H–0AFH)

32 words x 4 bits (Write only)

Unused area

I/O memory area Table 4.1.1(a), (b)

Fig. 4.1.1

Memory map

Note Memory is not mounted in unused area within the memory map

and in memory area not indicated in this chapter. For this reason,

normal operation cannot be assured for programs that have been

prepared with access to these areas.

14 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(a) I/O memory map

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E0H

K00

K03

K02

K01

K00

–

Input port data K03

Input port data K02

Input port data K01

Input port data K00

High

Low

K01K02K03

0E3H

TM0

TM3

TM2

TM1

TM0

–

Clock timer data 2 Hz

Clock timer data 4 Hz

Clock timer data 8 Hz

Clock timer data 16 Hz

High

Low

TM1TM2TM3

0E4H

TC0

R/W

TC3

TC2

TC1

TC0

Up/down counter data TC3

Up/down counter data TC2

Up/down counter data TC1

Up/down counter data TC0 (LSB)

TC1TC2TC3 –

–

TC4

R/W

TC7

TC6

TC5

TC4

–

Up/down counter data TC7

Up/down counter data TC6

Up/down counter data TC5

Up/down counter data TC4

TC5TC6TC7

0E5H

0E6H

TC8

R/W

TC11

TC10

TC9

TC8

–

Up/down counter data TC11

Up/down counter data TC10

Up/down counter data TC9

Up/down counter data TC8

TC9TC10TC11

0E7H

TC12

R/W

TC15

TC14

TC13

TC12

–

Up/down counter data TC15 (MSB)

Up/down counter data TC14

Up/down counter data TC13

Up/down counter data TC12

TC13TC14TC15

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

S1C60N05 TECHNICAL MANUAL EPSON 15

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(b) I/O memory map

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F4H

P00

R/W

P03

P02

P01

P00

–

I/O port data P03

I/O port data P02

I/O port data P01

I/O port data P00

High

Low

P01P02P03

0F5H

R/W

Up-counter data C3

Up-counter data C2

Up-counter data C1

Up-counter data C0 (LSB)

C1C2C3 –

–

R/W

–

Up-counter data C7

Up-counter data C6

Up-counter data C5

Up-counter data C4

C5C6C7

0F6H

0F7H

R/W

C11

C10

–

Up-counter data C11

Up-counter data C10

Up-counter data C9

Up-counter data C8

C9C10C11

0F8H

C12

R/W

C15

C14

C13

C12

–

Up-counter data C15 (MSB)

Up-counter data C14

Up-counter data C13

Up-counter data C12

C13C14C15

0F9H

TMRST

TMRST Reset

Clock timer reset

Reset –

0FBH

0CSDC

LCD drive switch

Static Dynamic

0CSDC

R/W

0FDH

XFOUT0

R/W

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

FOUT frequency control

2 kHz 4 kHz

XFOUT10

XBZR

R/W

0FCH

IOC

R/W

IOC 0

I/O port I/O control register

Out In

0FEH

ADCLK

R/W

ADCLK 0

A/D clock selection 65 kHz/32 kHz

65 kHz 32 kHz

0F1H

ADRUN

R/W

CHTH

ADRUN

A/D channel selection

A/D conversion Start/Stop

TH2

Start

TH1

Stop

00CHTH

R/W

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

0F3H

R00

FOUT

R03

R02

R01

BUZZER

R00

FOUT

Output port data R03

Output port data R02

Output port data R01

Buzzer On/Off control register

Output port data R00

Frequency output control register

High

Low

Off

Low

Off

R01

BUZZER

R02R03

R/W

0FAH

0HLMOD

Heavy load protection mode register

Heavy Normal

00HLMOD

R/W

16 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

Oscillation Circuit

The S1C60N05 Series has a built-in oscillation circuit.

For the oscillation circuit, eiter crystal oscillation or CR

oscillation may be selected by a mask option.

The crystal oscillation circuit generates the operating clock

for the CPU and peripheral circuit on connection to an

external crystal oscillator (typ. 32.768 kHz) and trimmer

capacitor (5–25 pF).

Figure 4.2.1 is the block diagram of the crystal oscillation

circuit.

4.2

Crystal oscillation

circuit

Fig. 4.2.1

Crystal oscillation circuit

X'tal

OSC2

OSC1

To CPU and

peripheral circuits

The S1C60N05 Series

As Figure 4.2.1 indicates, the crystal oscillation circuit can

be configured simply by connecting the crystal oscillator

(X'tal) between the OSC1 and OSC2 pins and the trimmer

capacitor (CG) between the OSC1 and VDD pins.

S1C60N05 TECHNICAL MANUAL EPSON 17

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)

For the S1C60N05 Series, CR oscillation circuit (typ. 65

kHz) may be selected by a mask option. Figure 4.2.2 is the

block diagram of the CR oscillation circuit.

CR oscillation circuit

Fig. 4.2.2

CR oscillation circuit

OSC2

OSC1

To CPU and

peripheral circuits

The S1C60N05 Series

RCR

As Figure 4.2.2 indicates, the CR oscillation circuit can be

configured simply by connecting the register (RCR) between

pins OSC1 and OSC2 since capacity (C) is built-in.

See Chapter 6, "ELECTRICAL CHARACTERISTICS" for RCR

value.

18 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Input Ports (K00–K03)

The S1C60N05 Series has a general-purpose input (4 bits).

Each of the input port pins (K00–K03) has an internal pull-

down resistance. The pull-down resistance can be selected

for each bit with the mask option.

Figure 4.3.1 shows the configuration of input port.

K0x

Mask option

Address

Interrupt

request

Data bus

Selecting "pull-down resistance enabled" with the mask

option allows input from a push button, key matrix, and so

forth. When "pull-down resistance disabled" is selected, the

port can be used for slide switch input and interfacing with

other LSIs.

4.3

Configuration of

input ports

Fig. 4.3.1

Configuration of input port

S1C60N05 TECHNICAL MANUAL EPSON 19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Input comparison

registers and inter-

rupt function

The interrupt mask registers (EIK00–EIK03) enable the

interrupt mask to be selected individually for K00–K03. An

interrupt occurs when the input value which are not

masked change and the interrupt factor flag (IK0) is set to

"1".

Fig. 4.3.2

Input interrupt circuit

configuration (K00–K03)

All four input port bits (K00–K03) provide the interrupt

function. The conditions for issuing an interrupt can be set

by the software for the four bits. Also, whether to mask the

interrupt function can be selected individually for all four

bits by the software. Figure 4.3.2 shows the configuration of

K00–K03.

Data bus

Address

Interrupt mask

K0x

Address

Mask option

(K00–K03)

Noise

rejector

One for each pin series

Interrupt

request

Address

Interrupt factor

flag (IK)

20 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

The contents that can be selected with the input port mask

option are as follows:

(1) An internal pull-down resistance can be selected for each

of the four bits of the input ports (K00–K03). Having

selected "pull-down resistance disabled", take care that

the input does not float. Select "pull-down resistance

enabled" for input ports that are not being used.

(2) The input interrupt circuit contains a noise rejection

circuit to prevent interrupts form occurring through

noise. The mask option enables selection of the noise

rejection circuit for each separate pin series. When "use"

is selected, a maximum delay of 0.5 ms (fosc = 32 kHz)

occurs from the time an interrupt condition is established

until the interrupt factor flag (IK) is set to "1".

Table 4.3.1 list the input port control bits and their ad-

dresses.

Mask option

Control of input ports

Table 4.3.1 Input port control bits

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E0H

K00

K03

K02

K01

K00

–

Input port data K03

Input port data K02

Input port data K01

Input port data K00

High

Low

K01K02K03

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

S1C60N05 TECHNICAL MANUAL EPSON 21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Input port data (0E0H)

The input data of the input port pins can be read with these

registers.

When "1" is read: High level

When "0" is read: Low level

Writing: Invalid

The value read is "1" when the pin voltage of the four bits of

the input ports (K00–K03) goes high (VDD), and "0" when the

voltage goes low (VSS). These bits are reading, so writing

cannot be done.

Interrupt mask registers (0E8H)

Masking the interrupt of the input port pins can be done

with these registers.

When "1" is written: Enable

When "0" is written: Mask

Reading: Valid

With these registers, masking of the input port bits can be

done for each of the four bits. After an initial reset, these

registers are all set to "0".

Interrupt factor flags (0EDH D0)

These flags indicate the occurrence of an input interrupt.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flag IK0 is associated with K00–K03,

respectively. From the status of these flags, the software

can decide whether an input interrupt has occurred.

These flags are reset when the software has read them.

Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to "1", an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated.

After an initial reset, these flags are set to "0".

K00–K03

IK0

EIK00–EIK03

22 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Output Ports (R00–R03)

The S1C60N05 Series has 4 bits for general output ports

(R00–R03).

Output specifications of the output ports can be selected

individually with the mask option. Three kinds of output

specifications are available: complementary output and Pch

open drain output. Also, the mask option enables the

output ports R00 and R01 to be used as special output

ports. Figure 4.4.1 shows the configuration of the output

ports.

Configuration of

output ports

4.4

Data bus

Address

R0x

Complementary

Pch open drain

Mask option

Fig. 4.4.1

Configuration of output ports

S1C60N05 TECHNICAL MANUAL EPSON 23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

The mask option enables the following output port selection.

(1)Output specifications of output ports

The output specifications for the output ports (R00–R03)

may be either complementary output or Pch open drain

output for each of the four bits. However, even when Pch

open drain output is selected, a voltage exceeding the

source voltage must not be applied to the output port.

(2)Special output

In addition to the regular DC output, special output can

be selected for output ports R00 and R01, as shown in

Table 4.4.1. Figure 4.4.2 shows the structure of output

ports R00–R03.

Mask option

Table 4.4.1

Special output

FOUT or BUZZER

BUZZER

R00

R01

Pin name When special output is selected

Fig. 4.4.2

Structure of output port

R00–R03

Address

(0F3H)

FOUT

Data bus

Mask option

R02

R01

BUZZER

(R03) R03

R00

BUZZER

(R02)

(R01)

(R00)

24 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

FOUT (R00) When output port R00 is set for FOUT output, this port will

generate fosc (CPU operating clock frequency) or clock

frequency divided into fosc. Clock frequency may be se-

lected individually for F1–F4, from among 5 types by mask

option; one among F1–F4 is selected by software and used.

The types of frequency which may be selected are shown in

Table 4.4.2.

Output ports R01 and R00 may be set to BUZZER output

and BUZZER output (BUZZER reverse output), respectively,

allowing for direct driving of the piezo-electric buzzer.

BUZZER output (R00) may only be set if R01 is set to

BUZZER output. In such case, whether ON/OFF of the

BUZZER output is done through R00 register or is control-

led through R01 simultaneously with BUZZER output is

also selected by mask option.

The frequency of buzzer output may be selected by software

to be either 2 kHz or 4 kHz.

Table 4.4.2

FOUT clock frequency

A hazard may occur when the FOUT signal is turned on or off.Note

(D1, D0) = (XFOUT1, XFOUT0)

Setting

value

Clock frequency (Hz)

256

(fosc/128) 512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

512

(fosc/64) 1,024

(fosc/32) 2,048

(fosc/16)

8,192

(fosc/4)

1,024

(fosc/32) 2,048

(fosc/16) 4,096

(fosc/8)

4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

4,096

(fosc/8)

32,768

(fosc/1)

2,048

(fosc/16) 4,096

(fosc/8) 8,192

(fosc/4) 16,384

(fosc/2)

(D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1)

F1 F2 F3 F4

fosc = 32,768

BUZZER, BUZZER

(R01, R00)

A hazard may occur when the BUZZER signal is turned on or off.Note

S1C60N05 TECHNICAL MANUAL EPSON 25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Output port data (0F3H)

Sets the output data for the output ports.

When "1" is written: High output

When "0" is written: Low output

Reading: Valid

The output port pins output the data written to the corre-

sponding registers (R00–R03) without changing it. When "1"

is written to the register, the output port pin goes high

(VDD), and when "0" is written, the output port pin goes low

(VSS). After an initial reset, all registers are set to "0".

R00–R03

Table 4.4.3 Control bits of output ports

Control of output

ports

Table 4.4.3 lists the output port control bits and their ad-

dresses.

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F3H

R00

FOUT

R03

R02

R01

BUZZER

R00

FOUT

Output port data R03

Output port data R02

Output port data R01

Buzzer On/Off control register

Output port data R00

Frequency output control register

High

Low

Off

Low

Off

R01

BUZZER

R02R03

R/W

0FDH

XFOUT0

R/W

XBZR

XFOUT1

XFOUT0

Buzzer frequency control

FOUT frequency control

2 kHz 4 kHz

XFOUT10

XBZR

R/W

26 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Special output port data (0F3H D0)

Controls the FOUT (clock) output.

When "1" is written: Clock output

When "0" is written: Low level (DC) output

Reading: Valid

FOUT output can be controlled by writing data to R00. After

an initial reset, this register is set to "0".

Figure 4.4.3 shows the output waveform for FOUT output.

R00 (when FOUT

is selected)

Fig. 4.4.3

FOUT output waveform

FOUT frequency control (0FDH D0, 0FDH D1)

Selects the output frequency when R00 port is set for FOUT

output.

XFOUT0, XFOUT1

Table 4.4.4

FOUT frequency selection

XFOUT1

XFOUT0

Frequency selection

After an initial reset, these registers are set to "0".

R00 register

FOUT output

waveform

S1C60N05 TECHNICAL MANUAL EPSON 27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Special output port data (0F3H D0, 0F3H D1)

Controls the buzzer output.

When "1" is written: Buzzer output

When "0" is written: Low level (DC) output

Reading: Valid

BUZZER and BUZZER output can be controlled by writing

data to R00 and R01.

When BUZZER output by R01 register control is selected by

mask option, BUZZER output and BUZZER output can be

controlled simultaneously by writing data to R01 register.

After an initial reset, these registers are set to "0".

Figure 4.4.4 shows the output waveform for buzzer output.

R00, R01 (when BUZZER

and BUZZER

is selected)

Fig. 4.4.4

Buzzer output waveform

Buzzer frequency control (0FDH D3)

Selects the frequency of the buzzer signal.

When "1" is written: 2 kHz

When "0" is written: 4 kHz

Reading: Valid

When R00 and R01 port is set to buzzer output, the fre-

quency of the buzzer signal can be selected by this register.

When "1" is written to this register, the frequency is set in 2

kHz, and in 4 kHz when "0" is written.

After an initial reset, this register is set to "0".

XBZR

R01 (R00) register

BUZZER output

waveform

BUZZER output

waveform

28 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

I/O Ports (P00–P03)

The S1C60N05 Series has a 4-bit general-purpose I/O port.

Figure 4.5.1 shows the configuration of the I/O port. The

four bits of the I/O port P00–P03 can be set to either input

mode or output mode. The mode can be set by writing data

to the I/O control register (IOC).

4.5

Configuration of I/O

ports

Fig. 4.5.1

Configuration of I/O port

Input or output mode can be set for the four bits of I/O port

P00–P03 by writing data into I/O control register IOC.

To set the input mode, "0" is written to the I/O control

ance becomes high and it works as an input port. However,

the input line is pulled down when input data is read.

The output mode is set when "1" is written to the I/O control

as an output port, it outputs a high signal (VDD) when the

port output data is "1", and a low signal (VSS) when the port

output data is "0".

After an initial reset, the I/O control register is set to "0",

and the I/O port enters the input mode.

I/O control register

and I/O mode

Address

Input

control

I/O control

(IOC)

Data bus

P0x

Address

S1C60N05 TECHNICAL MANUAL EPSON 29

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

The output specification during output mode (IOC = "1") of

the I/O port can be set with the mask option for either

complementary output or Pch open drain output. This

setting can be performed for each bit of the I/O port. How-

ever, when Pch open drain output has been selected, voltage

in excess of the supply voltage must not be applied to the

port.

Table 4.5.1 lists the I/O port control bits and their ad-

dresses.

Mask option

Control of I/O ports

Table 4.5.1 I/O port control bits

I/O port data (0F4H)

I/O port data can be read and output data can be written

through the port.

• When writing data

When "1" is written: High level

When "0" is written: Low level

When an I/O port is set to the output mode, the written

data is output from the I/O port pin unchanged. When

"1" is written as the port data, the port pin goes high

(VDD), and when "0" is written, the level goes low (VSS).

Port data can also be written in the input mode.

P00–P03

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0F4H

P00

R/W

P03

P02

P01

P00

–

I/O port data P03

I/O port data P02

I/O port data P01

I/O port data P00

High

Low

P01P02P03

0FCH

IOC

R/W

IOC 0

I/O port I/O control register

Out In

30 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

• When reading data

When "1" is read: High level

When "0" is read: Low level

The pin voltage level of the I/O port is read. When the I/

O port is in the input mode the voltage level being input

to the port pin can be read; in the output mode the

output voltage level can be read. When the pin voltage is

high (VDD) the port data read is "1", and when the pin

voltage is low (VSS) the data is "0". Also, the built-in pull-

down resistance functions during reading, so the I/O port

pin is pulled down.

- When the I/O port is set to the output mode and a low-imped-

ance load is connected to the port pin, the data written to the

- When the I/O port is set to the input mode and a low-level

voltage (Vss) is input by the built-in pull-down resistance, an

erroneous input results if the time constant of the capacitive

load of the input line and the built-in pull-down resistance load is

greater than the read-out time. When the input data is being

read, the time that the input line is pulled down is equivalent to

0.5 cycles of the CPU system clock. Hence, the electric poten-

tial of the pins must settle within 0.5 cycles. If this condition

cannot be met, some measure must be devised, such as

arranging a pull-down resistance externally, or performing

multiple read-outs.

I/O control register (0FCH D0)

The input or output I/O port mode can be set with this

When "1" is written: Output mode

When "0" is written: Input mode

Reading: Valid

The input or output mode of the I/O port is set in units of

four bits. For instance, IOC sets the mode for P00–P03.

Writing "1" to the I/O control register makes the I/O port

enter the output mode, and writing "0", the input mode.

After an initial reset, the IOC register is set to "0", so the I/O

port is in the input mode.

Note

IOC

S1C60N05 TECHNICAL MANUAL EPSON 31

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD Driver (COM0–COM3, SEG0–SEG19)

The S1C60N05 Series has four common pins and 20 (SEG0–

SEG19) segment pins, so that an LCD with a maximum of

80 (20 × 4) segments can be driven. The power for driving

the LCD is generated by the CPU internal circuit, so there is

no need to supply power externally.

The driving method is 1/4 duty (or 1/3, 1/2 duty by mask

option) dynamic drive, adopting the four types of potential

(1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias

dynamic drive that uses three types of potential, VDD, VL1 =

VL2 and VL3, can be selected by setting the mask option

(drive duty can also be selected from 1/4, 1/3 or 1/2). 1/2

bias drive is effective when the LCD system regulated voltage

circuit is not used. The VL1 terminal and the VL2 terminal

should be connected outside of the IC.

The frame frequency is 32 Hz for 1/4 duty and 1/2 duty,

and 42.7 Hz for 1/3 duty (in the case of fosc = 32.768 kHz).

Figure 4.6.1 shows the drive waveform for 1/4 duty (1/3 bias),

Figure 4.6.2 shows the drive waveform for 1/3 duty (1/3 bias),

Figure 4.6.3 shows the drive waveform for 1/2 duty (1/3 bias),

Figure 4.6.4 shows the drive waveform for 1/4 duty (1/2 bias),

Figure 4.6.5 shows the drive waveform for 1/3 duty (1/2 bias)

and Figure 4.6.6 shows the drive waveform for 1/2 duty (1/2

bias).

fosc indicates the oscillation frequency of the oscillation circuit.

Configuration of LCD

driver

4.6

Note

32 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.6.1

Drive waveform for

1/4 duty (1/3 bias)

LCD lighting status

COM0

COM1

COM2

COM3

Not lit

Lit

-VDD

-VL1

-VL2

-VL3

COM0

COM1

COM2

COM3

SEG

0–19

Frame frequency

SEG0–19

-VDD

-VL1

-VL2

-VL3

S1C60N05 TECHNICAL MANUAL EPSON 33

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.6.2

Drive waveform for

1/3 duty (1/3 bias)

Frame frequency

SEG

0–19

COM3

COM2

COM1

COM0 -VDD

-VL1

-VL2

-VL3

Not lit

Lit

SEG0–19

LCD lighting status

COM0

COM1

COM2

-VDD

-VL1

-VL2

-VL3

34 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Fig. 4.6.3

Drive waveform for

1/2 duty (1/3 bias)

COM0

COM1

COM2

COM3

SEG

0–19

Frame frequency

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

Not lit

Lit

SEG0–19

LCD lighting status

COM0

COM1

S1C60N05 TECHNICAL MANUAL EPSON 35

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

Not lit

Lit

SEG

0–19

SEG0–19

Frame frequency

COM0

COM1

COM2

COM3

COM0

COM1

COM2

COM3

-V

L1, L2

-V

L1, L2

-V

Fig. 4.6.4

Drive waveform for

1/4 duty (1/2 bias)

36 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

Not lit

Lit

SEG

0–19

Frame frequency

SEG0–19

COM0

COM1

COM2

COM0

COM1

COM2

COM3

-VDD

-VL1, L2

-VL3

-VDD

-VL1, L2

-VL3

COM0

COM1

COM0

COM1

COM2

COM3

-V

L1, L2

-V

L1, L2

-V

LCD lighting status

Not lit

Lit

SEG

0–19

Frame frequency

SEG0–19

Fig. 4.6.5

Drive waveform for

1/3 duty (1/2 bias)

Fig. 4.6.6

Drive waveform for

1/2 duty (1/2 bias)

S1C60N05 TECHNICAL MANUAL EPSON 37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Cadence adjust-

ment of oscillation

frequency

In the S1C60N05 Series, the LCD drive duty can be set to

1/1 duty by software. This function enables easy adjust-

ment (cadence adjustment) of the oscillation frequency of

the OSC circuit.

The procedure to set to 1/1 duty drive is as follows:

➀Write "1" to the CSDC register at address "0FBH D3".

➁Write the same value to all registers corresponding to

COMs 0 through 3 of the display memory.

The frame frequency is 32 Hz (fOSC1/1,024, when fOSC1 =

32.768 kHz).

- Even when l/3 or 1/2 duty is selected by the mask option, the

display data corresponding to all COM are valid during 1/1 duty

driving. Hence, for 1/1 duty drive, set the same value for all

display memory corresponding to COMs 0 through 3.

For cadence adjustment, set the display data corresponding to

COMs 0 through 3

, so that all the LCD segments go on.

Figure 4.6.7 shows the 1/1 duty drive waveform (1/3 bias).

Figure 4.6.8 shows the 1/1 duty drive waveform (1/2 bias).

Fig. 4.6.7

1/1 duty drive waveform

(1/3 bias)

Fig. 4.6.8

1/1 duty drive waveform

(1/2 bias)

Note

SEG

0–19

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–19

-VDD

-VL1, VL2

-VL3

Not lit Lit

-VDD

-VL1, VL2

-VL3

-VDD

-VL1, VL2

-VL3

SEG

0–19

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–19

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

Not lit Lit

38 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(1)Segment allocation

As shown in Figure 4.l.1, the S1C60N05 Series display

data is decided by the display data written to the display

memory (write-only) at address "090H–0AFH".

The address and bits of the display memory can be made

to correspond to the segment pins (SEG0–SEG19) in any

combination through mask option. This simplifies design

by increasing the degree of freedom with which the liquid

crystal panel can be designed.

Figure 4.6.9 shows an example of the relationship be-

tween the LCD segments (on the panel) and the display

memory in the case of 1/3 duty.

Mask option

(segment allocation)

Fig. 4.6.9

Segment allocation

aa'

ff'

ee'

dd' p'

SEG10 SEG11 SEG12

Common 0

Common 1

Common 2

09AH

09BH

09CH

09DH

Address

Data

Display data memory allocation

SEG10

SEG11

SEG12

9A, D0

(a)

9A, D1

(b)

9D, D1

(f')

9B, D1

(f)

9B, D2

(g)

9A, D2

(c)

9B, D0

(e)

9A, D3

(d)

9B, D3

(p)

Pin address allocation

Common 0 Common 1 Common 2

S1C60N05 TECHNICAL MANUAL EPSON 39

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(2)Drive duty

According to the mask option, either 1/4, 1/3 or 1/2

duty can be selected as the LCD drive duty.

Table 4.6.1 shows the differences in the number of seg-

ments according to the selected duty.

Pins used Maximum number Frame frequency

in common of segments (when fosc = 32 kHz)

1/4 COM0–3 80 (20 × 4) 32 Hz

1/3 COM0–2 60 (20 × 3) 42.7 Hz

1/2 COM0–1 40 (20 × 2) 32 Hz

(3)Output specification

➀The segment pins (SEG0–SEG19) are selected by mask

option in pairs for either segment signal output or DC

output (VDD and VSS binary output). When DC output

is selected, the data corresponding to COM0 of each

segment pin is output.

➁When DC output is selected, either complementary

output or Pch open drain output can be selected for

each pin by mask option.

The pin pairs are the combination of SEG (2

n) and SEG (2

n +

1) (where n is an integer from 0 to 9).

(4)Drive bias

For the drive bias of the S1C60N05 or the S1C60L05,

either 1/3 bias or 1/2 bias can be selected by the mask

option.

Table 4.6.1

Differences according to

selected duty

Duty

Note

40 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Table 4.6.2 shows the control bits of the LCD driver and

their addresses. Figure 4.6.10 shows the display memory

map.

Control of LCD

driver

CSDC

Display memory

Fig. 4.6.10

Display

memory map

Address 0123456789ABCDEF

090

0A0 Display memory (Write only)

32 words x 4 bits

Table 4.6.2 Control bits of LCD driver

LCD drive switch (0FBH D3)

The LCD drive format can be selected with this switch.

When "1" is written: Static drive

When "0" is written: Dynamic drive

Reading: Valid

After an initial reset, dynamic drive (CSDC = "0") is selected.

(090H–0AFH)

The LCD segments are turned on or off according to this

data.

When "1" is written: On

When "0" is written: Off

Reading: Invalid

By writing data into the display memory allocated to the

LCD segment (on the panel), the segment can be turned on

or off. After an initial reset, the contents of the display

memory are undefined.

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0FBH

0CSDC

LCD drive switch

Static Dynamic

0CSDC

R/W

S1C60N05 TECHNICAL MANUAL EPSON 41

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Clock Timer

The S1C60N05 Series has a built-in clock timer driven by

the source oscillator. The clock timer is configured as a

seven-bit binary counter that serves as a frequency divider

taking a 256 Hz source clock from a prescaler. The four

high-order bits (16 Hz–2 Hz) can be read by the software.

Figure 4.7.1 is the block diagram of the clock timer.

4.7

Configuration of

clock timer

Fig. 4.7.1

Block diagram of

clock timer

Normally, this clock timer is used for all kinds of timing

purpose, such as clocks.

128 Hz–32 Hz

Data bus

32 Hz, 8 Hz, 2 Hz

256 Hz

Clock timer reset signal

OSC

(oscillation

circuit)

Interrupt

request

Interrupt

control

16 Hz–2 Hz

42 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Interrupt function The clock timer can interrupt on the falling edge of the 32

Hz, 8 Hz, and 2 Hz signals. The software can mask any of

these interrupt signals.

Figure 4.7.2 is the timing chart of the clock timer.

Fig. 4.7.2 Timing chart of the clock timer

As shown in Figure 4.7.2, an interrupt is generated on the

falling edge of the 32 Hz, 8 Hz, and 2 Hz frequencies. When

this happens, the corresponding interrupt event flag (IT32,

IT8, IT2) is set to "1". Masking the separate interrupts can

be done with the interrupt mask register (EIT32, EIT8,

EIT2). However, regardless of the interrupt mask register

setting, the interrupt event flags will be set to "1" on the

falling edge of their corresponding signal (e.g. the falling

edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to

"1").

Write to the interrupt mask register (EIT32, EIT8, EIT2) only in the

DI status (interrupt flag = "0"). Otherwise, it causes malfunction.

Note

Clock timer timing chartFrequency

bits

Address

0E3H

D0 16 Hz

8 Hz

4 Hz

2 Hz

Occurrence of

32 Hz interrupt request

Occurrence of

8 Hz interrupt request

Occurrence of

2 Hz interrupt request

S1C60N05 TECHNICAL MANUAL EPSON 43

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Table 4.7.1 shows the clock timer control bits and their

addresses.

Control of clock

timer

Table 4.7.1 Control bits of clock timer

Timer data (0E3H)

The l6 Hz to 2 Hz timer data of the clock timer can be read

from this register. These four bits are read-only, and write

operations are invalid.

After an initial reset, the timer data is initialized to "0H".

Interrupt mask registers (0EBH D0–D2)

These registers are used to mask the clock timer interrupt.

When "1" is written: Enabled

When "0" is written: Masked

Reading: Valid

The interrupt mask register bits (EIT32, EIT8, EIT2) mask

the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz).

After an initial reset, these registers are all set to "0".

TM0–TM3

EIT32, EIT8, EIT2

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E3H

TM0

TM3

TM2

TM1

TM0

–

Clock timer data 2 Hz

Clock timer data 4 Hz

Clock timer data 8 Hz

Clock timer data 16 Hz

High

Low

TM1TM2TM3

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0F9H

TMRST

TMRST Reset

Clock timer reset

Reset –

44 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

Interrupt factor flags (0EFH D0–D2)

These flags indicate the status of the clock timer interrupt.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

The interrupt factor flags (IT32, IT8, IT2) correspond to the

clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can

determine from these flags whether there is a clock timer

interrupt. However, even if the interrupt is masked, the

flags are set to "1" on the falling edge of the signal. These

flags can be reset when the register is read by the software.

Reading of interrupt factor flags is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flags to be read is set to "1", an interrupt

request will be generated by the interrupt factor flags set

timing, or an interrupt request will not be generated. Be

very careful when interrupt factor flags are in the same

address.

After an initial reset, these flags are set to "0".

Clock timer reset (0F9H D0)

This bit resets the clock timer.

When "1" is written: Clock timer reset

When "0" is written: No operation

Reading: Always "0"

The clock timer is reset by writing "1" to TMRST. The clock

timer starts immediately after this. No operation results

when "0" is written to TMRST.

This bit is write-only, and so is always "0" when read.

IT32, IT8, IT2

TMRST

S1C60N05 TECHNICAL MANUAL EPSON 45

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Configuration of A/D

converter

4.8

Fig. 4.8.1

Configuration of

A/D converter

A/D Converter

The S1C60N05 Series has a CR oscillation type A/D

converter with two input channels. This A/D converter is

equipped with two CR oscillation circuit systems and a

counter that measures their oscillation frequency. Counted

values represent connected resistance values converted into

digital values. Connect a reference resistance that does not

change oscillation frequency according to temperature

between the RS and CS terminals and a sensor that does

change resistance values according to temperature between

the TH and CS terminals. Then, oscillate them alternately.

The difference in the counted value can be evaluated as the

difference between the respective oscillation frequencies.

Therefore, various sensor circuit such as a temperature-

measuring circuit using a thermistor can be easily created,

for example.

The configuration of the A/D converter is shown in Figure

4.8.1.

Tr2

Multiplying

circuit

Interrupt

request

OSC1

clock 32 kHz or 65 kHz TC15

–TC12 TC11

–TC8 TC7

–TC4 TC3

–TC0

Up/down counter

ADCLK

C15

–C12 C11

–C8 C7

–C4 C3

–C0

Start/Stop

ADRUN

Controller

Up-counter

Start/Stop

control

Up/Down

control Data bus

Start/Stop

control

Interrupt

controller

IAD EIAD

Tr1Tr3

TH1RS

CS R

TH1

TH2

ADOUT

Tr4 V

TH2

46 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Connect a reference resistance that only slightly changes

resistance values according to environmental conditions

between the oscillating I/O terminals RS and CS. Connect a

sensor that changes resistance values between the TH and

CS terminals. Furthermore, by connecting a condenser

between the CS and VSS, a CR oscillation circuit is com-

pleted.

This A/D converter performs CR oscillation using one of the

two resistances connected to external devices. Their oscilla-

tion frequency serves as a clock from which the oscillation

frequency is counted. Difference in counted oscillation

frequency can be evaluated in terms of the difference be-

tween the respective resistance values. Measurement results

can be obtained from the changes in resistance values after

correcting the difference according to the program.

(1)External resistances and condenser

Connect a sensor (a variable resistance element such as a

thermistor) between the TH1/TH2 and CS terminals.

Next, set the reference value of the item to be measured

(e.g. reference temperature in the case of temperature

measurement) and connect the reference resistance

equivalent to the sensor resistance value at the above

reference value between the RS and CS terminals. An

element that does not change due to temperature or other

environmental conditions must be used as the reference

resistance.

Connect an oscillating condenser that is used for CR

oscillation of both the reference resistance and the sensor

between the CS and VSS terminals.

Operation of A/D

converter

S1C60N05 TECHNICAL MANUAL EPSON 47

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

(2)Oscillation circuit

The CR oscillation circuit is designed so that either the

reference resistance side or the sensor side can be oper-

ated independently by the oscillation control circuit.

A/D conversion begins when "1" is written in the ADRUN

circuit also turns on. At first, the circuit of the reference

resistance side (RS) is operated by the oscillation control

circuit. Then, the circuit of the sensor side (TH1 or TH2)

turns on when counting by the oscillation clock of the

reference resistance is terminated.

TH1 or TH2 is controlled by the CHTH register (0F1H D3).

Each circuit performs the same oscillating operation as

follows (in this example, CHTH = "0", TH1 is selected):

The Tr1 (Tr2) turns on first, and the condenser connected

between the CS and VSS terminals is charged through the

reference resistance (sensor). If the voltage level of the CS

terminal decreases, the Tr1 (Tr2) turns off and the Tr3

turns on. As a result, the condenser becomes discharged,

and oscillation is performed according to CR time con-

stant. The time constant changes as the sensor resist-

ance value fluctuates, producing a difference from the

oscillation frequency of the reference resistance.

Oscillation waveforms are shaped by the Schmitt trigger

and transmitted to counter. The clock transmitted to the

counter is also output from the ADOUT terminal. As a

result, oscillation frequency can be identified by the

oscilloscope. Since this monitor has no effect on oscilla-

tion frequency, it can be used to adjust CR oscillation

frequency.

Oscillation waveforms and waveforms output from the

ADOUT terminal are shown in Figure 4.8.2.

Fig. 4.8.2

Oscillation waveforms

CS terminal

ADOUT VDD

VSS

VDD

VSS

48 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

(3)Counter

The A/D converter incorporates two types of 16-bit

counters. One is the up-counter C0–C15 that counts the

aforementioned oscillation clock, and the other is up/

down counter TC0–TC15 that counts the internal clock

for reference counting. Each counter permits reading and

writing on a 4-bit basis.

The input unit of the up/down counter TC0–TC15 incor-

porates a multiplying circuit so that either the OSC1

clock (Typ. 32.768 kHz) or its multiplication clock (Typ.

65.536 kHz) can be selected as an input clock.

When A/D conversion is initiated by the ADRUN register,

oscillation by the reference resistance begins first, and

the up-counter C0–C15 starts counting up according to

the oscillation clock. At the same time, the up/down

counter TC0–TC15 starts counting up.

Timing in starting oscillation and starting counting up

are shown in Figure 4.8.3.

The up-counter becomes ENABLE at the falling edge of

the first clock after CR oscillation is initiated and starts

counting up from the falling edge of the next clock.

The up/down counter becomes ENABLE at the falling

edge of the internal clock which is input immediately

after the first CR oscillation clock has fallen. Then, it

starts counting up from the falling edge of the next inter-

nal clock.

Fig. 4.8.3

Counting up start

timing

ADRUN register

CS terminal

ADOUT

Up-counter enable

Up-counter (C0)

Clock (Up/down counter)

Up/down counter enable

Up/down counter (TC0)

Start

If the up-counter C0–C15 becomes "0000H" due to over-

flow, the sensor side of the oscillation circuit turns on,

and the up-counter starts counting up according to the

oscillation clock on the sensor side.

S1C60N05 TECHNICAL MANUAL EPSON 49

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

The up/down counter TC0–TC15 shifts to the counting-

down mode at this point and starts counting down from

the value measured as a result of oscillation by the

reference resistance.

Timing in starting counting when oscillation is switched,

is same as Figure 4.8.3.

When the up/down counter TC0–TC15 has counted down

to "0000H", the counting operation of both counters and

CR oscillation stops, and an interrupt occurs. At the

same time, the ADRUN register is set to "0", and the A/D

converter circuit stops operation completely.

The sensor is oscillated for the same period of time as the

reference resistance is oscillated after the up/down

counter TC0–TC15 is set to "0000H" prior to A/D conver-

sion. Therefore, the difference in oscillation frequency can

be measured from the values counted by the up-counter

C0–C15.

Since the reference resistance is oscillated until the up-

counter C0–C15 overflows, an appropriate initial value

needs to be set before A/D conversion is started. If a

smaller initial value is set, a longer counting period is

possible, thereby ensuring more accurate detection.

Likewise, if the input clock of the up/down counter TC0–

TC15 is set at 65 kHz, the degree of precision is reduced.

However, since CR oscillation frequency is normally set

lower than the clock frequency of the up/down counter

TC0–TC15 to ensure accurate measurement, the up/

down counter TC0–TC15 may overflow while counting the

oscillation frequency of the reference resistance.

If an overflow occurs, CR oscillation and A/D conversion

is terminated immediately. Also in such cases, the up/

down counter indicates "0000H", and interrupt occurs.

However, it is impossible to judge whether the interrupt

has occurred due to an overflow or normal termination.

Note that correct measurement is impossible if an over-

flow occurs. The initial value to be set depends on the

measurable range by the sensor or where to set the

reference resistance value within that range.

The initial value must be set taking the above into con-

sideration.

50 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Convert the initial value into a complement (value sub-

tracted from 0000H) before setting it on the up-counter

C0–C15. Since the data output from the up-counter C0–

C15 after A/D conversion matches data detected by the

sensor, process the difference between that value and the

initial value before it is converted into a complement

according to the program and calculate the target value.

The above operations are shown in Figure 4.8.4.

Note - Before setting "1" to ADRUN, an input channel must be

selected from TH1 and TH2 (TH1 by default).

- Set the initial value of the up-counter C0–C15 taking into

account the measurable range and the overflow of the up/down

counter TC0–TC15.

- If the up/down counter TC0–TC15 is measured after A/D

conversion, it may not indicate "0000H". This is not due to

incorrect timing in terminating A/D conversion but because the

counting down clock is input after the control signal is output to

the up-counter to terminate counting.

Fig. 4.8.4

Sequence of A/D conversion

Up-counter

(C0–C15)

(0000H-n)

(1) Set the initial value

(0000H-n)

Count up

FFFFH

Count up

Up/down counter

(TC0–TC15)

0000H0000H

Count up

Count down

0001H

0000H

(2) Start A/D conversion

(Set "1" on the ADRUN)

(3) Read the up-counter and process the m–n value acoording to the program

Setting by software Set the complement of the initial

value n on the up-counter

Set "0000H" on the up /down

counter

Oscillation by

reference resistance

Switch CR oscillation when

the up-counter overflows and

shift the up/down counter to

the counting-down mode

When the value of the up/down

counter reaches 0000H, oscillation

and conting stops, and

an interruption occurs.

Oscillation by

sensor

S1C60N05 TECHNICAL MANUAL EPSON 51

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

The A/D converter has a function which allows interrupt to

occur after A/D conversion.

When the up/down counter TC0–TC15 is counted down to

"0000H", both counters stop counting. The interrupt factor

flag IAD is set to "1" at the falling edge of the next clock. If

the up/down counter TC0–TC15 overflow during counting-

up operation, the interrupt factor flag is set to "1" at the

rising edge of the clock immediately after the counter

reaches "0000H".

This interrupt factor allows masking by the interrupt mask

in the CPU. If the EIAD is set at "0", the interrupt factor flag

is set to "1". However, no interrupt will occur in the CPU.

The interrupt factor flag is reset to "0" by a reading opera-

tion.

Timing of interrupt by the A/D converter is shown in Figure

4.8.5.

Interrupt function

Fig. 4.8.5

Timing of A/D

converter interrupt

Temperature measurement is possible with the A/D con-

verter in which a thermistor is used as a sensor. Elements

to be connected and counter setting in the case of tempera-

ture measurement are as follows:

Example: Temperature measurement at -20°C to 70°C

Reference resistance .......49.8 kΩ

Thermistor......................50 kΩ

Oscillating condenser...... 2,200 pF

Usage example of

the A/D converter

ADRUN register

ADOUT

Up-counter data

Up/down counter clock

Up/down counter data

Interrupt

n n+1 n+2

0 123

FFFE FFFF

x-1 x-2x-1x-2x-3 x-3

3210

m-1

Oscillation with reference resistor Oscillation with sensor

52 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

When the above elements are connected, the oscillation

frequency of the reference resistance becomes about 10 kHz,

and the oscillation frequency of the thermistor varies within

the range of about 1 kHz to 50 kHz at -20°C to 70°C.

Reference resistance is adjusted to the thermistor resistance

value at 25°C.

In addition, Figure 4.8.6 indicates the resistance and oscil-

lation frequency ratio TYP at the time of A/D conversion.

Fig. 4.8.6

Resistance and oscillation

frequency ratio

10 k

0.1

( )

50 k 100 k 500 k

1.0

5.0

Resistance value

Oscillation frequency ratio

Ω

Resistance and oscillation frequency ratio

of A/D conversion circuit

For 50 k , set the oscillation frequency to 1.

S1C60N05 TECHNICAL MANUAL EPSON 53

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Table 4.8.2 shows the A/D converter control bits and their

addresses.

Control of A/D

converter

Table 4.8.2 Control bits of clock timer

*1 Initial value following initial reset *4 Reset (0) immediately after being read

*2 Not set in the circuit *5 Always "0" when being read

*3 Undefined *6 Refer to main manual

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E4H

TC0

R/W

TC3

TC2

TC1

TC0

Up/down counter data TC3

Up/down counter data TC2

Up/down counter data TC1

Up/down counter data TC0 (LSB)

TC1TC2TC3 –

–

TC4

R/W

TC7

TC6

TC5

TC4

–

Up/down counter data TC7

Up/down counter data TC6

Up/down counter data TC5

Up/down counter data TC4

TC5TC6TC7

0E5H

0E6H

TC8

R/W

TC11

TC10

TC9

TC8

–

Up/down counter data TC11

Up/down counter data TC10

Up/down counter data TC9

Up/down counter data TC8

TC9TC10TC11

0E7H

TC12

R/W

TC15

TC14

TC13

TC12

–

Up/down counter data TC15 (MSB)

Up/down counter data TC14

Up/down counter data TC13

Up/down counter data TC12

TC13TC14TC15

0F5H

R/W

Up-counter data C3

Up-counter data C2

Up-counter data C1

Up-counter data C0 (LSB)

C1C2C3 –

–

R/W

–

Up-counter data C7

Up-counter data C6

Up-counter data C5

Up-counter data C4

C5C6C7

0F6H

0F7H

R/W

C11

C10

–

Up-counter data C11

Up-counter data C10

Up-counter data C9

Up-counter data C8

C9C10C11

0F8H

C12

R/W

C15

C14

C13

C12

–

Up-counter data C15 (MSB)

Up-counter data C14

Up-counter data C13

Up-counter data C12

C13C14C15

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

0F1H

ADRUN

R/W

CHTH

ADRUN

A/D channel selection

A/D conversion Start/Stop

TH2

Start

TH1

Stop

00CHTH

R/W

0FEH

ADCLK

R/W

ADCLK 0

A/D clock selection 65 kHz/32 kHz

65 kHz 32 kHz

54 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Up/down counter (0E4H–0E7H)

Writing and reading is possible on a 4-bit basis by the up/

down counter that is used to adjust the CR oscillation time

between the reference resistance and the variable resistance

elements.

The up/down counter counts up during oscillation of the

reference resistance and counts down from the value it

reached when counting up to "0000H" during oscillation of

the sensor.

"0000H" needs to be entered in the counter prior to A/D

conversion in order to adjust the counting time of both

counts.

After an initial reset, data in this counter become indefinite.

Up-counter (0F5H–0F8H)

This counter counts up according to the CR oscillation

clock. It permits writing and reading on a 4-bit basis.

The complement of the number of clocks to be counted by

the oscillation of the reference resistance, must be entered

in this counter prior to A/D conversion.

If A/D conversion is initiated, the counter counts up from

the set initial value, first according to the oscillation clock of

the reference resistance. When the counter reaches "0000H"

due to overflow, the oscillation of the reference resistance

stops, and the sensor starts oscillating. The counter contin-

ues counting according to the sensor oscillation clock.

Counting time during the oscillation of the reference resist-

ance is calculated by the up/down counter TC0–TC15. Up-

counter C0–C15 stops counting when the same period of

time elapses. Difference from the reference resistance can be

evaluated from the value indicated by the counter when it

stops. Calculate the target value by processing the above

difference according to the program.

Measurable range and the overflow of the up/down counter

TC0–TC15 must be taken into account when setting an

initial value to be entered prior to A/D conversion.

After an initial reset, data in this counter become indefinite.

TC0–TC15

C0–C15

S1C60N05 TECHNICAL MANUAL EPSON 55

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

Input clock selection (0FEH D0)

Select the input clock of the up/down counter TC0–TC15.

When "1" is written: 65 kHz

When "0" is written: 32 kHz

Reading: Valid

Select the output clock of the multiplying circuit for the

counting operation of the up/down counter TC0–TC15.

When "1" is written in the ADCLK, 65 kHz, a multitude of

the OSC1 clock is selected. When "0" is written, the OSC1

clock is selected at 32 kHz.

If 65 kHz is selected, A/D conversion becomes more accu-

rate. However, the initial value must be set on the up-

counter C0–C15 so that the up/down counter TC0–TC15

will not overflow while CR oscillation is being counted.

After an initial reset, ADCLK is set to "0".

A/D conversion START/STOP (0F1H D0)

Start A/D conversion.

When "1" is written: A/D conversion starts

When "0" is written: A/D conversion stops

Reading: Valid

When "1" is written in the ADRUN, A/D conversion begins.

The register remains at "1" during A/D conversion and is set

to "0" when A/D conversion is terminated.

When "0" is written in the ADRUN during A/D conversion,

A/D conversion is paused.

ADRUN is set to "0" at initial reset, when the up/down

counter overflows or when measurement is finished.

A/D channel selection (0F1H D3)

Select an A/D converter channel.

When "1" is written: TH2 is selected

When "0" is written: TH1 is selected

Reading: Valid

Before running the A/D converter, either TH1 or TH2 must

be selected as an input channel.

After an initial reset, CHTH is set to "0".

ADRUN

CHTH

ADCLK

56 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)

EIAD Interrupt mask register (0ECH D0)

Select whether to mask interrupt with the A/D converter.

When "1" is written: Enable

When "0" is written: Mask

Reading: Valid

The A/D converter interrupt is permitted when "1" is written

in the EIAD. When "0" is written, interrupt is masked.

After an initial reset, this register is set to "0".

IAD Interrupt factor flag (0F0H D0)

This flag indicates interrupt caused by the A/D converter.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

Writing: Invalid

IAD is set to "1" when A/D conversion is terminated (when

the up/down counter counted up or down to "0000H"). From

the status of this flag, the software can decide whether an

A/D converter interrupt has occurred.

This flag is reset when the software has read it.

Reading of interrupt factor flag is available at EI, but be

careful in the following cases.

If the interrupt mask register value corresponding to the

interrupt factor flag to be read is set to "1", an interrupt

request will be generated by the interrupt factor flag set

timing, or an interrupt request will not be generated.

After an initial reset, this flag is set to "0".

S1C60N05 TECHNICAL MANUAL EPSON 57

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function)

4.9 Heavy Load Protection Function

The S1C60N05 Series has a heavy load protection function

for when the battery load becomes heavy and the supply

voltage drops, such as when an external buzzer sounds or

an external lamp lights. This function works in the heavy

load protection mode.

The normal mode changes to the heavy load protection mode

in the following case:

• When the software changes the mode to the heavy load

protection mode (HLMOD = "1")

In the heavy load protection mode, the internally regulated

voltage is switched to the high-stability mode from the low

current consumption mode. Consequently, more current is

consumed in the heavy load protection mode than in the

normal mode. Unless necessary, do not select the heavy

load protection mode with the software.

Operation of heavy

load protection

function

58 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function)

Table 4.9.1 shows the control bits and their addresses for

the heavy load protection function.

Table 4.9.1 Control bits for heavy load protection function

Control of heavy

load protection

function

Heavy load protection mode on/off (0FAH D3)

When "1" is written: Heavy load protection mode on

When "0" is written: Heavy load protection mode off

Reading: Valid

When HLMOD is set to "1", the IC enters the heavy load

protection mode.

In the heavy load protection mode, the consumed current

becomes larger. Unless necessary, do not select the heavy

load protection mode with the software.

HLMOD

Address Comment

D3 D2 D1 D0 Name Init 1 0

0FAH

0HLMOD

Heavy load protection mode register

Heavy Normal

00HLMOD

R/W

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

S1C60N05 TECHNICAL MANUAL EPSON 59

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Interrupt and HALT

The S1C60N05 Series provides the following interrupt set-

tings, each of which is maskable.

External interrupt: Input interrupt (one)

Internal interrupt: Timer interrupt (one)

A/D converter interrupt (one)

To enable interrupts, the interrupt flag must be set to "1"

(EI) and the necessary related interrupt mask registers must

be set to "1" (enable). When an interrupt occurs, the inter-

rupt flag is automatically reset to "0" (DI) and interrupts

after that are inhibited.

When a HALT instruction is input, the CPU operating clock

stops and the CPU enters the halt state. The CPU is reacti-

vated from the halt state when an interrupt request occurs.

Figure 4.10.1 shows the configuration of the interrupt

circuit.

4.10

Fig. 4.10.1

Configuration of

interrupt circuit

K00

EIK00

K01

EIK01

K02

EIK02

K03

EIK03

IAD

EIAD

IT2

EIT2

IT8

EIT8

IT32

EIT32

IK0

(MSB)

(LSB)

Program counter of CPU

(three low-order bits)

Interrupt vector

Interrupt factor flag

Interrupt mask register

Interrupt flag

INT

(Interrupt request)

60 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Table 4.10.1 shows the factors that generate interrupt

requests.

The interrupt factor flags are set to "1" depending on the

corresponding interrupt factors.

The CPU is interrupted when the following two conditions

occur and an interrupt factor flag is set to "1".

• The corresponding mask register is "1" (enabled)

• The interrupt flag is "1" (EI)

The interrupt factor flag is a read-only register, but can be

reset to "0" when the register data is read.

After an initial reset, the interrupt factor flags are reset to

"0".

Interrupt factors

Reading of interrupt factor flags is available at EI, but be careful in

the following cases.

If the interrupt mask register value corresponding to the interrupt

factor flags to be read is set to "1", an interrupt request will be

generated by the interrupt factor flags set timing, or an interrupt

request will not be generated. Be very careful when interrupt factor

flags are in the same address.

Note

Table 4.10.1

Interrupt factors Interrupt factor

Colck timer 2 Hz falling edge

Colck timer 8 Hz falling edge

Colck timer 32 Hz falling edge

A/D converter

A/D conversion completion

Input data (K00–K03)

Rising edge

Interrupt factor flag

IT2

IT8

IT32

IAD

IK0

(0F0H D0)

(0EDH D0)

(0EFH D2)

(0EFH D1)

(0EFH D0)

S1C60N05 TECHNICAL MANUAL EPSON 61

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

The interrupt factor flags can be masked by the correspond-

ing interrupt mask registers. The interrupt mask registers

are read/write registers. They are enabled (interrupt en-

abled) when "1" is written to them, and masked (interrupt

disabled) when "0" is written to them. After an initial reset,

the interrupt mask register is set to "0".

Table 4.10.2 shows the correspondence between interrupt

mask registers and interrupt factor flags.

Specific masks and

factor flags for inter-

rupt

Table 4.10.2

Interrupt mask registers and

interrupt factor flags

Interrupt mask register Interrupt factor flag

(0EBH D2)

(0EBH D1)

(0EBH D0)

(0ECH D0)

(0E8H D3)

(0E8H D2)

(0E8H D1)

(0E8H D0)

IT2

IT8

IT32

IAD

(0EFH D2)

(0EFH D1)

(0EFH D0)

(0F0H D0)

IK0 (0EDH D0)

EIT2

EIT8

EIT32

EIAD

EIK03*

EIK02*

EIK01*

EIK00*

* There is an interrupt mask register for each input port pin.

When an interrupt request is input to the CPU, the CPU

begins interrupt processing. After the program being exe-

cuted is suspended, interrupt processing is executed in the

following order:

➀The address data (value of the program counter) of the

program step to be executed next is saved on the stack

(RAM).

➁The interrupt request causes the value of the interrupt

vector (page 1, 01H–07H) to be loaded into the program

counter.

➂The program at the specified address is executed (execu-

tion of interrupt processing routine).

The processing in steps 1 and 2, above, takes 12 cycles of the

CPU system clock.

Interrupt vectors

Note

62 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

Control of interrupt Table 4.10.3 shows the interrupt control bits and their

addresses.

Table 4.10.3 Interrupt control bits

EIT32, EIT8, EIT2

IT32, IT8, IT2

EIAD

IAD

EIK00–EIK03

IK0

*1 Initial value following initial reset

*2 Not set in the circuit

*3 Undefined

*4 Reset (0) immediately after being read

*5 Always "0" when being read

*6 Refer to main manual

Interrupt mask registers (0EBH D0–D2)

Interrupt factor flags (0EFH D0–D2)

See 4.7, "Clock Timer".

Interrupt mask register (0ECH D0)

Interrupt factor flag (0F0H D0)

See 4.8, "A/D Converter".

Interrupt mask registers (0E8H)

Interrupt factor flag (0EDH D0)

See 4.3, "Input Ports".

Address Comment

D3 D2 D1 D0 Name Init 1 0

0E8H

EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Interrupt mask register K03

Interrupt mask register K02

Interrupt mask register K01

Interrupt mask register K00

Enable

Mask

EIK01EIK02EIK03

0EBH

EIT32 0

EIT2

EIT8

EIT32

Interrupt mask register (clock timer) 2 Hz

Interrupt mask register (clock timer) 8 Hz

Interrupt mask register (clock timer) 32 Hz

Enable

Mask

EIT8

R/W

EIT20

0ECH

EIAD

R/W

EIAD 0

Interrupt mask register (A/D)

Enable Mask

0EDH

IK0 0

Interrupt factor flag (K00–K03)

Yes No

000

0EFH

IT32

IT2

IT8

IT32

Interrupt factor flag (clock timer) 2 Hz

Interrupt factor flag (clock timer) 8 Hz

Interrupt factor flag (clock timer) 32 Hz

Yes

IT8IT20

0F0H

IAD 0

Interrupt factor flag (A/D)

Yes No

000

S1C60N05 TECHNICAL MANUAL EPSON 63

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

BASIC EXTERNAL WIRING DIAGRAM

(1) Piezo Buzzer Single Terminal Driving

CHAPTER 5

OSC1

OSC2

RESET

TEST

Vss

X'tal

1.5 V

3.0 V

Piezo

Buzzer

R01

K00

K03

P00

P03

R00

R02

R03

I/O

SEG0

SEG19

COM0

COM3

LCD

PANEL

S1C60N05/60L05

[The potential of the substrate

(back of the chip) is V

Coil

TH1

TH2

Capacitors (C

and C

) are connected.

Connection dependingon power supply

and LCD panel specification.

Please refer to page 7.

X'tal

, C

TH1, TH2

Crystal oscillator

Trimmer capacitor

Capacitor

Thermistor

Resistor

Capacitor

32,768 Hz CI(MAX) = 35 kΩ

5–25 pF

0.1 µF

3.3 µF

50 kΩ

49.8 kΩ

2,200 pF

64 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM

R00

K00

K03

P00

P03

R02

R03

I/O

SEG0

SEG19

COM0

COM3

LCD

PANEL

R01

OSC1

OSC2

RESET

TEST

Vss

1.5 V

3.0 V

S1C60N05/60L05

[The potential of the substrate

(back of the chip) is V

TH1

TH2

Piezo

Buzzer

X'tal

Capacitors (C

and C

) are connected.

Connection dependingon power supply

and LCD panel specification.

Please refer to page 7.

(2) Piezo Buzzer Direct Driving

X'tal

, C

TH1, TH2

, R

Crystal oscillator

Trimmer capacitor

Capacitor

Thermistor

Resistor

Capacitor

32,768 Hz CI(MAX) = 35 kΩ

5–25 pF

0.1 µF

3.3 µF

50 kΩ

49.8 kΩ

100 Ω

2,200 pF

S1C60N05 TECHNICAL MANUAL EPSON 65

CHAPTER 6: ELECTRICAL CHARACTERISTICS

CHAPTER 6 ELECTRICAL CHARACTERISTICS

6.1 Absolute Maximum Rating

S1C60L05

S1C60N05

Power voltage

Input voltage (1)

Input voltage (2)

Operating temperature

Storage temperature

Soldering temperature / Time

Allowable dissipation

Item Symbol

VSS

VIOSC

Topr

Tstg

Tsol

Rated value

-5.0 to 0.5

Vss-0.3 to 0.5

-20 to 70

-65 to 150

260°C, 10sec (lead section)

250

Unit

°C

–

(VDD=0V)

Power voltage

Input voltage (1)

Input voltage (2)

Operating temperature

Storage temperature

Soldering temperature / Time

Allowable dissipation

Item Symbol

VSS

VIOSC

Topr

Tstg

Tsol

Rated value

-5.0 to 0.5

Vss-0.3 to 0.5

-20 to 70

-65 to 150

260°C, 10sec (lead section)

250

Unit

°C

–

(VDD=0V)

*1 In case of QFP6-60 pin plastic package

66 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.2 Recommended Operating Conditions

S1C60N05

S1C60L05

*1 When there is no software control during CR oscillation or crystal oscillation.

Item

Power voltage

Oscillation frequency

Booster capacitor

Capacitor between V

and V

Symbol

OSC1

OSC2

Condition

=0V

Crystal oscillation

CR oscillation, R=420kΩ

Min

-3.5

0.1

Typ

-3.0

32,768

Unit

kHz

µF

Max

-1.8

(Ta=-20 to 70°C)

Item

Power voltage

Oscillation frequency

Booster capacitor

Capacitor between V

and V

Symbol

OSC1

OSC2

Condition

=0V

Crystal oscillation

CR oscillation, R=420kΩ

Min

-2.0

0.1

Typ

-1.5

32,768

Unit

kHz

µF

Max

-1.2

(Ta=-20 to 70°C)

S1C60N05 TECHNICAL MANUAL EPSON 67

CHAPTER 6: ELECTRICAL CHARACTERISTICS

6.3 DC Characteristics

S1C60N05

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal

voltages, and C1=C2=0.1 µF

Item Symbol

VIH1

VIH2

VIL1

VIL2

IIH1

IIH2

IIH3

IIL

IOH1

IOH2

IOH3

IOL1

IOL2

IOL3

IOH4

IOL4

IOH5

IOL5

IOH6

IOL6

Condition Min

0.2•VSS

0.15•VSS

VSS

-0.5

3.0

300

Typ Unit

µA

Max

0.8•VSS

0.85•VSS

0.5

100

-1.0

-3

-300

K00–K03, P00–P03

RESET, TEST

K00–K03, P00–P03

RESET, TEST

K00–K03, P00–P03

K00–K03

P00–P03

RESET, TEST

K00–K03, P00–P03

RESET, TEST

R02, R03, P00–P03

R00, R01

ADOUT

R02, R03, P00–P03

R00, R01

ADOUT

COM0–COM3

SEG0–SEG19

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

High level output current (1)

High level output current (2)

High level output current (3)

Low level output current (1)

Low level output current (2)

Low level output current (3)

Common output current

Segment output current

(during LCD output)

Segment output current

(during DC output)

VIH1=0V

Without pull down resistor

VIH2=0V

With pull down resistor

VIH3=0V

With pull down resistor

VIL=VSS

VOH1=0.1•VSS

VOH2=0.1•VSS

(built-in protection resistance)

VOH3=-1.0V

VOL1=0.9•VSS

VOL2=0.9•VSS

(built-in protection resistance)

VOL3=-2.0V

VOH4=-0.05V

VOL4=VL3+0.05V

VOH5=-0.05V

VOL5=VL3+0.05V

VOH6=0.1•VSS

VOL6=0.9•VSS

68 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60L05

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, VS1, VL1, VL2 and VL3 are internal

voltages, and C1=C2=0.1 µF

Item

Symbol

IH1

IH2

IL1

IL2

IH1

IH2

IH3

OH1

OH2

OH3

OL1

OL2

OL3

OH4

OL4

OH5

OL5

OH6

OL6

Condition Min

0.2•V

0.15•V

9.0

-0.5

700

130

Typ Unit

µA

Max

0.8•V

0.85•V

0.5

100

-200

-3

-100

K00–K03, P00–P03

RESET, TEST

K00–K03, P00–P03

RESET, TEST

K00–K03, P00–P03

K00–K03

P00–P03

RESET, TEST

K00–K03, P00–P03

RESET, TEST

R02, R03, P00–P03

R00, R01

ADOUT

R02, R03, P00–P03

R00, R01

ADOUT

COM0–COM3

SEG0–SEG19

High level input voltage (1)

High level input voltage (2)

Low level input voltage (1)

Low level input voltage (2)

High level input current (1)

High level input current (2)

High level input current (3)

Low level input current

High level output current (1)

High level output current (2)

High level output current (3)

Low level output current (1)

Low level output current (2)

Low level output current (3)

Common output current

Segment output current

(during LCD output)

Segment output current

(during DC output)

IH1

=0V

Without pull down resistor

IH2

=0V

With pull down resistor

IH3

=0V

With pull down resistor

OH1

=0.1•V

OH2

=0.1•V

(built-in protection resistance)

OH3

=-0.5V

OL1

=0.9•V

OL2

=0.9•V

(built-in protection resistance)

OL3

=-1.0V

OH4

=-0.05V

OL4

+0.05V

OH5

=-0.05V

OL5

+0.05V

OH6

=0.1•V

OL6

=0.9•V

S1C60N05 TECHNICAL MANUAL EPSON 69

CHAPTER 6: ELECTRICAL CHARACTERISTICS

Analog Circuit Characteristics and Power Current Con-

sumption

S1C60N05 (Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3

are internal voltages, and C1=C2=0.1 µF

(During A/D conversion: RS=49.8 kΩ, TH=50 kΩ, CAD=2,200 pF)

S1C60N05 (Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3

are internal voltages, and C1=C2=0.1 µF

(During A/D conversion: RS=49.8 kΩ, TH=50 kΩ, CAD=2,200 pF)

6.4

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

1/2•V

-0.1

3/2•V

-0.1

Typ

0.8

1.5

Unit

µA

Max

1/2•V

0.9

3/2•V

0.9

1.4

5.0

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

Internal voltage

Power current

consumption

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

1/2•V

-0.1

3/2•V

-0.1

Typ

2.0

5.5

Unit

µA

Max

1/2•V

0.85

3/2•V

0.85

5.5

10.0

41.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

70 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60L05 (Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3

are internal voltages, and C1=C2=0.1 µF

(During A/D conversion: RS=49.8 kΩ, TH=50 kΩ, CAD=2,200 pF)

S1C60L05 (Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3

are internal voltages, and C1=C2=0.1 µF

(During A/D conversion: RS=49.8 kΩ, TH=50 kΩ, CAD=2,200 pF)

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

2•V

-0.1

3•V

-0.1

Typ

0.8

1.5

Unit

µA

Max

2•V

0.9

3•V

0.9

1.4

5.0

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

2•V

-0.1

3•V

-0.1

Typ

2.0

5.5

Unit

µA

Max

2•V

0.85

3•V

0.85

5.5

10.0

41.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

S1C60N05 TECHNICAL MANUAL EPSON 71

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60N05 (CR, Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=0.1 µF, Recommended external resistance for CR

oscillation = 420 kΩ

(During A/D conversion: RS=49.8 kΩ, TH=50 kΩ, CAD=2,200 pF)

S1C60N05 (CR, Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=0.1 µF, Recommended external resistance for CR

oscillation = 420 kΩ

(During A/D conversion: RS=49.8 kΩ, TH=50 kΩ, CAD=2,200 pF)

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

1/2•V

-0.1

3/2•V

-0.1

Typ

8.0

15.0

Unit

µA

Max

1/2•V

0.9

3/2•V

0.9

15.0

20.0

52.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

1/2•V

-0.1

3/2•V

-0.1

Typ

16.0

30.0

Unit

µA

Max

1/2•V

0.85

3/2•V

0.85

30.0

40.0

57.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

72 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60L05 (CR, Normal Operating Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=0.1 µF, Recommended external resistance for CR

oscillation = 420 kΩ

(During A/D conversion: RS=49.8 kΩ, TH=50 kΩ, CAD=2,200 pF)

S1C60L05 (CR, Heavy Load Protection Mode)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25°C, CG=25 pF, VS1, VL1, VL2 and VL3 are

internal voltages, and C1=C2=0.1 µF, Recommended external resistance for CR

oscillation = 420 kΩ

(During A/D conversion: RS=49.8 kΩ, TH=50 kΩ, CAD=2,200 pF)

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

2•V

-0.1

3•V

-0.1

Typ

8.0

15.0

Unit

µA

Max

2•V

0.9

3•V

0.9

15.0

20.0

52.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

Internal voltage

Power current

consumption

Symbol

Condition

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Connect 1MΩ load resistor between V

and V

(without panel load)

Min

2•V

-0.1

3•V

-0.1

Typ

16.0

30.0

Unit

µA

Max

2•V

0.85

3•V

0.85

30.0

40.0

57.5

During HALT

During execution Without panel load

During A/D conversion (HALT)

Item

S1C60N05 TECHNICAL MANUAL EPSON 73

CHAPTER 6: ELECTRICAL CHARACTERISTICS

Oscillation Characteristics

Oscillation characteristics will vary according to different conditions (components

used, board pattern, etc.). Use the following characteristics are as reference

values.

S1C60N05

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25°C

6.5

S1C60L05

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25°C

*1 Items enclosed in parentheses ( ) are those used when operating at heavy load

protection mode.

Item

Oscillation start voltage

Oscillation stop voltage

Built-in capacity (drain)

Frequency voltage deviation

Frequency IC deviation

Frequency adjustment range

Higher harmonic oscillation

start voltage

Allowable leak resistance

Symbol

Vsta

(Vss)

Vstp

(Vss)

f/V

f/IC

f/CG

Vhho

(Vss)

Rleak

Condition Min

-1.8

-10

200

Typ

Unit

ppm

MΩ

Max

-3.6

tsta≤5sec

tstp≤10sec

Including the parasitic capacity inside the IC

Vss=-1.8 to -3.5V

CG=5–25pF

CG=5pF

Between OSC1 and VDD,

and between VSS and OSC1

Item

Oscillation start voltage

Oscillation stop voltage

Built-in capacity (drain)

Frequency voltage deviation

Frequency IC deviation

Frequency adjustment range

Higher harmonic oscillation

start voltage

Allowable leak resistance

Symbol

Vsta

(Vss)

Vstp

(Vss)

f/V

f/IC

f/CG

Vhho

(Vss)

Rleak

Condition Min

-1.2

-10

200

Typ

Unit

ppm

MΩ

Max

-2.0

tsta≤5sec

tstp≤10sec

Including the parasitic capacity inside the IC

Vss=-1.2 to -2.0V (-0.9)

CG=5–25pF

CG=5pF

Between OSC1 and VDD,

and between VSS and OSC1

74 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 6: ELECTRICAL CHARACTERISTICS

S1C60N05 (CR)

Unless otherwise specified

VDD=0 V, VSS=-3.0 V, RCR=480 kΩ, Ta=25°C

S1C60L05 (CR)

Unless otherwise specified

VDD=0 V, VSS=-1.5 V, RCR=480 kΩ, Ta=25°C

Item

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

Oscillation stop voltage

Symbol

fosc

Vsta

sta

Vstp

Condition

Vss=-1.8 to -3.5V

Min

-20

-1.8

Typ

65kHz

Unit

Max

Item

Oscillation frequency dispersion

Oscillation start voltage

Oscillation start time

Oscillation stop voltage

Symbol

fosc

Vsta

sta

Vstp

Condition

Vss=-1.2 to -2.0V

Min

-20

-1.2

Typ

65kHz

Unit

Max

S1C60N05 TECHNICAL MANUAL EPSON 75

CHAPTER 7: PACKAGE

CHAPTER 7 PACKAGE

7.1 Plastic Package

14±0.2

17.6±0.4

3145

14±0.2

17.6±0.4

INDEX

0.35±0.1

151

2.7±0.1

0.1

3.1

max

1.8

0.85±0.2

0°

10°

0.15±0.05

0.8

QFP6-60pin (Unit: mm)

76 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 7: PACKAGE

Ceramic Package for Test Samples

7.2

DIP-64pin (Unit: mm)

22.8

23.1

78.7

2.54

PIN NO. 1 2 31 32

34 3364 63

INDEX MARK

81.3

No.

Pin name

N.C.

SEG17

SEG18

SEG19

COM0

COM1

COM2

COM3

N.C.

No.

Pin name

OSC1

OSC2

P00

P01

P02

P03

N.C.

K00

K01

K02

K03

R00

R01

No.

Pin name

R02

R03

TH1

TH2

N.C.

ADOUT

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

No.

Pin name

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

N.C.

TEST

RESET

SEG12

SEG13

SEG14

SEG15

SEG16

N.C.

N.C. = No Connection

S1C60N05 TECHNICAL MANUAL EPSON 77

CHAPTER 8: PAD LAYOUT

CHAPTER 8 PAD LAYOUT

8.1 Diagram of Pad Layout

(0, 0)

678910111213

28 29 30 31 32 33 34 35 36 37 38 39 40 41

Die No.

2.58 mm

2.95 mm

78 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 8: PAD LAYOUT

8.2 Pad Coordinates

(Unit: µm)

Pad No.

Pad name

ADOUT

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

TEST

RESET

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

COM0

COM1

COM2

COM3

Pad name

VL3

VL2

VL1

VSS

VDD

OSC1

OSC2

VS1

P00

P01

P02

P03

K00

K01

K02

K03

R00

R01

R02

R03

TH1

TH2

644

511

381

251

121

-9

-139

-269

-399

-529

-659

-789

-919

-1,306

-1,259

-1,129

-998

-868

-737

-81

185

337

490

863

993

1,123

1,253

1,306

1,121

987

854

724

597

464

334

204

-56

-186

-371

-509

-639

-769

-1,121

-665

-535

-404

-274

-49

310

440

582

721

857

1,038

S1C60N05 TECHNICAL MANUAL EPSON 79

CHAPTER 9: PRECAUTIONS ON MOUNTING

CHAPTER 9 PRECAUTIONS ON MOUNTING

Oscillation circuit • Oscillation characteristics change depending on conditions

(board pattern, components used, etc.).

In particular, when a ceramic oscillator or crystal oscillator is

used, use the oscillator manufacturer’s recommended values for

constants such as capacitance and resistance.

• Disturbances of the oscillation clock due to noise may cause a

malfunction. Consider the following points to prevent this:

(1) Components which are connected to the OSC1 and OSC2

terminals, such as oscillators, resistors and capacitors,

should be connected in the shortest line.

(2) As shown in the right hand figure, make a VDD pattern as

large as possible at circumscription of the OSC1 and OSC2

terminals and the components connected to these terminals.

Furthermore, do not use this VDD pattern for any purpose

other than the oscillation system.

OSC2

OSC1

VDD

Sample VDD pattern

• In order to prevent unstable operation of the oscillation circuit

due to current leak between OSC1 and VSS, please keep enough

distance between OSC1 and VSS or other signals on the board

pattern.

Reset circuit • The power-on reset signal which is input to the RESET terminal

changes depending on conditions (power rise time, components

used, board pattern, etc.).

Decide the time constant of the capacitor and resistor after

enough tests have been completed with the application product.

When the built-in pull-down resistor is added to the RESET

terminal by mask option, take into consideration dispersion of

the resistance for setting the constant.

• In order to prevent any occurrences of unnecessary resetting

caused by noise during operating, components such as

capacitors and resistors should be connected to the RESET

terminal in the shortest line.

Power supply circuit • Sudden power supply variation due to noise may cause

malfunction. Consider the following points to prevent this:

(1) The power supply should be connected to the VDD and VSS

terminal with patterns as short and large as possible.

80 EPSON S1C60N05 TECHNICAL MANUAL

CHAPTER 9: PRECAUTIONS ON MOUNTING

(2) When connecting between the VDD and VSS terminals with a

bypass capacitor, the terminals should be connected as

short as possible.

Bypass capacitor connection example

(3) Components which are connected to the VS1, VL1–VL3

terminals, such as capacitors and resistors, should be

connected in the shortest line.

In particular, the VL1–VL3 voltages affect the display quality.

• Do not connect anything to the VL1–VL3 terminals when the

LCD driver is not used.

Arrangement of

signal lines

• In order to prevent generation of electromagnetic induction

noise caused by mutual inductance, do not arrange a large

current signal line near the circuits that are sensitive to noise

such as the oscillation unit.

• When a signal line is parallel with a high-speed line in long

distance or intersects a high-speed line, noise may generated by

mutual interference between the signals and it may cause a

malfunction.

Do not arrange a high-speed signal line especially near circuits

that are sensitive to noise such as the oscillation unit.

OSC2

OSC1

VDD

Large current signal line

High-speed signal line

Prohibited pattern

Precautions for

visible radiation

(when bare chip is

mounted)

• Visible radiation causes semiconductor devices to change the

electrical characteristics. It may cause this IC to malfunction.

When developing products which use this IC, consider the

following precautions to prevent malfunctions caused by visible

radiations.

(1) Design the product and implement the IC on the board so

that it is shielded from visible radiation in actual use.

(2) The inspection process of the product needs an environment

that shields the IC from visible radiation.

(3) As well as the face of the IC, shield the back and side too.

S1C60N05 TECHNICAL MANUAL EPSON 81

APPENDIX: TECHNICAL INFORMATION

TECHNICAL INFORMATION

This chapter presents the information necessary for designing a

thermometer using a Seiko Epson S1C60N05 and a Thermistor

manufactured by Ishizuka Denshi Inc.

Appendices

Appendix A Design Steps for Designing Thermometer

This section describes the design steps for the thermometer using

the S1C60N05 and the Thermistor.

Thermometer design

steps

The following shows the design steps:

(1) Obtain the external capacitor value and the oscillation fre-

quency.

(2) Obtain the initial value that is set to the up-counter of the A/D

converter.

(3) After A/D conversion, calculate the displayed temperature from

the counter value that has been set in the up-counter.

Details of these steps are described in later sections.

Before designing the thermometer, the measured temperature

range, standard temperature, and thermistor to be used have to be

determined.

Measured temperature range

Determine for your application.

Standard temperature

The standard temperature is the most precise value. Determine

the standard temperature as the temperature that you want to be

the most precise.

Thermistor

Select the thermistor considering the measured temperature range

and the standard temperature. It also should match the IC.

Note that this document assumes the following:

Measured temperature range: -30°C–70°C

Standard temperature: 20°C

Thermistor: Thermistor 103AT (Compatibility with S1C60N05)

82 EPSON S1C60N05 TECHNICAL MANUAL

APPENDIX: TECHNICAL INFORMATION

The following A/D converter circuit diagram is shown for your

reference.

Fig. A.1

A/D converter configuration

Tr2

Multiplying

circuit

Interrupt

request

OSC1

clock 32 kHz or 65 kHz TC15

–TC12 TC11

–TC8 TC7

–TC4 TC3

–TC0

Up/down counter

ADCLK

C15

–C12 C11

–C8 C7

–C4 C3

–C0

Start/Stop

ADRUN

Controller

Up-counter

Start/Stop

control

Up/Down

control Data bus

Start/Stop

control

Interrupt

controller

IAD EIAD

Tr1Tr3

TH1RS

CS R

ADOUT

Tr4 V

TH2

External capacitor Standard

resistor

Thermistor

S1C60N05 TECHNICAL MANUAL EPSON 83

APPENDIX: TECHNICAL INFORMATION

How to obtain

capacitor value and

oscillation frequency

The standard resistor and the thermistor are oscillated according

to S1C60N05 A/D converter principles. It is necessary to

determine the value of the external capacitor for the oscillation.

This section describes how to determine the standard resistor

value, the external capacitor value and the CR oscillation fre-

quency.

Table A.1

Item

Standard resistor

value (R1)

Computation of

capacitor for

oscillation

Computation of

frequency from the

standard resistance

Description

Thermistor resistance value at the standard

temperature.

The relationship between the frequency,

capacitor, and the resistor is as follows:

f = K f: Oscillation frequency

CR K: CR oscillation frequency

coefficient

C: Capacitor

R: Resistance

From the equation above, C can be obtained

based on f and K conditions of S1C60N05.

If the C value is smaller within the conditions,

the precision is higher.

If the C value is determined by the above

equation, the frequency (fCR1) by the standard

resistance can be obtained by the following

equation:

fCR1 (kHz) = K

CR1

Thermistor 103AT usage example

At 25°C, the 103AT resistance is 10 kΩ.

Thus the standard resistance is 10 kΩ.

The f and K conditions of S1C60N05 are as follows:

f(max) = 85 kHz (limit of IC operation)

1≤K≤3 (Oscillation coefficient in S1C60N05)

With these conditions, the following equation can be

derived:

85 kHz ≥K

CR2(TMAX)

R2(TMAX): Minimum resistance of Thermistor

K=3 is the worst condition, then

C ≥3

85×103×2.23×103= 15,800 (pF)

As a result, the following is determined:

C = 22,000 (pF) (Value for general purpose product)

The following is obtained:

fCR1 = (1 to 3)

22,000×10-12×10×103= 4.5 to 13.5 (kHz)

By the above equations, the capacitor value (22,000 pF) and the

oscillation frequency (4.5–13.5 kHz) by the standard resistance are

determined.

For the details of 103AT, see Appendix C.

84 EPSON S1C60N05 TECHNICAL MANUAL

APPENDIX: TECHNICAL INFORMATION

Setting up counter

initial value

The capacitor value and the oscillation frequency by the standard

resistance are determined in the previous section.

This section describes how to set the initial value of the A/D

converter's up counter.

For A/D converter principals, see the technical manual for the

S1C60N05.

fx'tal:

fCR1:

fCR2:

65535 - CUPI:

CUPS:

65535:

tA:

Crystal oscillation frequency

Standard oscillation frequency

Thermistor oscillation frequency

Up counter initial value

Thermistor count value

MAX. counter value

Count time

655350

65535 - CUPI

CUPS

fCR1 tA

fCR2 tA

Up counter ➀

➁

655350 tA

fx'tal

Up-down counter

➀fx'tal

➁

Fig. A.2

Figure A.2 shows the relationship between the up counter and the

up-down counter.

The following conditions should be satisfied:

Condition (A): The up-down counter should not overflow during an

up-count

Condition (B): The up counter should not overflow during a down-

count

With these conditions, the up counter initial value can be obtained

with the following equations:

Table A.2

Item

Obtain the up

counter initial value

from the condition

(A)

Obtain the up

counter initial value

from the condition

(B)

Description

From the condition (A) the following equation is

derived:

65535 > t

•fx'tal = 65535 - C

UPI

CR1

× fx'tal

UPI

> ( 1- f

CR1

fx'tal )× 65535

Initial value ≤ 65535 - C

UPI

...(a)

From the condition (B) the following equation is

derived:

65535 > C

UPS

= t

×f

CR2(3)

CR2

CR1

×(65535 - C

UPI

)

UPI

= ( 1 - f

CR1

CR2(3)

)×65535

Initial value ≤ 65535 - C

UPI

...(b)

From the above equations (a) and (b) the initial

value can be determined.

Thermistor 103AT usage example

From fx'tal = 65 kHz, f

CR1

= 4.5–13.5 kHz

UPI

= ( 1 - 4.5×10

65×10

)×65535 ≈ 59571

UPI

= ( 1 - 13.5×10

65×10

)× 65535 ≈ 50707

Initial value ≤ 65535 - 59571 = 5964 ...(a)'

CR1

= 4.5–13.5 kHz,

CR2

= 85 kHz (IC operational maximum)

UPI

= ( 1 - 4.5×10

85×10

)×65535 ≈ 60608

UPI

= ( 1 - 13.5×10

85×10

)×65535 ≈ 53837

Initial value ≤ 65535 - 60608 = 4927 ...(b)'

From (a)' and (b)', the initial value should be set less

than 4927. Here, it is set to 3000.

(Under the conditions, if the initial value is smaller,

the precision is higher.)

The initial value (3,000) for the up counter is derived from the

above equations.

S1C60N05 TECHNICAL MANUAL EPSON 85

APPENDIX: TECHNICAL INFORMATION

Computation

method of displayed

temperature by

linear approximation

The following shows the linear approximation equation to derive

the displayed temperature.

Displayed temperature (°C) = (Count after A/D conversion - Count for

minimum in the temperature range) × linear approximation coefficient +

minimum value of the temperature range

This equation derives the displayed temperature. The following

shows the method. First, each value is described.

[Count value after A/D conversion]

This is the up counter value after an A/D conversion.

[Count for the minimum value of the temperature range]

[Minimum value of the temperature range]

To derive the displayed temperature by the linear approximation,

the temperature range must be determined for the linear approxi-

mation. In this example, the measured temperature range is -30 to

70°C.

If the temperature range for the linear approximation is set for

every 10°C, the temperature range is -30 to -20°C, -20 to -10°C,

and so on. The smallest value of each temperature range segment

is the minimum value of the temperature range. The largest value

is the maximum value of the temperature range.

The count value for the minimum value for the temperature range

is expressed by the following equation:

A/D converter count value = fCR2(3) × up counter initial value

fCR1

=(K/CR2(3))× up counter initial value

(K/CR1)

=R1× up counter initial value

R2(3)

By substituting R2 (Thermistor resistance), R1 (standard resist-

ance), and the up counter initial value with actual values, the

count value for the minimum of the temperature range is obtained.

[Linear approximation coefficient]

The linear approximation coefficient is the value that shows how

many degrees (centigrade) for one count in the temperature range.

The linear approximation coefficient is expressed by the following

equation:

Linear approximation coefficient =

Temperature range

Count for max. of temperature range - Count for min. of temperature range

(As you can see, the temperature range is smaller, the precision is

higher.)

86 EPSON S1C60N05 TECHNICAL MANUAL

APPENDIX: TECHNICAL INFORMATION

The following table shows the various values for every 10°C.

Table A.3

Temperature

(°C)

-30

-20

-10

103AT Thermistor

resistance (kΩ)

111.3

67.74

42.45

27.28

17.96

12.09

8.313

5.828

4.161

3.021

2.229

Count value

269

443

706

1099

1670

2481

3608

5147

7209

9930

13459

Linear approximation

coefficient in the specified

temperature range

0.0575

0.0380

0.0254

0.0175

0.0123

0.00887

0.00650

0.00485

0.00368

0.00283

The following example derives a displayed temperature using the

values in the above table.

Example: Assume the count value after an A/D conversion is 3200. Then, it

is between 3608 and 2481 in the table. As a result the tempera-

ture range is 20° to 30°C.

• The count value for the minimum value of the temperature

range: 2481

• The count value for the maximum value of the temperature

range: 3608

Then, the linear approximation coefficient of the temperature range

is 0.00887.

As a result, the displayed temperature is derived as follows:

Displayed temperature = (3200 - 2481) × 0.00887 + 20 (°C) = 26.377 (°C)

S1C60N05 TECHNICAL MANUAL EPSON 87

APPENDIX: TECHNICAL INFORMATION

Appendix B Error Factors

When a temperature is computed using the S1C60N05 A/D con-

verter and the Thermistor, the following error factors should be

taken in account:

Thermistor resistance

dispersion

The Thermistor manufacturer should guarantee the precision.

A/D converter error

factors

Error (circuit) by A/D conversion in R1 (standard resistance)

and R2 (Thermistor)

By the CR oscillation at the standard resistor (R1), the up counter

and the up-down counter increment the counter with the timing

shown below.

Fig. B.1

ADRUN register

CS pin

ADOUT output

Up counter enable

Up counter (C0)

Clock (Up-down counter)

Up-down counter enable

Up-down counter (TC0)

Starts counting

After the A/D RUN, the first trailing edge of the CS pin triggers the

up counter enable. From the next trailing edge, the up counter

starts to count. In addition, the first trailing edge of the clock after

the up counter is enabled, the up-down counter is enabled and it

starts to count from the next trailing edge.

When the up counter value becomes 0, the up counter is disabled.

The next trailing edge of the clock disables the up-down counter.

If this situation occurs, the error described below will result.

Started: Min. ≈ 0

Max. Up-down counter - 1 count Total up-down counter

Stopped: Min ≈ 0 - 2 counts

Max. Up-down counter - 1 count

The same is true in the CR oscillation by Thermistor R2, and a

similar error occurs. Exception: because the up-down counter is

down-counted the following counting error occurs:

Started: Min. ≈ 0

Max. Up-down counter - 1 count Total up-down counter

Stopped: Min ≈ 0 - 2 counts

Max. Up-down counter - 1 count

Therefore, as for the error from the circuit, a maximum of 2 count

errors results.

88 EPSON S1C60N05 TECHNICAL MANUAL

APPENDIX: TECHNICAL INFORMATION

The effect of the maximum 2 count error is given below.

∆1MAX (%) = 2× 100 --- (1)

(fCLK/fCR1) × CUPI1

∆2MAX (%) = 2× 100 --- (2)

(fCLK/fCR2) × CUPS

fCLK: Clock frequency (32 kHz/64 kHz)

fCR1: CR oscillation frequency by standard resistor

CUPI1: Up counter initial value (times)

∆1MAX:Maximum error (%) at CR oscillation by standard resistor

fCR2: CR oscillation frequency by Thermistor

CUPS: Thermistor count (times)

∆2MAX:Maximum error (%) at CR oscillation by Thermistor

In addition, the number of counts of the up-down counter should

be the same. Then the following equation is true:

fCLK × CUPI1 = fCLK × CUPS --- (3)

fCR1 fCR2

Then, from (3), assume the up-down counter counts shifted 2

counts, the following equations are true:

fCLK × CUPI1 = fCLK × CUPS ±2

fCR1 fCR2

fCR2 =CUPS ± 2 × (fCR2/fCLK)--- (3)'

fCR1 CUPI1

(1) is the count error at the CR oscillation by the standard resistor.

(2) is the count error at the CR oscillation by Thermistor.

The total error is expressed by the equation (3)' with the ratio of

fCR1 and fCR2.

The segment that represents the error in the equation (3)' is ±2 ×

(fCR2/fCLK). If the values CUPI1 and CUPS are large, this error factor

may be ignored.

For how to determine the initial value (CUPI1) of the up counter, see

the section describing thermometer design steps.

CR oscillation constant (K) error

The constant, K, is determined by the logic level of the internal

Schmidt trigger of the IC. However, in S1C60N05, the Schmidt

trigger shares the circuit with the standard resistor and Thermis-

tor. As a result, oscillation is canceled and no error occurs.

Error by transistor ON resistance

The transistor ON resistance is directly connected to the standard

resistor and Thermistor; this may cause an error.

See the circuit shown next to Figure B.2 below. In this circuit, the

capacitor is charged by Tr1, T2 ON and Tr3 OFF. If the voltage at

the CS pin changes to a certain level, the capacitor charge is

drained by Tr1, Tr2 OFF and Tr3 ON. As a result, the CR oscilla-

tion is generated as in Figure B.3.

S1C60N05 TECHNICAL MANUAL EPSON 89

APPENDIX: TECHNICAL INFORMATION

At this time, if the ON resistance of Tr1 and Tr2 ON is t1 and the

ON resistance of Tr3 is t2, the constance may be effected.

The S1C60N05 transistors are standardized to have a maximum of

100 Ω.

This standard includes dispersion by temperature characteristics,

Pch and Nch.

The Evaluation board transistor uses standard ICs and the actual

resistance is about 1 kΩ. (This is not guaranteed and should be

regarded as just a reference.)

The error by ON resistance of this transistor is expressed by the

following equations:

∆3 (%) = Up counter count - Actual upcounter count × 100

Up counter count

CUPI1 - C(R1 + RTr) × CUPI1

=fCR1 × 100 = { 1- R1} × 100

CUPI1 (R1 + RTr)

∆4 (%) = Up counter count - Actual upcounter count × 100

Up counter count

CUPS - C(R2 + RTr) × CUPI1

=fCR2 × 100 = { 1- R2} × 100

CUPS (R2 + RTr)

∆3: Error (%) by transistor ON resistance (CR oscillation by standard resistance)

∆4: Error (%) by transistor ON resistance (CR oscillation by Thermistor)

CUPI1:Up counter initial value (times)

CUPS: Thermistor count value (times)

RTr: Transistor ON resistance (Ω)

fCR1: Oscillation frequency (Hz) (CR oscillation by standard resistance)

fCR2: Oscillation frequency (Hz) (CR oscillation by Thermistor)

Fig. B.2

Tr2 VDD

Tr1Tr3

TH1RS

CS R1R2

VSS

ADOUT

Tr4 VDD

TH2

VSS C

Fig. B.3

90 EPSON S1C60N05 TECHNICAL MANUAL

APPENDIX: TECHNICAL INFORMATION

Transistor ON resistance error when Thermistor 103AT measures

60°C

∆3 = { 1 - 10 × 103} × 100 ≈ 1%

(10 × 103 + 100)

∆4 = { 1 - 3.217 × 103} × 100 ≈ 3%

(3.217 × 103 + 100)

As a result, the following errors occur by directly connecting the

transistor ON resistance:

1% at CR oscillation on the standard resistor

3% at CR oscillation on Thermistor

The transistor ON resistance effect is smaller if R1 and R2 are

larger. (See Equation ∆3 and ∆4.)

In the high temperature range, the R2 value becomes small and ∆4

becomes large. This causes precision degradation. Compensation

is needed to implement a user's required precision.

Figure B.4 shows the A/D converter ON resistance errors (∆4 - ∆3)

of the Evaluation board and the actual IC when the thermistor

103AT is used.

ON resistance errors when thermistor 103AT is used

Example:

Fig. B.4

-10

-20

-50 -20 0 25 50 70 100

Error

∆4 - ∆3 (%)

Temperature

(°C)

Error by ON resistance (1 kΩ)

in the Evaluation board

Error by ON resistance (100 Ω)

in the actual IC

This figure shows the plot of errors when the ON resistance in the

Evaluation board is 1 kΩ and that of the actual IC is 100 Ω. As

shown in the figure, the Evaluation board's error is larger than the

actual IC, therefore, programs evaluated using the Evaluation

board may not operate normally in the actual IC.

To avoid this problem, it is necessary to reduce the ON resistance

error.

Choose a thermistor resistance as large as possible to reduce the

ON resistance error. At least 10 kΩ (Ta = 25°C) of resistance is

required. The plot (Figure B.4) is in this case shows a 10 kΩ

thermistor resistance that satisfies the minimum resistance

condition, note, however, that there is a large error increase in

temperature over 60°C.

S1C60N05 TECHNICAL MANUAL EPSON 91

APPENDIX: TECHNICAL INFORMATION

Error by floating

capacity

The floating capacity of the inside of an IC, board, lead of a sensor

and others may be an error factor. Floating capacity inside an IC

may be several pF and it may be ignored by increasing the capaci-

tor value.

Software error In the software, it is normal to convert the counter value to an

actual temperature by a linear approximation. In this method, an

error may be caused by the linear approximation in the tempera-

ture measured range.

As shown in Figure B.5 below, if the temperature range measured

is 20°C to 30°C, the weight of 1 count differs between 20°C and

29°C.

Fig. B.5

(1) (2)

Temperature (°C)

Counts (times)

On the slope (1), the linear approximation coefficient in this seg-

ment for 1 count is large, and the slope (2) has a smaller coeffi-

cient.

For example, if this segment (20°C to 30°C) is calculated by the

same linear approximation coefficient, and if the 20°C is the

reference point, then, at 29°C, the linear approximation coefficient

becomes the largest and, at 29°C, the error is maximum.

The error may differ depending on the temperature measured by

the software, up counter initial value and Thermistor type.

For example, when using a 10 kΩ (Ta = 25°C) thermistor for the

actual IC, the ON resistance in the Evaluation board can be close

to that of the actual IC by connecting 10 thermistors in series to

configure a 100 kΩ (Ta = 25°C) thermistor and by using a 100 kΩ

reference resistance and reducing the capacitance to 1/10.

However, ON resistance is so susceptible to source voltage levels

and board mount conditions affect the conversion results, there-

fore, it is impossible to obtain exactly the same results between the

Evaluation board and the actual IC even if the methods described

above are used. It is necessary to evaluate the A/D conversion

using the results of several samples from the final product.

92 EPSON S1C60N05 TECHNICAL MANUAL

APPENDIX: TECHNICAL INFORMATION

AT Thermistor

High precision thermistor

Appendix C

Features The AT Thermistor has a high precision thermistor with small

resistance and B constant error margin.

Using the AT Thermistor as a temperature sensor does not require

adjustment between a control circuit and the sensor; and the AT

Thermistor provides a temperature precision of ±0.3°C. As a

result, a high precision temperature control and temperature

display are possible.

•Error margins of resistance and temperature characteristics are

very small.

•Small age-based change and high reliability

•Low price

•High durability

Usage Air conditioners, fan heaters, FF heaters, refrigerators, water

heaters, boiler/kitchen appliances, copiers, printers, facsimiles,

automatic vending machines, agricultural equipment, automobiles

(for external temperature, internal temperature, air flow sensor),

portable thermometers, medical equipment, thermos-type contain-

ers, solar heating system, automatic toilet seats, fire alarms, home

automation

Type number 103 AT - 2External type

High precision AT Thermistor

Zero load resistance (25°C) 103: 10 kΩ

Resistance margin graph

Temperature precision

graph

-40

-30 -20 -10 0 10 20 30 405060708090100

Ambient temperature (°C)

Resistance margin (±%)

-40

0.5

1.0

1.5

2.0

2.5

-30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

±0.5°C

±0.7°C

±1°C

Ambient temperature (°C)

Temperature margin (±°C)

S1C60N05 TECHNICAL MANUAL EPSON 93

APPENDIX: TECHNICAL INFORMATION

Comparison between AT type and others

Ratings

Thermistor

AT type

Other type

R25 margin

±1%

±5%

B margin

±1%

±3%

Temperature margine

(25°C)

±0.3°C

±1.3°C

Temperature control (display) for

every 1°C

Circuit adhustment - not required

Circuit adjystment - required

Type

102AT-1

202AT-1

502AT-1

103AT-1

102AT-2

202AT-2

502AT-2

103AT-2, 3

203AT-2

103AT-4

R25

1 kΩ ±1%

2 kΩ ±1%

5 kΩ ±1%

10 kΩ ±1%

1 kΩ ±1%

2 kΩ ±1%

5 kΩ ±1%

10 kΩ ±1%

20 kΩ ±1%

10 kΩ ±1%

B constant

3100K ±1%

3182K ±1%

3324K ±1%

3435K ±1%

3100K ±1%

3182K ±1%

3324K ±1%

3435K ±1%

4013K ±1%

3435K ±1%

Thermal radiation

constant (mW/°C)

Approx. 3

Approx. 2

Thermal

constant (s)

Approx. 75

Approx. 15

Approx. 10

Maximum power

(mW) at 25°C

Temperature

range (°C)

-50 to 90

-50 to 105

-50 to 90

-50 to 110

-30 to 90

External dimension (AT-3, 4 in omission)

103AT

AT-1 AT-2

max. 15

max. φ5

600 5±1

max.3.5 max.2.4

2.54±0.25

0.7

max.4.0

8.5±1

17±1.5

+20

–0

Printed Taper cut

Color code

Epoxy resin

0.5° tinned 42 alloy

Color code :

Black :

Red :

Yellow :

White :

No color :

Type

102AT-2

202AT-2

502AT-2

103AT-2

203AT-2

Soldered

Thermistor

TPE resin TPE resin covered parallel line

φ0.18×12 core (0.3SQ) Black

Thermal response

63.2

95.0

86.5

100

0102030405060708090100

Time (s)

Temperature difference (%)

AT-2 (in the air)

AT-1 (in the air)

Board soldering method

8.5

Board

Proper usage example

Proper soldering conditions:

260°C, 10 seconds or less

2.54

94 EPSON S1C60N05 TECHNICAL MANUAL

APPENDIX: TECHNICAL INFORMATION

Resistance - Temperature characteristics

-50 to 29°C 30 to110°C

Temp

(°C)

-50

-49

-48

-47

-46

-45

-44

-43

-42

-41

-40

-39

-38

-37

-36

-35

-34

-33

-32

-31

-30

-29

-28

-27

-26

-25

-24

-23

-22

-21

-20

-19

-18

-17

-16

-15

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

Rmax (kΩ)

344.4

324.7

306.4

289.2

273.2

258.1

244.0

230.8

218.5

206.8

195.9

185.4

175.5

166.2

157.5

149.3

141.6

134.4

127.6

121.2

115.1

109.3

103.8

98.63

93.75

89.15

84.82

80.72

76.85

73.20

69.74

66.42

63.27

60.30

57.49

54.83

52.31

49.93

47.67

45.53

43.50

41.54

39.68

37.91

36.24

34.65

33.14

31.71

30.35

29.06

27.83

26.64

25.51

24.44

23.42

22.45

21.52

20.64

19.80

19.00

18.24

17.51

16.80

16.13

15.50

14.89

14.31

13.75

13.22

12.72

12.23

11.77

11.32

10.90

10.49

10.10

9.732

9.381

9.044

8.721

Rst (kΩ)

329.2

310.7

293.3

277.0

261.8

247.5

234.1

221.6

209.8

198.7

188.4

178.3

168.9

160.1

151.8

144.0

136.6

129.7

123.2

117.1

111.3

105.7

100.4

95.47

90.80

86.39

82.22

78.29

74.58

71.07

67.74

64.54

61.52

58.66

55.95

53.39

50.96

48.66

46.48

44.41

42.45

40.56

38.76

37.05

35.43

33.89

32.43

31.04

29.72

28.47

27.28

26.13

25.03

23.99

22.99

22.05

21.15

20.29

19.48

18.70

17.96

17.24

16.55

15.90

15.28

14.68

14.12

13.57

13.06

12.56

12.09

11.63

11.20

10.78

10.38

10.00

9.632

9.281

8.944

8.622

Rmin (kΩ)

314.7

297.2

280.7

265.3

250.8

237.3

224.6

212.7

201.5

191.0

181.1

171.5

162.6

154.2

146.2

138.8

131.8

125.2

118.9

113.1

107.5

102.2

97.16

92.41

87.93

83.70

79.71

75.93

72.36

68.99

65.80

62.72

59.81

57.05

54.44

51.97

49.63

47.42

45.31

43.32

41.43

39.59

37.85

36.20

34.63

33.14

31.73

30.39

29.11

27.89

26.74

25.62

24.55

23.54

22.57

21.66

20.78

19.95

19.15

18.40

17.67

16.97

16.31

15.67

15.06

14.48

13.93

13.40

12.89

12.41

11.95

11.50

11.07

10.66

10.27

9.900

9.533

9.181

8.845

8.523

103AT

Temp

(°C)

100

101

102

103

104

105

106

107

108

109

Rmax (kΩ)

8.412

8.113

7.826

7.551

7.288

7.036

6.793

6.561

6.338

6.124

5.918

5.719

5.527

5.343

5.166

4.996

4.833

4.676

4.525

4.380

4.240

4.104

3.973

3.847

3.726

3.609

3.497

3.389

3.285

3.184

3.088

2.994

2.903

2.816

2.732

2.650

2.572

2.496

2.423

2.353

2.285

2.219

2.155

2.093

2.034

1.976

1.920

1.866

1.814

1.764

1.716

1.668

1.623

1.578

1.536

1.494

4.454

1.415

1.378

1.341

1.306

1.271

1.238

1.206

1.175

1.144

1.115

1.087

1.059

1.032

1.006

0.9812

0.9567

0.9330

0.9100

0.8877

0.8660

0.8456

0.8245

0.8047

Rst (kΩ)

8.313

8.015

7.729

7.455

7.192

6.941

6.699

6.468

6.246

6.033

5.828

5.630

5.439

5.256

5.080

4.912

4.749

4.594

4.444

4.300

4.161

4.026

3.897

3.772

3.652

3.537

3.426

3.319

3.216

3.116

3.021

2.928

2.838

2.752

2.669

2.589

2.512

2.437

2.365

2.296

2.229

2.163

2.101

2.040

1.981

1.924

1.870

1.817

1.766

1.716

1.669

1.622

1.577

1.534

1.492

1.451

1.412

1.374

1.337

1.301

1.266

1.233

1.200

1.169

1.138

1.108

1.080

1.052

1.025

0.9988

0.9735

0.9489

0.9250

0.9018

0.8793

0.8575

0.8364

0.8159

0.7960

0.7767

Rmin (kΩ)

8.215

7.917

7.632

7.359

7.097

6.846

6.606

6.375

6.154

5.942

5.739

5.541

5.352

5.170

4.996

4.828

4.667

4.512

4.364

4.221

4.084

3.950

3.822

3.698

3.579

3.465

3.355

3.249

3.148

3.049

2.955

2.863

2.775

2.690

2.608

2.529

2.452

2.379

2.308

2.240

2.174

2.109

2.047

1.987

1.930

1.874

1.820

1.768

1.718

1.669

1.622

1.577

1.533

1.490

1.449

1.409

1.371

1.333

1.297

1.262

1.228

1.195

1.163

1.132

1.102

1.073

1.045

1.018

0.9918

0.9663

0.9416

0.9175

0.8942

0.8716

0.8496

0.8284

0.8077

0.7877

0.7683

0.7495

103AT

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Technical Manual

S1C60N05

First issue September, 1998

Printed January, 2004 in Japan A

Document code: 404492803