1
LTC1064-7
10647fb
Linear Phase, 8th Order
Lowpass Filter
■
Steeper Roll-Off Than 8th Order Bessel Filters
■
f
CUTOFF
up to 100kHz
■
Phase Equalized Filter in 14-Pin Package
■
Phase and Group Delay Response Fully Tested
■
Transient Response Exhibits 5% Overshoot and
No Ringing
■
Wide Dynamic Range
■
72dB THD or Better Throughout a 50kHz Passband
■
No External Components Needed
■
Available in 14-Pin DIP and 16-Pin SO Wide
Packages
The LTC
®
1064-7 is a clock-tunable monolithic 8th order
lowpass filter with linear passband phase and flat group
delay. The amplitude response approximates a maximally
flat passband while it exhibits steeper roll-off than an
equivalent 8th order Bessel filter. For instance, at twice the
cutoff frequency the filter attains 34dB attenuation (vs
12dB for Bessel), while at three times the cutoff frequency,
the filter attains 68dB attenuation (vs 30dB for Bessel).
The cutoff frequency of the LTC1064-7 is tuned via an
external TTL or CMOS clock.
The LTC1064-7 features wide dynamic range. With single
5V supply, the S/N + THD is 76dB. Optimum 92dB S/N is
obtained with ±7.5V supplies.
The clock-to-cutoff frequency ratio of the LTC1064-7 can
be set to 50:1 (Pin 10 to V
+
) or 100:1 (Pin 10 to V
–
).
When the filter operates at clock-to-cutoff frequency ratio
of 50:1, the input is double-sampled to lower the risk of
aliasing.
The LTC1064-7 is pin-compatible with the LTC1064-X
series, LTC1164-7 and LTC1264-7.
■
Data Communication Filters
■
Time Delay Networks
■
Phase-Matched Filters
80kHz Linear Phase Lowpass Filter
Eye Diagram
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LTC1064-7
VIN
7.5V
–7.5V
CLK = 4MHz
7.5V
VOUT
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
PIN AND THE fCLK LINE.
1064-7 TA01
1V/DIV
1064-7 TA02
1µs/DIV
V
S
= ±7.5V
f
CLK
= 4MHz
RATIO = 50:1
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1064-7
10647fb
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
Total Supply Voltage (V
+
to V
–
) .......................... 16.5V
Power Dissipation............................................. 400mW
Burn-In Voltage ................................................... 16.5V
Voltage at Any Input ..... (V
–
– 0.3V) ≤ V
IN
≤ (V
+
+ 0.3V)
Storage Temperature Range ................ – 65°C to 150°C
Operating Temperature Range
LTC1064-7C ....................................... – 40°C to 85°C
LTC1064-7M OBSOLETE .............. –55°C to 125°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ELECTRICAL C CHARA TERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.VS = ±7.5V, RL = 10k, TA = 25°C, fCUTOFF = 10kHz or 20kHz, fCLK = 1MHz,
TTL or CMOS level (maximum clock rise and fall time ≤ 1µs) and all gain measurements are referenced to passband gain, unless
otherwise specified. The filter cutoff frequency is abbreviated as fCUTOFF or fC.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Passband Gain 0.1Hz ≤ f ≤ 0.25 f
CUTOFF
f
TEST
= 5kHz, (f
CLK
/f
C
) = 50:1 ●– 0.60 0.10 0.65 dB
Gain at 0.5 f
CUTOFF
f
TEST
= 10kHz, (f
CLK
/f
C
) = 50:1 ●– 0.90 – 0.35 0.15 dB
f
TEST
= 5kHz, (f
CLK
/f
C
) = 100:1 ●– 1.30 – 0.35 1.25 dB
Gain at 0.75 f
CUTOFF
f
TEST
= 15kHz, (f
CLK
/f
C
) = 50:1 ●– 2.0 –1.0 – 0.35 dB
Gain at f
CUTOFF
f
TEST
= 20kHz, (f
CLK
/f
C
) = 50:1 ●– 4.50 – 3.4 – 2.50 dB
f
TEST
= 10kHz, (f
CLK
/f
C
) = 100:1 ●– 5.75 – 4.5 – 3.75 dB
Gain at 2 f
CUTOFF
f
TEST
= 40kHz, (f
CLK
/f
C
) = 50:1 ●– 36.5 – 34.0 – 31.75 dB
f
TEST
= 20kHz, (f
CLK
/f
C
) = 100:1 ●– 37.0 – 34.5 – 31.75 dB
Gain with f
CLK
= 20kHz f
TEST
= 200Hz, (f
CLK
/f
C
) = 100:1 – 6.5 – 4.3 – 3.5 dB
Gain with f
CLK
= 400kHz, V
S
= ±2.375V f
TEST
= 4kHz, (f
CLK
/f
C
) = 50:1 – 0.9 – 0.3 0.25 dB
f
TEST
= 8kHz, (f
CLK
/f
C
) = 50:1 – 4.5 – 3.3 – 2.00 dB
Phase Factor (
F
) 0.1Hz ≤ f ≤ f
CUTOFF
Phase = 180° –
F
(f/f
C
) (f
CLK
/f
C
) = 50:1 430 ± 2.0 Deg
(Note 2) (f
CLK
/f
C
) = 100:1 421 ± 2.5 Deg
(f
CLK
/f
C
) = 50:1 ●422 430 437 Deg
(f
CLK
/f
C
) = 100:1 ●414 421 429 Deg
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
LTC1064-7CN
LTC1064-7CJ
LTC1064-7MJ
ORDER PART
NUMBER
LTC1064-7CSW
TJMAX = 110°C, θJA = 85°C/W
TJMAX = 110°C, θJA = 65°C/W (N)
TOP VIEW
SW PACKAGE
16-LEAD PLASTIC SO (WIDE)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
V
IN
GND
V
+
GND
NC
LP (A)
INV
(A)
R
IN
(A)
NC
V
–
NC
f
CLK
50/100
NC
V
OUT
(Note 1)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consider the N Package as an Alternate Source
1
2
3
4
5
6
7
TOP VIEW
N PACKAGE
14-LEAD PLASTIC DIP
14
13
12
11
10
9
8
NC
V
IN
GND
V
+
GND
LP (A)
INV
(A)
R
IN
(A)
NC
V
–
f
CLK
50/100
V
OUT
NC
TJMAX = 150°C, θJA = 65°C/W (J)
J PACKAGE 14-LEAD CERAMIC DIP
OBSOLETE PACKAGE
3
LTC1064-7
10647fb
ELECTRICAL C CHARA TERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Phase Nonlinearity (f
CLK
/f
C
) = 50:1 ±1.0 %
(Notes 2, 4) (f
CLK
/f
C
) = 100:1 ±1.0 %
(f
CLK
/f
C
) = 50:1 ●±2.0 %
(f
CLK
/f
C
) = 100:1 ●±2.0 %
Group Delay (t
d
)(f
CLK
/f
C
) = 50:1, f ≤ f
CUTOFF
59.7 ± 0.5 µs
t
d
= (
F
/360)(1/f
C
)(f
CLK
/f
C
) = 100:1, f ≤ f
CUTOFF
117.0 ± 1.0 µs
(Note 3) (f
CLK
/f
C
) = 50:1, f ≤ f
CUTOFF
● 58.6 59.7 60.7 µs
(f
CLK
/f
C
) = 100:1, f ≤ f
CUTOFF
●115.0 117.0 119.0 µs
Group Delay Deviation (f
CLK
/f
C
) = 50:1, f ≤ f
CUTOFF
±1.0 %
(Notes 3, 4) (f
CLK
/f
C
) = 100:1, f ≤ f
CUTOFF
±1.0 %
(f
CLK
/f
C
) = 50:1, f ≤ f
CUTOFF
●±2.0 %
(f
CLK
/f
C
) = 100:1, f ≤ f
CUTOFF
●±2.0 %
Input Frequency Range (Table 9) (f
CLK
/f
C
) = 50:1 <f
CLK
kHz
(f
CLK
/f
C
) = 100:1 <f
CLK
/2 kHz
Maximum f
CLK
V
S
= 5V (AGND = 2V) 2.0 MHz
V
S
= ±5V 3.5 MHz
V
S
= ±7.5V 5.0 MHz
Clock Feedthrough (f ≥ f
CLK
) 50:1 200 µV
RMS
Wideband Noise V
S
= ±2.5V 95 ± 5% µV
RMS
(1Hz ≤ f ≤ f
CLK
)V
S
= ±5V 105 ± 5% µV
RMS
V
S
= ±7.5V 115 ± 5% µV
RMS
Input Impedance 25 40 70 kΩ
Output DC Voltage Swing V
S
= ±2.375V ±1.0 ±1.2 V
(Note 5) V
S
= ±5V ●±2.1 ±3.2 V
V
S
= ±7.5V ●±3.0 ±5.0 V
Output DC Offset 50:1, V
S
= ±5V ±150 ±220 mV
100:1, V
S
= ±5V ±150 mV
Output DC Offset TempCo 50:1, V
S
= ±5V ±200 µV/°C
100:1, V
S
= ±5V ±200 µV/°C
Power Supply Current V
S
= ±2.375V, T
A
= 25°C1122mA
●22 mA
V
S
= ±5V, T
A
= 25°C1426mA
●28 mA
V
S
= ±7.5V, T
A
= 25°C1728mA
●32 mA
Power Supply Range ±2.375 ±8V
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±7.5V, RL = 10k, fCUTOFF = 10kHz or 20kHz, fCLK = 1MHz, TTL or
CMOS level (maximum clock rise and fall time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise
specified. The filter cutoff frequency is abbreviated as fCUTOFF or fC.
4
LTC1064-7
10647fb
Figure 1. Phase Response in the Passband (Note 2)
FREQUENCY (kHz)
0
–360
PHASE (DEG)
–270
–180
–90
0
90
180
4 8 12 16
1164-7 F01
202 6 10 14 18
f
CLK
= 1MHz
RATIO = 50:1
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input frequencies, f, are linearly phase shifted through the filter as
long as f ≤ f
C
; f
C
= cutoff frequency.
Figure 1 curve shows the typical phase response of an LTC1064-7
operating at f
CLK
= 1MHz, ratio = 50:1, f
C
= 20kHz and it closely matches
an ideal straight line. The phase shift is described by: phase shift =
180° –
F
(f/f
C
); f ≤ f
C
.
F
is arbitrarily called the “phase factor” expressed in degrees. The phase
factor allows the calculation of the phase at a given frequency.
Example: The phase shift at 14kHz of the LTC1064-7 shown in Figure 1 is:
phase shift = 180° – 430° (14kHz/20kHz) ± nonlinearity = –121° ± 1% or
–121°± 1.20°.
Note 3: Group delay and group delay deviation are calculated from the
measured phase factor and phase deviation specifications.
Note 4: Phase deviation and group delay deviation for LTC1064-7MJ is
±4%.
Note 5: The AC swing is typically 11V
P-P
, 7V
P-P
, 2.8V
P-P
, with ±7.5V, ±5V,
±2.5V Supply respectively. For more information refer to the THD + Noise
vs Input graphs.
ELECTRICAL CHARACTERISTICS
5
LTC1064-7
10647fb
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Phase Factor vs fCLK
(Typical Unit)
Passband Gain and Phase
Gain vs Frequency
Phase Factor vs fCLK (Min and
Max Representative Units)
Phase Factor vs fCLK (Min and
Max Representative Units)
Passband Gain and Phase
FREQUENCY (kHz)
0.1
–50
GAIN (dB)
–40
–30
–20
–10
1 10 100
1064-7 G01
–60
–70
–90
0
–80
10
–100
–110
50:1
100:1
V
S
= ±5V
f
CLK
= 1MHz
T
A
= 25°C
fCLK (MHz)
0.5
435
PHASE FACTOR
425
455
465
485
1064-7 G02
445
475
2.0 3.5
1.0 2.5 3.0
415
1.5
VS = ±5V
(fCLK/fC) = 50:1
70°C
25°C
0°C
fCLK (MHz)
0.5
435
PHASE FACTOR
425
455
465
485
1064-7 G03
445
475
2.0 3.5
1.0 2.5 3.0
415
1.5
25°C
70°C
0°C
VS = ±5V
(fCLK/fC) = 100:1
Phase Factor vs fCLK
(Typical Unit)
fCLK (MHz)
0.5
435
PHASE FACTOR
430
440
1064-7 G05
445
2.0
1.5
420
1.0
425
VS = 5V
TA = 25°C
PINS 3, 5 AT 2V
(fCLK/fC) = 50:1
f
CLK
(MHz)
0.5
435
PHASE FACTOR
430
440
1064-7 G04
445
2.0 3.5
1.0 2.5 3.0
420
1.5
V
S
= ±5V
T
A
= 25°C
(f
CLK
/f
C
) = 50:1
425
FREQUENCY (kHz)
4
GAIN (dB)
–1
0
20
1064-7 G06
–3
–5
612 16
PHASE (DEG)
2
3
2
1
–2
–4
–6
180
120
60
0
–60
–120
–180
–240
–300
–360
810141822
VS = ±5V
fCLK = 1MHz
(fCLK/fC) = 50:1
PHASE
GAIN
FREQUENCY (kHz)
4
GAIN (dB)
–1
0
20
1064-7 G07
–3
–5
612 16
PHASE (DEG)
2
3
2
1
–2
–4
–6
180
120
60
0
–60
–120
–180
–240
–300
–360
810141822
VS = ±5V
fCLK = 2MHz
(fCLK/fC) = 100:1
PHASE
GAIN
6
LTC1064-7
10647fb
THD + Noise vs Frequency
Delay vs Frequency and fCLK
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Delay vs Frequency and fCLK THD + Noise vs Frequency
FREQUENCY (kHz)
1
0
DELAY (µs)
50
100
150
200
250
61621
1064-7 G14
3611 26 31
A
D
B
C
V
S
= ±5V
T
A
= 25°C
(f
CLK
/f
C
) = 100:1
A. f
CLK
= 0.5MHz
B. f
CLK
= 1.5MHz
C. f
CLK
= 2.5MHz
D. f
CLK
= 3.5MHz
FREQUENCY (kHz)
1
–90
THD + NOISE (dB)
–80
–70
–60
–50
10
1064-7 G15
–85
–75
–65
–55
–45 V
S
= ±7.5V
V
IN
= 2V
RMS
f
CLK
= 1MHz
(f
CLK
/f
C
) = 50:1
(100k RESISTOR
PIN 9 TO V
–
)
–40
20
FREQUENCY (kHz)
11050
1064-7 G16
–90
THD + NOISE (dB)
–80
–50
–70
–65
–55
–40
–45
–60
–75
–85
V
S
= ±7.5V
V
IN
= 1V
RMS
f
CLK
= 2.5MHz
(f
CLK
/f
C
) = 50:1
(100k RESISTOR
PIN 9 TO V
–
)
FREQUENCY (kHz)
2
0
DELAY (µs)
25
50
75
100
125
12 32 42
1064-7 G13
7222 52 62
A
D
B
C
V
S
= ±5V
T
A
= 25°C
(f
CLK
/f
C
) = 50:1
A. f
CLK
= 0.5MHz
B. f
CLK
= 1.5MHz
C. f
CLK
= 2.5MHz
D. f
CLK
= 3.5MHz
FREQUENCY (kHz)
1
–5
GAIN (dB)
–3
–1
1
3
10 100
1064-7 G12
–4
–2
0
2
4V
S
= SINGLE 5V
(f
CLK
/f
C
) = 50:1
5
A. f
CLK
= 0.5MHz
B. f
CLK
= 1.0MHz
C. f
CLK
= 1.5MHz
D. f
CLK
= 2.0MHz
D
ABC
FREQUENCY (kHz)
1
–5
GAIN (dB)
–3
–1
1
3
10 100
1064-7 G11
–4
–2
0
2
4VS = SINGLE 5V
TA = 25°C
(fCLK/fC) = 50:1
5
A. f
CLK
= 0.5MHz
B. f
CLK
= 1.0MHz
C. f
CLK
= 1.5MHz
D. f
CLK
= 2.0MHz
DC
AB
FREQUENCY (kHz)
10
–5
GAIN (dB)
–3
–1
1
3
100 1000
1064-7 G08
–4
–2
0
2
4
E
5
10
C
A
D
A. f
CLK
= 1MHz
B. f
CLK
= 2MHz
C. f
CLK
= 3MHz
D. f
CLK
= 4MHz
E. f
CLK
= 5MHz
V
S
= ±7.5V
T
A
= 25°C
(f
CLK
/f
C
) = 50:1
B
FREQUENCY (kHz)
1
–5
GAIN (dB)
–3
–1
1
3
100 1000
1064-7 G09
–4
–2
0
2
4
E
5
10
C
A
D
A. f
CLK
= 1MHz
B. f
CLK
= 2MHz
C. f
CLK
= 3MHz
D. f
CLK
= 4MHz
E. f
CLK
= 5MHz
VS = ±7.5V
(fCLK/fC) = 50:1
B
FREQUENCY (kHz)
1
–5
GAIN (dB)
–3
–1
1
3
10 100
1064-7 G10
–4
–2
0
2
4V
S
= ±5V
(f
CLK
/f
C
) = 50:1
5
A. f
CLK
= 0.5MHz
B. f
CLK
= 1.5MHz
C. f
CLK
= 2.5MHz
D. f
CLK
= 3.5MHz
DC
AB
Passband Gain vs Frequency
and fCLK
Passband Gain vs Frequency and
fCLK at TA = 85°C
Passband Gain vs Frequency and
fCLK at TA = 85°C
Passband Gain vs Frequency and
fCLK at TA = 85°C
Passband Gain vs Frequency
and fCLK
7
LTC1064-7
10647fb
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
THD + Noise vs Frequency
THD + Noise vs Input Phase Matching vs Frequency
TOTAL POWER SUPPLY VOLTAGE (V)
0
POWER SUPPLY CURRENT (mA)
48
44
40
36
32
28
24
20
16
12
8
4
0
2 6 12 16
1064-7 G25
204 8 10 14 18 22 24
–55°C
25°C
125°C
f
CLK
= 1MHz
FREQUENCY (f
CUTOFF
/FREQUENCY)
0
PHASE DIFFERENCE (DEG)
3
4
5
0.8
1064-7 G24
2
1
00.2 0.4 0.6 1.0
PHASE DIFFERENCE BETWEEN
ANY TWO UNITS (SAMPLE OF
50 REPRESENTATIVE UNITS)
V
S
≥ ±5V
f
CLK
≤ 2.5MHz
(f
CLK
/f
C
) = 50:1 OR 100:1
T
A
= 0°C TO 70°C
INPUT (V
RMS
)
0.1
–90
THD + NOISE (dB)
–80
–70
–60
–50
1
1064-7 G23
–85
–75
–65
–55
–45 V
S
= SINGLE 5V
f
IN
= 1kHz
f
CLK
= 500kHz
(f
CLK
/f
C
) = 100:1
–40
2
B
A. PINS 3, 5 AT 2V
B. PINS 3, 5 AT 2.5V
A
INPUT (V
RMS
)
0.1 1 5
1064-7 G20
–90
THD + NOISE (dB)
–80
–50
–70
–65
–55
–40
–45
–60
–75
–85
f
IN
= 1kHz
f
CLK
= 1MHz
(f
CLK
/f
C
) = 50:1
(100k PIN 9
TO V
–
)
AB
A. V
S
= ±5V
B. V
S
= ±7.5V
INPUT (V
RMS
)
0.1 1 5
1064-7 G21
–90
THD + NOISE (dB)
–80
–50
–70
–65
–55
–40
–45
–60
–75
–85
f
IN
= 1kHz
f
CLK
= 2MHz
(f
CLK
/f
C
) = 100:1
AB
A. V
S
= ±5V
B. V
S
= ±7.5V
INPUT (V
RMS
)
0.1
–90
THD + NOISE (dB)
–80
–70
–60
–50
1
1064-7 G22
–85
–75
–65
–55
–45 V
S
= SINGLE 5V
f
IN
= 1kHz
f
CLK
= 1MHz
(f
CLK
/f
C
) = 50:1
–40
2
B
A. PINS 3, 5 AT 2V
B. PINS 3, 5 AT 2.5V
A
THD + Noise vs InputTHD + Noise vs InputTHD + Noise vs Input
Power Supply Current vs
Power Supply Voltage
THD + Noise vs FrequencyTHD + Noise vs Frequency
FREQUENCY (kHz)
1
–90
THD + NOISE (dB)
–80
–70
–60
–50
10
1064-7 G17
–85
–75
–65
–55
–45 V
S
= ±5V
V
IN
= 1V
RMS
f
CLK
= 1MHz
(f
CLK
/f
C
) = 50:1
(100k RESISTOR
PIN 9 TO V
–
)
–40
20
FREQUENCY (kHz)
1
–90
THD + NOISE (dB)
–80
–70
–60
–50
10
1064-7 G18
–85
–75
–65
–55
–45 V
S
= SINGLE 5V
V
IN
= 0.5V
RMS
f
CLK
= 1MHz
(f
CLK
/f
C
) = 50:1
(PINS 3, 5 AT 2V)
–40
20
FREQUENCY (kHz)
1
THD + NOISE (dB)
25
1064-7 G19
34
–90
–80
–45
–75
–65
–55
–40
–50
–60
–70
–85
V
S
= SINGLE 5V
V
IN
= 0.5V
RMS
f
CLK
= 500kHz
(f
CLK
/f
C
) = 100:1
(PINS 3, 5 AT 2V)
8
LTC1064-7
10647fb
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Table 2. Passband Gain and Phase
VS = ±7.5V, (fCLK /fC) = 100:1, TA = 25°C
FREQUENCY (kHz) GAIN (dB) PHASE (DEG)
f
CLK
= 1MHz (Typical Unit)
0.000 – 0.203 180.00
2.500 – 0.203 74.07
5.000 – 0.741 – 31.71
7.500 – 1.831 – 136.47
10.000 – 4.451 – 240.17
f
CLK
= 2MHz (Typical Unit)
0.000 – 0.152 180.00
5.000 – 0.152 73.79
10.000 – 0.575 – 32.47
15.000 – 1.501 – 138.11
20.000 – 3.973 – 243.84
f
CLK
= 3MHz (Typical Unit)
0.000 – 0.123 180.00
7.500 – 0.123 73.32
15.000 – 0.481 – 33.64
22.500 – 1.312 – 140.14
30.000 – 3.654 – 247.11
Table 1. Passband Gain and Phase
VS = ±7.5V, (fCLK /fC) = 50:1, TA = 25°C
FREQUENCY (kHz) GAIN (dB) PHASE (DEG)
f
CLK
= 1MHz (Typical Unit)
0.000 – 0.086 180.00
5.000 – 0.086 73.54
10.000 – 0.334 –33.60
15.000 – 1.051 –140.81
20.000 – 3.316 – 249.30
f
CLK
= 2MHz (Typical Unit)
0.000 – 0.131 180.00
10.000 – 0.131 72.88
20.000 – 0.442 – 34.71
30.000 – 1.108 –141.99
40.000 – 3.115 – 250.45
f
CLK
= 3MHz (Typical Unit)
0.000 – 0.156 180.00
15.000 – 0.156 72.54
30.000 – 0.459 – 35.01
45.000 – 0.941 –141.95
60.000 – 2.508 – 250.53
f
CLK
= 4MHz (Typical Unit)
0.000 – 0.121 180.00
20.000 – 0.121 72.12
40.000 – 0.292 – 35.75
60.000 – 0.476 –142.92
80.000 – 1.539 – 252.63
f
CLK
= 5MHz (Typical Unit)
0.000 – 0.045 180.00
25.000 – 0.045 70.85
50.000 – 0.006 – 38.25
75.000 0.185 –146.77
100.000 – 0.356 – 259.27
FREQUENCY (kHz) GAIN (dB) PHASE (DEG)
f
CLK
= 4MHz (Typical Unit)
0.000 – 0.116 180.00
10.000 – 0.116 72.49
20.000 – 0.436 – 35.21
30.000 – 1.171 – 142.33
40.000 – 3.353 – 250.12
f
CLK
= 5MHz (Typical Unit)
0.000 – 0.097 180.00
12.500 – 0.097 71.00
25.000 – 0.351 – 38.08
37.500 – 0.951 – 146.51
50.000 – 2.999 – 256.13
Table 3. Passband Gain and Phase
VS = ±5V, (fCLK /fC) = 50:1, TA = 25°C
FREQUENCY (kHz) GAIN (dB) PHASE (DEG)
f
CLK
= 0.5MHz (Typical Unit)
0.000 – 0.081 180.00
2.500 – 0.081 73.71
5.000 – 0.345 – 33.31
7.500 – 1.063 – 140.36
10.000 – 3.283 – 248.52
f
CLK
= 1MHz (Typical Unit)
0.000 – 0.071 180.00
5.000 – 0.071 73.44
10.000 – 0.322 – 33.83
15.000 – 1.036 – 141.13
20.000 – 3.284 – 249.68
f
CLK
= 1.5MHz (Typical Unit)
0.000 – 0.095 180.00
7.500 – 0.095 73.03
15.000 – 0.392 – 34.53
22.500 – 1.075 – 141.89
30.000 – 3.155 – 250.45
f
CLK
= 2MHz (Typical Unit)
0.000 – 0.127 180.00
10.000 – 0.127 72.81
20.000 – 0.447 – 34.70
30.000 – 1.041 – 141.77
40.000 – 2.856 – 250.24
f
CLK
= 2.5MHz (Typical Unit)
0.000 – 0.126 180.00
12.500 – 0.126 72.61
25.000 – 0.411 – 34.91
37.500 – 0.864 – 141.88
50.000 – 2.397 – 250.62
f
CLK
= 3MHz (Typical Unit)
0.000 – 0.102 180.00
15.000 – 0.102 72.23
30.000 – 0.292 – 35.64
45.000 – 0.546 – 142.96
60.000 – 1.769 – 252.73
9
LTC1064-7
10647fb
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Table 5. Passband Gain and Phase
VS = Single 5V, (fCLK/f
C) = 50:1, TA = 25°C
FREQUENCY (kHz) GAIN (dB) PHASE (DEG)
f
CLK
= 0.5MHz (Typical Unit)
0.000 – 0.134 180.00
2.500 – 0.134 73.52
5.000 – 0.391 – 33.67
7.500 – 1.109 – 140.92
10.000 – 3.351 – 249.32
f
CLK
= 1MHz (Typical Unit)
0.000 – 0.148 180.00
5.000 – 0.148 73.07
10.000 – 0.423 – 34.63
15.000 – 1.111 – 142.25
20.000 – 3.241 – 251.03
f
CLK
= 1.5MHz (Typical Unit)
0.000 – 0.157 180.00
7.500 – 0.157 72.73
15.000 – 0.456 – 34.83
22.500 – 0.981 – 142.08
30.000 – 2.687 – 251.09
f
CLK
= 2MHz (Typical Unit)
0.000 – 0.188 180.00
10.000 – 0.188 71.37
20.000 – 0.304 – 37.52
30.000 – 0.513 – 146.11
40.000 – 1.824 – 257.46
Table 4. Passband Gain and Phase
VS = ±5V, (fCLK /fC) = 100:1, TA = 25°C
FREQUENCY (kHz) GAIN (dB) PHASE (DEG)
f
CLK
= 0.5MHz (Typical Unit)
0.000 – 0.186 180.00
1.250 – 0.186 74.10
2.500 – 0.726 – 31.65
3.750 – 1.805 – 136.48
5.000 – 4.402 – 240.33
f
CLK
= 1MHz (Typical Unit)
0.000 – 0.184 180.00
2.500 – 0.184 74.02
5.000 – 0.712 – 31.80
7.500 – 1.785 – 136.61
10.000 – 4.387 – 240.43
f
CLK
= 1.5MHz (Typical Unit)
0.000 – 0.145 180.00
3.750 – 0.145 73.84
7.500 – 0.596 – 32.32
11.250 – 1.556 – 137.73
15.000 – 4.047 – 242.95
f
CLK
= 2MHz (Typical Unit)
0.000 – 0.116 180.00
5.000 – 0.116 73.64
10.000 – 0.494 – 32.93
15.000 – 1.361 – 139.03
20.000 – 3.761 – 245.57
f
CLK
= 2.5MHz (Typical Unit)
0.000 – 0.101 180.00
6.250 – 0.101 73.17
12.500 – 0.452 – 33.93
18.750 – 1.273 – 140.58
25.000 – 3.611 – 247.80
f
CLK
= 3MHz (Typical Unit)
0.000 – 0.105 180.00
7.500 – 0.105 72.36
15.000 – 0.445 – 35.47
22.500 – 1.228 – 142.70
30.000 – 3.509 – 250.58
f
CLK
= 3.5MHzMHz (Typical Unit)
0.000 – 0.104 180.00
8.750 – 0.104 70.81
17.500 – 0.437 – 38.39
26.250 – 1.188 – 146.85
35.000 – 3.478 – 256.10
Table 3. Passband Gain and Phase
VS = ±5V, (fCLK /fC) = 50:1, TA = 25°C
FREQUENCY (kHz) GAIN (dB) PHASE (DEG)
f
CLK
= 3.5MHz (Typical Unit)
0.000 – 0.054 180.00
17.500 – 0.054 71.07
35.000 – 0.108 – 38.00
52.500 – 0.137 – 146.68
70.000 – 1.104 – 258.97
Table 6. Passband Gain and Phase
VS = Single 5V, (fCLK/f
C) = 100:1, TA = 25°C
FREQUENCY (kHz) GAIN (dB) PHASE (DEG)
f
CLK
= 0.5MHz (Typical Unit)
0.000 – 0.243 180.00
1.250 – 0.243 73.91
2.500 – 0.776 – 31.98
3.750 – 1.861 – 136.98
5.000 – 4.483 – 240.90
f
CLK
= 1MHz (Typical Unit)
0.000 – 0.208 180.00
2.500 – 0.208 73.76
5.000 – 0.678 – 32.47
7.500 – 1.679 – 137.87
10.000 – 4.221 – 242.65
f
CLK
= 1.5MHz (Typical Unit)
0.000 – 0.115 180.00
3.750 – 0.115 73.26
7.500 – 0.473 – 33.73
11.250 – 1.314 – 140.40
15.000 – 3.715 – 247.66
f
CLK
= 2MHz (Typical Unit)
0.000 – 0.209 180.00
5.000 – 0.209 71.18
10.000 – 0.499 – 37.85
15.000 – 1.281 – 146.27
20.000 – 3.695 – 255.38
10
LTC1064-7
10647fb
PI FU CTIO S
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Power Supply Pins (4, 12)
The V
+
(Pin 4) and the V
–
(Pin 12) should be bypassed with
a 0.1µF capacitor to an adequate analog ground. The
filter’s power supplies should be isolated from other
digital or high voltage analog supplies. A low noise linear
supply is recommended. Using a switching power supply
will lower the signal-to-noise ratio of the filter. The supply
during power-up should have a slew rate less than 1V/µs.
When V
+
is applied before V
–
and V
–
is allowed to go
above ground, a signal diode should clamp V
–
to prevent
latch-up. Figures 2 and 3 show typical connections for
dual and single supply operation.
Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 50:1
Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 50:1
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 7 shows the clock’s low and high
level threshold values for a dual or single supply operation.
A pulse generator can be used as a clock source provided
the high level ON time is greater than 0.1µs. Sine waves are
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤ 1µs). The clock signal should be routed from the
right side of the IC package and perpendicular to it to avoid
coupling to any input or output analog signal path. A 200Ω
resistor between clock source and pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 2 and 3).
Table 7. Clock Source High and Low Threshold Levels
POWER SUPPLY HIGH LEVEL LOW LEVEL
Dual Supply = ±7.5V ≥ 2.18V ≤ 0.5V
Dual Supply = ±5V ≥ 1.45V ≤ 0.5V
Dual Supply = ±2.5V ≥ 0.73V ≤– 2.0V
Single Supply = 12V ≥ 7.80V ≤ 6.5V
Single Suppl = 5V ≥ 1.45V ≤ 0.5V
Analog Ground Pins (3, 5)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, Pin 3 should be connected to the analog
ground plane. For single supply operation pin 3 should be
biased at 1/2 supply and should be bypassed to the analog
ground plane with at least a 1µF capacitor (Figure 3). For
single 5V operation at the highest f
CLK
of 2MHz, Pin 3
should be biased at 2V. This minimizes passband gain and
phase variations.
Ratio Input Pin (10)
The DC level at this pin determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10 at V
+
gives a 50:1 ratio and Pin 10 at V
–
gives a 100:1 ratio. For
single supply operation the ratio is 50:1 when Pin 10 is at
V
+
and 100:1 when Pin 10 is at ground. When Pin 10 is not
tied to ground, it should be bypassed to analog ground
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
IN
V
+
200Ω
V
–
V
OUT
LTC1064-7
DIGITAL SUPPLY
+
GND
CLOCK SOURCE
1064-7 F02
0.1µF
0.1µF
V
+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
IN
V
+
200Ω
V
OUT
DIGITAL SUPPLY
+
GND
CLOCK SOURCE
1064-7 F03
+
LTC1064-7
0.1µF
1µF
10k
10k
V
+
11
LTC1064-7
10647fb
PI FU CTIO S
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External Connection Pins (7, 14)
Pins 7 and 14 should be connected together. In a printed
circuit board the connection should be done under the IC
package through a short trace surrounded by the analog
ground plane.
NC Pins (1, 5, 8, 13)
Pins 1, 5, 8 and 13 are not connected to any internal circuit
point on the device and should preferably be tied to analog
ground.
Figure 4. Buffer for Filter Output
1k
1064-7 F04
–
+
LT1220
with a 0.1µF capacitor. If the DC level at Pin 10 is switched
mechanically or electrically at slew rates greater than
1V/µs while the device is operating, a 10k resistor should
be connected between Pin 10 and the DC source.
Filter Input Pin (2)
The input pin is connected internally through a 40k resis-
tor tied to the inverting input of an op amp.
Filter Output Pins (9, 6)
Pin 9 is the specified output of the filter; it can typically
source 3mA and sink 1mA. Driving coaxial cables or
resistive loads less than 20k will degrade the total har-
monic distortion of the filter. When evaluating the device’s
distortion an output buffer is required. A noninverting
buffer, Figure 4, can be used provided that its input
common mode range is well within the filter’s output
swing. Pin 6 is an intermediate filter output providing an
unspecified 6th order lowpass filter. Pin 6 should not be
loaded.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pin (9). The clock feedthrough is tested with the
input pin (2) grounded and it depends on PC board layout
and on the value of the power supplies. With proper layout
techniques the values of the clock feedthrough are shown
in Table 8.
Table 8. Clock Feedthrough
V
S
50:1 100:1
Single 5V 90µV
RMS
100µV
RMS
±5V 100µV
RMS
300µV
RMS
±7.5V 120µV
RMS
650µV
RMS
Note: The clock feedthrough at single 5V is imbedded in the
wideband noise of the filter. Clock waveform is a square wave.
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple R/C lowpass network at the output of
the filter pin (9). This R/C will completely eliminate any
switching transients.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering. For instance, the
LTC1064-7 wideband noise at ±5V supply is 105µV
RMS
,
95µV
RMS
of which have frequency contents from DC up to
the filter’s cutoff frequency. The total wideband noise
(µV
RMS
) is nearly independent of the value of the clock.
The clock feedthrough specifications are not part of the
wideband noise.
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
feedthrough specifications. Switching transients have fre-
quency contents much higher than the applied clock; their
U
S
A
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PPLICATI
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12
LTC1064-7
10647fb
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PPLICATI
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Speed Limitations
To avoid op amp slew rate limiting at maximum clock
frequencies, the signal amplitude should be kept below a
specified level as shown in Table 9.
Table 9. Maximum VIN vs VS and Clock
POWER SUPPLY MAXIMUM f
CLK
MAXIMUM V
IN
±7.5V 5.0MHz 1.8V
RMS
(f
IN
> 80kHz)
4.5MHz 2.3V
RMS
(f
IN
> 80kHz)
4.0MHz 2.7V
RMS
(f
IN
> 80kHz)
≥3.5MHz 1.4V
RMS
(f
IN
> 500kHz)
±5V 3.5MHz 1.6V
RMS
(f
IN
> 80kHz)
≥3.0MHz 0.7V
RMS
(f
IN
> 400kHz)
Single 5V 2.0MHz 0.5V
RMS
(f
IN
> 250kHz)
Table 10. Transient Response of LTC Lowpass Filters
DELAY RISE SETTLING OVER-
TIME* TIME** TIME*** SHOOT
LOWPASS FILTER (SEC) (SEC) (SEC) (%)
LTC1064-3 Bessel 0.50/f
C
0.34/f
C
0.80/f
C
0.5
LTC1164-5 Bessel 0.43/f
C
0.34/f
C
0.85/f
C
0
LTC1164-6 Bessel 0.43/f
C
0.34/f
C
1.15/f
C
1
LTC1264-7 Linear Phase 1.15/f
C
0.36/f
C
2.05/f
C
5
LTC1164-7 Linear Phase 1.20/f
C
0.39/f
C
2.2/f
C
5
LTC1064-7 Linear Phase 1.20/f
C
0.39/f
C
2.2/f
C
5
LTC1164-5 Butterworth 0.80/f
C
0.48/f
C
2.4/f
C
11
LTC1164-6 Elliptic 0.85/f
C
0.54/f
C
4.3/f
C
18
LTC1064-4 Elliptic 0.90/f
C
0.54/f
C
4.5/f
C
20
LTC1064-1 Elliptic 0.85/f
C
0.54/f
C
6.5/f
C
20
* To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5%
Table 11. Aliasing (fCLK = 100kHz)
INPUT FREQUENCY OUTPUT LEVEL OUTPUT FREQUENCY
(V
IN
= 1V
RMS
, (Relative to Input, (Aliased Frequency
f
IN
= f
CLK
± f
OUT
) 0dB = 1V
RMS
)f
OUT
= ABS [f
CLK
± f
IN
])
(kHz) (dB) (kHz)
50:1, f
CUTOFF
= 2kHz
190 (or 210) –76.1 10.0
195 (or 205) – 51.9 5.0
196 (or 204) – 36.3 4.0
197 (or 203) – 18.4 3.0
198 (or 202) – 3.0 2.0
199.5 (or 200.5) –0.2 0.5
100:1, f
CUTOFF
= 1kHz
97 (or 103) –74.2 3.0
97.5 (or 102.5) –53.2 2.5
98 (or 102) –36.9 2.0
98.5 (or 101.5) – 19.6 1.5
99 (or 101) – 5.2 1.0
99.5 (or 100.5) – 0.7 0.5
Transient Response
2V/DIV
50µs/DIV
1064-7 F05
V
S
= ±7.5V, f
IN
= 2kHz ± 3V
f
CLK
= 1MHz, RATIO = 50:1
Figure 6.
INPUT
90%
50%
10%
OUTPUT
tr
td
ts
1064-7 F06
RISE TIME (t
r
) = ±5%
0.39
f
CUTOFF
SETTLING TIME (t
s
) = ±5%
(TO 1% of OUTPUT)
2.2
f
CUTOFF
DELAY TIME (t
d
) = GROUP DELAY ≈
(TO 50% OF OUTPUT)
1.2
f
CUTOFF
Figure 5.
Aliasing
Aliasing is an inherent phenomenon of sampled data
systems and it occurs when input frequencies close to the
sampling frequency are applied. For the LTC1064-7 case
at 100:1, an input signal whose frequency is in the range
of f
CLK
±3%, will be aliased back into the filter’s passband.
If, for instance, an LTC1064-7 operating with a 100kHz
clock and 1kHz cutoff frequency receives a 98kHz, 10mV
input signal, a 2kHz, 143µV
RMS
alias signal will appear at
its output. When the LTC1064-7 operates with a clock-to-
cutoff frequency of 50:1, aliasing occurs at twice the clock
frequency. Table 11 shows details.
13
LTC1064-7
10647fb
OBSOLETE PACKAGE
J Package
14-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
U
PACKAGE DESCRIPTIO
J14 0801
.045 – .065
(1.143 – 1.651)
.100
(2.54)
BSC
.014 – .026
(0.360 – 0.660)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.125
(3.175)
MIN
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457) 0° – 15°
1234567
.220 – .310
(5.588 – 7.874)
.785
(19.939)
MAX
.005
(0.127)
MIN 14 11 891013 12
.025
(0.635)
RAD TYP
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
14
LTC1064-7
10647fb
N14 1103
.020
(0.508)
MIN
.120
(3.048)
MIN
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
.065
(1.651)
TYP
.018 ± .003
(0.457 ± 0.076)
.005
(0.127)
MIN
.255 ± .015*
(6.477 ± 0.381)
.770*
(19.558)
MAX
31 24567
8910
11
1213
14
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
U
PACKAGE DESCRIPTIO
15
LTC1064-7
10647fb
S16 (WIDE) 0502
NOTE 3
.398 – .413
(10.109 – 10.490)
NOTE 4
16 15 14 13 12 11 10 9
1
N
2345678
N/2
.394 – .419
(10.007 – 10.643)
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.005
(0.127)
RAD MIN
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
1 2 3 N/2
.050 BSC
.030 ±.005
TYP
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16
LTC1064-7
10647fb
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1992
LT/LT 0905 REV B • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC1064 Universal Filter Building Block Allows for Bandpass (Up to 50kHz) Using External Resistors
LTC1064-1/2/3/4 8th Order Low Pass Filters, F
O
Max = 100kHz Elliptic, Butterworth, Bessel, Cauer
LTC1164 Universal Filter Building Block Allows for Bandpass (Up to 20kHz) Using External Resistors
LTC1164-5/6/7 8th Order Low Pass Filters, F
O
Max = 20kHz Butterworth, Bessel or Elliptic
LTC1264 Universal Filter Building Block Allows for Bandpass (Up to 100kHz) Using External Resistors
LTC1264-7 8th Order Low Pass Filter, F
O
Max = 200kHz Flat Group Delay, High Speed Lowpass Filter
LT6600-2.5 Low Noise Differential Amp and 10MHz Lowpass 55µV
RMS
Noise 100kHz to 10MHz 3V Supply
LT6600-10 Low Noise Differential Amp and 20MHz Lowpass 86µV
RMS
Noise 100kHz to 20MHz 3V Supply
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LTC1064-7
VIN
7.5V
–7.5V
CLK = 4MHz
7.5V
VOUT
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
PIN AND THE fCLK LINE.
1064-7 TA01
80kHz Linear Phase Lowpass Filter Eye Diagram
1V/DIV
1064-7 TA02
1µs/DIV
V
S
= ±7.5V
f
CLK
= 4MHz
RATIO = 50:1
U
TYPICAL APPLICATIO
