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1
DS1017_02.5
LA-ispMACH 4000V/Z
Automotive Family
3.3V/1.8V In-System Programmable
SuperFAST
High Density PLDs
May 2009 Data Sheet DS1017
TM
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Features
■
High Performance
•f
MAX
= 168MHz maximum operating frequency
•t
PD
= 7.5ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
■
Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-Fit
TM
and refit
• Fast path, SpeedLocking
TM
Path, and wide-PT
path
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
■
Zero Power (LA-ispMACH 4000Z)
• Typical static current 10µA (4032Z)
• 1.8V core low dynamic power
• LA-ispMACH 4000Z operational down to 1.6V
■
AEC-Q100 Tested and Qualified
• Automotive: -40 to 125°C ambient (T
A
)
■
Easy System Integration
• Superior solution for power sensitive consumer
applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V) or 1.8V (4000Z)
supplies
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable
(ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free (RoHS) package
Introduction
The high performance LA-ispMACH 4000V/Z automo-
tive family from Lattice offers a SuperFAST CPLD solu-
tion that is tested and qualified to the AEC-Q100
standard. The family is a blend of Lattice’s two most
popular architectures: the ispLSI
®
2000 and ispMACH
4A. Retaining the best of both families, the LA-ispMACH
4000V/Z architecture focuses on significant innovations
to combine the highest performance with low power in a
flexible CPLD family.
The LA-ispMACH 4000V/Z automotive family combines
high speed and low power with the flexibility needed for
ease of design. With its robust Global Routing Pool and
Output Routing Pool, this family delivers excellent First-
Time-Fit, timing predictability, routing, pin-out retention
and density migration.
Table 1. LA-ispMACH 4000V Automotive Family Selection Guide
LA-ispMACH 4032V LA-ispMACH 4064V LA-ispMACH 4128V
Macrocells 32 64 128
I/O + Dedicated Inputs 30+2/32+4 30+2/32+4/64+10 64+10/92+4/96+4
t
PD
(ns) 7.5 7.5 7.5
t
S
(ns) 4.5 4.5 4.5
t
CO
(ns) 4.5 4.5 4.5
f
MAX
(MHz) 168 168 168
Supply Voltage (V) 3.3V 3.3V 3.3V
Pins/Package 44-pin Lead-Free TQFP
48-pin Lead-Free TQFP
44-pin Lead-Free TQFP
48-pin Lead-Free TQFP
100-pin Lead-Free TQFP 100-pin Lead-Free TQFP
128-pin Lead-Free TQFP
144-pin Lead-Free TQFP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
2
Table 2. LA-ispMACH 4000Z Automotive Family Selection Guide
The LA-ispMACH 4000V/Z automotive family offers densities ranging from 32 to 128 macrocells. There are multiple
density-I/O combinations in Thin Quad Flat Pack (TQFP) packages ranging from 44 to 144 pins. Tables 1 and 2
show the macrocell, package and I/O options, along with other key parameters.
The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3V (4000V
and 1.8V (4000Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LA-
ispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper
latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LA-ispMACH 4000V/Z
automotive family is in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1
boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface sig-
nals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The LA-ispMACH 4000V/Z automotive devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks
(GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O
Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1.
Figure 1. Functional Block Diagram
LA-ispMACH 4032Z LA-ispMACH 4064Z LA-ispMACH 4128Z
Macrocells 32 64 128
I/O + Dedicated Inputs 32+4 32+4/64+10 64+10
t
PD
(ns) 7.5 7.5 7.5
t
S
(ns) 4.5 4.5 4.5
t
CO
(ns) 4.5 4.5 4.5
f
MAX
(MHz) 168 168 168
Supply Voltage (V) 1.8V 1.8V 1.8V
Pins/Package 48-pin Lead-Free TQFP 48-pin Lead-Free TQFP
100-pin Lead-Free TQFP 100-pin Lead-Free TQFP
I/O
Block
ORP ORP
16
16
GOE0
GOE1
VCC
GND
TCK
TMS
TDI
TDO
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
ORP ORP
16
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
I/O Bank 0
I/O Bank 1
I/O
Block
36
36
CLK0/I
CLK1/I
CLK2/I
CLK3/I
16
16
Global Routing Pool
VCCO0
GND
VCCO1
GND
16 16
16
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
3
The I/Os in the LA-ispMACH 4000V/Z automotive devices are split into two banks. Each bank has a separate I/O
power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs
support the standards compatible with the power supply provided to the bank. Support for a variety of standards
helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified
within an I/O bank that is connected to V
CCO
of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
LA-ispMACH 4000V/Z Automotive Architecture
There are a total of two GLBs in the LA-ispMACH 4032V/Z, increasing to 8 GLBs in the LA-ispMACH 4128V/Z.
Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into
the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same
GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with
consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them
to the associated I/O cells in the I/O block.
Generic Logic Block
The LA-ispMACH 4000V/Z Automotive GLB consists of a programmable AND array, logic allocator, 16 macrocells
and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O
pins are decoupled from macrocells through the ORP. Figure 2 illustrates the GLB.
Figure 2. Generic Logic Block
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
Logic Allocator
36 Inputs
from GRP
16 Macrocells
To ORP
To GRP
To
Product Term
Output Enable
Sharing
1+OE
16 MC Feedback Signals
Clock
Generator
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
CLK0
CLK1
CLK2
CLK3
1+OE
AND Array
36 Inputs,
83 Product Terms
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
4
Figure 3. AND Array
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the LA-ispMACH 4000V/Z automotive family is 4+1 (total
5) product terms. The software automatically considers the availability and distribution of product term clusters as it
fits the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path,
20-PT Speed Locking path and an up to 80-PT path. The availability of these three paths lets designers trade tim-
ing variability for increased performance.
The enhanced Logic Allocator of the LA-ispMACH 4000V/Z automotive family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
PT0
PT1 Cluster 0
PT2
PT3
PT4
In[0]
In[34]
In[35]
Note:
Indicates programmable fuse.
PT80
PT81
PT82
Shared PT Clock
Shared PT Initialization
Shared PTOE
PT76
PT77
PT78
PT79
PT75
Cluster 15
to
n+1
to
n-1
to
n-2
from
n-1
from
n-4
from
n+2
from
n+1
5-PT
From
n-4 1-80
PTs
To n+4
Fast 5-PT
Path
To XOR (MC)
Cluster
Individual Product
Term Allocator
Cluster
Allocator
SuperWIDE™
Steering Logic
n
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
5
Product Term Allocator
The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-
ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate
output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic
allocator.
Table 3. Individual PT Steering
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.
Table 4. Available Clusters for Each Macrocell
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-
tor
n
+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term
chains.
Product Term Logic Control
PT
n
Logic PT Single PT for XOR/OR
PT
n
+1 Logic PT Individual Clock (PT Clock)
PT
n
+2 Logic PT Individual Initialization or Individual Clock Enable (PT Initialization/CE)
PT
n
+3 Logic PT Individual Initialization (PT Initialization)
PT
n
+4 Logic PT Individual OE (PTOE)
Macrocell Available Clusters
M0 — C0C1C2
M1 C0 C1 C2 C3
M2 C1 C2 C3 C4
M3 C2 C3 C4 C5
M4 C3 C4 C5 C6
M5 C4 C5 C6 C7
M6 C5 C6 C7 C8
M7 C6 C7 C8 C9
M8 C7 C8 C9 C10
M9 C8 C9 C10 C11
M10 C9 C10 C11 C12
M11 C10 C11 C12 C13
M12 C11 C12 C13 C14
M13 C12 C13 C14 C15
M14 C13 C14 C15 —
M15 C14 C15 — —
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
6
Table 5. Product Term Expansion Capability
Every time the super cluster allocator is used, there is an incremental delay of t
EXP
. When the super cluster alloca-
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
• Block CLK0
• Block CLK1
• Block CLK2
Expansion Chains Macrocells Associated with Expansion Chain (with Wrap Around) Max PT/Macrocell
Chain-0 M0
→
M4
→
M8
→
M12
→
M0 75
Chain-1 M1
→
M5
→
M9
→
M13
→
M1 80
Chain-2 M2
→
M6
→
M10
→
M14
→
M2 75
Chain-3 M3
→
M7
→
M11
→
M15
→
M3 70
Single PT Block CLK0
Block CLK1
Block CLK2
Block CLK3
PT Clock (optional)
Shared PT Clock
CE
D/T/L Q
RP
Shared PT Initialization
PT Initialization/CE (optional)
PT Initialization (optional)
From Logic Allocator
Power-up
Initialization
To ORP
To GRP
From I/O Cell
Delay
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
7
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High
Initialization Control
The LA-ispMACH 4000V/Z automotive family architecture accommodates both block-level and macrocell-level set
and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB.
At the macrocell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for
set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be
exchanged, providing flexibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the V
CC
rise must be monotonic, and the clock must be inactive until the reset
delay time has elapsed.
GLB Clock Generator
Each LA-ispMACH 4000V/Z automotive device has up to four clock pins that are also routed to the GRP to be used
as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four
clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of com-
binations of the true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
CLK0
CLK1
CLK2
CLK3
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
8
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-
put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the LA-ispMACH 4000V/Z family
consists of the following elements:
• Output Routing Multiplexers
• OE Routing Multiplexers
• Output Routing Pool Bypass Multiplexers
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 6-10 provide the connection details.
Table 6. ORP Combinations for I/O Blocks with 8 I/Os
I/O Cell Available Macrocells
I/O 0 M0, M1, M2, M3, M4, M5, M6, M7
I/O 1 M2, M3, M4, M5, M6, M7, M8, M9
I/O 2 M4, M5, M6, M7, M8, M9, M10, M11
I/O 3 M6, M7, M8, M9, M10, M11, M12, M13
I/O 4 M8, M9, M10, M11, M12, M13, M14, M15
I/O 5 M10, M11, M12, M13, M14, M15, M0, M1
I/O 6 M12, M13, M14, M15, M0, M1, M2, M3
I/O 7 M14, M15, M0, M1, M2, M3, M4, M5
Out
p
ut Routin
g
Multi
p
lexer
OE Routing Multiplexer
ORP
Bypass
Multiplexer
From Macrocell
From PTOE To I/O
Cell
To I/O
Cell
Output
OE
5-PT Fast Path
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
9
Table 7. ORP Combinations for I/O Blocks with 16 I/Os
Table 8. ORP Combinations for I/O Blocks with 12 I/Os
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster t
CO
.
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.
I/O Cell Available Macrocells
I/O 0 M0, M1, M2, M3, M4, M5, M6, M7
I/O 1 M1, M2, M3, M4, M5, M6, M7, M8
I/O 2 M2, M3, M4, M5, M6, M7, M8, M9
I/O 3 M3, M4, M5, M6, M7, M8, M9, M10
I/O 4 M4, M5, M6, M7, M8, M9, M10, M11
I/O 5 M5, M6, M7, M8, M9, M10, M11, M12
I/O 6 M6, M7, M8, M9, M10, M11, M12, M13
I/O 7 M7, M8, M9, M10, M11, M12, M13, M14
I/O 8 M8, M9, M10, M11, M12, M13, M14, M15
I/O 9 M9, M10, M11, M12, M13, M14, M15, M0
I/O 10 M10, M11, M12, M13, M14, M15, M0, M1
I/O 11 M11, M12, M13, M14, M15, M0, M1, M2
I/O 12 M12, M13, M14, M15, M0, M1, M2, M3
I/O 13 M13, M14, M15, M0, M1, M2, M3, M4
I/O 14 M14, M15, M0, M1, M2, M3, M4, M5
I/O 15 M15, M0, M1, M2, M3, M4, M5, M6
I/O Cell Available Macrocells
I/O 0 M0, M1, M2, M3, M4, M5, M6, M7
I/O 1 M1, M2, M3, M4, M5, M6, M7, M8
I/O 2 M2, M3, M4, M5, M6, M7, M8, M9
I/O 3 M4, M5, M6, M7, M8, M9, M10, M11
I/O 4 M5, M6, M7, M8, M9, M10, M11, M12
I/O 5 M6, M7, M8, M9, M10, M11, M12, M13
I/O 6 M8, M9, M10, M11, M12, M13, M14, M15
I/O 7 M9, M10, M11, M12, M13, M14, M15, M0
I/O 8 M10, M11, M12, M13, M14, M15, M0, M1
I/O 9 M12, M13, M14, M15, M0, M1, M2, M3
I/O 10 M13, M14, M15, M0, M1, M2, M3, M4
I/O 11 M14, M15, M0, M1, M2, M3, M4, M5
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
10
Figure 8. I/O Cell
Each output supports a variety of output standards dependent on the V
CCO
supplied to its I/O bank. Outputs can
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V
CCO
supplied to its I/O bank. The I/O standards supported are:
• LVTTL • LVCMOS 1.8
• LVCMOS 3.3 • 3.3V PCI Compatible
• LVCMOS 2.5
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
configured to be a Pull-up Resistor.
Each LA-ispMACH 4000V/Z automotive device I/O has an individually programmable output slew rate control bit.
Each output can be individually configured for fast slew or slow slew. The typical edge rate difference between fast
and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will intro-
duce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well ter-
minated lines, the fast slew rate can be used to achieve the highest speed.
Global OE Generation
Most LA-ispMACH 4000V/Z automotive family devices have a 4-bit wide Global OE Bus, except the LA-ispMACH
4032V and LA-ispMACH4032Z devices that have a 2-bit wide Global OE Bus. This bus is derived from a 4-bit inter-
nal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be
inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
128-macrocell device (with 16 blocks), each line of the bus is driven from 8 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
GOE 0
From ORP
*Global fuses
From ORP
To Macrocell
To GRP
GOE 1
GOE 2
GOE 3
VCC
VCCO
VCCO
**
*
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
11
Figure 9. Global OE Generation for All Devices Except LA-ispMACH 4032V/Z
Figure 10. Global OE Generation for LA-ispMACH 4032V/Z
Zero Power/Low Power and Power Management
The LA-ispMACH 4000V/Z automotive family is designed with high speed low power design techniques to offer
both high speed and low power. With an advanced E2 low power cell and non sense-amplifier design approach (full
CMOS logic approach), the LA-ispMACH 4000V/Z automotive family offers SuperFAST pin-to-pin speeds, while
simultaneously delivering low standby power without needing any “turbo bits” or other power management
schemes associated with a traditional sense-amplifier approach.
Shared PTOE
(Block 0)
Shared PTOE
(Block n)
Global
Fuses GOE (0:3)
to I/O cells
Internal Global OE
PT Bus
(4 lines)
4-Bit
Global OE Bus
Global OE
Fuse connection
Hard wired
Shared PTOE
(Block 0)
Shared PTOE
(Block 1)
Global
Fuses GOE (3:0)
to I/O cells
Internal Global OE
PT Bus
(2 lines)
4-Bit
Global OE Bus
Global OE
Fuse connection
Hard wired
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
12
The zero power LA-ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design
changes, the LA-ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.
IEEE 1149.1-Compliant Boundary Scan Testability
All LA-ispMACH 4000V/Z automotive devices have boundary scan cells and are compliant to the IEEE 1149.1
standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan
path that can access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition,
these devices can be linked into a board-level serial scan path for more board-level testing. The test access port
operates with an LVCMOS interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The LA-ispMACH 4000V/Z automotive fam-
ily of devices allows this by offering the user the ability to quickly configure the physical nature of the I/O cells. This
quick configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be pro-
grammed. Lattice's ispVM™ System programming software can either perform the quick configuration through the
PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inven-
tory levels, higher quality and the ability to make in-field modifications. The LA-ispMACH 4000V/Z automotive
devices provide In-System Programming (ISP™) capability through the Boundary Scan Test Access Port. This
capability has been implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1
standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, users get the ben-
efit of a standard, well-defined interface. All LA-ispMACH 4000V/Z automotive devices are also compliant with the
IEEE 1532 standard.
The LA-ispMACH 4000V/Z automotive devices can be programmed across the commercial temperature and volt-
age range. The PC-based Lattice software facilitates in-system programming of LA-ispMACH 4000V/Z automotive
devices. The software takes the JEDEC file output produced by the design implementation software, along with
information about the scan chain, and creates a set of vectors used to drive the scan chain. The software can use
these vectors to drive a scan chain via the parallel port of a PC. Alternatively, the software can output files in for-
mats understood by common automated test equipment. This equipment can then be used to program LA-
ispMACH 4000V/Z automotive devices during the testing of a circuit board.
User Electronic Signature
The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the
device, stored in E2CMOS memory. The LA-ispMACH 4000V/Z automotive device contains 32 UES bits that can be
configured by the user to store unique data such as ID codes, revision numbers or inventory control codes.
Security Bit
A programmable security bit is provided on the LA-ispMACH 4000V/Z automotive devices as a deterrent to unau-
thorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the pro-
grammed pattern by a device programmer, securing proprietary designs from competitors. Programming and
verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The LA-ispMACH 4000V/Z automotive devices are well-suited for applications that require hot socketing capability.
Hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the I/Os
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
13
and inputs without being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active
signals. The LA-ispMACH 4000V/Z automotive devices provide this capability for input voltages in the range 0V to
3.0V.
Density Migration
The LA-ispMACH 4000V/Z automotive family has been designed to ensure that different density devices in the
same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing
design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utili-
zation design targeted for a high density device to a lower density device. However, the exact details of the final
resource utilization will impact the likely success in each case.
AEC-Q100 Tested and Qualified
The Automotive Electronics Council (AEC) consists of two committees: the Quality Systems Committee and the
Component Technical Committee. These committees are composed of representatives from sustaining and other
associate members. The AEC Component Technical Committee is the standardization body for establishing stan-
dards for reliable, high quality electronic components. In particular, the AEC-Q100 specification “Stress Test for
Qualification for Integrated Circuits” defines qualification and re-qualification requirements for electronic compo-
nents. Components meeting these specifications are suitable for use in the harsh automotive environment without
additional component-level qualification testing. Lattice's LA-ispMACH 4000V/Z and LA-MachXO devices com-
pleted and passed the requirements of the AEC-Q100 specification.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
14
Absolute Maximum Ratings1, 2, 3
LA-ispMACH 4000V (3.3V) LA-ispMACH 4000Z (1.8V)
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 2.5V
Output Supply Voltage (VCCO) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input or I/O Tristate Voltage Applied4, 5 . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature (Tj) with Power Applied . . . . . . . . . . -55 to 150°C . . . . . . . . . . . . . . . -55 to 150°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.
2. Compliance with Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Undershoot of -2V and overshoot of (VIH (MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns.
5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
Recommended Operating Conditions
Erase Reprogram Specifications
Hot Socketing Characteristics1,2,3
Symbol Parameter Min. Max. Units
VCC
LA-ispMACH 4000V Supply Voltage 3.0 3.6 V
LA-ispMACH 4000Z Supply Voltage 1.7 1.9 V
LA-ispMACH 4000Z, Extended Functional Voltage Operations 1.611.9 V
TAAmbient Temperature (Automotive) -40 125 C
1. Devices operating at 1.6V can expect performance degradation up to 35%.
Parameter Min. Max. Units
Erase/Reprogram Cycle 1,000 — Cycles
Note: Valid over commercial temperature range.
Symbol Parameter Condition Min. Typ. Max. Units
IDK Input or I/O Leakage Current 0 ≤ VIN ≤ 3.0V, Tj = 105°C — ±30 ±150 µA
0 ≤ VIN ≤ 3.0V, Tj = 130°C — ±30 ±200 µA
1. Insensitive to sequence of VCC or VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) ≤ 3.6V.
2. 0 < VCC < VCC (MAX), 0 < VCCO < VCCO (MAX).
3. IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
15
I/O Recommended Operating Conditions
DC Electrical Characteristics
Over Recommended Operating Conditions
Standard
VCCO (V)1
Min. Max.
LVTTL 3.0 3.6
LVCMOS 3.3 3.0 3.6
Extended LVCMOS 3.322.7 3.6
LVCMOS 2.5 2.3 2.7
LVCMOS 1.8 1.65 1.95
PCI 3.3 3.0 3.6
1. Typical values for VCCO are the average of the min. and max. values.
2. LA-ispMACH 4000Z only.
Symbol Parameter Condition Min. Typ. Max. Units
IIL, IIH1, 4 Input Leakage Current
(LA-ispMACH 4000Z) 0 ≤ VIN < VCCO — 0.5 1 µA
IIH1, 2
Input High Leakage Current
(LA-ispMACH 4000V)
3.6V < VIN ≤ 5.5V, Tj = 105°C
3.0V ≤ VCCO ≤ 3.6V — — 20 µA
3.6V < VIN ≤ 5.5V, Tj = 130°C
3.0V ≤ VCCO ≤ 3.6V — — 50 µA
Input High Leakage Current
(LA-ispMACH 4000Z) VCCO < VIN ≤ 5.5V — — 10 µA
IPU
I/O Weak Pull-up Resistor Current
(LA-ispMACH 4000V) 0 ≤ VIN ≤ 0.7VCCO -30 — -200 µA
I/O Weak Pull-up Resistor Current
(LA-ispMACH 4000Z) 0 ≤ VIN ≤ 0.7VCCO -30 — -150 µA
IPD I/O Weak Pull-down Resistor Current VIL (MAX) ≤ VIN ≤ VIH (MIN) 30 — 150 µA
IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCO -30 — — µA
IBHLO Bus Hold Low Overdrive Current 0V ≤ VIN ≤ VBHT — — 150 µA
IBHHO Bus Hold High Overdrive Current VBHT ≤ VIN ≤ VCCO — — -150 µA
VBHT Bus Hold Trip Points — VCCO * 0.35 — VCCO * 0.65 V
C1I/O Capacitance3VCCO = 3.3V, 2.5V, 1.8V — 8—pf
VCC = 1.8V, VIO = 0 to VIH (MAX) — —
C2Clock Capacitance3VCCO = 3.3V, 2.5V, 1.8V — 6—pf
VCC = 1.8V, VIO = 0 to VIH (MAX) — —
C3Global Input Capacitance3VCCO = 3.3V, 2.5V, 1.8V — 6—pf
VCC = 1.8V, VIO = 0 to VIH (MAX) — —
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V ≤ VCCO ≤ 3.6V.
3. TA = 25°C, f = 1.0MHz.
4. IIH excursions of up to 1.5µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of
the device’s I/O pins.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
16
Supply Current, LA-ispMACH 4000V
Over Recommended Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
LA-ispMACH 4032V
ICC Operating Power Supply Current Vcc = 3.3V — 11.8 — mA
Standby Power Supply Current Vcc = 3.3V — 11.3 — mA
LA-ispMACH 4064V
ICC Operating Power Supply Current Vcc = 3.3V — 12 — mA
Standby Power Supply Current Vcc = 3.3V — 11.5 — mA
LA-ispMACH 4128V
ICC Operating Power Supply Current Vcc = 3.3V — 12 — mA
Standby Power Supply Current Vcc = 3.3V — 11.5 — mA
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
17
Supply Current, LA-ispMACH 4000Z
Over Recommended Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
LA-ispMACH 4032Z
ICC1, 2, 3, 5 Operating Power Supply Current
Vcc = 1.8V, TA = 25°C — 50 — µA
Vcc = 1.9V, TA = 70°C — 58 — µA
Vcc = 1.9V, TA = 85°C — 60 — µA
Vcc = 1.9V, TA = 125°C — 70 — µA
ICC4, 5 Standby Power Supply Current
Vcc = 1.8V, TA = 25°C — 10 — µA
Vcc = 1.9V, TA = 70°C — 13 20 µA
Vcc = 1.9V, TA = 85°C — 15 25 µA
Vcc = 1.9V, TA = 125°C — 22 µA
LA-ispMACH 4064Z
ICC1, 2, 3, 5 Operating Power Supply Current
Vcc = 1.8V, TA = 25°C — 80 — µA
Vcc = 1.9V, TA = 70°C — 89 — µA
Vcc = 1.9V, TA = 85°C — 92 — µA
Vcc = 1.9V, TA = 125°C — 109 — µA
ICC4, 5 Standby Power Supply Current
Vcc = 1.8V, TA = 25°C — 11 — µA
Vcc = 1.9V, TA = 70°C — 15 25 µA
Vcc = 1.9V, TA = 85°C — 18 35 µA
Vcc = 1.9V, TA = 125°C — 37 µA
LA-ispMACH 4128Z
ICC1, 2, 3, 5 Operating Power Supply Current
Vcc = 1.8V, TA = 25°C — 168 — µA
Vcc = 1.9V, TA = 70°C — 190 — µA
Vcc = 1.9V, TA = 85°C — 195 — µA
Vcc = 1.9V, TA = 125°C — 212 — µA
ICC4, 5 Standby Power Supply Current
Vcc = 1.8V, TA = 25°C — 12 — µA
Vcc = 1.9V, TA = 70°C — 16 35 µA
Vcc = 1.9V, TA = 85°C — 19 50 µA
Vcc = 1.9V, TA = 125°C — 42 — µA
1. TA = 25°C, frequency = 1.0 MHz.
2. Device configured with 16-bit counters.
3. ICC varies with specific device configuration and operating frequency.
4. VCCO = 3.6V, VIN = 0V or VCCO, bus maintenance turned off. VIN above VCCO will add transient current above the specified standby ICC.
5. Includes VCCO current without output loading.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
18
I/O DC Electrical Characteristics
Over Recommended Operating Conditions
Standard
VIL VIH VOL
Max (V)
VOH
Min (V)
IOL1
(mA)
IOH1
(mA)Min (V) Max (V) Min (V) Max (V)
LVTTL -0.3 0.80 2.0 5.5 0.40 VCCO - 0.40 8.0 -4.0
0.20 VCCO - 0.20 0.1 -0.1
LVCMOS 3.3 -0.3 0.80 2.0 5.5 0.40 VCCO - 0.40 8.0 -4.0
0.20 VCCO - 0.20 0.1 -0.1
LVCMOS 2.5 -0.3 0.70 1.70 3.6 0.40 VCCO - 0.40 8.0 -4.0
0.20 VCCO - 0.20 0.1 -0.1
LVCMOS 1.8
(4000V) -0.3 0.63 1.17 3.6 0.40 VCCO - 0.45 2.0 -2.0
0.20 VCCO - 0.20 0.1 -0.1
LVCMOS 1.8
(4000Z) -0.3 0.35 * VCC 0.65 * VCC 3.6 0.40 VCCO - 0.45 2.0 -2.0
0.20 VCCO - 0.20 0.1 -0.1
PCI 3.3 (4000V) -0.3 1.08 1.5 5.5 0.1 VCCO 0.9 VCCO 1.5 -0.5
PCI 3.3 (4000Z) -0.3 0.3 * 3.3 * (VCC / 1.8) 0.5 * 3.3 * (VCC / 1.8) 5.5 0.1 VCCO 0.9 VCCO 1.5 -0.5
1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
V
O
Output Voltage (V)
Typical I/O Output Current (mA)
3.3V V
CCO
VO Output Voltage (V)
0
0
0
20
40
60
80
100
10
20
30
40
50
60
0
10
20
30
40
50
60
70
2.01.51.00.5
0 2.0 2.5 3.0 3.51.51.00.5 0 2.0 2.51.51.00.5
Typical I/O Output Current (mA)
1.8V V
CCO
VO Output Voltage (V)
IOH
Typical I/O Output Current (mA)
2.5V V
CCO
IOL
IOH
IOL
IOH
IOL
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
19
LA-ispMACH 4000V/Z External Switching Characteristics
Over Recommended Operating Conditions
Parameter Description1, 2, 3
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
UnitsMin. Max. Min. Max.
tPD 5-PT bypass combinatorial propagation delay — 7.5 — 7.5 ns
tPD_MC 20-PT combinatorial propagation delay through macro-
cell — 8.0 — 8.0 ns
tSGLB register setup time before clock 4.5 — 4.5 — ns
tST GLB register setup time before clock with T-type regis-
ter 4.7 — 4.7 — ns
tSIR GLB register setup time before clock, input register
path 1.7 — 1.4 — ns
tSIRZ GLB register setup time before clock with zero hold 2.7 — 2.7 — ns
tHGLB register hold time after clock 0.0 — 0.0 — ns
tHT GLB register hold time after clock with T-type register 0.0 — 0.0 — ns
tHIR GLB register hold time after clock, input register path 1.0 — 1.3 — ns
tHIRZ GLB register hold time after clock, input register path
with zero hold 0.0 — 0.0 — ns
tCO GLB register clock-to-output delay — 4.5 — 4.5 ns
tRExternal reset pin to output delay — 9.0 — 9.0 ns
tRW External reset pulse duration 4.0 — 4.0 — ns
tPTOE/DIS Input to output local product term output enable/dis-
able — 9.0 — 9.0 ns
tGPTOE/DIS Input to output global product term output enable/dis-
able — 10.3 — 10.5 ns
tGOE/DIS Global OE input to output enable/disable — 7.0 — 7.0 ns
tCW Global clock width, high or low 2.8 — 2.8 — ns
tGW Global gate width low (for low transparent) or high (for
high transparent) 2.8 — 2.8 — ns
tWIR Input register clock width, high or low 2.8 — 2.8 — ns
fMAX4Clock frequency with internal feedback — 168 — 168 MHz
fMAX (Ext.) Clock frequency with external feedback, [1/ (tS + tCO)] — 111 — 111 MHz
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. Timing v.3.2
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
20
Timing Model
The task of determining the timing through the LA-ispMACH 4000V/Z automotive family, like any CPLD, is relatively
simple. The timing model provided in Figure 11 shows the specific delay paths. Once the implementation of a given
function is determined either conceptually or from the software report file, the delay path of the function can easily
be determined from the timing model. The Lattice design tools report the timing delays based on the same timing
model for a particular design. Note that the internal timing parameters are given for reference only, and are not
tested. The external timing parameters are tested and guaranteed for every device. For more information on the
timing model and usage, refer to TN1004, ispMACH 4000 Timing Model Design and Usage Guidelines.
Figure 11. LA-ispMACH 4000V/Z Automotive Timing Model
DATA
MC Reg.
C.E.
S/R
Q
SCLK
IN
OE
In/Out
Delays
In/Out
Delays
Control
Delays
Register/Latch
Delays
Routing/GLB Delays
Out
Note: Italicized items are optional delay adders.
t
FBK
Feedback
From
Feedback
t
BUF
t
PDb
t
MCELL
t
PTCLK
t
BCLK
t
PTSR
t
BSR
t
GPTOE
t
PTOE
t
EXP
t
ROUTE
t
BLA
t
INREG
t
INDIO
t
IN
t
IOI
t
GCLK_IN
t
IOI
t
GOE
t
IOI
t
PDi
t
IOO
t
ORP
t
EN
t
DIS
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
21
LA-ispMACH 4000V/Z Internal Timing Parameters
Over Recommended Operating Conditions
Parameter Description
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
UnitsMin. Max. Min. Max.
In/Out Delays
tIN Input Buffer Delay — 1.50 — 1.80 ns
tGOE Global OE Pin Delay — 6.04 — 4.30 ns
tGCLK_IN Global Clock Input Buffer Delay — 2.28 — 2.15 ns
tBUF Delay through Output Buffer — 1.50 — 1.30 ns
tEN Output Enable Time — 0.96 — 2.70 ns
tDIS Output Disable Time — 0.96 — 2.70 ns
Routing/GLB Delays
tROUTE Delay through GRP — 2.26 — 2.50 ns
tMCELL Macrocell Delay — 1.45 — 1.00 ns
tINREG Input Buffer to Macrocell Register Delay — 0.96 — 1.00 ns
tFBK Internal Feedback Delay — 0.00 — 0.05 ns
tPDb 5-PT Bypass Propagation Delay — 2.24 — 1.90 ns
tPDi Macrocell Propagation Delay — 1.24 — 1.00 ns
Register/Latch Delays
tSD-Register Setup Time (Global Clock) 1.57 — 1.35 — ns
tS_PT D-Register Setup Time (Product Term Clock) 1.32 — 2.45 — ns
tST T-Register Setup Time (Global Clock) 1.77 — 1.55 — ns
tST_PT T-Register Setup Time (Product Term Clock) 1.32 — 2.75 — ns
tHD-Register Hold Time 2.93 — 3.15 — ns
tHT T-Register Hold Time 2.93 — 3.15 — ns
tSIR D-Input Register Setup Time (Global Clock) 1.57 — 0.75 — ns
tSIR_PT D-Input Register Setup Time (Product Term
Clock)
1.45 — 1.45 — ns
tHIR D-Input Register Hold Time (Global Clock) 1.18 — 1.95 — ns
tHIR_PT D-Input Register Hold Time (Product Term
Clock)
1.18 — 1.18 — ns
tCOi Register Clock to Output/Feedback MUX Time — 0.67 — 1.05 ns
tCES Clock Enable Setup Time 2.25 — 2.00 — ns
tCEH Clock Enable Hold Time 1.88 — 0.00 — ns
tSL Latch Setup Time (Global Clock) 1.57 — 1.65 — ns
tSL_PT Latch Setup Time (Product Term Clock) 1.32 — 2.15 — ns
tHL Latch Hold Time 1.17 — 1.17 — ns
tGOi Latch Gate to Output/Feedback MUX Time — 0.33 — 0.33 ns
tPDLi Propagation Delay through Transparent Latch to
Output/Feedback MUX
— 0.25 — 0.25 ns
tSRi Asynchronous Reset or Set to Output/Feedback
MUX Delay
0.28 — — 0.28 ns
tSRR Asynchronous Reset or Set Recovery Time 1.67 — — 1.67 ns
Control Delays
tBCLK GLB PT Clock Delay — 1.12 — 1.25 ns
tPTCLK Macrocell PT Clock Delay — 0.87 — 1.25 ns
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
22
tBSR GLB PT Set/Reset Delay — 1.83 — 1.83 ns
tPTSR Macrocell PT Set/Reset Delay — 3.41 — 2.72 ns
tGPTOE Global PT OE Delay — 5.58 — 3.50 ns
tPTOE Macrocell PT OE Delay — 4.28 — 2.00 ns
Timing v.3.2
Note: Internal Timing Parameters are not tested and are for reference only. Refer to the Timing Model in this data sheet for further details.
LA-ispMACH 4000V/Z Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
Parameter Description
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
UnitsMin. Max. Min. Max.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
23
LA-ispMACH 4000V/Z Timing Adders1
Adder Type Base Parameter Description
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
UnitsMin. Max. Min. Max.
Optional Delay Adders
tINDIO tINREG Input register delay — 1.00 — 1.30 ns
tEXP tMCELL Product term expander delay — 0.33 — 0.50 ns
tORP — Output routing pool delay — 0.05 — 0.40 ns
tBLA tROUTE Additional block loading adder — 0.05 — 0.05 ns
tIOI Input Adjusters
LVTTL_in tIN, tGCLK_IN, tGOE Using LVTTL standard — 0.60 — 0.60 ns
LVCMOS33_in tIN, tGCLK_IN, tGOE Using LVCMOS 3.3 standard — 0.60 — 0.60 ns
LVCMOS25_in tIN, tGCLK_IN, tGOE Using LVCMOS 2.5 standard — 0.60 — 0.60 ns
LVCMOS18_in tIN, tGCLK_IN, tGOE Using LVCMOS 1.8 standard — 0.00 — 0.00 ns
PCI_in tIN, tGCLK_IN, tGOE Using PCI compatible input — 0.60 — 0.60 ns
tIOO Output Adjusters
LVTTL_out tBUF, tEN, tDIS Output configured as TTL buffer — 0.20 — 0.20 ns
LVCMOS33_out tBUF, tEN, tDIS Output configured as 3.3V buffer — 0.20 — 0.20 ns
LVCMOS25_out tBUF, tEN, tDIS Output configured as 2.5V buffer — 0.10 — 0.10 ns
LVCMOS18_out tBUF, tEN, tDIS Output configured as 1.8V buffer — 0.00 — 0.00 ns
PCI_out tBUF, tEN, tDIS Output configured as PCI
compatible buffer — 0.20 — 0.20 ns
Slow Slew tBUF, tEN Output configured for slow slew
rate — 1.00 — 1.00 ns
Note: Open drain timing is the same as corresponding LVCMOS timing. Timing v.3.2
1. Refer to TN1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
24
Boundary Scan Waveforms and Timing Specifications
Symbol Parameter Min. Max. Units
tBTCP TCK [BSCAN test] clock cycle 40 — ns
tBTCH TCK [BSCAN test] pulse width high 20 — ns
tBTCL TCK [BSCAN test] pulse width low 20 — ns
tBTSU TCK [BSCAN test] setup time 8 — ns
tBTH TCK [BSCAN test] hold time 10 — ns
tBRF TCK [BSCAN test] rise and fall time 50 — mV/ns
tBTCO TAP controller falling edge of clock to valid output — 10 ns
tBTOZ TAP controller falling edge of clock to data output disable — 10 ns
tBTVO TAP controller falling edge of clock to data output enable — 10 ns
tBTCPSU BSCAN test Capture register setup time 8 — ns
tBTCPH BSCAN test Capture register hold time 10 — ns
tBTUCO BSCAN test Update reg, falling edge of clock to valid output — 25 ns
tBTUOZ BSCAN test Update reg, falling edge of clock to output disable — 25 ns
tBTUOV BSCAN test Update reg, falling edge of clock to output enable — 25 ns
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
25
Power Consumption
Power Estimation Coefficients1
Device A B
LA-ispMACH 4032V 11.3 0.010
LA-ispMACH 4064V 11.5 0.010
LA-ispMACH 4128V 11.5 0.011
LA-ispMACH 4032Z 0.010 0.010
LA-ispMACH 4064Z 0.011 0.010
LA-ispMACH 4128Z 0.012 0.010
1. For further information about the use of these coefficients, refer to TN1005, Power Esti-
mation in ispMACH 4000V/B/C/Z Devices.
0 10050 150 200 250 300 350 400 50 100 200150 250
ICC (mA)
ICC (mA)
4032Z
4032V
4064V
4128V
4064Z
4128Z
60
80
100
40
20
Note: The devices are configured with the maximum number
of 16-bit counters, typical current at 1.8V, 25°C.
Note: The devices are configured with the maximum number
of 16-bit counters, typical current at 3.3V, 2.5V, 25°C.
LA-ispMACH 4000Z
Typical I
CC
vs. Frequency
(Preliminary Information)
LA-ispMACH 4000V
Typical I
CC
vs. Frequency
0 300
Frequency (MHz)Frequency (MHz)
00
50
100
150
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
26
Switching Test Conditions
Figure 12 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 9.
Figure 12. Output Test Load, LVTTL and LVCMOS Standards
Table 9. Test Fixture Required Components
Test Condition R1R2CL1Timing Ref. VCCO
LVCMOS I/O, (L -> H, H -> L) 106Ω106Ω35pF
LVCMOS 3.3 = 1.5V LVCMOS 3.3 = 3.0V
LVCMOS 2.5 = VCCO/2 LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = VCCO/2 LVCMOS 1.8 = 1.65V
LVCMOS I/O (Z -> H) ∞106Ω35pF 1.5V 3.0V
LVCMOS I/O (Z -> L) 106Ω∞ 35pF 1.5V 3.0V
LVCMOS I/O (H -> Z) ∞106Ω5pF VOH - 0.3 3.0V
LVCMOS I/O (L -> Z) 106Ω∞ 5pF VOL + 0.3 3.0V
1. CL includes test fixtures and probe capacitance.
VCCO
R1
R2CL
DUT Test
Point
0213A/ispm4
k
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
27
Signal Descriptions
LA-ispMACH 4000V ORP Reference Table
LA-ispMACH 4000Z ORP Reference Table
Signal Names Description
TMS Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
the state machine
TCK Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
state machine
TDI Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data
TDO Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out
GOE0/IO, GOE1/IO These pins are configured to be either Global Output Enable Input or as general I/O
pins
GND Ground
NC Not Connected
VCC The power supply pins for the logic core and JTAG port
CLK0/I, CLK1/I, CLK2/I, CLK3/I These pins are configured to be either CLK input or as an input
VCCO0, VCCO1 The power supply pins for each I/O bank
yzz
Input/Output1 – These are the general purpose I/O used by the logic array. y is GLB
reference (alpha) and z is macrocell reference (numeric). z: 0-15
LA-ispMACH 4032V/Z y: A-B
LA-ispMACH 4064V/Z y: A-D
LA-ispMACH 4128V/Z y: A-H
1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details.
4032V 4064V 4128V
Number of I/Os 30132 30232 64 64 92396
Number of GLBs 2244 4 888
Number of I/Os /GLB 16 16 8 8 16 8 12 12
Reference ORP Table 16 I/Os / GLB 8 I/Os / GLB 16 I/Os / GLB 8 I/Os /GLB 12 I/Os / GLB
1. 32-macrocell device, 44 TQFP: 2 GLBs have 15 out of 16 I/Os bonded out.
2. 64-macrocells device, 44 TQFP: 2 GLBs have 7 out of 8 I/Os bonded out.
3. 128-macrocell device, 128 TQFP: 4 GLBs have 11 out of 12 I/Os
4032Z 4064Z 4128Z
Number of I/Os 32 32 64 64
Number of GLBs 2448
Number of I/Os / GLB 16 8 16 8
Reference ORP Table 16 I/Os /
GLB
8 I/Os /
GLB
16 I/Os /
GLB
8 I/Os /
GLB
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
28
LA-ispMACH 4000V/Z Power Supply and NC Connections1
Signal 44 TQFP248 TQFP2100 TQFP2128 TQFP2144 TQFP2
VCC 11, 33 12, 36 25, 40, 75, 90 32, 51, 96, 115 36, 57, 108, 129
VCCO0
VCCO (Bank 0) 6 6 13, 33, 95 3, 17, 30, 41, 122 3, 19, 34, 47, 136
VCCO1
VCCO (Bank 1) 28 30 45, 63, 83 58, 67, 81, 94, 105 64, 75, 91, 106, 119
GND 12, 34 13, 37 1, 26, 51, 76 1, 33, 65, 97 1, 37, 73, 109
GND (Bank 0) 5 5 7, 18, 32, 96 10, 24, 40, 113, 123 10, 186, 27, 46, 127,
137
GND (Bank 1) 27 29 46, 57, 68, 82 49, 59, 74, 88, 104 55, 65, 82, 906, 99,
118
NC None None None None 17, 20, 38, 45, 72,
89, 92, 110, 117,
144
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
the bank shown.
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
29
LA-ispMACH 4032V and 4064V Logic Signal Connections: 44-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4032V LA-ispMACH 4064V
GLB/MC/Pad ORP GLB/MC/Pad ORP
1 - TDI - TDI -
2 0 A5 A^5 A10 A^5
3 0 A6 A^6 A12 A^6
4 0 A7 A^7 A14 A^7
5 0 GND (Bank 0) - GND (Bank 0) -
6 0 VCCO (Bank 0) - VCCO (Bank 0) -
7 0 A8 A^8 B0 B^0
8 0 A9 A^9 B2 B^1
9 0 A10 A^10 B4 B^2
10 - TCK - TCK -
11 - VCC - VCC -
12 - GND - GND -
13 0 A12 A^12 B8 B^4
14 0 A13 A^13 B10 B^5
15 0 A14 A^14 B12 B^6
16 0 A15 A^15 B14 B^7
17 1 CLK2/I - CLK2/I -
18 1 B0 B^0 C0 C^0
19 1 B1 B^1 C2 C^1
20 1 B2 B^2 C4 C^2
21 1 B3 B^3 C6 C^3
22 1 B4 B^4 C8 C^4
23 - TMS - TMS -
24 1 B5 B^5 C10 C^5
25 1 B6 B^6 C12 C^6
26 1 B7 B^7 C14 C^7
27 1 GND (Bank 1) - GND (Bank 1) -
28 1 VCCO (Bank 1) - VCCO (Bank 1) -
29 1 B8 B^8 D0 D^0
30 1 B9 B^9 D2 D^1
31 1 B10 B^10 D4 D^2
32 - TDO - TDO -
33 - VCC - VCC -
34 - GND - GND -
35 1 B12 B^12 D8 D^4
36 1 B13 B^13 D10 D^5
37 1 B14 B^14 D12 D^6
38 1 B15/GOE1 B^15 D14/GOE1 D^7
39 0 CLK0/I - CLK0/I -
40 0 A0/GOE0 A^0 A0/GOE0 A^0
41 0 A1 A^1 A2 A^1
42 0 A2 A^2 A4 A^2
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
30
43 0 A3 A^3 A6 A^3
44 0 A4 A^4 A8 A^4
LA-ispMACH 4032V/Z and 4064V/Z Logic Signal Connections: 48-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4032V/Z LA-ispMACH 4064V/Z
GLB/MC/Pad ORP GLB/MC/Pad ORP
1 - TDI - TDI -
2 0 A5 A^5 A10 A^5
3 0 A6 A^6 A12 A^6
4 0 A7 A^7 A14 A^7
5 0 GND (Bank 0) - GND (Bank 0) -
6 0 VCCO (Bank 0) - VCCO (Bank 0) -
7 0 A8 A^8 B0 B^0
8 0 A9 A^9 B2 B^1
9 0 A10 A^10 B4 B^2
10 0 A11 A^11 B6 B^3
11 - TCK - TCK -
12 - VCC - VCC -
13 - GND - GND -
14 0 A12 A^12 B8 B^4
15 0 A13 A^13 B10 B^5
16 0 A14 A^14 B12 B^6
17 0 A15 A^15 B14 B^7
18 0 CLK1/I - CLK1/I -
19 1 CLK2/I - CLK2/I -
20 1 B0 B^0 C0 C^0
21 1 B1 B^1 C2 C^1
22 1 B2 B^2 C4 C^2
23 1 B3 B^3 C6 C^3
24 1 B4 B^4 C8 C^4
25 - TMS - TMS -
26 1 B5 B^5 C10 C^5
27 1 B6 B^6 C12 C^6
28 1 B7 B^7 C14 C^7
29 1 GND (Bank 1) - GND (Bank 1) -
30 1 VCCO (Bank 1) - VCCO (Bank 1) -
31 1 B8 B^8 D0 D^0
32 1 B9 B^9 D2 D^1
33 1 B10 B^10 D4 D^2
34 1 B11 B^11 D6 D^3
35 - TDO - TDO -
LA-ispMACH 4032V and 4064V Logic Signal Connections: 44-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4032V LA-ispMACH 4064V
GLB/MC/Pad ORP GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
31
36 - VCC - VCC -
37 - GND - GND -
38 1 B12 B^12 D8 D^4
39 1 B13 B^13 D10 D^5
40 1 B14 B^14 D12 D^6
41 1 B15/GOE1 B^15 D14/GOE1 D^7
42 1 CLK3/I - CLK3/I -
43 0 CLK0/I - CLK0/I -
44 0 A0/GOE0 A^0 A0/GOE0 A^0
45 0 A1 A^1 A2 A^1
46 0 A2 A^2 A4 A^2
47 0 A3 A^3 A6 A^3
48 0 A4 A^4 A8 A^4
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4064V/Z LA-ispMACH 4128V/Z
GLB/MC/Pad ORP GLB/MC/Pad ORP
1 - GND - GND -
2 - TDI - TDI -
3 0 A8 A^8 B0 B^0
4 0 A9 A^9 B2 B^1
5 0 A10 A^10 B4 B^2
6 0 A11 A^11 B6 B^3
7 0 GND (Bank 0) - GND (Bank 0) -
8 0 A12 A^12 B8 B^4
9 0 A13 A^13 B10 B^5
10 0 A14 A^14 B12 B^6
11 0 A15 A^15 B13 B^7
12* 0 I - I -
13 0 VCCO (Bank 0) - VCCO (Bank 0) -
14 0 B15 B^15 C14 C^7
15 0 B14 B^14 C12 C^6
16 0 B13 B^13 C10 C^5
17 0 B12 B^12 C8 C^4
18 0 GND (Bank 0) - GND (Bank 0) -
19 0 B11 B^11 C6 C^3
20 0 B10 B^10 C5 C^2
21 0 B9 B^9 C4 C^1
22 0 B8 B^8 C2 C^0
23*0I-I-
24 - TCK - TCK -
LA-ispMACH 4032V/Z and 4064V/Z Logic Signal Connections: 48-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4032V/Z LA-ispMACH 4064V/Z
GLB/MC/Pad ORP GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
32
25 - VCC - VCC -
26 - GND - GND -
27*0I-I-
28 0 B7 B^7 D13 D^7
29 0 B6 B^6 D12 D^6
30 0 B5 B^5 D10 D^5
31 0 B4 B^4 D8 D^4
32 0 GND (Bank 0) - GND (Bank 0) -
33 0 VCCO (Bank 0) - VCCO (Bank 0) -
34 0 B3 B^3 D6 D^3
35 0 B2 B^2 D4 D^2
36 0 B1 B^1 D2 D^1
37 0 B0 B^0 D0 D^0
38 0 CLK1/I - CLK1/I -
39 1 CLK2/I - CLK2/I -
40 - VCC - VCC -
41 1 C0 C^0 E0 E^0
42 1 C1 C^1 E2 E^1
43 1 C2 C^2 E4 E^2
44 1 C3 C^3 E6 E^3
45 1 VCCO (Bank 1) - VCCO (Bank 1) -
46 1 GND (Bank 1) - GND (Bank 1) -
47 1 C4 C^4 E8 E^4
48 1 C5 C^5 E10 E^5
49 1 C6 C^6 E12 E^6
50 1 C7 C^7 E14 E^7
51 - GND - GND -
52 - TMS - TMS -
53 1 C8 C^8 F0 F^0
54 1 C9 C^9 F2 F^1
55 1 C10 C^10 F4 F^2
56 1 C11 C^11 F6 F^3
57 1 GND (Bank 1) - GND (Bank 1) -
58 1 C12 C^12 F8 F^4
59 1 C13 C^13 F10 F^5
60 1 C14 C^14 F12 F^6
61 1 C15 C^15 F13 F^7
62*1I-I-
63 1 VCCO (Bank 1) - VCCO (Bank 1) -
64 1 D15 D^15 G14 G^7
65 1 D14 D^14 G12 G^6
66 1 D13 D^13 G10 G^5
67 1 D12 D^12 G8 G^4
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4064V/Z LA-ispMACH 4128V/Z
GLB/MC/Pad ORP GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
33
68 1 GND (Bank 1) - GND (Bank 1) -
69 1 D11 D^11 G6 G^3
70 1 D10 D^10 G5 G^2
71 1 D9 D^9 G4 G^1
72 1 D8 D^8 G2 G^0
73*1I-I-
74 - TDO - TDO -
75 - VCC - VCC -
76 - GND - GND -
77*1I-I-
78 1 D7 D^7 H13 H^7
79 1 D6 D^6 H12 H^6
80 1 D5 D^5 H10 H^5
81 1 D4 D^4 H8 H^4
82 1 GND (Bank 1) - GND (Bank 1) -
83 1 VCCO (Bank 1) - VCCO (Bank 1) -
84 1 D3 D^3 H6 H^3
85 1 D2 D^2 H4 H^2
86 1 D1 D^1 H2 H^1
87 1 D0/GOE1 D^0 H0/GOE1 H^0
88 1 CLK3/I - CLK3/I -
89 0 CLK0/I - CLK0/I -
90 - VCC - VCC -
91 0 A0/GOE0 A^0 A0/GOE0 A^0
92 0 A1 A^1 A2 A^1
93 0 A2 A^2 A4 A^2
94 0 A3 A^3 A6 A^3
95 0 VCCO (Bank 0) - VCCO (Bank 0) -
96 0 GND (Bank 0) - GND (Bank 0) -
97 0 A4 A^4 A8 A^4
98 0 A5 A^5 A10 A^5
99 0 A6 A^6 A12 A^6
100 0 A7 A^7 A14 A^7
*This pin is input only.
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4064V/Z LA-ispMACH 4128V/Z
GLB/MC/Pad ORP GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
34
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4128V
GLB/MC/Pad ORP
1 0 GND -
2 0 TDI -
3 0 VCCO (Bank 0) -
4 0 B0 B^0
5 0 B1 B^1
6 0 B2 B^2
7 0 B4 B^3
8 0 B5 B^4
9 0 B6 B^5
10 0 GND (Bank 0) -
11 0 B8 B^6
12 0 B9 B^7
13 0 B10 B^8
14 0 B12 B^9
15 0 B13 B^10
16 0 B14 B^11
17 0 VCCO (Bank 0) -
18 0 C14 C^11
19 0 C13 C^10
20 0 C12 C^9
21 0 C10 C^8
22 0 C9 C^7
23 0 C8 C^6
24 0 GND (Bank 0) -
25 0 C6 C^5
26 0 C5 C^4
27 0 C4 C^3
28 0 C2 C^2
29 0 C0 C^0
30 0 VCCO (Bank 0) -
31 0 TCK -
32 0 VCC -
33 0 GND -
34 0 D14 D^11
35 0 D13 D^10
36 0 D12 D^9
37 0 D10 D^8
38 0 D9 D^7
39 0 D8 D^6
40 0 GND (Bank 0) -
41 0 VCCO (Bank 0) -
42 0 D6 D^5
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
35
43 0 D5 D^4
44 0 D4 D^3
45 0 D2 D^2
46 0 D1 D^1
47 0 D0 D^0
48 0 CLK1/I -
49 1 GND (Bank 1) -
50 1 CLK2/I -
51 1 VCC -
52 1 E0 E^0
53 1 E1 E^1
54 1 E2 E^2
55 1 E4 E^3
56 1 E5 E^4
57 1 E6 E^5
58 1 VCCO (Bank 1) -
59 1 GND (Bank 1) -
60 1 E8 E^6
61 1 E9 E^7
62 1 E10 E^8
63 1 E12 E^9
64 1 E14 E^11
65 1 GND -
66 1 TMS -
67 1 VCCO (Bank 1) -
68 1 F0 F^0
69 1 F1 F^1
70 1 F2 F^2
71 1 F4 F^3
72 1 F5 F^4
73 1 F6 F^5
74 1 GND (Bank 1) -
75 1 F8 F^6
76 1 F9 F^7
77 1 F10 F^8
78 1 F12 F^9
79 1 F13 F^10
80 1 F14 F^11
81 1 VCCO (Bank 1) -
82 1 G14 G^11
83 1 G13 G^10
84 1 G12 G^9
85 1 G10 G^8
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP (Cont.)
Pin Number Bank Number
LA-ispMACH 4128V
GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
36
86 1 G9 G^7
87 1 G8 G^6
88 1 GND (Bank 1) -
89 1 G6 G^5
90 1 G5 G^4
91 1 G4 G^3
92 1 G2 G^2
93 1 G0 G^0
94 1 VCCO (Bank 1) -
95 1 TDO -
96 1 VCC -
97 1 GND -
98 1 H14 H^11
99 1 H13 H^10
100 1 H12 H^9
101 1 H10 H^8
102 1 H9 H^7
103 1 H8 H^6
104 1 GND (Bank 1) -
105 1 VCCO (Bank 1) -
106 1 H6 H^5
107 1 H5 H^4
108 1 H4 H^3
109 1 H2 H^2
110 1 H1 H^1
111 1 H0/GOE1 H^0
112 1 CLK3/I -
113 0 GND (Bank 0) -
114 0 CLK0/I -
115 0 VCC -
116 0 A0/GOE0 A^0
117 0 A1 A^1
118 0 A2 A^2
119 0 A4 A^3
120 0 A5 A^4
121 0 A6 A^5
122 0 VCCO (Bank 0) -
123 0 GND (Bank 0) -
124 0 A8 A^6
125 0 A9 A^7
126 0 A10 A^8
127 0 A12 A^9
128 0 A14 A^11
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP (Cont.)
Pin Number Bank Number
LA-ispMACH 4128V
GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
37
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP
Pin Number Bank Number
LA-ispMACH 4128V
GLB/MC/Pad ORP
1 - GND -
2 - TDI -
3 0 VCCO (Bank 0) -
4 0 B0 B^0
5 0 B1 B^1
6 0 B2 B^2
7 0 B4 B^3
8 0 B5 B^4
9 0 B6 B^5
10 0 GND (Bank 0) -
11 0 B8 B^6
12 0 B9 B^7
13 0 B10 B^8
14 0 B12 B^9
15 0 B13 B^10
16 0 B14 B^11
17 - NC -
18 0 GND (Bank 0)1-
19 0 VCCO (Bank 0) -
20 0 NC -
21 0 C14 C^11
22 0 C13 C^10
23 0 C12 C^9
24 0 C10 C^8
25 0 C9 C^7
26 0 C8 C^6
27 0 GND (Bank 0) -
28 0 C6 C^5
29 0 C5 C^4
30 0 C4 C^3
31 0 C2 C^2
32 0 C1 C^1
33 0 C0 C^0
34 0 VCCO (Bank 0) -
35 - TCK -
36 - VCC -
37 - GND -
38 0 NC -
39 0 D14 D^11
40 0 D13 D^10
41 0 D12 D^9
42 0 D10 D^8
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
38
43 0 D9 D^7
44 0 D8 D^6
45 0 NC -
46 0 GND (Bank 0) -
47 0 VCCO (Bank 0) -
48 0 D6 D^5
49 0 D5 D^4
50 0 D4 D^3
51 0 D2 D^2
52 0 D1 D^1
53 0 D0 D^0
54 0 CLK1/I -
55 1 GND (Bank 1) -
56 1 CLK2/I -
57 - VCC -
58 1 E0 E^0
59 1 E1 E^1
60 1 E2 E^2
61 1 E4 E^3
62 1 E5 E^4
63 1 E6 E^5
64 1 VCCO (Bank 1) -
65 1 GND (Bank 1) -
66 1 E8 E^6
67 1 E9 E^7
68 1 E10 E^8
69 1 E12 E^9
70 1 E13 E^10
71 1 E14 E^11
72 1 NC -
73 - GND -
74 - TMS -
75 1 VCCO (Bank 1) -
76 1 F0 F^0
77 1 F1 F^1
78 1 F2 F^2
79 1 F4 F^3
80 1 F5 F^4
81 1 F6 F^5
82 1 GND (Bank 1) -
83 1 F8 F^6
84 1 F9 F^7
85 1 F10 F^8
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
Pin Number Bank Number
LA-ispMACH 4128V
GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
39
86 1 F12 F^9
87 1 F13 F^10
88 1 F14 F^11
89 1 NC -
90 1 GND (Bank 1)1-
91 1 VCCO (Bank 1) -
92 1 NC -
93 1 G14 G^11
94 1 G13 G^10
95 1 G12 G^9
96 1 G10 G^8
97 1 G9 G^7
98 1 G8 G^6
99 1 GND (Bank 1) -
100 1 G6 G^5
101 1 G5 G^4
102 1 G4 G^3
103 1 G2 G^2
104 1 G1 G^1
105 1 G0 G^0
106 1 VCCO (Bank 1) -
107 - TDO -
108 - VCC -
109 - GND -
110 1 NC -
111 1 H14 H^11
112 1 H13 H^10
113 1 H12 H^9
114 1 H10 H^8
115 1 H9 H^7
116 1 H8 H^6
117 1 NC -
118 1 GND (Bank 1) -
119 1 VCCO (Bank 1) -
120 1 H6 H^5
121 1 H5 H^4
122 1 H4 H^3
123 1 H2 H^2
124 1 H1 H^1
125 1 H0/GOE1 H^0
126 1 CLK3/I -
127 0 GND (Bank 0) -
128 0 CLK0/I -
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
Pin Number Bank Number
LA-ispMACH 4128V
GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
40
129 - VCC -
130 0 A0/GOE0 A^0
131 0 A1 A^1
132 0 A2 A^2
133 0 A4 A^3
134 0 A5 A^4
135 0 A6 A^5
136 0 VCCO (Bank 0) -
137 0 GND (Bank 0) -
138 0 A8 A^6
139 0 A9 A^7
140 0 A10 A^8
141 0 A12 A^9
142 0 A13 A^10
143 0 A14 A^11
144 0 NC2-
1. For device migration considerations, these NC pins are GND pins for I/O banks in LA-ispMACH 4128V devices.
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
Pin Number Bank Number
LA-ispMACH 4128V
GLB/MC/Pad ORP
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
41
Part Number Description
Ordering Information
Automotive Disclaimer
Products are not designed, intended or warranted to be fail-safe and are not designed, intended or warranted for
use in applications related to the deployment of airbags. Further, products are not intended to be used, designed or
warranted for use in applications that affect the control of the vehicle unless there is a fail-safe or redundancy fea-
ture and also a warning signal to the operator of the vehicle upon failure. Use of products in such applications is
fully at the risk of the customer, subject to applicable laws and regulations governing limitations on product liability.
For Further Information
In addition to this data sheet, the following technical notes may be helpful when designing with the LA-ispMACH
4000V/Z automotive family:
• TN1004, ispMACH 4000 Timing Model Design and Usage Guidelines
• TN1005, Power Estimation in ispMACH 4000V/B/C/Z Devices
Device Part Number Macrocells Voltage tPD Package
Pin/Ball
Count I/O Grade
LA4032V LA4032V-75TN48E 32 3.3 7.5 Lead-free TQFP 48 32 E
LA4032V-75TN44E 32 3.3 7.5 Lead-free TQFP 44 30 E
LA4064V
LA4064V-75TN100E 64 3.3 7.5 Lead-free TQFP 100 64 E
LA4064V-75TN48E 64 3.3 7.5 Lead-free TQFP 48 32 E
LA4064V-75TN44E 64 3.3 7.5 Lead-free TQFP 44 30 E
LA4128V
LA4128V-75TN144E 128 3.3 7.5 Lead-free TQFP 144 96 E
LA4128V-75TN128E 128 3.3 7.5 Lead-free TQFP 128 92 E
LA4128V-75TN100E 128 3.3 7.5 Lead-free TQFP 100 64 E
LA4032Z LA4032ZC-75TN48E 32 1.8 7.5 Lead-free TQFP 48 32 E
LA4064Z LA4064ZC-75TN100E 64 1.8 7.5 Lead-free TQFP 100 64 E
LA4064ZC-75TN48E 64 1.8 7.5 Lead-free TQFP 48 32 E
LA4128Z LA4128ZC-75TN100E 128 1.8 7.5 Lead-free TQFP 100 64 E
Device Number
4032 = 32 Macrocells
4064 = 64 Macrocells
4128 = 128 Macrocells
LA XXXX XX – XX XX XXX X
Power
Blank = Low Power
Z = Zero Power
Supply Voltage
V = 3.3V
C = 1.8V
Device Family
Speed
75 = 7.5ns
Pin/Ball Count
44 (1.0mm thickness)
48 (1.0mm thickness)
100
128
144
Package
TN = Lead-free TQFP
Operating Temperature Range
E = Automotive
Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
42
Revision History
Date Version Change Summary
April 2006 01.0 Initial release.
October 2006 02.0 Added LA-ispMACH 4000Z support information throughout.
March 2007 02.1 Updated ispMACH 4000 Introduction section.
Updated Signal Descriptions table.
September 2007 02.2 DC Electrical Characteristics table, removed duplicate specifications.
July 2008 02.3 Lowered the maximum supply current at 85°C to match the commercial product values.
Added automotive disclaimer.
May 2009 02.4 Correction to tCW, tGW, tWIR and fMAX parameters in External Switching Characteristics table.
May 2009 02.5 Correction to tCW, tGW and tWIR parameters in External Switching Characteristics table.
