@ 20070HBook Page 1 Tuesday, July 7, 1998 12:00 PM MICROCHIP 24LC16B 16K 2.5V 2C" Serial EEPROM FEATURES Single supply with operation down to 2.5V Low power CMOS technology - 1 mA active current typical - 10 pA standby current typical at 5.5V - 5 A standby current typical at 3.0V Organized as 8 blocks of 256 bytes (8 x 256 x 8) 2-wire serial interface bus, I2 compatible Schmitt trigger inputs for noise suppression Output slope control to eliminate ground bounce 100 kHz (2.5V) and 400 kHz (5V) compatibility Self-timed write cycle (including auto-erase) * Page-write buffer for up to 16 bytes * 2 ms typical write cycle time for page-write * Hardware write protect for entire memory * Can be operated as a serial ROM * Factory programming (QTP) available * ESD protection > 4,000V * 1,000,000 erase/write cycles guaranteed * Data retention > 200 years * 8-pin DIP, 8-lead or 14-lead SOIC packages Available for extended temperature ranges - Commercial (C): orc to +70C - Industrial (I): -40C to +85C DESCRIPTION The Microchip Technology Inc. 24LC16B is a 16K bit Electrically Erasable PROM. The device is organized as eight blocks of 256 x 8 bit memory with a 2-wire serial interface. Low voltage design permits operation down to 2.5 volts with standby and active currents of only 5 pA and 1 mA respectively. The 24LC16B also has a page-write capability for up to 16 bytes of data. The 24LC16B is available in the standard 8-pin DIP and both 8-lead and 14-lead surface mount SOIC pack- ages. PC is a trademark of Philips Corporation. 1998 Microchip Technology Inc. PACKAGE TYPES Vs PDIP Ao(}1 8[]Vcc At L2 % 7[]wP a A2[]3 & 6{]SCL vss []4 5 ]SDA soic 4 Aoc_] 1 8T vce acl? 8 7 owe a acl 8 &[yser vssc_| 4 51 4 spa UY soe Nec | INC AoL_| 1 8 ea Vec AIL 5 Twp Cc 7 Nec] Q | INC acl] 3 6 scr VssL_ 4 5 4 SDA NCC | INC BLOCK DIAGRAM WP 1 HV GENERATOR ie) MEMORY Lm} EEPROM CONTROL et CONTROL{o> ARRAY LOGIC LOGIC XDEC-e PAGE LATCHES SDA SCL vec [> SENSE AMP Vss [> RAW CONTROL DS20070H-page 1@ 20070HBook Page 2 Tuesday, July 7, 1998 12:00 PM 24LC16B 1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: | PINFUNCTION TABLE 1.1 Maximum Ratinqgs* Name Function VCC cessessoseessssenesessereeenzsessssnesseensesssennsstnnssesessenseee 7.0V vss Ground ..0.3V to Voc +1.0V SDA Serial Address/Data I/O All inputs and outputs w.r.t. VSS Storage temperature oo... cesses -65C to +150C SCL Serial Clock Ambient temp. with power applied.............. -65C to +125C . Soldering temperature of leads (10 seconds). . +300C wp Write Protect Input ESD protection on all pins... 24kV Vcc +2.5V to 5.5V Power Supply *Notice: Stresses above those listed under Maximum ratings AO, At, A2 No Internal Connection may cause permanent damage to the device. This is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: DC CHARACTERISTICS Vec = +2.5V to +5.5V Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C Parameter Symbol Min Max Units Conditions WP, SCL and SDA pins: High level input voltage VIH .7 VCC _ Vv Low level input voltage VIL _ 3 Voc Vv Hysteresis of Schmitt trigger VHYS .05 Vcc _ Vv (Note) inputs 0 Low level output voltage VOL _ .40 Vv loL = 3.0 mA, Vcc = 2.5V 0 Input leakage current ILI -10 10 HA |VIN=.1V to Vcc Output leakage current ILo -10 10 HA | VOUT =.1V to Voc Pin capacitance CIN, COUT _ 10 pF Vcc = 5.0V (Note) (all inputs/outputs) Tamb = 25C, FCLkK = 1MHz Operating current Icc write _ 3 mA | Vcc = 5.5V, SCL = 400 kHz Icc read _ 1 mA Standby current Iccs _ 30 HA | Vcc =3.0V, SDA = SCL = Vcc _ 100 HA | Vcc = 5.5V, SDA=SCL = Vcc WP =Vss Note: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: | BUS TIMING START/STOP SCL / TSU:STA 7 THD:STA TSU:STO SDA ; /..\ : tf Le on START STOP DS20070H-page 2 1998 Microchip Technology Inc.@ 20070HBook Page 3 Tuesday, July 7, 1998 12:00 PM 24LC16B TABLE 1-3: AC CHARACTERISTICS STANDARD Vee = 4.5V - 5.5V Parameter Symbol MODE FAST MODE Units Remarks Min Max Min Max Clock frequency FCLK _ 100 _ 400 kHz Clock high time THIGH 4000 _ 600 _ ns Clock low time TLOW 4700 _ 1300 = ns SDA and SCL rise time TR _ 1000 _ 300 ns__ | (Note 1) SDA and SCL fall time TF _ 300 _ 300 ns__ | (Note 1) START condition hold time | THD:sTA} 4000 _ 600 _ ns_ | After this period the first clock pulse is generated START condition setup time | Tsu:sTA | 4700 _ 600 _ ns_ | Only relevant for repeated START condition Data input hold time THD:DAT 0 _ 0 _ ns Data input setup time TSU:DAT| 250 _ 100 _ ns STOP condition setup time | TsU:sTo} 4000 = 600 _ ns Output valid from clock TAA _ 3500 _ 900 ns__ | (Note 2) Bus free time TBUF 4700 _ 1300 _ ns_ | Time the bus must be free before a new transmission can start Output fall time from VIH TOF _ 250 =| 20+0.1 250 ns_ | (Note 1), CB < 100 pF min to VIL max CB Input filter spike suppres- TSP _ 50 _ 50 ns_ | (Note 3) sion (SDA and SCL pins) Write cycle time TWR _ 10 _ 10 ms_ | Byte or Page mode 0 Endurance _ 1M _ 1M _ cycles | 25C, Vcc = 5.0V, Block 0 Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TsP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website. FIGURE 1-2: BUSTIMING DATA TF TR SCL te SU:DAT TSU:STO>] SCL -- : | THD:STA TBUF SCL OUT 1998 Microchip Technology Inc. DS20070H-page 3@ 20070HBook Page 4 Tuesday, July 7, 1998 12:00 PM 24LC16B 2.0 FUNCTIONAL DESCRIPTION The 24LC16B supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LC16B works as slave. Both, master and slave can operate as transmitter or receiver but the master device deter- mines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Bus not Busy (A) Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condi- tion. 3.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 3.4 Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last six- teen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24LC16B does not generate any acknowledge bits if an internal program- ming cycle is in progress. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24LC16B) will leave the data line HIGH to enable the master to generate the STOP condition. FIGURE 3-1: _DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) | A) SCL \ I / SDA TT \ JT re If ut 1 tl START ADDRESS OR DATA STOP CONDITION ACKNOWLEDGE ALLOWED CONDITION VALID TO CHANGE DS20070H-page 4 1998 Microchip Technology Inc.@ 20070HBook Page S Tuesday, July 7, 1998 12:00 PM 24LC16B 3.6 Device Addressing A control byte is the first byte received following the start condition from the master device. The control byte consists of a four bit control code, for the 24LC16B this is set as 1010 binary for read and write operations. The next three bits of the control byte are the block select bits (B2, B1, BO). They are used by the master device to select which of the eight 256 word blocks of memory are to be accessed. These bits are in effect the three most significant bits of the word address. It should be noted that the protocol limits the size of the memory to eight blocks of 256 words, therefore the pro- tocol can support only one 24LC16B per system. The last bit of the control byte defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Following the start condition, the 24LC16B monitors the SDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC16B will select a read or write operation. Operation Control Block Select | R/W Read 1010 Block Address 1 Write 1010 Block Address 0 FIGURE 3-2: CONTROL BYTE ALLOCATION START READ/WRITE , SLAVE ADDRESS my A | , . 1 0 1 0 Xx Xx Xx X = Don't care 4.0 WRITE OPERATION 4.1 Byte Write Following the start condition from the master, the device code (4 bits), the block address (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will fol- low after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmit- ted by the master is the word address and will be writ- ten into the address pointer of the 24LC16B. After receiving another acknowledge signal from the 24LC16B the master device will transmit the data word to be written into the addressed memory location. The 24LC16B acknowledges again and the master gener- ates a stop condition. This initiates the internal write cycle, and during this time the 24LC16B will not gener- ate acknowledge signals (Figure 4-1). 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LC16B in the same way as in a byte write. But instead of generating a stop con- dition the master transmits up to 16 data bytes to the 24LC16B which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remains constant. If the master should transmit more than 16 words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (Figure 4-2). FIGURE 4-1: BYTE WRITE s s $ BUS ACTIVITY A CONTROL WORD DATA T MASTER A BYTE ADDRESS oO Ty AY . AY A P TT TT TTT TTT SDA LINE s P | | | J | Lt |] | | J | A A A BUS ACTIVITY c Cc c K K K FIGURE 4-2: PAGE WRITE Ss s BUS ACTIVITY h T MASTER R CON et appa (n) DATA n DATAn +1 DATA n+15 . T A. A a a. AN TTTTIqgTg. TTTTITqTg. TTTTqTqgT. TTITTT SDA LINE SUL | L LX LF | Jj tj i | J | Jt 1 1 i 1 1 jt] i tt | Jj i 1 A A A A BUS ACTIVITY c Cc c c Cc K K K K 1998 Microchip Technology Inc. DS20070H-page 5@ 20070HBook Page 6 Tuesday, July 7, 1998 12:00 PM 24LC16B 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send- ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle ! Send Start i 4 Send Control Byte with RW =0 Did Device Acknowledge Next Operation 6.0 WRITE PROTECTION The 24LC16B can be used as a serial ROM when the WP pin is connected to Vcc. Programming will be inhibited and the entire memory will be write-protected. 7.0 READ OPERATION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 7.1 Current Address Read The 24LC16B contains an address counter that main- tains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LC16B issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does gen- erate a stop condition and the 24LC16B discontinues transmission (Figure 7-1). 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC16B as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC16B will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC16B dis- continues transmission (Figure 7-2). 7.3 Sequential Read Sequential reads are initiated in the same way as a ran- dom read except that after the 24LC16B transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LC16B to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads the 24LC16B contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 7.4 Noise Protection The 24LC16B employs a Vcc threshold detector circuit which disables the internal erase/write logic if the Vcc is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. DS20070H-page 6 1998 Microchip Technology Inc.@ 20070HBook Page 7 Tuesday, July 7, 1998 12:00 PM 24LC16B FIGURE 7-1: CURRENT ADDRESS READ s BUS ACTIVITY A CONTROL $ MASTER R BYTE DATA n O T P SDA LINE s| >| A N BUS ACTIVITY c A c K FIGURE 7-2: RANDOM READ ; ; ; BUS ACTIVITY CONTROL WORD CONTROL oO MASTER A BYTE ADDRESS (n) a BYTE DATA (n) P T . T SDA LINE is Phiri s Pitiridt A A A N c c c oO K K BUS ACTIVITY A c K FIGURE 7-3: SEQUENTIAL READ s T Kae NITY CONTROL DATAn DATAn +1 DATAn +2 DATAn+X , an sy TTTTITl TTTIItil rer TrTT) Th TTTIItit SDA LINE ee ee iil C C C C 5 BUS ACTIVITY K K K K A c K 8.0 PIN DESCRIPTIONS 8.3 WP 8.1 SDA Serial Address/Data Input/ Qutput This is a Bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to Vcc (typical 10KQ for 100 kHz, 2 KQ for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP condi- tions. 8.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. This pin must be connected to either Vss or Vcc. If tied to Vss normal memory operation is enabled (read/write the entire memory 000-7FF). If tied to Vcc, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected. This feature allows the user to use the 24LC16B as a serial ROM when WP is enabled (tied to Vcc). 8.4 AO, Ai, A2 These pins are not used by the 24LC16B. They may be left floating or tied to either Vss or Vcc. 1998 Microchip Technology Inc. DS20070H-page 7@ 20070HBook Page 8 Tuesday, July 7, 1998 12:00 PM & 24LC16B NOTES: DS20070H-page 8 1998 Microchip Technology Inc.@ 20070HBook Page 9 Tuesday, July 7, 1998 12:00 PM 24LC16B NOTES: 1998 Microchip Technology Inc. DS20070H-page 9@ 20070HBook Page 10 Tuesday, July 7, 1998 12:00 PM & 24LC16B NOTES: DS20070H-page 10 1998 Microchip Technology Inc.@ 20070HBook Page 11 Tuesday, July 7, 1998 12:00 PM 24LC16B 24LC16B Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24LC16B - iP P = Plastic DIP (300 mil Body), 8-lead Package: SL = Plastic SOIC (150 mil Body), 14-lead SN = Plastic SOIC (150 mil Body), 8-lead Temperature Blank = 0C to +70C Range: I = -40C to +85C Device: 24LC16B 16K IC Serial EEPROM . 24LC16BT 16K IC Serial EEPROM (Tape and Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com) 1998 Microchip Technology Inc. DS20070H-page 11@ 20070HBook Page 12 Tuesday, July 7, 1998 12:00 PM MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http ://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Dayton Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 6/11/98 The Netherlands DNV Corngation, Inc. DNV MSC of ED on Accredited by the RvA Ai iS > ANSI-RAB Chet? PNW) REGISTERED. FIRM Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PiCmicro 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (1SO). All rights reserved. 1998, Microchip Technology Incorporated, USA. 7/98 > Printed on recycled paper. Tnfomraticn contaired in this publication regarding device applications ard the like is intercd for suogestion only and may be suparsaded by updates. Nb representation or warranty is given ard no liability is assured by Microchip Tacmollogy Thoorporated with respact to the accuracy or use of such infomation, or infrirgarent of intellectual or otherwise. Use of Microchips products as critical components in life suport systats is rot authorized exogt with express written agoroval by Microchip. Nb licenses are cxneyed, inplicitly or otherwise, under arly intellectual proparty rights. The Microdnip Jogo ard nane are registered tradstarks of Microchip Tecrology Ihe. in the U.S.A. and cther cuntries. All rights reserved All cthar traderarks menticred herein are the property of their respective camanies. patents or other proparty rights arising fron such use 20070H-page 12 @ 1998 Microchip Technology Inc.