YA18 2.5 Gb/s Clock and Data Recovery Circuit Data Sheet Features Fully balanced, differential architecture from input to output Differential CML data input accepts signals of up to 2.7 Gb/s data rates - 50 terminated 50 terminated differential CML recovered clock and data outputs The Nortel Networks YA18 Clock and Data Recovery Circuit is a bipolar monolithic clock and data recovery device that accepts a nominal 2.5 Gb/s data stream and extracts a 2.5 GHz clock and the retimed 2.5 Gb/s data. of board real-estate and ultimately cost savings to the designer of fiber-based datacom or telecom solutions. The YA18 is fabricated using a high yield, silicon bipolar process. It is available in industry-standard packaging. The YA18 provides for power and chip-count savings that translate into better utilization Single 3.3 V supply for simplified system integration. On-chip regulator for 5 V operation Interface with 3.3 V or 5 V demultiplexers 16 Industry standard 7 mm LQFP package Applications SONET/SDH-based transmission systems, test equipment and modules Data 155 Mb/s 16:1 MUX & CLK GEN Overhead Processor Meets or exceeds all relevant ANSI, ITU and Bellcore specifications YA08 YA19 155 MHz 2 LDD 2.5 Gb/s Clk YA20 16 155 Mb/s YA18 1:16 DEMUX Data 2.5 Gb/s 2 2 OC-48 fiber optic modules and line termination WDM for 2.5 Gb/s SONET applications ATM over SONET/SDH Section repeaters, muxes, terminators, broadband cross-connects 155 MHz Clk AB89 AC10 2 Data Clk 2.5GHz Figure 1: System Block Diagram Clock & Data Recovery 2 AGC Post Amplifier 2 PRE AMP Functional Description The YA18 uses phase lock loop techniques to recover a high frequency clock from NRZ binary data presented to pins RXD_INP and RXD_INN at nominally 2.5 Gb/s. For SONET/SDH applications the device is tuned during manufacture to provide a VCO centre frequency close to 2.488 GHz. This coarse tuning is performed during production, so that no additional trimming is required for VCO alignment. Variants of the YA18 have been developed that enable coarse tuning to be performed using an external digital word. For 3.3 V operation, the only external components required are decoupling capacitors and loop filter components. System Inputs Inputs RXD_INP and RXD_INN are fully differential CML inputs designed to receive signals from a post amplifier. Normally, this would be the Nortel Networks AC10 Automatic Gain Control (AGC) Amplifier. These inputs include on-chip termination resistors of nominally 50 . GND_DATA should be connected to input ground. 2 YA18 2.5 Gb/s Clock and Data Recovery Circuit Phase Locked Loop Loss of Lock (LOL) Output The PLL used in the YA18 is a fully balanced differential design comprising VCO and phase/frequency detector. The VCO has been designed to minimize jitter and the effects of temperature and supply voltage ripple. The VCO centre frequency is digitally programmed during manufacture to minimize process variations. This also allows the device to be potentially set to frequencies other than exactly 2.488 GHz. The loss of lock indicator is an open-collector output (active low) which functions by monitoring cycle slips of the input relative to the VCO. It will be active for at least 2.5 s after the most recent frequency correction pulse, by which time the loop is assumed to be in phase lock and data is assumed to be valid. The loss of lock signal may be extended with external circuitry if required. The frequency correction current pulse is emitted if the phase of the data with respect to the clock is observed to slip past the 180 point. System Outputs Both the recovered clock outputs CK2G5_OUTP and CK2G5_OUTN, and the retimed data outputs RXD_OUTP and RXD_OUTN, are 400 mV CML differential drivers that are designed to drive corresponding CML inputs. In the case of the Nortel Networks YA20 1:16 Demultiplexer, these provide the required 50 termination. The data output transitions are retimed to the falling edge of the recovered clock, i.e. the falling edge of pin CK2G5_OUTP. These four output pins are provided with a local supply rail connected to pin VCC_OUT, which can be connected to VCC for 3.3 V output levels, or can be connected to a separate 5 V supply, if 5 V compatible output levels are required. Test Inputs and Outputs Various test inputs are available to enable testing at low speeds. These inputs, which are not internally terminated, bypass the internal VCO. Under normal operation these test inputs must be connected to 3.3 V. A divider is included to divide the 2.5 GHz VCO output down to 155 MHz, which is delivered as a single-ended low power PECL output at pin CK155_OUT. Under normal operation this output should be connected to 3.3 V. VCC_OUT RXD_OUTP RETIMING AND CML OUTPUT DRIVE RXD_INP BUFFER RXD_INN RXD_OUTN CK2G5_OUTP CK2G5_OUTN RECOVERED 2.5GHZ CLOCK PHASE LOCKED LOOP TEST_EN TESTCK LOL CK155_OUT TESTCQ OFF-CHIP LOOP COMPONENTS Figure 2: Functional Block Diagram Absolute Maximum Ratings These are stress ratings only. Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability of the device. Avoid operating the device outside the recommended operating conditions defined below. Symbol Parameter Min Max Unit VCC Supply voltage - any VCC pin any VCC_OUT pin -0.7 -0.7 5.0 6.0 V V VI Input voltage - PECL and/or CML (single ended wrt GND) 0 VCC +0.5 V IO Output current - PECL or CML -50 mA VO oc Input voltage - open collector outputs -0.5 VCC +0.5 V Tstg Storage temperature -65 135 C Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VCC Supply voltage - any VCC pin 3.13 3.3 3.47 V VCC_OUT Supply voltage for clock and data outputs 3.13 3.3 or 5.0 5.25 V VIDcml CML differential input voltage (peak to peak) 40 350 750 mV pk - pk VIHpecl PECL input HIGH voltage VCC -1.165 VCC -0.88 V VILpecl PECL input LOW voltage VCC -1.81 VCC -1.475 V Tamb Operating ambient temperature -40 85 C YA18 2.5 Gb/s Clock and Data Recovery Circuit 3 DC Electrical Characteristics Over recommended operating conditions, output load 50 , VX= VCC_OUT for CML outputs. Symbol Parameter Min Typ Max Unit VO (p-p) CML differential output voltage (peak) 370 400 430 mV VOHcml CML output HIGH voltage, referenced to VCC_OUT VX -0.01 VX VX +0.01 V VOLcml CML output LOW voltage, referenced to VCC_OUT VX -0.42 VX -0.40 VX -0.38 V VOHpecl PECL output HIGH voltage VCC -1.2 VCC -0.88 V VOLpecl PECL output LOW voltage VCC -1.81 VCC -1.52 V IOHpecl PECL input HIGH current (VIH = VCC -0.88V) 100 A IOLpecl PECL input LOW current (VIL = VCC -1.81V) 50 A RINdiff Differential input resistance 85 100 115 RINeff Effective signal input resistance 42 50 58 ICC Supply current (VCC and VCC_OUT) 250 365 mA Pd Device power dissipation 0.83 1.2 W AC Characteristics Over recommended operating conditions, output load 50 , VX= VCCout for CML outputs. Symbol Parameter Min Serial output clock rate Max Unit MHz 2488 Loop acquisition time (223 -1 PRBS) 10 ms Jitter generated at RXD_OUTP/N and CK2G5_OUTP/ N outputs, bandwidth 12 kHz to 20 MHz 0.0075 UI rms Jitter tolerance at jitter frequency of 1 MHz 0.15 UI p-p VCO output variation with VCC (open loop) 15 MHz/V 1000 kHz/C VCO output temperature dependence (open loop) 4 Typ TRcml CML output rise time 50 125 ps TFcml CML output fall time 50 125 ps CKmsr CK2G5_OUTP/N mark to space ratio 40 60 % YA18 2.5 Gb/s Clock and Data Recovery Circuit Typical Operating Characteristics Recovered Clock 250 mV 50 mV /div 100 -250 mV YA 18 Jitter Tolerance 10 100 ps/div Recovered Data 250 mV ITU OC48 Mask 1 50 mV /div 0.1 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz Frequency -250 mV 100 ps/div Figure 3: Recovered Clock and recovered Data Eye Figure 5: Jitter Tolerance Jitter Transfer 1 .5 0 3 ITU OC48 Mask -1 2.5 YA 18 Jitter Transfer 2 -2 Volts -3 1.5 -4 1 -5 0.5 -6 10 kHz 100 kHz 1 MHz Frequency Figure 4: Jitter Transfer 0 1e-10 1e-09 1e-08 1e-07 1e-06 BER 1e-05 1e-04 1e-03 1e-02 Figure 6: Typical Loss of Lock Output for various Bit Error Rates YA18 2.5 Gb/s Clock and Data Recovery Circuit 5 Design Procedure and Applications Information 22 uH ESR = 2.5 R max 1 100 uF GND_CORE VCC_CORE GND_CORE VCC_CORE GND_CORE VCC_CORE GND_CORE GND_CORE CK155_OUT VCC_CORE 37 GND_CORE VCC_CORE 48 GND_CORE TESTCK TESTCKQ VCC_VCO TEST_EN VCO_INN GND_CORE VCO_INP 36 100 nF FD_OUTP VCC_CORE 100 nF 20% YA18 GND_DATA Data Input RX_INP (50R Source) RX_INN Loss of Lock Output AMP_INP 1K AMP_INN Should be connected to ground 8.2 K VCC_CORE LOL (Requires Pullup) 1K FD_OUTN Exposed Heatsink GND_CORE 100 nF 20% 100 nF 8.2 K 82 R PD_OUTN VCC_CORE PD_OUTP VCC_CORE GND_CORE 13 25 GND_CORE GND_CORE IREG_5V GND_CORE VREG_5V RX_OUTN RX_OUTP VCC_OUT CK2G5_OUTN CK2G5_OUTP GND_CORE GND_CORE 82 R 12 24 +5V (Nominal) FZT968 This circuitry only required if device is being operated from a 5V supply Recovered Data Output (3.13 to 5.25 V) Output Supply Note: Capacitors drawn without values are decoupling types consisting of a parallel combination of 100 pF and 10 nF. Recovered Clock Output 10 nF 20% Figure 7: Typical Application Configuration Setting the Loop Filter Input Interfacing The YA18 is designed for regenerator and receiver applications. Its integrated PLL is a fully differential design offering greatly improved power supply rejection over typical single-ended variants, with loop bandwidth set by a pair of identical external networks. The configuration of these networks is shown in Figure 8 with typical component values listed in the Typical Loop Filter Component Values Table. These components should be surface mount parts of 0603 size, with 2% tolerance for resistors up to 2 M, 5% tolerance for capacitors up to 10 nF, and 10% tolerance for capacitors from 10 nF to 100 nF. As with other members of the 2.5 Gb/s optical networking IC family, the high speed (2.5 Gb/s/2.5 GHz) inputs and outputs of the YA18 are configured as fully differential CML signal pairs as shown in Figure 9. The inputs are internally terminated with a 100 resistor between the differential inputs and require a typical differential peak voltage of 350 mV. However, the inputs to the YA18 will continue to operate correctly with a peak differential input voltage as low as 60 mV (see Figure 10). 6 YA18 2.5 Gb/s Clock and Data Recovery Circuit Although the YA18 is specifically designed to interface with the AC10 AGC Amplifier, the internal self-biasing enables the device to be AC-coupled to any differential signal source providing differential voltage levels of between 60 mV and 750 mV peak differential. Single-ended operation not recommended. Typical Loop Filter Component Values Loop bandwidth Damping factor C1 a,b R0 a,b R1 a,b R2 a,b 1800 kHz 5 100 nF 82 8.2 k 1 k AMP_INP VCC R0a FD_OUTP R0b R1a R2a C1a PD_OUTN VCO_INN +-+ Internal loop amp PD_OUTP VCO_INP R1b R2b AMP_INN C1b FD_OUTN Figure 8: Loop Filter Configuration CML OUTPUT CML INPUT VCC VCC 50 50 R R R R OP OPB IP 100 IPB GND GND Figure 9: CML Input and Output Configurations OP 60 mV (min) 750 mV (max) OPB 120 mVp-p (min) 1500 Vp-p (max) OP-OPB Figure 10: CML Differential Voltage Levels YA18 2.5 Gb/s Clock and Data Recovery Circuit 7 Output Interfacing Power Supply Noise The differential CML outputs are configured to provide a nominal peak differential output voltage of 400 mV for simple interfacing to the YA20 1:16 Demultiplexer. Other devices can readily be driven from the output. Although the device has been designed to maximize supply noise rejection, it is recommended that you use an LC filter network shown in Figure 11 between the supply and pin 35 VCC_VCO. Using this configuration, the device will function within the jitter specification with a maximum supply noise of 50 mVpp, over a frequency range from 6 kHz to 2 MHz, on the supply. The effective series resistance of the network must not exceed 2.5 . L = 22 uH (2.5 Wmax.) Vsupply VCC_VCO C = 100 uF YA18 Figure 11: VCO Power Supply Filter 5 V Supply Operation A voltage regulator is provided on the YA18 to enable operation from a 5 V power supply if required. This requires an external circuit as shown in Figure 12. Pin VREG_5V is used to ensure start-up of the regulator and is connected directly to the 5 V supply, pin IREG_5V provides the regulator control current. Both pins should be left open when using a 3.3 V supply. All VCC pins must be connected as shown in Figure 12 and the RXD_INP/N inputs to the chip must be AC coupled for the regulation to function correctly. The recommended discrete PNP transistor is a Zetex +5V Decoupling Capacitance 10 nF 100 F VREG_5 V IREG_5 V +3.3 V YA18 Figure 12: 5 V to 3.3 V Regulator 8 +3.13 V to + 5.25 V YA18 2.5 Gb/s Clock and Data Recovery Circuit VCC_OUT FZT968, packaged in a surface-mounted SOT-223 case. Also suitable are the Zetex FZT1147A, FZT1149A, or FZT1151A in the same package format. A 10 nF surface mount capacitor must be connected across the base-collector of the PNP. When the regulator is used, stability requirements define a 100 nF limit on the maximum decoupling capacitor which can be connected across the 3.3 V supply pins. This value may be exceeded if a few ohms of resistance are placed in series. The circuit stability is not affected by the value of the capacitor on VCC_VCO, which is connected to the 3.3 V supply via an inductor. As a low impedance 5 V supply is required, a 100 F decoupling capacitor is recommended, with placement close to the package pin. Pin Assignment Pin No Symbol Type Description Function 1 TESTCK I PECL Test clock input (connect to GND for normal use) 2 TESTCKQ I PECL Test clock quadrature input (connect to GND for normal use) 3 TEST_EN I 3 V CMOS compatible Test enable input for test clock (connect to GND for normal use) 6 GND_DATA P Data ground to be connected to input ground 4, 9, 13, 14, 20, 23, 24, 25, 36, 37, 38, 41, 42, 44, 46 GND_CORE P Supply ground 5, 11, 12, 28, 39, 40, 43, 47, 48 VCC_CORE P Positive supply voltage (not including clock and data output buffers) 7 RXD_INP I CML Positive differential data input 8 RXD_INN I CML Negative differential data input 10 LOL O Open collector 15 CK2G5_OUTP O CML Positive recovered clock differential output 16 CK2G5_OUTN O CML Negative recovered clock differential output 17 VCC_OUT P 18 RXD_OUTP O CML Positive retimed data differential output 19 RXD_OUTN O CML Negative retimed data differential output 21 VREG_5V P Analog 5.0 V supply for regulator (see Figure 12) 22 IREG_5V P Analog 5 V regulator current control (see Figure 12) 26 PD_OUTP O Analog Loop filter pin 1B 27 PD_OUTN O Analog Loop filter pin 1A 29 AMP_INN I Analog Loop filter pin 2A 30 AMP_INP I Analog Loop filter pin 2B 31 FD_OUTN O Analog Loop filter pin 3A 32 FD_OUTP O Analog Loop filter pin 3B 33 VCO_INP I Analog Loop filter pin 4A 34 VCO_INN I Analog Loop filter pin 4B 35 VCC_VCO P 45 CK155_OUT O Loss of lock output 3.3 V or 5.0 V supply pin for clock and data outputs VCO positive supply voltage PECL VCO divided clock test output YA18 2.5 Gb/s Clock and Data Recovery Circuit 9 48 47 46 45 44 43 42 GND_CORE GND_CORE VCC_CORE VCC_CORE 4 1 40 39 38 37 2 35 VCC_VCO TEST_EN 3 34 VCO_INN GND_CORE 4 33 VCO_INP VCC_CORE 5 32 FD_OUTP GND_CORE 6 YA18 31 FD_OUTN RX_INP 7 TOP VIEW 30 AMP_INP RX_INN 8 29 AMP_INN GND_CORE 9 28 VCC_CORE 10 27 PD_OUTN VCC_CORE 11 26 PD_OUTP VCC_CORE 12 25 GND_CORE Figure 13: 48-pin LQFP Package Pinout (Top View) YA18 2.5 Gb/s Clock and Data Recovery Circuit GND_CORE 23 24 GND_CORE 21 22 IREG_5V 18 19 20 VREG_5V 17 GND_CORE 15 16 RX_OUTN 14 RX_OUTP 13 VCC_OUT TESTCKQ CK2G5_OUTN GND_CORE CK2G5_OUTP 36 GND_CORE 1 GND_CORE TESTCK LOL 10 GND_CORE GND_CORE VCC_CORE GND_CORE CK155_OUT GND_CORE VCC_CORE VCC_CORE Package Pin Configuration Package Outline and Dimensions D D1 A A2 C Exposed Heatsink: 4.32 mm +/- 0.12 mm diam Intrusion: 0.0127 mm max On underside of package. B E A1 Figure 14: Package Outline Dimension Min (mm) Nom (mm) Lead pitch (E) 0.50 Body size (D1) 7.00 Component tip-to-tip (D) 9.00 Component height (A) Max (mm) 1.60 Component standoff (A1) 0.05 Body thickness (A2) 1.35 1.40 1.45 Lead width, plated (B) 0.17 0.22 0.27 Lead thickness, plated (C) 0.09 0.15 0.20 YA18 2.5 Gb/s Clock and Data Recovery Circuit 11 Ordering information Please quote the Product Code from Table 1 below when ordering as this is the identification that appears on the part when shipped. Table 1: Product ordering information Product Code Product Name A0742100 (QMV1050-1AF5) YA18 2.5 Gb/s Clock and Data Recovery Circuit For additional information on Nortel Networks products and services offered, please contact your local representative. Nortel Networks High Performance Optical Component Solutions attn: Marketing Department 2745 Iris Street 6th Floor Ottawa, Ontario Canada K2C 3V5 Copyright 2001 Nortel Networks Corporation. All rights reserved. Nortel, Nortel Networks, the Nortel Networks corporate logo, and the globemark design are trademarks of Nortel Networks Corporation. Any third-party trademarks are the property of their respective owners. The information contained in this document is considered to be accurate as of the date of publication. No liability is assumed by Nortel Networks for use of any information contained in this document, or for infringement of any patent rights or any other proprietary rights of third parties which may result from such use. No license is granted by implication or otherwise under any patent right or any other proprietary right of Nortel Networks. Tel: 1-800-4 NORTEL Fax: 1-613-763-8416 Email: opticalcomponents@nortelnetworks.com www.nortelnetworks.com/hpocs Publication # 84002.37/03-01 Issue 3 Issued: 6 March 2001