of board real-estate and ultimately cost
savings to the designer of fiber-based
datacom or telecom solutions.
The YA18 is fabricated using a high yield,
silicon bipolar process. It is available in
industry-standard packaging.
Data Sheet
Features
Fully balanced, differential
architecture from input to output
Differential CML data input
accepts signals of up to 2.7Gb/s
data rates - 50 Ω terminated
50 Ω terminated differential CML
recovered clock and data outputs
Single 3.3V supply for simplified
system integration. On-chip
regulator for 5V operation
Interface with 3.3V or 5V
demultiplexers
Industry standard 7mm LQFP
package
Meets or exceeds all relevant ANSI,
ITU and Bellcore specifications
Applications
SONET/SDH-based transmission
systems, test equipment and
modules
OC-48 fiber optic modules and
line termination
WDM for 2.5 Gb/s SONET
applications
ATM over SONET/SDH
Section repeaters,muxes,
terminators, broadband
cross-connects
The Nortel Networks YA18 Clock and
Data Recovery Circuit is a bipolar
monolithic clock and data recovery device
that accepts a nominal 2.5 Gb/s data stream
and extracts a 2.5 GHz clock and the
retimed 2.5 Gb/s data.
The YA18 provides for power and chip-count
savings that translate into better utilization
YA18
2.5Gb/s Clock
and
Data Recovery Circuit
Overhead Processor
Clk
2.5GHz
16
Clk
Clk
YA18
YA19
1:16
DEMUX
YA20
155 Mb/s 2
2
2
155 MHz
Data
Data Data Clock &
Data
Recovery
AC10
AGC Post
Amplifier
2
16:1 MUX
& CLK GEN
16
155 Mb/s
155 MHz
2.5 Gb/s
2.5 Gb/s
2
AB89
LDD
YA08
2
PRE AMP
Overhead Processor
Clk
2.5GHz
16
Clk
Clk
YA18
YA19
1:16
DEMUX
YA20
155 Mb/s 2
2
2
155 MHz
Data
Data Data Clock &
Data
Recovery
AC10
AGC Post
Amplifier
2
16:1 MUX
& CLK GEN
16
155 Mb/s
155 MHz
2.5 Gb/s
2.5 Gb/s
2
AB89
LDD
YA08
2
PRE AMP
Figure 1: System Block Diagram
YA18 2.5 Gb/s Clock and Data Recovery Circuit2
Phase Locked Loop
The PLL used in the YA18 is a fully balanced
differential design comprising VCO and
phase/frequency detector. The VCO has
been designed to minimize jitter and the
effects of temperature and supply voltage
ripple. The VCO centre frequency is digi-
tally programmed during manufacture to
minimize process variations. This also
allows the device to be potentially set to
frequencies other than exactly 2.488 GHz.
System Outputs
Both the recovered clock outputs
CK2G5_OUTP and CK2G5_OUTN, and
the retimed data outputs RXD_OUTP
and RXD_OUTN, are 400 mV CML
differential drivers that are designed to
drive corresponding CML inputs. In the
case of the Nortel Networks YA20 1:16
Demultiplexer, these provide the required
50 Ωtermination. The data output transi-
tions are retimed to the falling edge of the
recovered clock, i.e. the falling edge of pin
CK2G5_OUTP. These four output pins
are provided with a local supply rail con-
nected to pin VCC_OUT, which can be
connected to VCC for 3.3 V output levels,
or can be connected to a separate 5 V supply,
if 5 V compatible output levels are required.
Loss of Lock (LOL) Output
The loss of lock indicator is an
open-collector output (active low) which
functions by monitoring cycle slips of the
input relative to the VCO. It will be active
for at least 2.5 µs after the most recent fre-
quency correction pulse, by which time the
loop is assumed to be in phase lock and
data is assumed to be valid. The loss of
lock signal may be extended with external
circuitry if required. The frequency
correction current pulse is emitted if the
phase of the data with respect to the clock
is observed to slip past the 180º point.
Test Inputs and Outputs
Various test inputs are available to enable
testing at low speeds. These inputs, which
are not internally terminated, bypass the
internal VCO. Under normal operation these
test inputs must be connected to 3.3 V.
A divider is included to divide the 2.5 GHz
VCO output down to 155 MHz, which is
delivered as a single-ended low power PECL
output at pin CK155_OUT. Under normal
operation this output should be connected
to 3.3 V.
Functional Description
The YA18 uses phase lock loop techniques
to recover a high frequency clock from
NRZ binary data presented to pins
RXD_INP and RXD_INN at nominally
2.5 Gb/s. For SONET/SDH applications
the device is tuned during manufacture to
provide a VCO centre frequency close to
2.488 GHz. This coarse tuning is performed
during production, so that no additional
trimming is required for VCO alignment.
Variants of the YA18 have been developed
that enable coarse tuning to be performed
using an external digital word.
For 3.3 V operation, the only external
components required are decoupling
capacitors and loop filter components.
System Inputs
Inputs RXD_INP and RXD_INN are fully
differential CML inputs designed to receive
signals from a post amplifier. Normally,
this would be the Nortel Networks AC10
Automatic Gain Control (AGC) Amplifier.
These inputs include on-chip termination
resistors of nominally 50 Ω. GND_DATA
should be connected to input ground.
YA18 2.5 Gb/s Clock and Data Recovery Circuit 3
Absolute Maximum Ratings
These are stress ratings only. Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability of
the device. Avoid operating the device outside the recommended operating conditions defined below.
Symbol Parameter Min Max Unit
VCC Supply voltage – any VCC pin -0.75.0V
any VCC_OUT pin -0.76.0V
VIInput voltage – PECL and/or CML (single ended wrt GND) 0VCC +0.5V
IOOutput current – PECL or CML -50 mA
VOoc Input voltage – open collector outputs -0.5VCC +0.5V
Tstg Storage temperature -65 135 °C
Recommended Operating Conditions
Symbol Parameter Min Typ Max Unit
VCC Supply voltage – any VCC pin 3.13 3.33.47 V
VCC_OUT Supply voltage for clock and data outputs 3.13 3.3or 5.05.25 V
VIDcml CML differential input voltage (peak to peak) 40 350 750 mV pk - pk
VIHpecl PECL input HIGH voltage VCC -1.165 VCC -0.88 V
VILpecl PECL input LOW voltage VCC -1.81 VCC -1.475 V
Tamb Operating ambient temperature -40 85 °C
BUFFER
RXD_INP
RXD_INN
VCC_OUT
TEST_EN
TESTCK
TESTCQ
RETIMING
AND
CML
OUTPUT
DRIVE
PHASE
LOCKED
LOOP
LOL
CK155_OUT
RECOVERED
2.5GHZ CLOCK
OFF-CHIP LOOP COMPONENTS
RXD_OUTP
RXD_OUTN
CK2G5_OUTP
CK2G5_OUTN
Figure 2: Functional Block Diagram
YA18 2.5 Gb/s Clock and Data Recovery Circuit4
DC Electrical Characteristics
Over recommended operating conditions, output load 50 Ω, VX= VCC_OUT for CML outputs.
Symbol Parameter Min Typ Max Unit
VO(p-p) CML differential output voltage (peak) 370 400 430 mV
VOHcml CML output HIGH voltage, VX -0.01 VXVX +0.01 V
referenced to VCC_OUT
VOLcml CML output LOW voltage, VX -0.42 VX -0.40 VX -0.38 V
referenced to VCC_OUT
VOHpecl PECL output HIGH voltage VCC -1.2VCC -0.88 V
VOLpecl PECL output LOW voltage VCC -1.81 VCC -1.52 V
IOHpecl PECL input HIGH current (VIH = VCC -0.88V) 100 µA
IOLpecl PECL input LOW current (VIL = VCC -1.81V) 50 µA
RINdiff Differential input resistance 85 100 115 Ω
RINeff Effective signal input resistance 42 50 58 Ω
ICC Supply current (VCC and VCC_OUT) 250 365 mA
Pd Device power dissipation 0.83 1.2W
AC Characteristics
Over recommended operating conditions, output load 50 Ω, VX= VCCout for CML outputs.
Symbol Parameter Min Typ Max Unit
Serial output clock rate 2488 MHz
Loop acquisition time (223 -1PRBS) 10 ms
Jitter generated at RXD_OUTP/N and 0.0075 UI rms
CK2G5_OUTP/ N outputs,bandwidth 12 kHz
to 20 MHz
Jitter tolerance at jitter frequency of 1MHz 0.15 UI p-p
VCO output variation with VCC (open loop) 15 MHz/V
VCO output temperature dependence (open loop) 1000 kHz/°C
TRcml CML output rise time 50 125 ps
TFcml CML output fall time 50 125 ps
CKmsr CK2G5_OUTP/N mark to space ratio 40 60 %
YA18 2.5 Gb/s Clock and Data Recovery Circuit 5
Typical Operating Characteristics
100 ps/div
250 mV
50 mV
/div
-250 mV
100 ps/div
250 mV
50 mV
/div
-250 mV
Recovered Clock
Recovered Data
Figure 3: Recovered Clock and recovered Data Eye
100
10
1
10 Hz 100 Hz
0.1 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz
Frequency
ITU OC48 Mask
YA 18 Jitter Tolerance
Figure 5: Jitter Tolerance
1
0
-6
10 kHz 100 kHz 1 MHz
Frequency
ITU OC48 Mask
YA 18 Jitter Transfer
-1
-2
-3
-4
-5
Figure 4: Jitter Transfer
Jitter Transfer
.5
1e-10 BER
2.5
2
1.5
1
0.5
0
3
1e-09 1e-08 1e-07 1e-06 1e-05 1e-04 1e-03 1e-02
Volts
Figure 6:Typical Loss of Lock Output for various Bit Error Rates
YA18 2.5 Gb/s Clock and Data Recovery Circuit6
TESTCK
TESTCKQ
TEST_EN
GND_CORE
VCC_CORE
GND_DATA
RX_INP
RX_INN
GND_CORE
LOL
VCC_CORE
VCC_CORE
GND_CORE
VCC_VCO
VCO_INN
VCO_INP
FD_OUTP
FD_OUTN
AMP_INP
AMP_INN
VCC_CORE
PD_OUTN
PD_OUTP
GND_CORE
Recovered
Clock Output
GND_CORE
GND_CORE
CK2G5_OUTP
CK2G5_OUTN
VCC_OUT
RX_OUTP
RX_OUTN
GND_CORE
VREG_5V
IREG_5V
GND_CORE
GND_CORE
VCC_CORE
VCC_CORE
GND_CORE
CK155_OUT
GND_CORE
VCC_CORE
GND_CORE
GND_CORE
VCC_CORE
VCC_CORE
GND_CORE
GND_CORE
Note:
Capacitors drawn without values are
decoupling types consisting of a parallel
combination of 100 pF and 10 nF.
2512
13 24
48 37
36
1
YA18
Exposed Heatsink
Should be connected
to ground
Loss of Lock
Output
(Requires Pullup)
100 nF
20%
100 nF
20%
Data Input
(50R Source)
Recovered
Data Output
Output Supply
(3.13 to 5.25 V)
22 uH
10 nF
20%
FZT968
This circuitry only required
if device is being operated
from a 5V supply
ESR = 2.5 R max
100 uF
100 nF100 nF
1 K
1 K
8.2 K8.2 K
82 R
82 R
+5V (Nominal)
Figure 7:Typical Application Configuration
Setting the Loop Filter
The YA18 is designed for regenerator and
receiver applications. Its integrated PLL is
a fully differential design offering greatly
improved power supply rejection over
typical single-ended variants, with loop
bandwidth set by a pair of identical exter-
nal networks. The configuration of these
networks is shown in Figure 8 with typical
component values listed in the Typical
Loop Filter Component Values Table.
These components should be surface mount
parts of 0603 size, with ±2% tolerance for
resistors up to 2 MΩ, ±5% tolerance for
capacitors up to 10 nF, and ±10% tolerance
for capacitors from 10 nF to 100 nF.
InputInterfacing
As with other members of the 2.5 Gb/s
optical networking IC family, the high speed
(2.5 Gb/s/2.5 GHz) inputs and outputs of
the YA18 are configured as fully differential
CML signal pairs as shown in Figure 9.
The inputs are internally terminated with
a 100 Ωresistor between the differential
inputs and require a typical differential
peak voltage of 350 mV. However, the
inputs to the YA18 will continue to operate
correctly with a peak differential input
voltage as low as 60 mV (see Figure 10).
Although the YA18 is specifically designed
to interface with the AC10 AGC Amplifier,
the internal self-biasing enables the device
to be AC-coupled to any differential signal
source providing differential voltage levels
of between 60 mV and 750 mV peak
differential. Single-ended operation
not recommended.
Design Procedure and Applications Information
OP
750 mV (max)
120 mVp-p (min)
OPB
OP-OPB
60 mV (min)
1500 Vp-p (max)
Figure 10: CML Differential Voltage Levels
GND
R
RR
R
100
IP
IPB
VCC
CML OUTPUT
VCC
50
OPB
OP
50
CML INPUT
GND
Figure 9: CML Input and Output Configurations
YA18 2.5 Gb/s Clock and Data Recovery Circuit 7
Typical Loop Filter Component Values
Loop bandwidth Damping factor C1a,b R0a,b R1a,b R2a,b
1800 kHz 5 100 nF 82 Ω8.2 kΩ 1kΩ
PD_OUTN
PD_OUTP VCO_INP
VCO_INN
AMP_INN FD_OUTN
AMP_INP FD_OUTP
C1aR2aR1a
C1bR2bR1b
Internal loop amp
+ -
- +
R0bR0a
VCC
Figure 8: Loop Filter Configuration
YA18 2.5 Gb/s Clock and Data Recovery Circuit8
+ 5 V
Decoupling
Capacitance
+3.13 V to
+ 5.25 V
10 nF
100 µF +3.3 V
IREG_5 V
VREG_5 V VCC_OUT
YA18
Figure 12:5V to 3.3 V Regulator
5V Supply Operation
A voltage regulator is provided on the
YA18 to enable operation from a 5 V
power supply if required. This requires an
external circuit as shown in Figure 12. Pin
VREG_5V is used to ensure start-up of the
regulator and is connected directly to the
5 V supply, pin IREG_5V provides the
regulator control current. Both pins should
be left open when using a 3.3 V supply. All
VCC pins must be connected as shown in
Figure 12 and the RXD_INP/N inputs to
the chip must be AC coupled for the regu-
lation to function correctly. The recom-
mended discrete PNP transistor is a Zetex
FZT968, packaged in a surface-mounted
SOT-223 case. Also suitable are the Zetex
FZT1147A, FZT1149A, or FZT1151A in
the same package format. A 10 nF surface
mount capacitor must be connected across
the base-collector of the PNP.
When the regulator is used, stability
requirements define a 100 nF limit on the
maximum decoupling capacitor which can
be connected across the 3.3 V supply pins.
This value may be exceeded if a few ohms
of resistance are placed in series. The circuit
stability is not affected by the value of the
capacitor on VCC_VCO, which is connected
to the 3.3 V supply via an inductor.
As a low impedance 5 V supply is required, a
100 µF decoupling capacitor is recommended,
with placement close to the package pin.
Output Interfacing
The differential CML outputs are configured
to provide a nominal peak differential output
voltage of 400 mV for simple interfacing to
the YA20 1:16 Demultiplexer. Other devices
can readily be driven from the output.
YA18
L = 22 uH (2.5
W
max.)
C = 100 uF
Vsupply
VCC_VCO
Figure 11:VCO Power Supply Filter
Power Supply Noise
Although the device has been designed
to maximize supply noise rejection, it is
recommended that you use an LC filter
network shown in Figure 11 between the
supply and pin 35 VCC_VCO. Using this
configuration, the device will function
within the jitter specification with a
maximum supply noise of 50mVpp,
over a frequency range from 6 kHz to
2 MHz, on the supply. The effective
series resistance of the network must
not exceed 2.5 Ω.
YA18 2.5 Gb/s Clock and Data Recovery Circuit 9
Pin Assignment
Pin No Symbol Type Description Function
1TESTCK I PECL Test clock input (connect to GND for normal use)
2TESTCKQ I PECL Test clock quadrature input
(connect to GND for normal use)
3TEST_EN I 3V CMOS compatible Test enable input for test clock
(connect to GND for normal use)
6GND_DATA P Data ground to be connected to input ground
4,9,13,14, GND_CORE P Supply ground
20,23,24,
25,36,37,
38,41,42,
44,46
5,11,12,28, VCC_CORE P Positive supply voltage
39,40, (not including clock and data output buffers)
43,47,48
7RXD_INP I CML Positive differential data input
8RXD_INN I CML Negative differential data input
10 LOL O Open collector Loss of lock output
15 CK2G5_OUTP O CML Positive recovered clock differential output
16 CK2G5_OUTN O CML Negative recovered clock differential output
17 VCC_OUT P 3.3V or 5.0V supply pin for clock and data outputs
18 RXD_OUTP O CML Positive retimed data differential output
19 RXD_OUTN O CML Negative retimed data differential output
21 VREG_5V P Analog 5.0V supply for regulator (see Figure 12)
22 IREG_5V P Analog 5V regulator current control (see Figure 12)
26 PD_OUTP O Analog Loop filter pin 1B
27 PD_OUTN O Analog Loop filter pin 1A
29 AMP_INN I Analog Loop filter pin 2A
30 AMP_INP I Analog Loop filter pin 2B
31 FD_OUTN O Analog Loop filter pin 3A
32 FD_OUTP O Analog Loop filter pin 3B
33 VCO_INP I Analog Loop filter pin 4A
34 VCO_INN I Analog Loop filter pin 4B
35 VCC_VCO P VCO positive supply voltage
45 CK155_OUT O PECL VCO divided clock test output
YA18 2.5 Gb/s Clock and Data Recovery Circuit10
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
VCC_CORE
VCC_CORE
GND_CORE
CK155_OUT
VCC_CORE
GND_CORE
GND_CORE
GND_CORE
VCC_CORE
VCC_CORE
GND_CORE
GND_CORE
GND_CORE
VCC_VCO
VCO_INN
VCO_INP
FD_OUTN
FD_OUTP
AMP_INP
AMP_INN
VCC_CORE
PD_OUTN
PD_OUTP
GND_CORE
GND_CORE
GND_CORE
CK2G5_OUTP
CK2G5_OUTN
RX_OUTP
VCC_OUT
RX_OUTN
GND_CORE
VREG_5V
IREG_5V
GND_CORE
GND_CORE
TESTCK
TESTCKQ
TEST_EN
GND_CORE
GND_CORE
VCC_CORE
RX_INP
RX_INN
GND_CORE
LOL
VCC_CORE
VCC_CORE
YA18
TOP VIEW
Figure 13:48-pin LQFP Package Pinout (Top View)
Package Pin Configuration
YA18 2.5 Gb/s Clock and Data Recovery Circuit 11
Dimension Min (mm) Nom (mm) Max (mm)
Lead pitch (E) 0.50
Body size (D1)7.00
Component tip-to-tip (D) 9.00
Component height (A) 1.60
Component standoff (A1)0.05 0.15
Body thickness (A2)1.35 1.40 1.45
Lead width, plated (B) 0.17 0.22 0.27
Lead thickness, plated (C) 0.09 0.20
Figure 14: Package Outline
Package Outline and Dimensions
E
B
D
D1A
A2
C
A1
Exposed Heatsink:
4.32 mm +/- 0.12 mm diam
Intrusion: 0.0127 mm max
On underside of package.
Table 1: Product ordering information
Product Code Product Name
A0742100 (QMV1050-1AF5) YA18 2.5 Gb/s Clock and Data Recovery Circuit
Ordering information
Please quote the Product Code from Table 1 below when
ordering as this is the identification that appears on the
part when shipped.
For additional information on Nortel Networks products and services
offered, please contact your local representative.
Nortel Networks
High Performance Optical Component Solutions
attn: Marketing Department
2745 Iris Street
6th Floor
Ottawa, Ontario
Canada K2C 3V5
Tel: 1-800-4 NORTEL
Fax: 1-613-763-8416
Email: opticalcomponents@nortelnetworks.com
www.nortelnetworks.com/hpocs
Copyright 2001 Nortel Networks Corporation. All rights reserved.
Nortel, Nortel Networks, the Nortel Networks corporate logo, and the globemark
design are trademarks of Nortel Networks Corporation. Any third-party trademarks
are the property of their respective owners.
The information contained in this document is considered to be accurate as of
the date of publication. No liability is assumed by Nortel Networks for use of any
information contained in this document, or for infringement of any patent rights
or any other proprietary rights of third parties which may result from such use.
No license is granted by implication or otherwise under any patent right or any
other proprietary right of Nortel Networks.
Publication # 84002.37/03-01 Issue 3Issued: 6 March 2001
