YA18 2.5 Gb/s Clock and Data Recovery Circuit2
Phase Locked Loop
The PLL used in the YA18 is a fully balanced
differential design comprising VCO and
phase/frequency detector. The VCO has
been designed to minimize jitter and the
effects of temperature and supply voltage
ripple. The VCO centre frequency is digi-
tally programmed during manufacture to
minimize process variations. This also
allows the device to be potentially set to
frequencies other than exactly 2.488 GHz.
System Outputs
Both the recovered clock outputs
CK2G5_OUTP and CK2G5_OUTN, and
the retimed data outputs RXD_OUTP
and RXD_OUTN, are 400 mV CML
differential drivers that are designed to
drive corresponding CML inputs. In the
case of the Nortel Networks YA20 1:16
Demultiplexer, these provide the required
50 Ωtermination. The data output transi-
tions are retimed to the falling edge of the
recovered clock, i.e. the falling edge of pin
CK2G5_OUTP. These four output pins
are provided with a local supply rail con-
nected to pin VCC_OUT, which can be
connected to VCC for 3.3 V output levels,
or can be connected to a separate 5 V supply,
if 5 V compatible output levels are required.
Loss of Lock (LOL) Output
The loss of lock indicator is an
open-collector output (active low) which
functions by monitoring cycle slips of the
input relative to the VCO. It will be active
for at least 2.5 µs after the most recent fre-
quency correction pulse, by which time the
loop is assumed to be in phase lock and
data is assumed to be valid. The loss of
lock signal may be extended with external
circuitry if required. The frequency
correction current pulse is emitted if the
phase of the data with respect to the clock
is observed to slip past the 180º point.
Test Inputs and Outputs
Various test inputs are available to enable
testing at low speeds. These inputs, which
are not internally terminated, bypass the
internal VCO. Under normal operation these
test inputs must be connected to 3.3 V.
A divider is included to divide the 2.5 GHz
VCO output down to 155 MHz, which is
delivered as a single-ended low power PECL
output at pin CK155_OUT. Under normal
operation this output should be connected
to 3.3 V.
Functional Description
The YA18 uses phase lock loop techniques
to recover a high frequency clock from
NRZ binary data presented to pins
RXD_INP and RXD_INN at nominally
2.5 Gb/s. For SONET/SDH applications
the device is tuned during manufacture to
provide a VCO centre frequency close to
2.488 GHz. This coarse tuning is performed
during production, so that no additional
trimming is required for VCO alignment.
Variants of the YA18 have been developed
that enable coarse tuning to be performed
using an external digital word.
For 3.3 V operation, the only external
components required are decoupling
capacitors and loop filter components.
System Inputs
Inputs RXD_INP and RXD_INN are fully
differential CML inputs designed to receive
signals from a post amplifier. Normally,
this would be the Nortel Networks AC10
Automatic Gain Control (AGC) Amplifier.
These inputs include on-chip termination
resistors of nominally 50 Ω. GND_DATA
should be connected to input ground.