Document Number: MC33981
Rev. 11.0, 7/2012
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007 - 2012. All rights reserved.
Single High Side Switch
(4.0 mOhm), PWM clock up to
60 kHz
The 33981 is a high frequency, self-protected 4.0 m RDS(ON) high
side switch used to replace electromechanical relays, fuses, and
discrete devices in power management applications.
The 33981 can be controlled by pulse-width modulation (PWM) with
a frequency up to 60 kHz. It is designed for harsh environments, and it
includes self-recovery features. The 33981 is suitable for loads with high
inrush current, as well as motors and all types of resistive and inductive
loads.
The 33981 is packaged in a 12 x 12 mm non-leaded power-enhanced
PQFN package with exposed tabs.
Features
• Single 4.0 m RDS(ON) maximum high side switch
• PWM capability up to 60 kHz with duty cycle from 5% to 100%
• Very low standby current
• Slew-rate control with external capacitor
• Over-current and over-temperature protection, under-voltage
shutdown, and fault reporting
• Reverse battery protection
• Gate drive signal for external low side N-channel MOSFET with
protection features
• Output current monitoring
• Temperature feedback
Figure 1. 33981 Simplified Application Diagram
HIGH SIDE SWITCH
33981
ORDERING INFORMATION
Device
(Add R2 Suffix for
Tape and Reel)
Temperature
Range (TA)Package
MC33981BHFK
- 40 to 125 °C 16 PQFN
MC33981ABHFK
Bottom View
FK (Pb-Free Suffix)
98ARL10521D
16-PIN PQFN (12 X 12)
VDD
I/O
I/O
I/O
I/O
A/D
A/D
MCU
CONF
FS
INLS
EN
INHS
TEMP
CSNS
OCLS SR GND
VPWR
CBOOT
OUT
DLS
GLS
VDD
M
VPWR
33981
Analog Integrated Circuit Device Data
2Freescale Semiconductor
33981
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Peak Solder Temperature
Device Description (1)
MC33981BHFK Original BOM and lower Peak Package Temperature solderability.
MC33981ABHFK Improved BOM and higher Peak Package Temperature solderability.
Notes
1. PPT values can be found on Freescale’s web site, or contact sales. Reference Peak Package Reflow
Temperature During Reflow(6), (7)
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
33981
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Figure 2. 33981 Simplified Internal Block Diagram
GND
OUT Current
Recopy
Logic
Gate Driver OUT
CSNS
VPWR
EN
INHS
INLS
CBOOT
Bootstrap Supply
Slew Rate Control
SR
Low Side
Gate Driver
GLS
Under-voltage
FS
CONF Cross-
Conduction
DLS
and Protection
TEMP Temperature
Feedback
OCLS
Current Protection
Over-temperature
Detection
5.0V
ICONF
IOCLS
IDWN
RDWN 5.0 V
Detection
Analog Integrated Circuit Device Data
4Freescale Semiconductor
33981
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. Pin Connections
Table 2. PIN DEFINITIONS
Descriptions of the pins listed in the table below can be found in the Functional Description section located on page 15.
Pin
Number Pin Name Pin
Function Formal Name Definition
1CSNS Reports Output Current Monitoring This pin is used to generate a ground-referenced voltage for the
microcontroller (MCU) to monitor output current.
2TEMP Reports Temperature Feedback This pin is used by the MCU to monitor board temperature.
3EN Input Enable
(Active High)
This pin is used to place the device in a low-current Sleep mode.
4INHS Input Serial Input High Side This input pin is used to control the output of the device.
5FS Reports Fault Status
(Active Low)
This pin monitors fault conditions and is active LOW.
6INLS Input Serial Input Low Side This pin is used to control an external low side N-channel MOSFET.
7CONF Input Configuration Input This input manages MOSFET N-channel cross-conduction.
8OCLS Input Low Side Overload This pin sets the VDS protection level of the external low side MOSFET.
9DLS Input Drain Low Side This pin is the drain of the external low side N-channel MOSFET.
10 GLS Output Low Side Gate This output pin drives the gate of the external low side N-channel
MOSFET.
11 SR Input Slew Rate Control This pin controls the output slew rate.
12 CBOOT Input Bootstrap Capacitor This pin provides the high pulse current to drive the device.
13 GND Ground Ground This is the ground pin of the device.
14 VPWR Input Positive Power Supply This pin is the source input of operational power for the device.
15, 16 OUT Output Output These pins provide a protected high side power output to the load
connected to the device.
1
11
10
9
8
7
6
5
4
3
2
1615
14
13
12
Package Transparent Top View
OUTOUT
CSNS
TEMP
EN
INHS
FS
INLS
CONF
OCLS
DLS
GLS
SR
CBOOT
GND
VPWR
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
33981
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit
ELECTRICAL RATINGS
Power Supply Voltage
Steady-state
VPWR
-16 to 41
V
Input/Output Pins Voltage(2) INHS, INLS,
CONF, CSNS, FS,
TEMP, EN
- 0.3 to 7.0 V
Output Voltage
Positive
Negative
VOUT
41.0
-5.0
V
Continuous Output Current(3) IOUT 40.0 A
CSNS Input Clamp Current ICL(CSNS) 15.0 mA
EN Input Clamp Current ICL(EN) 2.5 mA
SR Voltage VSR - 0.3 to 54.0 V
CBOOT Voltage CBOOT - 0.3 to 54.0 V
OCLS Voltage VOCLS - 5.0 to 7.0 V
Low Side Gate Voltage VGLS - 0.3 to 15.0 V
Low Side Drain Voltage VDLS - 5.0 to 41.0 V
ESD Voltage(4)
Human Body Model (HBM)
Charge Device Model (CDM)
Corner Pins (1, 12, 15, 16)
All Other Pins (2-11, 13-14)
VESD
± 2000
± 750
± 500
V
Notes
2. Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN pins may cause a malfunction or permanent damage to the
device.
3. Continuous high side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ) and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
Analog Integrated Circuit Device Data
6Freescale Semiconductor
33981
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
THERMAL RATINGS
Operating Temperature
Ambient
Junction
TA
TJ
- 40 to 125
- 40 to 150
°C
Storage Temperature TSTG - 55 to 150 C
Thermal Resistance(5)
Junction to Power Die Case
Junction to Ambient
RJC
RJA
1.0
30.0
C/W
Peak Package Reflow Temperature During Reflow(6), (7) TPPRT Note 7 °C
Notes
5. Device mounted on a 2s2p test board per JEDEC JESD51-2.
6. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
33981
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUT (VPWR)
Battery Supply Voltage Range
Fully Operational
Extended(8)
VPWR
6.0
4.5
–
–
27.0
27.0
V
VPWR Supply Current
INHS = 1 and OUT Open, INLS = 0
IPWR(ON)
–10.0 12.0
mA
VPWR Supply Current
INHS = INLS = 0, EN = 5.0 V, OUT Connected to GND
IPWR(SBY)
–10.0 12.0
mA
Sleep-state Supply Current
(VPWR < 14 V, EN = 0 V, OUT Connected to GND)
TA = 25 C
TA = 125 C
IPWR(SLEEP)
–
–
–
–
5.0
50.0
A
Under-voltage Shutdown VPWR(UV) 2.0 4.0 4.5 V
Under-voltage Hysteresis VPWR(UVHYS) 0.05 0.15 0.3 V
POWER OUTPUT (IOUT, VPWR)
Output Drain-to-Source ON Resistance (IOUT = 20 A, TA = 25 C)
VPWR = 6.0 V
VPWR = 9.0 V
VPWR = 13.0 V
RDS(ON)25
–
–
–
–
–
–
6.0
5.0
4.0
m
Output Drain-to-Source ON Resistance (IOUT = 20 A, TA = 150 C)
VPWR = 6.0 V
VPWR = 9.0 V
VPWR = 13.0 V
RDS(ON)150
–
–
–
–
–
–
10.2
8.5
6.8
m
Output Source-to-Drain ON Resistance (IOUT = -20 A, TA = 25 C)(9)
VPWR = - 12 V
RSD(ON)
– – 8.0
m
Output Over-current Detection Level
9.0 V < VPWR < 16 V
I OCH
75 100 125
A
Current Sense Ratio
9.0 V < VPWR < 16 V, CSNS < 4.5 V
CSR
–1/20000 –
–
Current Sense Ratio (CSR) Accuracy
9.0 V < VPWR < 16 V, CSNS < 4.5 V
Output Current
5.0 A
15 A, 20 A, and 30 A
CSR_ACC
-20
-15
–
–
20
15
%
Notes
8. OUT can be commanded fully on, PWM is available at room. Low Side Gate driver is available. Protections and Diagnosis are not
available. Min/max parameters are not guaranteed.
9. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
Analog Integrated Circuit Device Data
8Freescale Semiconductor
33981
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
POWER OUTPUT (VPWR) (continued)
Current Sense Voltage Clamp
I
CSNS = 15 mA
VCL(CSNS)
4.5 6.0 7.0
V
Current Sense Leakage(10)
I NHS = 1 with OUT opened of load or INHS = 0
ILEAK(CSNS)
013 17
A
Over-temperature Shutdown TSD 160 175 190 °C
Over-temperature Shutdown Hysteresis(11) TSDHYS 5.0 –20 C
LOW SIDE GATE DRIVER (VPWR, VGLS, VOCLS)
Low Side Gate Voltage
VPWR = 6.0 V
VPWR = 9.0 V
VPWR = 13 V
VPWR = 27 V
VGLS
5.0
8.0
12.0
12.0
5.4
8.4
12.4
12.4
6.0
9.0
13.0
13.0
V
Low Side Gate Sinked Current
VGLS = 2.0 V, VPWR = 13 V
I
GLSNEG
–100 –
mA
Low Side Gate Sourced Current
VGLS = 2.0 V, VPWR = 13 V
I
GLSPOS
–100 –
mA
Low Side Overload Detection Level versus Low Side Drain Voltage
VOCLS - VDLS, (VOCLS V
VDS_LS
-50 –+50
mV
CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS)
Input Logic High-voltage (CONF, INHS, INLS) VIH 3.3 – – V
Input Logic Low-voltage (CONF, INHS, INLS) VIL – – 1.0 V
Input Logic Voltage Hysteresis (CONF, INHS, INLS) VINHYS 100 600 1200 mV
Input Logic Active Pull-down Current (INHS, INLS) IDWN 5.0 10 20 A
Enable Pull-down Resistor (EN) RDWN 100 200 400 k
Enable Voltage Threshold (EN) VEN 2.5 V
Input Clamp Voltage (EN)
IEN < 2.5 mA
VCLEN
7.0 –14
V
Input Forward Voltage (EN) VF(EN) -2.0 –-0.3 V
Input Active Pull-up Current (OCLS) IOCLS p 50 100 200 A
Input Active Pull-up Current (CONF) I
CONF 5.0 10 20 A
Notes
10. This parameter is achieved by the design characterization by measuring a statistically relevant sample size across process variations
but not tested in production.
11. Parameter is guaranteed by process monitoring but is not production tested.
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
33981
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS) (continued)
FS Tri-state Capacitance(12) CFS – – 20 pF
FS Low-state Output Voltage
IFS = -1.6 mA
VFSL
–0.2 0.4
V
Temperature Feedback
TA = 25°C for VPWR = 14 V
VTFEED
3.35 3.45 3.55
V
Temperature Feedback Derating(12) DTFEED -8.5 -8.9 -9.3 mV/°C
Notes
12. Parameter is guaranteed by process monitoring but is not production tested.
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
33981
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
CONTROL INTERFACE AND POWER OUTPUT TIMING (CBOOT, VPWR)
Charge Blanking Time (CBOOT)(14) t
ON 10 25 50 s
Output Rising Slew Rate
VPWR = 13 V, from 10% to 90% of VOUT, SR Capacitor = 4.7 nF,
RL= 5.0
SRR
8.0 16 35
V/s
Output Falling Slew Rate
VPWR = 13 V, from 90% to 10% of VOUT, SR Capacitor = 4.7 nF,
RL= 5.0
SRF
8.0 16 35
V/s
Output Turn-ON Delay Time(15)
VPWR = 13 V, SR Capacitor = 4.7 nF
t DLYON
200 400 700
ns
Output Turn-OFF Delay Time(16)
VPWR = 13 V, SR Capacitor = 4.7 nF
t DLYOFF
500 1000 1500
ns
Input Switching Frequency(13) f
PWM –20 60 kHz
Output PWM ratio at 60 kHz(17) R
PWM 5.0 –95 %
Time to Reset Fault Diagnosis
(overload on high side or external low side)
t RSTDIAG
100 200 400
s
Output Over-current Detection Time t OCH 1.0 10 20 s
Notes
13. The MC33981 fully operates down to DC. To reset a latched Fault the INHS pin must go low for the “Time to reset Fault Diagnosis”
(tRSTDIAG).
14. Values for CBOOT=100 nF. Refer to Sleep Mode on page 16. Parameter is guaranteed by design and not production tested.
15. Turn-ON delay time measured from rising edge of INHS that turns the output ON to VOUT = 0.5 V with RL= 5.0 resistive load.
16. Turn-OFF delay time measured from falling edge of INHS that turns the output OFF to VOUT = VPWR -0.5 V with RL= 5.0 resistive load.
17. The ratio is measured at VOUT = 50% VPWR without SR capacitor. The device is capable of 100% duty cycle.
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
33981
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 4. Time Delays Functional Diagrams
Figure 5. Normal Mode, Cross-Conduction Management
0.5 V
VPWR - 0.5 V
VOUT
INHS
tDLY(ON) tDLY(OFF)
0.0 V
5.0 V
VOUT
90% Vout
10% Vout
SRF
SRR
50%VPWR
RPWM
EN
INHS
INLS
OUT
GLS
FS tON
After
CONF
5.0 V
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
33981
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Figure 6. Normal Mode, Independent High Side and Low Side
EN
INHS
INLS
OUT
GLS
FS
High Side ON
High Side OFF
tON
After
CONF
0.0 V
Analog Integrated Circuit Device Data
Freescale Semiconductor 13
33981
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
Figure 7. Typical RDS(ON) vs. Temperature at VPWR = 13 V
Figure 8. Typical Sleep-state Supply Current vs. VPWR at 150 °C
Figure 9. VOUT Rise Time vs. SR Capacitor From 10% to 90% of VOUT at 25 °C and VPWR = 13 V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
-50 0 50 100 150 200
Temperature (°C)
RdsON (mOhm)
R
DS(ON)
(m
)
Temperature (°C)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
4.5 6.0 9.0 12.0 12.5 13.0 14.0 17.0 21.0
Vpwr(V)
Ipwr(sleep)(µA)
VPWR (V)
IPWR(SLEEP) (A)
1600
1400
400
1200
1000
800
600
200
0
0 2.0 4.0 6.0 8.0 10
SR Capacitor (nF)
Vout Rise Time (ns)
Analog Integrated Circuit Device Data
14 Freescale Semiconductor
33981
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Figure 10. VOUT Fall Time vs. SR Capacitor From 10% to 90% of VOUT at 25 °C and VPWR = 13 V
0
200
400
600
800
1000
1200
1400
1600
Vout Fall Time (ns)
0 2.0 4.0 6.0 8.0 10
SR Capacitor (nF)
Analog Integrated Circuit Device Data
Freescale Semiconductor 15
33981
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33981 is a high-frequency self-protected silicon
4.0 mRDS(ON) high side switch used to replace
electromechanical relays, fuses, and discrete devices in
power management applications. The 33981 can be
controlled by pulse-width modulation (PWM) with a frequency
up to 60 kHz. It is designed for harsh environments, and it
includes self-recovery features.
The 33981 is suitable for loads with high inrush current, as
well as motors and all types of resistive and inductive loads.
A dedicated parallel input is available for an external low side
control with protection features and cross-conduction
management.
FUNCTIONAL PIN DESCRIPTIONS
OUTPUT CURRENT MONITORING (CSNS)
This pin is used to output a current proportional to the high
side OUT current and is used externally to generate a
ground-referenced voltage for the microcontroller (MCU) to
monitor OUT current.
TEMPERATURE FEEDBACK (TEMP)
This pin reports an analog value proportional to the
temperature of the GND flag (pin 13). It is used by the MCU
to monitor board temperature.
ENABLE [ACTIVE HIGH] (EN)
This is an input used to place the device in a low-current
Sleep Mode. This pin has an active passive internal pull-
down.
INPUT HIGH SIDE (INHS)
The input pin is used to directly control the OUT. This input
has an active internal pull-down current source and requires
CMOS logic levels.
FAULT STATUS (FS)
This pin is an open drain-configured output requiring an
external pull-up resistor to VDD (5.0 V) for fault reporting.
When a device fault condition is detected, this pin is active
LOW.
INPUT LOW SIDE (INLS)
This input pin is used to directly control an external low
side N-channel MOSFET and has an active internal pull-
down current source and requires CMOS logic levels. It can
be controlled independently of the INHS depending of CONF
pin.
CONFIGURATION INPUT (CONF)
This input pin is used to manage the cross-conduction
between the internal high side N-channel MOSFET and the
external low side N-channel MOSFET. The pin has an active
internal pull-up current source. When CONF is at 0 V, the
two MOSFETs are controlled independently. When CONF is
at VDD 5.0 V, the two MOSFETs cannot be on at the same
time.
LOW SIDE OVERLOAD (OCLS)
This pin sets the VDS protection level of the external low
side MOSFET. This pin has an active internal pull-up current
source. It must be connected to an external resistor.
DRAIN LOW SIDE (DLS)
This pin is the drain of the external low side N-channel
MOSFET. Its monitoring allows protection features: low side
short protection and VPWR short protection.
LOW SIDE GATE (GLS)
This pin is an output used to drive the gate of the external
low side N-channel MOSFET.
SLEW RATE CONTROL (SR)
A capacitor connected between this pin and ground is
used to control the output slew rate.
BOOTSTRAP CAPACITOR (CBOOT)
A capacitor connected between this pin and OUT is used
to switch the OUT in PWM mode.
GROUND (GND)
This pin is the ground for the logic and analog circuitry of
the device.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the
source input of operational power for the device. The VPWR
pin is a backside surface mount tab of the package.
OUTPUT (OUT)
Protected high side power output to the load. Output pins
must be connected in parallel for operation.
Analog Integrated Circuit Device Data
16 Freescale Semiconductor
33981
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33981 has 2 operating modes: Sleep and Normal
depending on EN input.
SLEEP MODE
Sleep Mode is the state of the 33981 when the EN is
logic [0]. In this mode, OUT, the gate driver for the external
MOSFET, and all unused internal circuitry are off to minimize
current draw.
NORMAL MODE
The 33981 will go to the Normal operating mode when the
EN pin is logic [1]. The INHS and INLS commands will be
disabled t
ON after the EN transitions to logic [1] to enable the
charge of the bootstrap capacitor.
PROTECTION AND DIAGNOSTIC FEATURES
UNDER-VOLTAGE
The 33981 incorporates under-voltage protection. In case
of VPWR<VPWR(UV), the OUT is switched OFF until the power
supply rises to VPWR(UV)+VPWR(UVHYS). The latched fault are
reset below VPWR(UV). The FS output pin reports the under-
voltage fault in real time.
OVER-TEMPERATURE FAULT
The 33981 incorporates over-temperature detection and
shutdown circuitry on OUT. Over-temperature detection also
protects the low side gate driver (GLS pin). Over-temperature
detection occurs when OUT is in the ON or OFF state and
GLS is at high or low level.
For OUT, an over-temperature fault condition results in
OUT turning OFF until the temperature falls below TSD. This
cycle will continue indefinitely until the offending load is
removed. Figure 12 and Figure 18 show an over-temperature
on OUT.
An over-temperature fault on the low side gate drive
results in OUT turning OFF and the GLS going to 0V until the
temperature falls below TSD. This cycle will continue until the
offending load is removed. FS pin transition to logic [1] will be
disabled typically t
ON after to enable the charge of the
bootstrap capacitor.
Over-temperature faults force the TEMP pin to 0 V.
OVER-CURRENT FAULT ON HIGH SIDE
The OUT pin has an over-current high-detection level
called I OCH for maximum device protection. If at any time the
current reaches this level, OUT will stay OFF and the CSNS
pin will go to 0V. The OUT pin is reset (and the fault is
delatched) by a logic [0] at the INHS pin for at least t RST(DIAG).
When INHS goes to 0 V, CSNS goes to 5.0 V.
In Figure 15, the OUT pin is short-circuited to 0V. When
the current reaches I OCH , OUT is turned OFF within t OCH
owing to internal logic circuit.
OVER-LOAD FAULT ON LOW SIDE
This fault detection is active when INLS is logic [1]. Low
side overload protection does not measure the current
Table 6. Operating Modes
Condition CONF INHS INLS OUT GLS FS EN Comments
Sleep x x x x x H L Device is in Sleep Mode. The OUT and low side gate are OFF.
Normal L H H H H H H Normal mode. High side and low side are controlled
independently. The high side and the low side are both on.
Normal L L L L L H H Normal mode. High side and low side are controlled
independently. The high side and the low side are both off.
Normal L L H L H H H Normal mode. Half-bridge configuration. The high side is off
and the low side is on.
Normal L H L H L H H Normal mode. Half-bridge configuration. The high side is on
and the low side is off.
Normal HPWM HPWM PWM_bar H H Normal mode. Cross-conduction management is activated.
Half-bridge configuration.
H = High level
L = Low level
x = Don’t care
PWM_bar = Opposite of pulse-width modulation signal.
Analog Integrated Circuit Device Data
Freescale Semiconductor 17
33981
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
directly but rather its effects on the low side MOSFET. When
VDLS > VOCLS, the GLS pin goes to 0 V and the OCLS
internal current source is disconnected and OCLS goes to
0 V. The GLS pin and the OCLS pin are reset (and the fault
is delatched) by a logic [0] at the INLS pin for at least
t RST(DIAG). Figure 13 and Figure 14 illustrate the behavior in
case of overload on the low side gate driver.
When connected to an external resistor, the OCLS pin with
its internal current source sets the VOCLS level. By changing
the external resistance, the protection level can be adjusted
depending on low side characteristics. A 33 k resistor gives
a VDS level of 3.3 V typical.
This protection circuitry measures the voltage between the
drain of the low side (DLS pin) and the 33981 ground (GND
pin). For this reason it is key that the low side source, the
33981 ground, and the external resistance ground
connection are connected together in order to prevent false
error detection due to ground shifts.
The maximum OCLS voltage being 4.0 V, a resistor bridge
on DLS must be used to detect a higher voltage across the
low side.
CONFIGURATION
The CONF pin manages the cross-conduction between
the internal MOSFET and the external low side MOSFET.
With the CONF pin at 0 V, the two MOSFETs can be
independently controlled. A load can be placed between the
high side and the low side.
With the CONF pin at 5.0 V, the two MOSFETs cannot be
on at the same time. They are in half-bridge configuration as
shown in the 33981 Simplified Application Diagram. If INHS
and INLS are at 5.0 V at the same time, INHS has priority and
OUT will be at VPWR. If INHS changes from 5.0 V to 0 V with
INLS at 5.0 V, GLS will go to high state as soon as the VGS
of the internal MOSFET is lower than 2.0 V typically. A half-
bridge application could consist in sending PWM signal to the
INHS pin and 5.0 V to the INLS pin with the CONF pin at
5.0 V.
Figure 20, illustrates the simplified application diagram in
the 33981 Simplified Application Diagram with a DC motor
and external low side. The CONF and INLS pins are at 5.0 V.
When INHS is at 5.0 V, current is flowing in the motor. When
INHS goes to 0 V, the load current recirculates in the external
low side.
BOOTSTRAP SUPPLY
Bootstrap supply provides current to charge the bootstrap
capacitor through the VPWR pin. A short time is required after
the application of power to the device to charge the bootstrap
capacitor. A typical value for this capacitor is 100 nF. An
internal charge pump allows continuous MOSFET drive.
When the device is in the sleep mode, this bootstrap supply
is off to minimize current consumption.
HIGH SIDE GATE DRIVER
The high side gate driver switches the bootstrap capacitor
voltage to the gate of the MOSFET. The driver circuit has a
low-impedance drive to ensure that the MOSFET remains
OFF in the presence of fast falling dV/dt transients on the
OUT pin.
This bootstrap capacitor connected between the power
supply and the CBOOT pin provides the high pulse current to
drive the device. The voltage across this capacitor is limited
to about 13 V typical.
An external capacitor connected between pins SR and
GND is used to control the slew rate at the OUT pin. Figure 9
and Figure 10 give VOUT rise and fall time versus different SR
capacitors.
LOW SIDE GATE DRIVER
The low side control circuitry is PWM capable. It can drive
a standard MOSFET with an RDS(ON) as low as 10.0 m at a
frequency up to 60 kHz. The VGS is internally clamped at
12 V typically to protect the gate of the MOSFET. The GLS
pin is protected against short by a local over-temperature
sensor.
THERMAL FEEDBACK
The 33981 has an analog feedback output (TEMP pin) that
provides a value in inverse proportion to the temperature of
the GND flag (pin 13). The controlling microcontroller can
“read” the temperature proportional voltage with its analog-
to-digital converter (ADC). This can be used to provide real-
time monitoring of the PC board temperature to optimize the
motor speed and to protect the whole electronic system.
TEMP pin value is VTFEED with a negative temperature
coefficient of DTFEED.
REVERSE BATTERY
The 33981 survives the application of reverse battery
voltage as low as -16 V. Under these conditions, the output’s
gate is enhanced to decrease device power dissipation. No
additional passive components are required. The 33981
survives these conditions until the maximum junction rating is
reached.
In the case of reverse battery in a half-bridge application,
a direct current passes through the external freewheeling
diode and the internal high side.
As Figure 11 shows, it is essential to protect this power
line. The proposed solution is an external N-channel low side
with its gate tied to battery voltage through a resistor. A high
side in the VPWR line could be another solution.
Analog Integrated Circuit Device Data
18 Freescale Semiconductor
33981
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Figure 11. Reverse Battery Protection
GROUND (GND) DISCONNECT PROTECTION
If the DC motor module ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the output state at the time of
disconnection. A 10 k resistor needs to be added between
the EN pin and the rest of the circuitry in order to ensure the
device turns off in case of ground disconnect and to prevent
exceeding this pin’s maximum ratings.
FAULT REPORTING
This 33981 indicates the faults below as they occur by
driving the FS pin to logic [0]:
• Over-temperature fault
• Over-current fault on OUT
• Overload fault on the external low side MOSFET
The FS pin will return to logic [1] when the over
temperature fault condition is removed. The two other faults
are latched.
M
V
PWR
V
DD
V
PWR
MCU
33981
No current
GND OUT
Diode
10.0 k
Analog Integrated Circuit Device Data
Freescale Semiconductor 19
33981
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Table 7. Functional Truth Table in Fault Mode
Conditions CONF INHS INLS OUT GLS FS EN TEMP CSNS OCLS Comments
Over-temperature
on OUT
x x x L H L H L x x The 33981 is currently in Fault mode.
The OUT is OFF. TEMP at 0V
indicates this fault. Once the fault is
removed 33981 recovers its normal
mode.
Over-temperature
on GLS
x x x L L L H L x x The 33981 is currently in Fault mode.
The OUT is OFF and GLS is at 0V.
TEMP at 0V indicates this fault. Once
the fault is removed 33981 recovers its
Normal Mode.
Over-current
on OUT
x H L L x L H x L x The 33981 is currently in Fault mode.
The OUT is OFF. It is reset by a
logic [0] at INHS for at least t RST(DIAG).
When INHS goes to 0V, CSNS goes to
5.0 V.
Overload
on External Low
Side MOSFET
L L H x L L H x x L The 33981 is currently in Fault mode.
GLS is at 0 V and OCLS internal
current source is off. The external
resistance connected between OCLS
and GND pin will pull OCLS pin to 0V.
The fault is reset by a logic [0] at INLS
for at least t RST(DIAG).
H = High level
L = Low level
x = Don’t care
Analog Integrated Circuit Device Data
20 Freescale Semiconductor
33981
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Figure 12. Over-temperature on Output
EN
CONF
INHS
INLS
OUT
Thermal Shutdown
GLS
FS
TEMP
High Side ON High Side OFF
Temperature
OUT
TSD
TSD
Hysteresis
Hysteresis
0.0 V
5.0 V
0.0 V
0.0 V
5.0 V
0.0 V
5.0 V
5.0 V
on OUT
Thermal Shutdown
on OUT
Analog Integrated Circuit Device Data
Freescale Semiconductor 21
33981
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Figure 13. Overload on Low Side Gate Drive, Case 1
Figure 14. Overload on Low Side Gate Drive, Case 2
EN
INLS
GLS
FS
Overload on Low Side
tRST(DIAG)
OCLS
VDS_LS
Low Side OFF
V
DS_LS =
V
OCLS
Case 1: Overload Removed
0.0 V
0.0 V
0.0 V
5.0 V
0.0 V
5.0 V
5.0 V
INLS
GLS
FS
Overload on Low Side
tRST(DIAG)
OCLS
VDS_LS
Case 2: Low Side Still Overloaded
Low Side OFF
VDS_LS = VOCLS
0.0 V
0.0 V
0.0 V
0.0 V
EN
5.0 V
Analog Integrated Circuit Device Data
22 Freescale Semiconductor
33981
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Figure 15. Over-current on Output
Figure 16. High Side Over-current
INHS
OUT
FS
tRST(DIAG)
CSNS
IOUT
I
OCH
Fault Removed
Over-current on High Side
0.0 V
0.0 V
0.0 V
VCL (CSNS)
0.0 V
5.0 V
EN
5.0 V
Analog Integrated Circuit Device Data
Freescale Semiconductor 23
33981
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Figure 17. Cross-Conduction with Low Side
Figure 18. Over-temperature on OUT
Recirculation in Low SideCurrent in Motor
Over-temperature
TEMP
INHS
OUT
IOUT
Analog Integrated Circuit Device Data
24 Freescale Semiconductor
33981
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Figure 19. Maximum Operating Frequency for SR Capacitor of 4.7 nF
Analog Integrated Circuit Device Data
Freescale Semiconductor 25
33981
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Figure 20 shows a typical application for the 33981. A brush DC motor is connected to the output. A low side gate driver is
used for the freewheeling phase. Typical values for external capacitors and resistors are given.
.
Figure 20. 33981 Typical Application Diagram
EMC AND EMI RECOMMENDATIONS
INTRODUCTION
This section relates the EMC capability for 33981, high
frequency high-current high side switch. This device is a self-
protected silicon switch used to replace electromechanical
relays, fuses, and discrete circuits in power management
applications.
This section presents the key features of the device and its
targeted applications. The automotive standard to measure
conducted and radiated emissions is provided. Concrete
measurements on the 33981 and improvements to reduce
electromagnetic emission are described.
DEVICE FEATURES
This 33981 is a 4.0 m self-protected, high side switch
digitally controlled from a microcontroller (MCU) with
extended diagnostics, able to drive DC motors up to 60 kHz.
A bootstrap architecture has been used to provide fast
transient gate voltage in order to reach 4.0 m RDS(ON)
maximum at room temperature. In parallel, a charge pump is
implemented to offer continuous on-state capability. This
dual current supply of the high side MOSFET allows a duty
cycle from 5% to 100%. An external capacitor connected
between pins SR and GND is used to control the slew rate at
the output and, therefore, reduce electromagnetic
perturbations.
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. To reduce global
power dissipation, the freewheeling diode can be replaced by
an external discrete MOSFET in low side configuration. The
IC integrates a gate driver that controls and protects this
external MOSFET in the event of short-circuit to battery. The
product manages the cross conduction between the internal
high side and the external low side when used in a half-bridge
configuration. The two MOSFETs can be controlled
independently when the CONF pin is at 0 V. To eliminates
fuses, the device is self-protected from severe short-circuits
(100 A typical) with an innovative over-current strategy.
The 33981 has a current feedback for real-time monitoring
of the load current through an MCU analog/digital converter
to facilitate closed-loop operation for motor speed control.
The 33981 has an analog thermal feedback that can be
used by the MCU to monitor PC board temperature to
optimize the motor control and to protect the entire electronic
system. Therefore, an over-temperature shutdown feature
protects the IC against high overload condition.
Figure 21 illustrates the typical application diagram.
MCU
33981
OUT
SR
EN
FS
INHS
CSNS
I/O
I/O
I/O
A/D
GND
VPWR
V
DD
CBOOT
GLS
INLS
I/O DLS
TEMP
A/D
CONF
OCLS
V
PWR
V
DD
M
2.2 nF
1.0 k
1.0 k
33 k
330
F
100 nF
100 nF
10 k
10 k
10 k
10 k
Voltage regulator
V
PWR
Analog Integrated Circuit Device Data
26 Freescale Semiconductor
33981
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
Figure 21. Typical Application Diagram
APPLICATION
Engine cooling, air conditioning, and fuel pump are the
targeted automotive applications for the 33981. Conventional
solutions are designed with discrete components that are not
optimized in terms of component board size, protection, and
diagnostics. The 33981 is the right candidate to develop
lighter and more compact units.
DC motor speed adjustment allows optimization of energy
consumption by reducing supply voltage, hence the mean
voltage applied to the motor. The commonly used control
technique is pulse wide modulation (PWM) where the
average voltage is proportional to the duty cycle. Most
applications require a PWM frequency of at least 20 kHz to
avoid audible noise. Figure 22 illustrates typical waveforms
when switching the 33981 at 20 kHz with a duty cycle of 80%.
The output voltage (OUT) and current in the motor (IMOTOR)
waveforms are represented.
Figure 22. Current and Voltage waveforms
HOW TO MEASURE ELECTROMAGNETIC
EMISSION ACCORDING TO THE CISPR25
One EMC standard in the automotive world (at system
level) is the CISPR25, edited by the International
Electrotechnical Commission. This standard describes the
measurement method to measure both conducted and
radiated emission.
CONDUCTED EMISSION MEASUREMENT
Conducted emission is the emission produced by the
device on the battery cable. The test bench is described by
CISPR25 (see Figure 23).
The Line Impedance Stabilization Network (LISN), also
called artificial network (AN), in a given frequency range
(150 kHz to 108 MHz), provides a specified load impedance
for the measurement of disturbance voltages and isolates the
equipment under test (EUT) from the supply in that frequency
range.
Figure 23. Test Bench for Conducted Emission
The EUT must operate under typical loading and other
conditions just as it must in the vehicle so maximum emission
state occurs. These operating conditions must be clearly
defined in the test plan to ensure that both supplier and
customer are performing identical tests.
For the testing described in this application note, the out
pin of the 33981 was connected to an inductive load (0.47
+ 1.0 H) switching at 20 kHz with a duty cycle of 80%. The
output current was 17 A continuous.
The ground return of the EUT to the chassis must be as
short as possible. The power supply is 13.5 V.
RADIATED EMISSION MEASUREMENT
The radiated emission measurement consists of
measuring the electromagnetic radiation produced by the
equipment under test. CISPR 25 gives the schematic test
bench described in Figure .
Imotor (10A/div)
OUT
MC33981 ON
MC33981 OFF
Load
BF Generator
LISN
Spectrum Analyzer
EUT
Out
Ground
Contact to
Ground Plane
+
-
Ground Plane in Copper
Su
pp
l
y
mm
200
0
200
+
Coaxial Cable
Electrical to Optical
Converter
High Side Driver Signal
12V Power Supply
Power Supply
Non-Conductive
Material
Analog Integrated Circuit Device Data
Freescale Semiconductor 27
33981
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
To measure radiated emission over all frequency ranges,
several antenna types must be used:
•0.15 MHz to 30 MHz: 1.0 m vertical monopole in
vertical polarization.
•30 MHz to 200 MHz: a biconical antenna used in
vertical and horizontal polarization.
• 200 MHz to 1,000 MHz: a log-periodic antenna used in
vertical and horizontal polarization.
Figure 24. Test Bench for Radiated Emission
EMC RESULTS AND IMPROVEMENTS
The 33981 OUT is connected to an inductive load (0.47
+ 1.0mH) switching at 20 kHz with duty = 80%. The current in
the load was 17 A continuous.
BOARD SETUP
The initial configuration of our 33981 board is represented
in Figure 25.
No SR capacitor is used. Therefore, the obtained
switching times are the maximum values. A capacitor of
1000 F is connected between VPWR and GND.
Figure 25. 33981 Initial Configuration
CONDUCTED MEASUREMENTS
TEST SETUP
To perform a conducted emission measurement in
accordance with the CISPR 25 standard, the test bench in
Figure 26 was developed.
Figure 26. Conducted Emission Test Setup
Key
1EUT (grounded locally if
required in test plan)
8Biconical antenna
2Test harness – –
3Load simulator (placement
and ground connection)
10 High quality double-
shielded coaxial cable
(50 )
4Power supply (location
optional)
11 Bulkhead connector
5Artificial Network (AN) 12 Measuring instrument
6Ground plane (bonded to
shielded enclosure)
13 RF absorber material
7Low relative permittivity
support ( 1.4)
14 Stimulation and monitoring
system
Out GND
V
PWR
33981
Power Supply
LISN
Measurement
Point for
Conducted
Emission
EUT
Non-Conductive
Material
Optical PWM Signal
Load (1.0 mH + 0.47 Ω)
Analog Integrated Circuit Device Data
28 Freescale Semiconductor
33981
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
EFFECTS OF SOME PARAMETERS
The conducted emissions level rise with the duty cycle.
When the duty increases the di/dt on the VPWR line is higher.
The device has to deliver more current and provide more
energy. Figure 27 describes the effect of duty cycle increase
on the VPWR current waveform. The conducted emission
level rises with the output frequency. This is due to the
increasing number of commutations.
Figure 27. VPWR Current
HOW TO REDUCE ELECTROMAGNETIC EMISSION
By adjusting the slew rate of the device during turn ON and
turn OFF with SR capacitor, the electromagnetic emissions
can be reduced.
Conductive emission tests were performed (taking care of
the board filtering and routing that have a big impact on EMC
performances).
An optimized solution was found by adding the following
external components to the initial board:
• PI filter on the VPWR: 2 x 3 F and 3.5H
• RC IN filter between VPWR and GND: a 2.0 resistor in
series with a 100 nF capacitor
• RC Out filter between OUT and GND: a 4.7 resistor
in series with a 100 nF capacitor
• Capacitor C1 of 10 nF between VPWR and GND
• Capacitor C2 of 10 nF between OUT and GND
• Capacitor C3 of 10 nF between OUT and VPWR
• Capacitor SR of 3.3 nF
Figure 28. 33981 with Filter
The EMC enhanced board with adapted value filter is
represented in Figure 29.
Figure 29. Enhanced Board
The chart in Figure 30 shows the spectrum of the
enhanced board and the initial board. The improvement is
appreciatively 15 dB to 20 dB in the all frequency range. The
enhanced board is now in accordance with the Class 3 limits
of the CISPR25 standard for conducted emission.
Figure 30. Conducted Emission Spectrum for 33981
RADIATED MEASUREMENTS
This test was performed in order to evaluate the
characteristic of the device relating to radiated emission.
Measurements have been done in accordance with the
CISPR 25 standard as shown in Figure 31. The tested board
was the EMC enhanced board.
di/dt
di/dt
Duty Cycle
Increase
I(t) on V
BAT
t
33891
100 nF
2 Ω
C1 = 10 nF
SR
3.3 nF
100 nF
4.7 Ω
PI filter
C3 = 10 nF
C2 = 10 nF
3000 μF
3.5 μH
Inductive Load
Free Wheel Diode
OUT
V
BAT
RC In Filter RC Out Filter
GND
33981
PI
Filter
C3
C1
SR
RC Out
Filter C2
RC In
Filter
Analog Integrated Circuit Device Data
Freescale Semiconductor 29
33981
TYPICAL APPLICATIONS
POWER DISSIPATION
Figure 31. Radiated Emission Test Set-up
The results of these measurements are represented in
Figure 32. The enhanced board is in accordance with the
Class 3 limits of the CISPR25 standard for radiated emission.
Figure 32. Radiated Emission Spectrum for 33981
CONCLUSION
This document explains how to measure conducted and
radiated emission in accordance with the automotive
CISPR25 standard. Measurements were performed on the
33981 in real application conditions, when driving an
inductive load. An optimized filtering solution was put in place
to have the tested system in accordance with the Class 3
limits. The same method can be used with other PC boards.
POWER DISSIPATION
INTRODUCTION
This section relates to the power dissipation capability for
33981, high frequency high-current high side switch. This
device is a self-protected silicon switch used to replace
electromechanical relays, fuses, and discrete circuits in
power management applications.
This section presents the key features of the device and its
targeted applications. The theoretical calculations for power
dissipation and die junction temperatures are determined in
this document for inductive loads. A concrete example with
DC motor driven by the 33981 is analyzed in DC Motor 200W.
DEVICE FEATURES
This 33981 is a 4.0 m self-protected, high side switch
digitally controlled from a microcontroller (MCU) with
extended diagnostics, able to drive DC motors up to 60 kHz.
A bootstrap architecture has been used to provide fast
transient gate voltage in order to reach 4.0 m RDS(ON)
maximum at room temperature. In parallel, a charge pump is
implemented to offer continuous on-state capability. This
dual current supply of the high side MOSFET allows a duty
cycle from 5% to 100%. An external capacitor connected
between pins SR and GND is used to control the slew rate at
the output and, therefore, reduce electromagnetic
perturbations.
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. To reduce global
power dissipation, the freewheeling diode can be replaced by
an external discrete MOSFET in low side configuration. The
IC integrates a gate driver that controls and protects this
external MOSFET in the event of short-circuit to battery. The
product manages the cross conduction between the internal
high side and the external low side when used in a half-bridge
configuration. The two MOSFETs can be controlled
independently when the CONF pin is at 0 V. To eliminates
fuses, the device is self-protected from severe short-circuits
(100 A typical) with an innovative over-current strategy.
The 33981 has a current feedback for real-time monitoring
of the load current through an MCU analog/digital converter
to facilitate closed-loop operation for motor speed control.
The 33981 has an analog thermal feedback that can be
used by the MCU to monitor PC board temperature to
optimize the motor control and to protect the entire electronic
system. Therefore, an over-temperature shutdown feature
protects the IC against high overload condition.
Figure 33 illustrates the typical application diagram.
Figure 33. Typical Application Diagram
1.5 m Length
of Cable
LISN and
Inductive Load
1 m Vertical
Monopole
Antenna
Anechoic
Chamber
EUT
CISPR
Class 3
Limits
33981
Emission
Analog Integrated Circuit Device Data
30 Freescale Semiconductor
33981
TYPICAL APPLICATIONS
POWER DISSIPATION
APPLICATION
Engine cooling, air conditioning, and fuel pump are the
targeted automotive applications for the 33981. Conventional
solutions are designed with discrete components that are not
optimized in terms of component board size, protection, and
diagnostics. The 33981 is the right candidate to develop
lighter and more compact units.
The adjustment of the DC motor speed allows optimizing
of energy consumption. It is realized by chopping the supply
voltage, hence the mean voltage, applied to the motor. The
commonly used control technique is pulse wide modulation
(PWM) where the average voltage is proportional to the duty
cycle. Most applications require a PWM frequency of at least
20 kHz to avoid audible noise. Figure 34 illustrates typical
waveforms when switching the 33981 at 20 kHz with a duty
cycle of 80%. The output voltage (OUT) and current in the
motor (IMOTOR) waveforms are represented.
Figure 34. Current and Voltage waveforms
POWER DISSIPATION
The 33981 power dissipation is the sum of two kinds of
losses:
• On-State losses when device is fully ON,
• Switching losses when the device switches ON and
OFF.
The analysis that follows assumes an inductive load and
assumes that the current is constant in the load.
The case being considered in this paper is inductive load
and the hypothesis is that the current is constant in the load.
ON-STATE LOSSES
The mean on-state loss periods in the 33981 can be
calculated as follows:
Pon_state = a · RDS(ON) · IOUT2 where ‘a’ is the duty cycle.
The critical parameter is the on resistance (RDS(ON)) that
increases with temperature. The 33981 has a maximum
RDS(ON) at 25 ºC of 4.0 m and its deviation with
temperature is only 1.7 as shown in Figure 35.
Figure 35. RDS(ON) vs. Temperature
SWITCHING LOSSES
The mean switching losses in the 33981 can be calculated
as follows:
Pswitching = (tON . FREQ . VPWR . IOUT) / 2 + (tOFF . FREQ .
VPWR . IOUT) / 2
where tON/tOFF is the turn on/off time.
The switching time is a critical parameter. The 33981
provides adjustable slew rates through an external capacitor
(SR) that slow down the rise and fall times to reduce the
electromagnetic emissions. However, this adjustment will
have an impact on power dissipation. Figure 36 gives the
positive (SRR) and negative (SRF) slew rate versus different
values of SR. This is illustrated in Figure 37.
Imotor (10A/div)
OUT
MC33981 ON
MC33981 OFF
0
1
2
3
4
5
6
7
-50 0 50 100 150 200
Temperature (°C)
R
DSON
(mOhm)
Analog Integrated Circuit Device Data
Freescale Semiconductor 31
33981
TYPICAL APPLICATIONS
POWER DISSIPATION
Figure 36. Positive and Negative Slew Rate
vs. SR Capacitor
Figure 37. OUT switching vs. SR Capacitor
JUNCTION TEMPERATURE
The junction temperature of the 33981 can be calculated
knowing the power dissipation and the thermal
characteristics of the PC board with this formula:
TJ = TA + (Pon_state + Pswitching). RTHJA
where TJ is the junction temperature, TA the ambient
temperature, and RTHJA the thermal impedance junction to
ambient.
RECIRCULATION PHASE
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. With the 33981,
the freewheeling diode can be replaced by an external low-
side discrete MOSFET.
The power dissipation during the recirculation phase is
calculated as follows for the diode and the low-side MOSFET
respectively:
Pdiode = (1-a) . VF . IOUT
where ‘a’ is the duty cycle
Pmosfet_ls = (1-a) . RDS(ON)_ls . IOUT2
where RDS(ON)_ls is the on resistance of the low side.
APPLICATIONS EXAMPLES
EXCEL TOOL
An excel tool has been created with all the above formulas
to calculate the dissipated power and the junction
temperature knowing the application conditions. An example
of the interface is given in Figure 38. The parameters to enter
concern the load, the high side device, the recirculation, and
the board. They are VPWR, DC current in the load (Imax for
100% of duty cycle), PWM frequency, 33981 RDS(ON) at
150 ºC, SR capacitor, low side RDS(ON) at 150 ºC, ambient
temperature, and thermal impedance.
Figure 38. Excel Tool
The calculations are done with the maximum RDS(ON) for
the 33981 and the low side. The current is also considered
constant in the load. The model taken for the VF of the diode
is (0.4 + 0.01 . IOUT) Volts.
The listed conditions in Figure 38 are the ones chosen for
the entire document.
0
20
40
60
80
100
120
4.56 91427
Vbat
SRr(V/µs)
0
1
2.2
3.3
4.7
6.8
0
10
20
30
40
50
60
70
80
90
4.5 6 9 14 27
Vbat
SRf(V/µs)
0
1
2.2
3.3
4.7
6.8
Vpwr
12
V
Imax
20
A
Frequency
20
KHz
R
DSON
@150°C
6.8
mOhm
SR
Capacitor
0
nF
R
DSON
@150°C
20
mOhm
Rthja
15
°C/W
T ambiant
85
°C
INPUTS
Low Side Characteristics
High Side
Device (HS)
Load
Recirculation
Board
Analog Integrated Circuit Device Data
32 Freescale Semiconductor
33981
TYPICAL APPLICATIONS
POWER DISSIPATION
DC MOTOR 200W
A concrete example is the 33981. A 200 W DC motor, a
frequency of 20 kHz, and an ambient temperature of 85 ºC
are chosen. The 33981 is evaluated using the following
board. The thermal impedance of the board is in the range of
15 ºC/W.
Figure 39. 33981 Evaluation Board
POWER DISSIPATION
Figure 40 illustrates the power dissipation in the 33981.
The conditions are listed in Figure 38. Maximum power
dissipation of 3.1 W is obtained with a duty of 95%.
Figure 40. Power Dissipation (Pon and Pswitching) vs.
Duty Cycle
INFLUENCE OF SR CAPACITOR
The SR capacitor value has an impact on these switching
losses. Figure 41 illustrates the percentage of the switching
losses versus the total power dissipation for the same load
conditions as Figure 38. The higher the SR capacitor value,
the higher the switching losses. They can be more than 50%
of the total power dissipation in the 33981 with a 4.7 nF
capacitor and is a basic applications trade-off. A compromise
should be found between the power dissipation and the
electromagnetic capability (EMC) performance.
Figure 41. Power Switching vs. SR Capacitor
RECIRCULATION PHASE
Figure 42 illustrates the power dissipation for the two
recirculation approaches, diode or low side MOSFET. The
power dissipation gain for the entire system when using the
low side instead of the diode can reach up to 1.5 W with a
duty cycle of 50%.
Figure 42. Total Board Power Dissipation
0
0.5
1.5
2.5
3.5
0
10
20
30
40
50
60
70
80
90
100
Pon_state
P switching
Ptotal
MC33981 Power Dissipation
3.0
2.0
1.0
Duty Cycle (%)
MC33981 Power Dissipation (W)
0
1
2
3
4
5
6
02.23.34.7
Pswitching
Pon
Csr (nF)
Power Dissipation (W)
0
1
2
3
4
5
6
02.23.34.7
Pswitching
Pon
Csr (nF)
Power Dissipation (W)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 10 20 30 40 50 60 70 80 90 100
Power HS
Power Diode
Power Total Board with Diode
Power LS
Power Total Board with LS
Total Board Power Dissipation
Power Dissipation (W)
Ratio PWM %
Analog Integrated Circuit Device Data
Freescale Semiconductor 33
33981
TYPICAL APPLICATIONS
POWER DISSIPATION
JUNCTION TEMPERATURE
The junction temperature of the 33981 versus duty cycle
for the condition listed in Figure 38, is given in Figure 43. The
maximum obtained junction temperature is 132 ºC with a duty
cycle of 95%. This value is far from the 150ºC maximum
guaranteed junction.
Figure 43. Junction Temperature vs. Duty Cycle
CONCLUSION
Knowing the application conditions, this document
explained how to calculate power dissipation during on-state
and switching phases and the junction temperature for the
33981 when controlling a DC motor. A concrete example with
a 200 W DC motor was given in DC Motor 200W. The same
principle can be used for other DC motors and other
environmental conditions.
0.00
20.00
40.00
60.00
80.00
100.00
120.00
140.00
0
10
20
30
40
50
60
70
80
90
100
Duty cycle (%)
Junction Temperature (°C)
Analog Integrated Circuit Device Data
34 Freescale Semiconductor
33981
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 33981 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit
board. The AN2467 provides guidelines for Printed Circuit Board design and assembly.
PACKAGING DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using “98ARL10521D”.
Dimensions shown are provided for reference ONLY.
FK SUFFIX
16-PIN PQFN
98ARL10521D
ISSUE C
Analog Integrated Circuit Device Data
Freescale Semiconductor 35
33981
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
16-PIN PQFN
98ARL10521D
ISSUE C
Analog Integrated Circuit Device Data
36 Freescale Semiconductor
33981
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
INTRODUCTION
This thermal addendum is provided as a supplement to the 33981 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
PACKAGING AND THERMAL CONSIDERATIONS
This package is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures,
TJ1 and TJ2, and a thermal resistance matrix with RJAmn.
For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RJ21 and RJ22, respectively.
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
STANDARDS
Figure 44. Surface mount for power PQFN
with exposed pads
16-PIN
PQFN
33981
98ARL10521D
16-PIN PQFN
12 MM X 12 MM
Note For package dimensions, refer to
98ARL10521D.
TJ1
TJ2 =
RJA11
RJA21
RJA12
RJA22
.P1
P2
Table 8. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [C/W]
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
JAmn(1), (2) 22 18 41
JBmn(2), (3) 7.0 4.0 27
JAmn(1), (4) 62 48 81
JCmn(5) <1.0 0.0 1.0
Notes
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
0.2 mm spacing
between PCB pads
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
0.2 mm spacing
between PCB pads
Analog Integrated Circuit Device Data
Freescale Semiconductor 37
33981
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
Figure 45. Thermal Test Board
Device on Thermal Test Board
RJA is the thermal resistance between die junction and
ambient air
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
16-Pin PQFN
0.90 mm Pitch
12.0mm x 12.0mm Body
33981 Pin Connections
Transparent Top View
A
with exposed pads
1
11
10
9
8
7
6
5
4
3
2
1615
14
13
12
OUTOUT
CSNS
TEMP
EN
INHS
FS
INLS
CONF
OCLS
DLS
GLS
SR
CBOOT
GND
VPWR
Material: Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Outline: 80 mm x 100 mm board area,
including edge connector for thermal
testing
Area A: Cu heat-spreading areas on board
surface
Ambient Conditions: Natural convection, still air
Table 9. Thermal Resistance Performance
Thermal
Resistance
Area A
(mm2)
1 = Power Chip, 2 = Logic Chip (C/W)
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
JAmn 066 51 84
300 47 37 73
600 43 34 70
Analog Integrated Circuit Device Data
38 Freescale Semiconductor
33981
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
Figure 46. Device on Thermal Test Board RJA
Figure 47. Transient Thermal Resistance RJA,
1 W Step response,Device on Thermal Test Board Area A = 600(mm2)
0
10
20
30
40
50
60
70
80
90
Heat spreading area A [m m²]
Thermal Resistance [ºC/W]
0 300 600
R
JA11
R
JA22
R
JA12
=R
JA21
x
0.1
1
10
100
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Thermal Resistance [ºC/W]
R
JA11
R
JA22
R
JA12
=R
JA21
x
Analog Integrated Circuit Device Data
Freescale Semiconductor 39
33981
REVISION HISTORY
REVISION HISTORY
Revision Date Description of Changes
3.0 1/2006 • Implemented Revision History page
• Made content updates and changes
• Converted to Freescale format
• Added Thermal Addendum
4.0 3/2006 • Made minor content changes to pages 6 and 7.
• Updated to Product Preview status
5.0 5/2006 • Changed Part Number from PC33981PNA to MC33981BPNA in the ordering information
• Changed Electrical Characteristics, Maximum Ratings, Table 2, Maximum Ratings, Electrical
Ratings, OCLS Voltage, from “-5.0 to 5.0” to “-5.0 to 7.0” (page 5).
• Changed Electrical Characteristics, Static Electrical Characteristics, Table 3, Static Electrical
Characteristics, Low Side Gate Driver (VPWR, VGLS, VOCLS), Low-Side Overload Detection
Level versus Low-Side Drain Voltage Minimum, from “-75” to “-50” and Maximum from “+75” to
“+50” (page 8).
• Changed Electrical Characteristics, Dynamic Electrical Characteristics, Table 4, Dynamic Electrical
Characteristics, Control Interface and Power Output Timing (CBOOT, VPWR), Input Switching
Frequency, Minimum from “20” to “-” and Typical from “-” to “20” (page 10).
• Updated to Advanced status
6.0 5/2007 • Changed CSNS Input Clamp Current in MAXIMUM RATINGS
• Changed Figure 11, Reverse Battery Protection
• Removed unnecessary line in Figure 14, Overload on Low Side Gate Drive, Case 2
• Corrected label in Figure 28, 33981 with Filter
7.0 10/2008 • Updated Freescale form and style
• Minor text corrections.
• Added Current Sense Leakage(10)
8.0 6/2009 • Corrected Reference to Figure 15 on Page 13.
9.0 10/2010 • Reworded Notes 5 and 11.
10.0 5/2012 • Updated Orderable part number from MC33981BPNA to MC33981BHFK
• Updated (6)
• Updated soldering information
• Updated Freescale form and style
11.0 7/2012 • Added MC33981ABHFK to the ordering information
• Added Device Variations table
Document Number: MC33981
Rev. 11.0
7/2012
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