FUJITSU SEMICONDUCTOR DATA SHEET DS05-11306-4E MEMORY CMOS 2 M x 8 BIT HYPER PAGE MODE DYNAMIC RAM MB81V17805B-50/-60/-50L/-60L CMOS 2,097,152 x 8 Bit Hyper Page Mode Dynamic RAM DESCRIPTION The Fujitsu MB81V17805B is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory cells accessible in 8-bit increments. The MB81V17805B features a "hyper page" mode of operation whereby high-speed random access of up to 1024 x 8 bits of data within the same row can be selected. The MB81V17805B DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. Since the standby current of the MB81V17805B is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. The MB81V17805B is fabricated using silicon gate CMOS and Fujitsu's advanced four-layer polysilicon and twolayer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for the MB81V17805B are not critical and all inputs are LVTTL compatible. PRODUCT LINE & FEATURES MB81V17805B Parameter -50 -50L -60 -60L RAS Access Time 50 ns max. 60 ns max. Random Cycle Time 84 ns min. 104 ns min. Address Access Time 25 ns max. 30 ns max. CAS Access Time 13 ns max. 15 ns max. Hyper Page Mode Cycle Time 20 ns min. 25 ns min. 468 mW max. 396 mW max. Operating Current Low Power Dissipation Standby Current LVTTL level 3.6 mW max. 3.6 mW max. 3.6 mW max. 3.6 mW max. CMOS level 1.8 mW max. 0.54 mW max. 1.8 mW max. 0.54 mW max. * 2,097,152 words x 8 bits organization * Silicon gate, CMOS, Advanced Stacked Capacitor Cell * All input and output are LVTTL compatible * 2,048 refresh cycles every 32.8 ms * Self refresh function (Low power version) * Early write or OE controlled write capability * RAS-only, CAS-before-RAS, or Hidden Refresh * Hyper Page Mode, Read-Modify-Write capability * On chip substrate bias generator for high performance * Standard and low power versions MB81V17805B-50/-60/-50L/-60L PACKAGE 28-pin plastic SOJ 28-pin plastic TSOP (II) (LCC-28P-M07) (FPT-28P-M14) (Normal Bend) Package and Ordering Information - 28-pin plastic (400 mil) SOJ, order as MB81V17805B-xxPJ - 28-pin plastic (400 mil) TSOP(II) with normal bend leads, order as MB81V17805B-xxPFTN and MB81V17805B-xxLPFTN (Low Power) 2 MB81V17805B-50/-60/-50L/-60L PIN ASSIGNMENTS AND DESCRIPTIONS 28-Pin SOJ (TOP VIEW) <LCC-28P-M07> VCC DQ1 DQ2 DQ3 DQ4 WE RAS N.C. A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 1 Pin Index 26 25 24 23 22 21 20 19 18 17 16 15 Designator VSS DQ8 DQ7 DQ6 DQ5 CAS OE A9 A8 A7 A6 A5 A4 VSS A0 to A10 Function Address inputs row : A0 to A10 column : A0 to A9 refresh : A0 to A10 RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable DQ1 to DQ8 Data Input/Output VCC +3.3 volt power supply VSS Circuit ground N.C. No Connection 28-Pin TSOP(II) (TOP VIEW) <Normal Bend: FPT-28P-M14> VCC DQ1 DQ2 DQ3 DQ4 WE RAS N.C. A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 1 Pin Index 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ8 DQ7 DQ6 DQ5 CAS OE A9 A8 A7 A6 A5 A4 VSS 3 MB81V17805B-50/-60/-50L/-60L Fig. 1 - MB81V17805B DYNAMIC RAM - BLOCK DIAGRAM RAS Clock Gen #1 CAS Write Clock Gen WE Mode Control Clock Gen #2 Data In Buffer A0 A1 Column Decoder A2 A3 A4 A5 Address Buffer & PreDecoder DQ1 to DQ8 Sense Amp & I/O Gate A6 Row Decoder A7 16,777,216 Bit Storage Cell Data Out Buffer A8 A9 A10 OE Refresh Address Counter Substrate Bias Gen VCC VSS 4 MB81V17805B-50/-60/-50L/-60L FUNCTIONAL TRUTH TABLE Clock Input Operation Mode Address Input Input/Output Data Refresh Note RAS CAS WE OE Row Column Input Output Standby H H X X -- -- -- High-Z -- Read Cycle L L H L Valid Valid -- Valid Yes* tRCS tRCS (min) Write Cycle (Early Write) L L L X Valid Valid Valid High-Z Yes* tWCS tWCS (min) Read-ModifyWrite Cycle L L Valid Valid Valid Valid Yes* RAS-only Refresh Cycle L H X X Valid X -- High-Z Yes CAS-beforeRAS Refresh Cycle L L X X X X -- High-Z Yes tCSR tCSR (min) HL L HX L X X -- Valid Yes Previous data is kept. Hidden Refresh Cycle HL LH X: "H" or "L" * : It is impossible in Hyper Page Mode. FUNCTIONAL OPERATION ADDRESS INPUTS Twenty-one input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. Since only eleven address bits (A0 to A10) are available, the column and row inputs are separately strobed by CAS and RAS as shown in Figure 1. First, eleven row address bits are input on pins A0-through-A10 and latched with the row address strobe (RAS) then, ten column address bits are input and latched with the column address strobe (CAS). Both row and column addresses must be stable on or before the falling edges of RAS and CAS, respectively. The address latches are of the flow-through type; thus, address information appearing after tRAH (min) + tT is automatically treated as the column address. WRITE ENABLE The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is selected. During the read mode, input data is ignored. DATA INPUTS Input data is written into memory in either of three basic ways: an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data is strobed by CAS and the setup/hold times are referenced to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal. 5 MB81V17805B-50/-60/-50L/-60L DATA OUTPUTS The three-state buffers are LVTTL compatible with a fanout of one TTL load. Polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs and High-Z state are obtained under the following conditions: tRAC : tCAC : tAA : tOEA : tOEZ : tOFF : tOFR : tWEZ : from the falling edge of RAS when tRCD (max) is satisfied. from the falling edge of CAS when tRCD is greater than tRCD (max). from column address input when tRAD is greater than tRAD (max), and tRCD (max) is satisfied. from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA. from OE inactive. from CAS inactive while RAS inactive. from RAS inactive while CAS inactive. from WE active while CAS inactive. The data remains valid before either OE is inactive, or both RAS and CAS are inactive, or CAS is reactived. When an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. HYPER PAGE MODE OPERATION The hyper page mode operation provides faster memory access and lower power dissipation. The hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each page of memory (within column address locations), any of 1,024 x 8 bits can be accessed and, when multiple MB81V17805Bs are used, CAS is decoded to select the desired memory page. Hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. Hyper page mode features that output remains valid when CAS is inactive until CAS is reactivated. 6 MB81V17805B-50/-60/-50L/-60L ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Value Unit VIN, VOUT -0.5 to +4.6 V Voltage of VCC Supply Relative to VSS VCC -0.5 to +4.6 V Power Dissipation PD 1.0 W Short Circuit Output Current IOUT -50 to +50 mA Operating Temperature TOPE 0 to +70 C Storage Temperature TSTG -55 to +125 C Voltage at Any Pin Relative to VSS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS Parameter Notes Symbol Min. Typ. Max. VCC 3.0 3.3 3.6 VSS 0 0 0 Unit Ambient Operating Temp. V Supply Voltage *1 Input High Voltage, All Inputs *1 VIH 2.0 -- VSS +0.3 V Input Low Voltage, All Inputs* *1 VIL -0.3 -- 0.8 V 0C to +70C * : Undershoots of up to -2.0 volts with a pulse width not exceeding 20 ns are acceptable. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. CAPACITANCE (TA = 25C, f = 1 MHz) Parameter Symbol Max. Unit Input Capacitance, A0 to A10 CIN1 5 pF Input Capacitance, RAS, CAS, WE, OE CIN2 5 pF Input/Output Capacitance, DQ1 to DQ8 CDQ 7 pF 7 MB81V17805B-50/-60/-50L/-60L DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Note 3 Value Parameter Notes Symbol Min. Typ. Max. Unit Std power Low power Output High Voltage *1 VOH IOH = -2.0 mA 2.4 -- -- -- Output Low Voltage *1 VOL IOL = +2.0 mA -- -- 0.4 0.4 I I(L) 0 V VIN 3.6 V; 3.0 V VCC 3.6 V; VSS = 0 V; All other pins not under test = 0 V -10 -- 10 10 IDO(L) 0 V VOUT 3.6 V; 3.0 V VCC 3.6 V; Data out disabled -10 -- ICC1 RAS & CAS cycling; tRC = min. -- -- Input Leakage Current (Any Input) Output Leakage Current Operating Current (Average Power Supply Current) *2 Standby Current (Power Supply Current) *2 Refresh Current#1 (Average Power Supply Current) Hyper Page Mode Current Refresh Current#2 (Average Power Supply Current) MB81V17805B -50/50L MB81V17805B -60/60L LVTTL Level *2 *2 *2 CMOS Level MB81V17805B -50/50L MB81V17805B -60/60L MB81V17805B -50/50L MB81V17805B -60/60L MB81V17805B -50/50L MB81V17805B -60/60L ICC3 ICC4 ICC5 Battery Backup Current (Average Power Supply Current) *2 ICC6 MB81V17805B -50L/60L Refresh Current#3 (Average Power Supply Current) MB81V17805B -50L/60L ICC9 RAS = CAS VCC -0.2 V CAS = VIH, RAS cycling; tRC = min. V A RAS = CAS = VIH ICC2 MB81V17805B -50/60 8 Conditions -- -- -- -- 10 10 130 130 110 110 1.0 1.0 mA 500 150 A 130 130 110 110 100 100 90 90 130 130 110 110 1000 -- mA mA RAS = VIL, CAS cycling; tHPC = min. -- RAS cycling; CAS-before-RAS; tRC = min. -- RAS cycling; CAS-before-RAS; tRC = 16 s tRAS = min. to 300 ns VIH VCC -0.2 V, VIL 0.2 V -- RAS cycling; CAS-before-RAS; tRC = 64 s tRAS = min. to 300 ns VIH VCC -0.2 V, VIL 0.2 V -- -- -- 300 RAS = VIL, CAS = VIL Self refresh; -- -- -- 250 -- mA -- -- mA A A MB81V17805B-50/-60/-50L/-60L AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 3, 4, 5 No. Parameter Notes Std power Symbol MB81V17805B -60/60L Min. Max. Min. Max. -- 32.8 -- 32.8 -- 128 -- 128 Unit ms 1 Time between Refresh 2 Random Read/Write Cycle Time tRC 84 -- 104 -- ns 3 Read-Modify-Write Cycle Time tRWC 114 -- 138 -- ns 4 Access Time from RAS *6,9 tRAC -- 50 -- 60 ns 5 Access Time from CAS *7,9 tCAC -- 13 -- 15 ns 6 Column Address Access Time *8,9 tAA -- 25 -- 30 ns 7 Output Hold Time tOH 3 -- 3 -- ns 8 Output Hold Time from CAS tOHC 3 -- 3 -- ns 9 Output Buffer Turn On Delay Time tON 0 -- 0 -- ns 10 Output Buffer Turn Off Delay Time *10 tOFF -- 13 -- 15 ns 11 Output Buffer Turn Off Delay Time from RAS *10 tOFR -- 13 -- 15 ns 12 Output Buffer Turn Off Delay Time from WE *10 tWEZ -- 13 -- 15 ns 13 Transition Time tT 1 50 1 50 ns 14 RAS Precharge Time tRP 30 -- 40 -- ns 15 RAS Pulse Width tRAS 50 100000 60 100000 ns 16 RAS Hold Time tRSH 13 -- 15 -- ns 17 CAS to RAS Precharge Time *21 tCRP 5 -- 5 -- ns 18 RAS to CAS Delay Time *11,12,22 tRCD 11 37 14 45 ns 19 CAS Pulse Width tCAS 7 -- 10 -- ns 20 CAS Hold Time tCSH 38 -- 40 -- ns 21 CAS Precharge Time (Normal) tCPN 7 -- 10 -- ns 22 Row Address Setup Time tASR 0 -- 0 -- ns 23 Row Address Hold Time tRAH 7 -- 10 -- ns 24 Column Address Setup Time tASC 0 -- 0 -- ns 25 Column Address Hold Time tCAH 7 -- 10 -- ns 26 Column Address Hold Time from RAS tAR 18 -- 24 -- ns 27 RAS to Column Address Delay Time tRAD 9 25 12 30 ns 28 Column Address to RAS Lead Time tRAL 25 -- 30 -- ns 29 Column Address to CAS Lead Time tCAL 18 -- 23 -- ns 30 Read Command Setup Time tRCS 0 -- 0 -- ns Low power *19 *13 tREF MB81V17805B -50/50L (Continued) 9 MB81V17805B-50/-60/-50L/-60L No. Parameter Notes Symbol MB81V17805B -50/50L MB81V17805B -60/60L Min. Max. Min. Max. Unit 31 Read Command Hold Time Referenced to RAS *14 tRRH 0 -- 0 -- ns 32 Read Command Hold Time Referenced to CAS *14 tRCH 0 -- 0 -- ns 33 Write Command Setup Time *15,*20 tWCS 0 -- 0 -- ns 34 Write Command Hold Time tWCH 7 -- 10 -- ns 35 Write Command Hold Time from RAS tWCR 18 -- 24 -- ns 36 WE Pulse Width tWP 7 -- 10 -- ns 37 Write Command to RAS Lead Time tRWL 13 -- 15 -- ns 38 Write Command to CAS Lead Time tCWL 7 -- 10 -- ns 39 DIN Setup Time tDS 0 -- 0 -- ns 40 DIN Hold Time tDH 7 -- 10 -- ns 41 Data Hold Time from RAS tDHR 18 -- 24 -- ns 42 RAS to WE Delay Time *20 tRWD 65 -- 77 -- ns 43 CAS to WE Delay Time *20 tCWD 28 -- 32 -- ns 44 Column Address to WE Delay Time *20 tAWD 40 -- 47 -- ns 45 RAS Precharge Time to CAS Active Time (Refresh Cycles) tRPC 5 -- 5 -- ns 46 CAS Setup Time for CAS-beforeRAS Refresh tCSR 0 -- 0 -- ns 47 CAS Hold Time for CAS-before-RAS Refresh tCHR 10 -- 10 -- ns 48 Access Time from OE *9 tOEA -- 13 -- 15 ns 49 Output Buffer Turn Off Delay from OE *10 tOEZ -- 13 -- 15 ns 50 OE to RAS Lead Time for Valid Data tOEL 5 -- 5 -- ns 51 OE to CAS Lead Time tCOL 5 -- 5 -- ns 52 OE Hold Time Referenced to WE tOEH 5 -- 5 -- ns 53 OE to Data In Delay Time tOED 13 -- 15 -- ns 54 RAS to Data In Delay Time tRDD 13 -- 15 -- ns 55 CAS to Data In Delay Time tCDD 13 -- 15 -- ns 56 DIN to CAS Delay Time *17 tDZC 0 -- 0 -- ns 57 DIN to OE Delay Time *17 tDZO 0 -- 0 -- ns 58 OE Precharge Time tOEP 5 -- 5 -- ns 59 OE Hold Time Referenced to CAS tOECH 7 -- 10 -- ns 60 WE Precharge Time tWPZ 5 -- 5 -- ns *16 (Continued) 10 MB81V17805B-50/-60/-50L/-60L (Continued) No. Parameter Notes Symbol MB81V17805B -50/50L MB81V17805B -60/60L Min. Max. Min. Max. Unit 61 WE to Data In Delay Time tWED 13 -- 15 -- ns 62 Hyper Page Mode RAS Pulse Width tRASP -- 100000 -- 100000 ns 63 Hyper Page Mode Read/Write Cycle Time tHPC 20 -- 25 -- ns 64 Hyper Page Mode Read-ModifyWrite Cycle Time tHPRWC 59 -- 69 -- ns 65 Access Time from CAS Precharge tCPA -- 30 -- 35 ns 66 Hyper Page Mode CAS Precharge Time tCP 7 -- 10 -- ns 67 Hyper Page Mode RAS Hold Time from CAS Precharge tRHCP 30 -- 35 -- ns 68 Hyper Page Mode CAS Precharge to WE Delay Time tCPWD 45 -- 52 -- ns *9,18 *20 11 MB81V17805B-50/-60/-50L/-60L Notes: *1. Referenced to VSS. *2. ICC depends on the output load conditions and cycle rates; the specified values are obtained with the output open. ICC depends on the number of address change as RAS = VIL, CAS = VIH and VIL > -0.3 V. ICC1, ICC3, ICC4 and ICC5 are specified at one time of address change during RAS = VIL and CAS = VIH. ICC2 is specified during RAS = VIH and VIL > -0.3 V. ICC6 is measured on condition that all address signals are fixed steady state. *3. An initial pause (RAS = CAS = VIH) of 200 s is required after power-up followed by any eight RASonly cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. *4. AC characteristics assume tT = 2 ns. *5. Input voltage levels are 0 V and 3.0 V, and input reference levels are V IH (min) and VIL (max) for measuring timing of input signals. Also, transition time (tT) is measured between V IH (min) and VIL (max). The output reference levels are VOH = 2.0 V and VOL = 0.8 V. *6. Assumes that tRCD tRCD (max), tRAD tRAD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig.2 and 3. *7. If tRCD tRCD (max), tRAD tRAD (max), and tASC tAA - tCAC - tT, access time is tCAC. *8. If tRAD tRAD (max) and tASC tAA - tCAC - tT, access time is tAA. *9. Measured with a load equivalent to one TTL load and 100 pF. *10. tOFR, tWEZ, tOFF and tOEZ are specified that output buffer change to high-impedance state. *11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC or tAA. *12. tRCD (min) = tRAH (min) + 2tT + tASC (min). *13. Operation within the tRAD (max) limit ensures that t RAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled exclusively by tCAC or tAA. *14. Either tRRH or tRCH must be satisfied for a read cycle. *15. tWCS is specified as a reference point only. If t WCS tWCS (min) the data output pin will remain High-Z state through entire cycle. *16. Assumes that tWCS < tWCS (min). *17. Either tDZC or tDZO must be satisfied. *18. tCPA is access time from the selection of a new column address (that is caused by changing both CAS from "L" to "H"). Therefore, if tCP is long, tCPA is longer than tCPA (max). *19. Assumes that CAS-before-RAS refresh. *20. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as an electrical characteristic only. If tWCS > tWCS (min), the cycle is an early write cycle and DQ pin will maintain high-impedance state throughout the entire cycle. If tCWD > tCWD (min), tRWD > tRWD (min), tAWD > tAWD (min) and tCPWD > tCPWD (min) the cycle is a read-modify-write cycle and data from the selected cell will appear at the DQ pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle and invalid data will appear the DQ pin, and write operation can be executed by satisfying t RWL, tCWL, tRAL and tCAL specifications. *21. The last CAS rising edge. *22. The first CAS falling edge. 12 MB81V17805B-50/-60/-50L/-60L Fig. 2 - tRAC vs. tRCD Fig. 3 - tRAC vs. tRAD Fig. 4 - tCPA vs. tCP tRAC (ns) tRAC (ns) tCPA (ns) 90 90 70 80 80 60 70 70 60 ns version 60 ns version 60 60 50 ns version 50 0 10 20 30 50 50 ns version 50 40 tRCD (ns) 50 60 60 ns version 40 50 ns version 30 0 10 20 30 40 tRAD (ns) 50 60 0 10 20 30 40 50 tCP (ns) 13 MB81V17805B-50/-60/-50L/-60L Fig. 5 - READ CYCLE tRC tRAS RAS tAR VIH VIL tCRP tCSH tRP tRCD CAS tCAS VIH VIL tRAD tASR A0 to A10 VIH VIL tRSH tCDD tRAL tCAL tRAH tASC ROW ADDRESS tCAH tOEL tCOL COLUMN ADDRESS tRRH tRCS WE tRDD tRCH VIH VIL tWPZ tAA tCAC tOH tRAC DQ (Output) VOH VOL tOFF HIGH-Z tDZC DQ (Input) tON tOEZ tOEA VIH VIL HIGH-Z tDZO OE tWED tWEZ tON tOH tOED VIH VIL "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) Valid Data DESCRIPTION To implement a read operation, a valid address is latched by the RAS and CAS address strobes and with WE set to a High level and OE set to a Low level, the output is valid once the memory access time has elapsed. DQ pins are valid when RAS and CAS are High or until OE goes High. The access time is determined by RAS(tRAC), CAS(tCAC), OE(tOEA) or column addresses (tAA) under the following conditions: If tRCD > tRCD (max), access time = tCAC. If tRAD > tRAD (max), access time = tAA. If OE is brought Low after tRAC, tCAC, or tAA (whichever occurs later), access time = tOEA. However, if either CAS or OE goes High, the output returns to a high-impedance state after tOH is satisfied. 14 MB81V17805B-50/-60/-50L/-60L Fig. 6 - EARLY WRITE CYCLE tRC tRAS RAS VIH VIL tCRP tCSH tRP tRCD tRSH tCAS CAS VIH VIL tAR tASR tASC tRAH tCAH tCAL tRAL A0 to A10 VIH VIL ROW ADDRESS COLUMN ADDRESS tWCR tWCS WE tWCH VIH VIL tDHR tDS DQ (Input) VIH VIL VOH DQ (Output) VOL tDH VALID DATA IN HIGH-Z "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) DESCRIPTION A write cycle is similar to a read cycle except WE is set to a Low state and OE is an "H" or "L" signal. A write cycle can be implemented in either of three ways - early write, delayed write, or read-modify-write. During all write cycles, timing parameters tRWL, tCWL, tRAL and tCAL must be satisfied. In the early write cycle shown above tWCS satisfied, data on the DQ pins are latched with the falling edge of CAS and written into memory. 15 MB81V17805B-50/-60/-50L/-60L Fig. 7 - DELAYED WRITE CYCLE (OE CONTROL) tRC tRAS RAS tAR VIH VIL tRP tCSH tCRP tRCD tCAS tRSH CAS VIH VIL tASR tRAH tASC tCAH tCAL tRAL A0 to A10 VIH VIL ROW ADD COL ADD tCWL tRCS tWCH tRWL tWP WE VIH VIL tDS tDZC DQ (Input) VIH VIL tDH HIGH-Z tOED VALID DATA IN tON VOH DQ (Output) VOL HIGH-Z tDZO HIGH-Z tOEH tON tOEZ OE VIH VIL "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) Invalid Data DESCRIPTION IIn the delayed write cycle, tWCS is not satisfied; thus, the data on the DQ pins are latched with the falling edge of WE and written into memory. The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED + tT + tDS). 16 MB81V17805B-50/-60/-50L/-60L Fig. 8 - READ-MODIFY-WRITE CYCLE tRWC tRAS RAS tAR VIH VIL tRP tCRP CAS tRCD VIH VIL tRAD tASR A0 to A10 VIH VIL tRAH tASC ROW ADD tCAH COL ADD tRWD WE tCWL tAWD tCWD tRCS tRWL VIH VIL tDS tDZC DQ (Input) VIH VIL tWP tDH VALID DATA IN HIGH-Z tOED tCAC tOEH tAA tRAC VOH DQ (Output) VOL VALID DATA HIGH-Z tDZO HIGH-Z tON tOEA tON tOEZ OE VIH VIL tOH "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) DESCRIPTION The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the readmodify-write cycle, OE must be changed from Low to High after the memory access time. 17 MB81V17805B-50/-60/-50L/-60L Fig. 9 - HYPER PAGE MODE READ CYCLE tRASP tRCD RAS tRHCP VIH VIL tRAD tHPC tCRP CAS tCSH VIH VIL tAR tASC tCAL ROW ADD tCAH tASC tRRH tCAL tCAL tRCS tRCH tRAL COL ADD COL ADD tRCH tRCS tOH tCPA tCPA tCDD tOHC VIH VIL HIGH-Z tOFR tDZO tCAC tON tRAC DQ (Output) VOH VOL tCAC tON tON tOHC tOFF tOH HIGH-Z tAA OE tRCH VIH VIL tDZC DQ (Input) tCAS tCAH tASC tCAH COL ADD tRCS WE tRP tRDD tRAH VIH VIL tCAS tCAS tASR A0 to A10 tRSH tCP tAA tOH tOEZ tOED VIH VIL During one cycle is achieved, the input/output timing apply the same manner as the former cycle. "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) Valid Data DESCRIPTION The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The address time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring. 18 MB81V17805B-50/-60/-50L/-60L Fig. 10 - HYPER PAGE MODE READ CYCLE (OE CONTROL) tRASP tRCD RAS tRHCP VIH VIL tRAD tCRP CAS tHPC tCSH tASR ROW ADD tASC tASC tRAH A0 to A10 tCAH tCAH tASC tRRH tCAS tCAS tCAL tRP tRSH tCP tCAS VIH VIL VIH VIL tCP tCAH tCDD tCAL tCAL COL ADD tRAL COL ADD COL ADD tRCS WE tRCH tRDD VIH VIL tOH tDZC DQ (Input) tOHC VIH VIL HIGH-Z HIGH-Z tCPA tCPA tRAC tAA tAA tCAC DQ (Output) VOH VOL HIGH-Z tAA tCAC tCAC tOH tOECH tON tOH tOEZ tOEP VIH VIL tOFF tON tDZO OE tOFR tOH tOEA tOH tOEZ tOED tCOL tOEA tOEA tOEZ During one cycle is achieved, the input/output timing apply the same manner as the former cycle. "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) Valid Data DESCRIPTION The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The address time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring. 19 MB81V17805B-50/-60/-50L/-60L Fig. 11 - HYPER PAGE MODE READ CYCLE (WE CONTROL) tRASP tRHCP RAS VIH VIL tRCD tCRP CAS tHPC tRAD tASR tCAL tASC tRAH VIH VIL ROW ADD tASC tCAH COL ADD tRCS tRCH tWPZ tOFR tCAH COL ADD tRCH tRDD tCAL tCAL COL ADD tRCS WE tRAL tCAH tASC A0 to A10 tCAS tCAS tCAS VIH VIL tRP tRSH tCSH tOH tRCS tRCH tWPZ tWPZ VIH VIL tCDD tWED tDZC tOH DQ (Input) VIH VIL HIGH-Z tAA tRAC tAA tCAC DQ (Output) VOH VOL tWEZ tCAC tON HIGH-Z HIGH-Z tWEZ tAA tCAC tOFF tWEZ tON tON tOH tOEZ tDZO OE VIH VIL tOED tON tOEA During one cycle is achieved, the input/output timing apply the same manner as the former cycle. "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) Valid Data DESCRIPTION The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The address time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring. 20 MB81V17805B-50/-60/-50L/-60L Fig. 12 - HYPER PAGE MODE EARLY WRITE CYCLE tRASP VIH VIL RAS tRHCP tHPC tCSH tCRP tRCD tCAS tCP tRSH tRP tCAS tCAS VIH VIL CAS tAR tASC tASR A0 to A10 VIH VIL tCAH tCAH tRAH tASC tCAL tASC tCAL COL ADD COL ADD tWCH tWCR tWCH tWCS tCAH tRAL tCAL COL ADD ROW ADD tCAL tWCS tCWL tWCH tWCS tCWL tRWL tCWL VIH VIL WE tDHR tDH tDS DQ (Input) VIH VIL DQ (Output) VOH VOL VALID DATA tDS tDH VALID DATA tDS tDH VALID DATA HIGH-Z During one cycle is achieved, the input/output timing apply the same manner as the former cycle. "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) DESCRIPTION The hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of WE and OE are reversed. Data appearing on the DQ pins are latched on the falling edge of CAS and the data is written into the memory. During the hyper page mode early write cycle, including the delayed (OE) write and read-modify-write cycles, tCWL must be satisfied. 21 MB81V17805B-50/-60/-50L/-60L Fig. 13 - HYPER PAGE MODE DELAYED WRITE CYCLE RAS tRASP VIH VIL tRP tCSH tCRP tRCD CAS VIH VIL tASR VIH VIL tASC tRAH tCAL ROW ADDRESS VIH VIL tWCH tWP DQ (Output) VOH VOL tWCH tWP tDS tDH tDH VALID DATA IN tOED tON tOEH VALID DATA IN tON tOED HIGH-Z tON tDZO OE tRWL tCWL tDS VIH VIL tCWL COL ADD tDZC DQ (Input) tCAL tRAL tCAH tCAH COLUMN ADDRESS tRCS WE tRSH tCAS tASC tAR A0 to A10 tCP tCAS tHPC tON tOEZ tOEH tOEZ VIH VIL "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and Invalid Data DESCRIPTION The hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the hyper page mode delayed write cycle, OE must be changed from Low to High before WE goes Low (tOED + tT + tDS). 22 MB81V17805B-50/-60/-50L/-60L Fig. 14 - HYPER PAGE MODE READ/WRITE MIXED CYCLE RAS tRASP VIH VIL tRHCP tRCD tCRP CAS VIH VIL A0 to A10 VIH VIL tCP tCSH tASC tRAH ROW ADD tCAL tCAH tCAH tASC COL ADD COL ADD tRAL tCAH tCAL COL ADD tRCH tRCS WE tCAS tCAL tASC tWCH tWCS VIH VIL tDZC tWED tDH tDS DQ (Input) VIH VIL VALID DATA IN HIGH-Z tCPA tRAC tAA tAA tOHC tCAC DQ VOH (Output) VOL tCAC HIGH-Z tON tOEZ tOED tON OE tWEZ HIGH-Z tDZO VIH VIL tRP tRSH tCAS tCAS tRAD tASR tHPC tOEA "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) Valid Data DESCRIPTION The hyper page mode performs read/write operations repetitively during one RAS cycle. At this time, tHPC (min) is invalid. 23 MB81V17805B-50/-60/-50L/-60L Fig. 15 - HYPER PAGE MODE READ-MODIFY-WRITE CYCLE RAS tRASP VIH VIL tRP tCRP CAS tHPRWC tCWD tCP tRAD tASR A0 to A10 tRCD VIH VIL VIH VIL tRWL tASC tCAH tASC tRAH tCAH COLUMN ADDRESS ROW ADDRESS COL ADD tAWD tCPWD tCWL tRCS WE VIH VIL VIH VIL tOED tAA VOH VOL VALID DATA tOED tCAC tAA VALID DATA tCAC tON tON HIGH-Z tDH tDH tON tOEH tRAC tDZO OE tWP tDS tDS tDZC DQ (Output) tCWL tRCS tWP tRWD DQ (Input) tCWD tON tOEA tOEZ tOEZ tOEH VIH VIL tOEA tCPA "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) Valid Data DESCRIPTION During the hyper page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input data appears at the DQ pins during a normal cycle. 24 MB81V17805B-50/-60/-50L/-60L Fig. 16 - RAS-ONLY REFRESH (WE = OE = "H" or "L") tRC RAS tRAS VIH VIL tASR A0 to A10 VIH VIL tRP tRAH tRPC ROW ADDRESS tCRP tCRP CAS VIH VIL tOFF tOH VOH DQ (Output) VOL HIGH-Z "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) DESCRIPTION Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row addresses every 32.8-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state. Fig. 17 - CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = "H" or "L") tRC RAS tRP tRAS VIH VIL tCPN tCSR tCHR tRPC tCSR tCPN CAS VIH VIL tOFF tOH VOH DQ (Output) VOL HIGH-Z DESCRIPTION CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low for the specified setup time (tCSR) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-before-RAS refresh operation. 25 MB81V17805B-50/-60/-50L/-60L Fig. 18 - HIDDEN REFRESH CYCLE tRC tRC tRAS RAS tRP tOEL VIH VIL tRCD tRP tCRP tRSH tRAD CAS tRAS VIH VIL tCHR tRAH tASR tASC tAR tRAL tCAH A0 to A10 VIH VIL ROW ADDRESS COLUMN ADDRESS tRRH tRCS WE VIH VIL tAA tRAC tDZC DQ (Input) tCDD tCAC VIH VIL HIGH-Z tOFR tOFF tON tOH tOH DQ VOH (Output) VOL HIGH-Z tDZO OE VALID DATA OUT tOEA tOEZ tOED VIH VIL "H" or "L" level (excluding Address and DQ) "H" or "L" level, "HL" or "LH" transition (Address and DQ) DESCRIPTION A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of CAS and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row address that is required by DRAMs that do not have CAS-before-RAS refresh capability. 26 MB81V17805B-50/-60/-50L/-60L Fig. 19 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE RAS VIH VIL tCHR tCP tFRSH tFCAS tCSR CAS VIH VIL tFCAH tASC A0 to A10 VIH VIL COLUMN ADDRESSES tRCS WE tRP VIH VIL tCWL tRWL tFCWD tDZC tWP tDS tDH DQ (Input) VIH VIL DQ (Output) VOH VOL HIGH-Z tOED tFCAC HIGH-Z tDZO OE VALID DATA IN tON tOEA VIH VIL HIGH-Z tOEH tOEZ "H" or "L" level (excluding Address and DQ) "H" or "L" level, "H L" or "L"H" transition (Address and DQ) Valid Data DESCRIPTION A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function of CAS-before-RAS refresh circuitry. If a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows: Row Addresses: Bits A0 through A10 are defined by the on-chip refresh counter. Column Addresses: Bits A0 through A9 are defined by latching levels on A0 to A9 at the second falling edge of CAS. The CAS-before-RAS Counter Test procedure is as follows; 1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles. 2) Use the same column address throughout the test. 3) Write "0" to all 2,048 row addresses at the same column address by using normal write cycles. 4) Read "0" written in procedure 3) and check; simultaneously write "1" to the same addresses by using CASbefore-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 2,048 times with addresses generated by the internal refresh address counter. 5) Read and check data written in procedure 4) by using normal read cycle for all 2,048 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5). (At recommended operating conditions unless otherwise noted.) No. Parameter 69 Access Time for CAS 70 Symbol MB81V17805B-50/50L MB81V17805B-60/60L Unit Min. Max. Min. Max. tFCAC -- 45 -- 50 ns Column Address Hold Time tFCAH 35 -- 35 -- ns 71 CAS to WE Delay Time tFCWD 63 -- 70 -- ns 72 CAS Pulse Width tFCAS 45 -- 50 -- ns 73 RAS Hold Time tFRSH 45 -- 50 -- ns Note: Assumes that CAS-before-RAS refresh counter test cycle only. 27 MB81V17805B-50/-60/-50L/-60L Fig. 20 - SELF REFRESH CYCLE (A0 to A10 = WE = OE = "H" or "L") RAS tCPN CAS tRPS tRASS VIH VIL tCSR tRPC tCHS VIH VIL tOFF tOH DQ VOH (Output) VOL HIGH-Z "H" or "L" level (excluding Address and DQ) "H" or "L" level, "H" "L" or "L" "H" transition (Address and DQ) (At recommended operating conditions unless otherwise noted.) No. Parameter MB81V17805B-50L Symbol MB81V17805B-60L Min. Max. Min. Max. Unit 74 RAS Pulse Width tRASS 100 -- 100 -- s 75 RAS Precharge Time tRPS 84 -- 104 -- ns 76 CAS Hold Time tCHS -50 -- -50 -- ns Note: Assumes Self Refresh cycle only. DESCRIPTION The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter. If CAS goes to "L" before RAS goes to "L" (CBR) and the condition of CAS "L" and RAS "L" is kept for term of tRASS (more than 100 s), the device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using internal refresh address counter during "RAS=L" and "CAS=L". Exit from self refresh cycle is performed by toggling RAS and CAS to "H" with specified tCHS min.. In this time, RAS must be kept "H" with specified tRPS min. Using self refresh mode, data can be retained without external CAS signal during system is in standby. Restriction for Self Refresh operation ; For self refresh operation, the notice below must be considered. 1) In the case that distributed CBR refresh are operated between read/write cycles Self Refresh cycles can be executed without special rule if 2,048 cycles of distributed CBR refresh are executed within tREF max. 2) In the case that burst CBR refresh or distributed/burst RAS only refresh are operated between read/write cycles 2,048 times of burst CBR refresh or 2,048 times of burst RAS only refresh must be executed before and after Self Refresh cycles. Read/Write operation RAS VIH VIL Self Refresh operation tRASS tNS < 2 ms 2,048 burst refresh cycle Read/Write operation tSN < 2 ms * 2,048 burst refresh cycle * * Read/Write operation can be performed non refresh time within tNS or tSN 28 MB81V17805B-50/-60/-50L/-60L PACKAGE DIMENSIONS : Resin protrusion. (Each side: 0.15 (.006) MAX) 28-pin plastic SOJ (LCC-28P-M07) +0.35 3.40 -0.20 +.014 .134 -.008 28 * 18.420.13(.725.005) 2.75(.108)NOM 0.64(.025)MIN 15 R0.81(.032)TYP 10.16 (.400) 10.970.13 (.432.005) NOM 9.400.51 (.370.020) INDEX LEAD No 1 +0.05 1.270.13 (.050.005) 0.20 -0.02 +.002 .008 -.001 14 16.51(.650)REF Details of "A" part 2.50(.098)NOM 0.10(.004) 0.81(.032)MAX "A" 0.430.10(.017.004) C 1995 FUJITSU LIMITED C28058S-2C-1 Dimensions in mm (inches) 29 MB81V17805B-50/-60/-50L/-60L (Continued) 28-pin plastic TSOP (II) (FPT-28P-M14) : Resin protrusion. (Each side: 0.15 (.006) MAX) 15 28 Details of "A" part 0.15(.006) 0.25(.010) 0.15(.006) MAX 0.50(.020) MAX INDEX LEAD No. 1 "A" 14 * 18.410.10 (.725.004) 0.400.10 (.016.004) 1.27(.050) TYP. 0.21(.008) 30 1994 FUJITSU LIMITED F28040S-2C-1 M 1.150.05(.045.002) 0.10(.004) 16.51(.650) REF. C 11.760.20 (.463.008) 0.500.10 (.020.004) 10.160.10 (.400.004) 0.1250.05 (.005.002) 10.760.20 (.424.008) 0.05(.002)MIN (STAND OFF) Dinensions in mm (inches) MB81V17805B-50/-60/-50L/-60L FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. http://www.fmap.com.sg/ F9709 FUJITSU LIMITED Printed in Japan 31