
   
SCES219N − APRIL 1999 − REVISED JUNE 2005
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DAvailable in the Texas Instruments
NanoStarand NanoFreePackages
DSupports 5-V VCC Operation
DInputs Accept Voltages to 5.5 V
DMax tpd of 3.6 ns at 3.3 V
DLow Power Consumption, 10-µA Max ICC
D±24-mA Output Drive at 3.3 V
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
3
2
4
51
AV
CC
Y
B
GND
DBV PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
51
AV
CC
Y
B
GND
3
2
4
51
AV
CC
Y
B
GND A
GND
VCC
Y
B
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
1
4
2
3
5
description/ordering information
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G32 performs the Boolean function Y+A)BorY+AB in positive logic.
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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   
SCES219N − APRIL 1999 − REVISED JUNE 2005
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA SN74LVC1G32YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
Reel of 3000
SN74LVC1G32YZAR
_ _ _CG_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Reel of 3000 SN74LVC1G32YEPR _ _ _CG_
−40°C to 85°CNanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free) SN74LVC1G32YZPR
SOT (SOT-23) − DBV
Reel of 3000 SN74LVC1G32DBVR
C32_
SOT (SOT-23) − DBV Reel of 250 SN74LVC1G32DBVT C32_
SOT (SC-70) − DCK
Reel of 3000 SN74LVC1G32DCKR
SOT (SC-70) − DCK
Reel of 250 SN74LVC1G32DCKT CG_
SOT (SOT-553) − DRL Reel of 4000 SN74LVC1G32DRLR
CG_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
A B
OUTPUT
Y
H X H
XHH
L L L
logic diagram (positive logic)
1
24
A
BY
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 252°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRL package 142°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEA/YZA package 154°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package 132°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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   
SCES219N − APRIL 1999 − REVISED JUNE 2005
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recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC
Supply voltage
Operating 1.65 5.5
V
VCC Supply voltage Data retention only 1.5 V
VCC = 1.65 V to 1.95 V 0.65 ×VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V 1.7
V
VIH High-level input voltage VCC = 3 V to 3.6 V 2V
VCC = 4.5 V to 5.5 V 0.7 ×VCC
VCC = 1.65 V to 1.95 V 0.35 ×VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V 0.7
V
VIL Low-level input voltage VCC = 3 V to 3.6 V 0.8 V
VCC = 4.5 V to 5.5 V 0.3 ×VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V −4
VCC = 2.3 V −8
I
OH
High-level output current
VCC = 3 V
−16 mA
IOH
High-level output current
VCC = 3 V −24
mA
VCC = 4.5 V −32
VCC = 1.65 V 4
VCC = 2.3 V 8
I
OL
Low-level output current
VCC = 3 V
16 mA
IOL
Low-level output current
VCC = 3 V 24
mA
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
t/vInput transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
t/v
Input transition rise or fall rate
VCC = 5 V ±0.5 V 5
ns/V
TAOperating free-air temperature −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IOH = −100 mA1.65 V to 5.5 V VCC0.1
IOH = −4 mA 1.65 V 1.2
IOH = −8 mA 2.3 V 1.9
V
VOH IOH = −16 mA
3 V
2.4 V
IOH = −24 mA 3 V 2.3
IOH = −32 mA 4.5 V 3.8
IOL = 100 mA1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
V
VOL IOL = 16 mA
3 V
0.4 V
IOL = 24 mA 3 V 0.55
IOL = 32 mA 4.5 V 0.55
IIA or B inputs VI = 5.5 V or GND 0 to 5.5 V ±5mA
Ioff VI or VO = 5.5 V 0±10 mA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 mA
ICC One input at VCC − 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 mA
CiVI = VCC or GND 3.3 V 4 pF
All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
tpd A or B Y1.9 7.2 0.8 4.4 0.9 3.6 0.8 3.4 ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF or
50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
tpd A or B Y2.8 8 1.2 5.5 1.1 4.5 1 4 ns
operating characteristics, TA = 25°C
PARAMETER
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
UNIT
PARAMETER
TYP TYP TYP TYP
UNIT
Cpd Power dissipation capacitance f = 10 MHz 20 20 21 22 pF

   
SCES219N − APRIL 1999 − REVISED JUNE 2005
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V
VOH − V
0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 M
1 M
1 M
1 M
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms

   
SCES219N − APRIL 1999 − REVISED JUNE 2005
7
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V
VOH − V
0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 k
500
500
500
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
Figure 2. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LVC1G32DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DCKT ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DRLR ACTIVE SOP DRL 5 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32DRLRG4 ACTIVE SOP DRL 5 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G32YEAR ACTIVE WCSP YEA 5 3000 TBD SNPB Level-1-260C-UNLIM
SN74LVC1G32YEPR ACTIVE WCSP YEP 5 3000 TBD SNPB Level-1-260C-UNLIM
SN74LVC1G32YZAR ACTIVE WCSP YZA 5 3000 Pb-Free
(RoHS) SNAGCU Level-1-260C-UNLIM
SN74LVC1G32YZPR ACTIVE WCSP YZP 5 3000 Pb-Free
(RoHS) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
PACKAGE OPTION ADDENDUM
www.ti.com 10-Oct-2005
Addendum-Page 1
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Oct-2005
Addendum-Page 2
MECHANICAL DATA
MPDS025C – FEBRUAR Y 1997 – REVISED FEBRUAR Y 2002
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE
0,10
M
0,10
0,65
0°–8°0,46
0,26
0,13 NOM
4093553-2/D 01/02
0,15
0,30
1,40
1,10 2,40
1,80
45
2,15
1,85
1 3
1,10
0,80 0,10
0,00
Seating Plane
0,15
Gage Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
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