1. Product profile
1.1 General description
400 W LDMOS power transistor for base station applications at frequencies from
716MHz to 960MHz.
[1] 3GPP test model 1; 64 DPCH; PAR = 8.4 dB at 0.01 % probability on CCDF; 10 MHz carrier spacing.
1.2 Features and benefits
Excellent ruggedness
Device can operate with the supply current delivered through the video leads
High efficiency
Low thermal resistance providing excellent thermal stability
Designed for broadband operation
Lower output capacitance for improved performa nce in Doherty applications
Decoupling leads to enable improved video bandwidth (45 MHz typical)
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use
Integrated ESD protection
Design optimized for gull-wing
Compliant to Directive 2002/95/EC, rega rd in g Restr i ctio n of Haza rdou s Sub stances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 716 MHz to
960 MHz frequency range
BLF8G09LS-400PW;
BLF8G09LS-400PGW
Power LDMOS transistor
Rev. 4 — 28 July 2015 Product data sheet
Table 1. Typical performance
Typical RF performance at Tcase = 25
C in a common source class-AB production test circuit, tested
on straight lead device.
Test sign al f IDq VDS PL(AV) GpDACPR5M
(MHz) (mA) (V) (W) (dB) (%) (dBc)
2-carrier W-CDMA 716 to 728 3400 28 95 20.6 30 35 [1]
BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 July 2015 2 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
2. Pinning information
[1] Connected to flange.
[2] Device can operate with the supply current delivered through the combined decoupling leads.
3. Ordering information
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLF8G09LS-400PW (SOT 1242B)
1drain1
2drain2
3gate1
4gate2
5source [1]
6 decoupling1 [2]
7 decoupling2 [2]
8n.c.
9n.c.
BLF8G09LS-400PGW (SOT1242C)
1drain1
2drain2
3gate1
4gate2
5source [1]
6 decoupling1 [2]
7 decoupling2 [2]
8n.c.
9n.c.
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Table 3. Ordering informati on
Type number Package
Name Description Version
BLF8G09LS-400PW - earless flanged ceramic package; 8 leads SOT1242B
BLF8G09LS-400PGW - earless fla nged ceramic package; 8 leads SOT1242C
BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 July 2015 3 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
4. Limiting values
[1] Continuous use at maximum temperature will affect the reliability, for details refer to the on-line MTF
calculator.
5. Thermal characteristics
6. Characteristics
Table 4. Limiting va lues
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 65 V
VGS gate-source voltage 0.5 +13 V
Tstg storage temperature 65 +150 C
Tjjunction temperature [1] - 225 C
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-c) thermal resist ance from junction to case Tcase =80C; PL= 95 W 0.26 K/W
Table 6. DC charac teristics
Tj = 25
C; per section unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source brea kdown voltage VGS =0V; I
D=3 mA 65--V
VGS(th) gate-source threshold voltage VDS =10 V; I
D= 300 mA 1.5 1.8 2.3 V
VGSq gate-source quiescent voltage VDS =28 V; I
D= 1700 mA 1.7 2 2.5 V
IDSS drain leakage current VGS =0V; V
DS =28V --2.8A
IDSX drain cut-off current VGS =V
GS(th) +3.75 V;
VDS =10V 55 - A
IGSS gate leakage current VGS =11 V; V
DS =0V --280nA
gfs forward transconductance VDS =10V; I
D=15A - 26 - S
RDS(on) drain-source on-state resistance VGS =V
GS(th) + 3.75 V ;
ID= 12.25 A -0.06-
Table 7. RF characteristics
Test signal: 2-carrier W-CDMA; PAR = 8.4 dB at 0.01 % probability on the CCDF; 3GPP test
model 1; 1-64 DPCH; f1= 718.5 MHz; f2= 723.5 MHz; f3= 720.5 MHz; f4= 725.5 MHz;
RF performance at VDS =28V; I
Dq = 3400 mA; Tcase =25
C; unless otherwise specified; in a
class-AB production test circuit, tested on straight lead device.
Symbol Parameter Conditions Min Typ Max Unit
Gppower gain PL(AV) = 95 W 18.8 20.6 - dB
RLin input return loss PL(AV) =95W - 19 11 dB
Ddrain efficiency PL(AV) =95W 26 30 - %
ACPR5M adjacent channel power ratio (5 MHz) PL(AV) =95W - 35 32 dBc
BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 July 2015 4 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
7. Test information
7.1 Ruggedness in class-AB operation
The BLF8G09LS-400 PW and BLF8G09LS-400PGW are capable of withstanding a load
mismatch corresponding to VSWR = 7 : 1 through all phases under the following
conditions: VDS =28V; I
Dq = 3400 mA; 2-carrier W-CDMA signal; PL=200W;
f = 716 MHz; 5 MHz carrier spacing; 46 % clipping.
7.2 Impedance information
[1] ZS and ZL defined in Figure 1.
7.3 VBW in class-AB operation
The BLF8G09LS-400 PW and BLF8G09LS-400PGW show 45 MHz (typical) video
bandwidth in class-AB test circuit in 722 MHz band at VDS = 28 V and IDq = 3400 mA.
Table 8. Typical impedance
Measured load-pull data for the top-half of the push-pull package; IDq =1800mA; V
DS =28V;
Tcase =25
C, water cooled.
f ZS[1] ZL[1]
(MHz) () ()
BLF8G09LS-400PW (straight lead)
720 1.26 j2.89 1.8 j1.94
757 1.44 j3.82 2 j1.6
769 1.55 j3.64 1.9 j1.75
805 1.7 j4.5 1.5 j1.3
BLF8G09LS-400PGW (gull-wing)
720 1.37 j3 1.7 j2.1
757 1.4 j3.6 1.6 j2.3
769 1.3 j3.9 1.7 j2.2
805 1.6 j4.3 1.48 j1.97
Fig 1. Definition of transis tor imp e da nc e
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BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 5 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
7.4 Test circuit
Printed-Circuit Board (PCB): Rogers RO4350B; r = 3.66; thickness = 0.508 mm;
thickness copper plating = 35 m.
See Table 9 for a list of components.
Fig 2. Component layout
Table 9. List of compone nts
For test circuit see Figure 2.
Component Description Value Remarks
C1, C2, C3, C8, C9 multilayer ceramic chip capacitor 100 pF ATC 100A
C4, C5 multilayer ceramic chip capacitor 9.1 pF ATC 100A
C6, C7 multilayer ceramic chip capacitor 10 pF ATC 100A
C10, C11, C13, C17 multilayer ceramic chip capacitor 1 F, 50 V Murata
C12, C16 multilayer ceramic chip capacitor 100 nF, 50 V Murata
C14, C15, C18, C19 multilayer ceramic chip capacitor 10 F, 50 V Murata
C20, C21 multilayer ceramic chip capacitor 5.1 pF ATC 100A
C22 multilayer ceramic chip capacitor 82 pF AT C 100B
C23, C24 electrolytic capacitor 470 F, 63 V
C25, C26 multilayer ceramic chip capacitor 3 pF ATC 100A
R1 resistor 10
R2, R3, R4, R5 resistor 5.1
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BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 6 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
7.5 Graphical data
7.5.1 Pulsed CW
VDS = 28 V; IDq = 3400 mA; tp= 100 s; =10%.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
VDS = 28 V; IDq = 3400 mA; tp= 100 s; =10%.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 3. Power gain as a function of output power;
typical values Fig 4. Drain efficiency as a function of output power;
typical values
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BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 7 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
7.5.2 IS-95
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 5. Power gain as a function of output power;
typical values Fig 6. Drain efficiency as a function of output power;
typical values
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 7. Adjacent channe l powe r ratio (8 85 kHz) as a
function of output power; typical values Fig 8. Adjacent channel power ratio (1980 kHz) as a
function of output power; typical values
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BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 8 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
7.5.3 1-Carrier W-CDMA
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 9. Peak-to-ave r ag e rat io as a function of output
power; typical values Fig 10. Peak output power as a functi on of output;
typical values
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(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 11. Power gain as a function of output power;
typical values Fig 12. Drain efficiency as a function of output power;
typical values
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BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 9 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
7.5.4 2-Carrier W-CDMA
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 13. Pe ak -to -a verage ratio as a function of output
power; typical values Fig 14. Input return loss as a function of output
power; typical values
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VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 15. Power gain as a function of output power;
typical values Fig 16. Drain efficiency as a function of output power;
typical values
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BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 10 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 17. Input return loss as a function of output power; typical values
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
VDS = 28 V; IDq = 3400 mA.
(1) f = 716 MHz
(2) f = 722 MHz
(3) f = 728 MHz
Fig 18. Adjacent channel power ratio (5 MHz) as a
function of output power; typical values Fig 19. Ad jacen t channel power ratio (10 MHz) as a
function of output power; typical values
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BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 11 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
7.5.5 2-Tone VBW
VDS = 28 V; IDq = 3400 mA.
(1) IMD low
(2) IMD high
Fig 20. VBW capability in class-AB test circuit
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BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 12 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
8. Package outline
Fig 21. Package outline SOT1242B
BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 13 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
Fig 22. Package outline SOT1242C
BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 14 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
9. Handling information
10. Abbreviations
11. Revision history
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
Table 10. Abbreviations
Acronym Description
3GPP 3rd Generation Partnership Project
CCDF Complementary Cumulative Distribution Function
CW Continuous Wave
DPCH Dedicated Physical CHannel
ESD ElectroStatic Discharge
IS-95 Interim Standard 95
LDMOS Laterally Diffused Metal Oxide Semiconductor
MTF Median Time to Failure
PAR Peak-to-Average Ratio
VBW Video Bandwidth
VSWR Voltage Standing Wave Ra tio
W-CDMA Wideband Code Division Multiple Access
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BLF8G09LS-400PW_
8G09LS-400 PG W v.4 20150728 Product data sheet - BLF8G09LS-400PW_
8G09LS-400PGW v.3
Modifications: •Figure 21 on page 12: This figure has been updated
BLF8G09LS-400PW_
8G09LS-400 PG W v.3 20140324 Product data sheet - BLF8G09LS-400PW_
8G09LS-400PGW v.2
BLF8G09LS-400PW_
8G09LS-400 PG W v.2 20131220 Preliminary data sheet - BLF8G09LS-400PW_
8G09LS-400PGW v.1
BLF8G09LS-400PW_
8G09LS-400 PG W v.1 20130927 Objective data sheet - -
BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 15 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
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Product data sheet.
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Notwithstanding any damages that customer might incur for any reason
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Applications — Applications that are described herein for any of these
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Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
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NXP Semiconductors does not accept any liabil i ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
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testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
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applying the customer’s general terms and conditions with regard to the
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conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
BLF8G09LS-400PW_8G09LS-400PGW All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserv ed.
Product data sheet Rev. 4 — 28 July 2015 16 of 17
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
Export control — This document as well as the item(s) described herein
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Non-automotive qualified products — Unless this data sheet expressly
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the product is not suitable for automotive use. It i s neither qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or app lications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
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between the translated and English versions.
12.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BLF8G09LS-400P(G)W
Power LDMOS transistor
© NXP Semiconductors N.V. 2015. All right s reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 July 2015
Document identifier: BLF8G09LS-400PW_8G09LS-400PGW
Please be aware that important notices concerning this document and the product(s)
described herei n, have been included in section ‘Legal information’.
14. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 4
7.1 Ruggedness in class-AB operation . . . . . . . . . 4
7.2 Impedance information. . . . . . . . . . . . . . . . . . . 4
7.3 VBW in class-AB operation . . . . . . . . . . . . . . . 4
7.4 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.5 Graphical data . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.5.1 Pulsed CW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.5.2 IS-95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.5.3 1-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 8
7.5.4 2-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 9
7.5.5 2-Tone VBW . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
9 Handling information. . . . . . . . . . . . . . . . . . . . 14
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Contact information. . . . . . . . . . . . . . . . . . . . . 16
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17