1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020, SST39VF040 are 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. Features * Organized as 128K x8 / 256K x8 / 512K x8 * Single Voltage Read and Write Operations - 3.0-3.6V for SST39LF010/020/040 - 2.7-3.6V for SST39VF010/020/040 * Fast Erase and Byte-Program: - Sector-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: 2 seconds (typical) for SST39LF/VF010 4 seconds (typical) for SST39LF/VF020 8 seconds (typical) for SST39LF/VF040 * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 14 MHz) - Active Current: 5 mA (typical) - Standby Current: 1 A (typical) * Sector-Erase Capability - Uniform 4 KByte sectors * Fast Read Access Time: - 55 ns for SST39LF010/020/040 - 70 ns for SST39VF010/020/040 * Latched Address and Data * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) * All devices are RoHS compliant (c)2012 Silicon Storage Technology, Inc. www.microchip.com DS25023B 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Product Description The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020, SST39VF040 are 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF010/020/040 and SST39VF010/020/040 devices provide a maximum Byte-Program time of 20 sec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, they are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39LF010/020/040 and SST39VF010/020/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improves performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39LF010/020/040 and SST39VF010/020/040 devices are offered in 32-lead PLCC and 32-lead TSOP packages. See Figures 2 and 3 for pin assignments. (c)2012 Silicon Storage Technology, Inc. DS25023B 2 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Block Diagram X-Decoder Memory Address SuperFlash Memory Address Buffers & Latches Y-Decoder CE# OE# Control Logic I/O Buffers and Data Latches WE# DQ7 - DQ0 1150 B1.1 Figure 1: Functional Block Diagram (c)2012 Silicon Storage Technology, Inc. DS25023B 3 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet A17 A17 NC WE# WE# WE# VDD VDD VDD A18 NC 4 3 2 1 32 31 30 29 NC A16 A16 A16 A15 A15 A15 A12 SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 A12 A12 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 Pin Assignments SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 A7 A7 A7 5 A14 A14 A14 A6 A6 A6 6 28 A13 A13 A13 A5 A5 A5 7 27 A8 A8 A8 A4 A4 A4 8 26 A9 A9 A9 A3 A3 A3 9 25 A11 A11 A11 A2 A2 A2 10 24 OE# OE# OE# A1 A1 A1 11 23 A10 A10 A10 A0 A0 A0 12 22 CE# CE# CE# DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ7 DQ7 32-lead PLCC Top View DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 1150 32-plcc NH P4.4 Figure 2: Pin Assignments for 32-lead PLCC (c)2012 Silicon Storage Technology, Inc. DS25023B 4 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1150 32-tsop WH P1.1 Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) Table 1: Pin Description Symbol AMS1-A0 DQ7-DQ0 CE# OE# WE# VDD VSS NC Pin Name Address Inputs Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. Chip Enable To activate the device when CE# is low. Output Enable To gate the data output buffers. Write Enable To control the Write operations. Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF010/020/040 2.7-3.6V for SST39VF010/020/040 Ground No Connection Unconnected pins. T1.1 25023 1. AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 (c)2012 Silicon Storage Technology, Inc. DS25023B 5 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39LF010/020/040 and SST39VF010/020/040 devices are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4). Byte-Program Operation The SST39LF010/020/040 and SST39VF010/020/040 are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Chip-Erase Operation The SST39LF010/020/040 and SST39VF010/020/040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the `1's state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the (c)2012 Silicon Storage Technology, Inc. DS25023B 6 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the Chip-Erase operation will be ignored. Write Operation Status Detection The SST39LF010/020/040 and SST39VF010/020/040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-ofWrite detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. (c)2012 Silicon Storage Technology, Inc. DS25023B 7 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Data# Polling (DQ7) When the SST39LF010/020/040 and SST39VF010/020/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a "0". Once the internal Erase operation is completed, DQ7 will produce a "1". The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. Data Protection The SST39LF010/020/040 and SST39VF010/020/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. (c)2012 Silicon Storage Technology, Inc. DS25023B 8 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Software Data Protection (SDP) The SST39LF010/020/040 and SST39VF010/020/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. Product Identification The Product Identification mode identifies the devices as the SST39LF/VF010, SST39LF/VF020, and SST39LF/VF040 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 17 for the Software ID entry command sequence flowchart. Table 2: Product Identification Address Data 0000H BFH SST39LF/VF010 0001H D5H SST39LF/VF020 0001H D6H SST39LF/VF040 0001H D7H Manufacturer's ID Device ID T2.1 25023 Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform, and Figure 17 for a flowchart. (c)2012 Silicon Storage Technology, Inc. DS25023B 9 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Operations Table 3: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN VIL X1 Sector address, XXH for Chip-Erase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit VIH Product Identification Software Mode See Table 4 T3.4 25023 1. X can be VIL or VIH, but no other value. Table 4: Software Command Sequence Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle Addr1 Addr1 Data 3rd Bus Write Cycle Data Addr1 4th Bus Write Cycle Data Addr1 BA2 Data 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX3 30H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H 55H 5555H F0H Software ID Exit6 Software ID Exit6 XXH Data F0H 5555H AAH 2AAAH T4.2 25023 1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 2. BA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer's ID = BFH, is read with A0 = 0, SST39LF/VF010 Device ID = D5H, is read with A0 = 1, SST39LF/VF020 Device ID = D6H, is read with A0 = 1, SST39LF/VF040 Device ID = D7H, is read with A0 = 1. 6. Both Software ID Exit operations are equivalent (c)2012 Silicon Storage Technology, Inc. DS25023B 10 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. Table 5: Operating Range SST39LF010/020/040 Range Commercial Ambient Temp VDD 0C to +70C 3.0-3.6V T5.1 25023 Table 6: Operating Range SST39VF010/020/040 Range Commercial Industrial Ambient Temp VDD 0C to +70C 2.7-3.6V -40C to +85C 2.7-3.6V T6.1 25023 Table 7: AC Conditions of Test1 Input Rise/Fall Time Output Load CL = 30 pF for SST39LF010/020/040 5ns CL = 100 pF for SST39VF010/020/040 T7.1 25023 1. See Figures 13 and 14 (c)2012 Silicon Storage Technology, Inc. DS25023B 11 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Table 8: DC Operating Characteristics -VDD = 3.0-3.6V for SST39LF010/020/040 and 2.73.6V for SST39VF010/020/0401 Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min VDD=VDD Max Read2 20 mA CE#=VIL, OE#=WE#=VIH, all I/Os open Program and Erase3 30 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 15 A CE#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max VOL Output Low Voltage V IOL=100 A, VDD=VDD Min VOH Output High Voltage V IOH=-100 A, VDD=VDD Min 0.2 VDD-0.2 T8.7 25023 1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25C (room temperature), and VDD = 3V for VF devices. Not 100% tested. 2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information. 3. 30 mA max for Erase operations in the industrial temperature range. Table 9: Recommended System Power-up Timings Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 s Power-up to Program/Erase Operation 100 s T9.1 25023 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 10: Capacitance (Ta = 25C, f=1 Mhz, other pins open) Parameter Description CI/O1 CIN1 Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T10.0 25023 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 11: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method NEND1,2 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T11.3 25023 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. (c)2012 Silicon Storage Technology, Inc. DS25023B 12 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet AC Characteristics Table 12: Read Cycle Timing Parameters - VDD = 3.0-3.6V for SST39LF010/020/040 and 2.7-3.6V for SST39VF010/020/040 Symbol Parameter TRC Read Cycle Time SST39LF010-55 SST39LF020-55 SST39LF040-55 SST39VF010-70 SST39VF020-70 SST39VF040-70 Min Min Max 55 Max Units 70 ns TCE Chip Enable Access Time 55 70 ns TAA Address Access Time 55 70 ns TOE Output Enable Access Time 35 ns TCLZ1 CE# Low to Active Output 0 1 OE# Low to Active Output 0 TOLZ 30 TCHZ1 CE# High to High-Z Output TOHZ1 OE# High to High-Z Output TOH1 Output Hold from Address Change 0 ns 0 ns 15 25 15 ns 25 0 ns 0 ns T12.2 25023 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 13: Program/Erase Cycle Timing Parameters Symbol Parameter Min TBP Byte-Program Time TAS Address Setup Time 0 Max Units 20 s ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 40 ns Data Hold Time 0 TDH 1 ns TIDA1 Software ID Access and Exit Time TSE Sector-Erase 25 ms TSCE Chip-Erase 100 ms 150 ns T13.1 25023 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2012 Silicon Storage Technology, Inc. DS25023B 13 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TRC TAA ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCLZ DQ7-0 TOH HIGH-Z Note: TCHZ DATA VALID DATA VALID HIGH-Z 1150 F03.0 AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 Figure 4: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS AMS-0 2AAA 5555 ADDR TAH TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ7-0 Note: AA 55 A0 DATA SW0 SW1 SW2 BYTE (ADDR/DATA) 1150 F04.0 AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 Figure 5: WE# Controlled Program Cycle Timing Diagram (c)2012 Silicon Storage Technology, Inc. DS25023B 14 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS AMS-0 2AAA 5555 ADDR TAH TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ7-0 Note: AA 55 A0 DATA SW0 SW1 SW2 BYTE (ADDR/DATA) 1150 F05.0 AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 Figure 6: CE# Controlled Program Cycle Timing Diagram ADDRESS AMS-0 TCE CE# TOEH TOES OE# TOE WE# D DQ7 Note: D# D# D 1150 F06.0 AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 Figure 7: Data# Polling Timing Diagram (c)2012 Silicon Storage Technology, Inc. DS25023B 15 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet ADDRESS AMS-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 TWO READ CYCLES Note: WITH SAME OUTPUTS AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 1150 F07.0 Figure 8: Toggle Bit Timing Diagram TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 30 SW0 SW1 SW2 SW3 SW4 SW5 1150 F08.0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 Figure 9: WE# Controlled Sector-Erase Timing Diagram (c)2012 Silicon Storage Technology, Inc. DS25023B 16 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 10 SW0 SW1 SW2 SW3 SW4 SW5 1150 F17.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) AMS = Most significant address AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 Figure 10:WE# Controlled Chip-Erase Timing Diagram Three-byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ7-0 TAA AA 55 90 SW0 SW1 SW2 BF Device ID 1150 F09.2 Note: Device ID = D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040. Figure 11:Software ID Entry and Read (c)2012 Silicon Storage Technology, Inc. DS25023B 17 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 5555 2AAA AA DQ7-0 5555 55 F0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 1150 F10.0 Figure 12:Software ID Exit and Reset VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1150 F12.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test Figure 13:AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1150 F11.1 Figure 14:A Test Load Example (c)2012 Silicon Storage Technology, Inc. DS25023B 18 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1150 F13.1 Figure 15:Byte-Program Algorithm (c)2012 Silicon Storage Technology, Inc. DS25023B 19 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Internal Timer Toggle Bit Data# Polling Byte-Program/ Erase Initiated Byte-Program/ Erase Initiated Byte-Program/ Erase Initiated Read byte Read DQ7 Wait TBP, TSCE, or TSE Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1150 F14.0 Figure 16:Wait Options (c)2012 Silicon Storage Technology, Inc. DS25023B 20 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Software ID Entry Command Sequence Software ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 1150 F15.2 Figure 17:Software ID Command Flowcharts (c)2012 Silicon Storage Technology, Inc. DS25023B 21 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: 30H Address: SAX Wait TSCE Wait TSE Chip erased to FFH Sector erased to FFH 1150 F16.1 Figure 18:Erase Command Sequence (c)2012 Silicon Storage Technology, Inc. DS25023B 22 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Product Ordering Information SST 39 VF 010 - 55 - 4C - NHE XX XX XXX - XX - XX - XXX Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads Package Type N = PLCC W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns 70 = 70 ns Device Density 040 = 4 Mbit 020 = 2 Mbit 010 = 1 Mbit Voltage L = 3.0-3.6V V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are RoHS compliant. (c)2012 Silicon Storage Technology, Inc. DS25023B 23 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Valid combinations for SST39LF010 SST39LF010-55-4C-NHE SST39LF010-55-4C-WHE Valid combinations for SST39VF010 SST39VF010-70-4C-NHE SST39VF010-70-4C-WHE SST39VF010-70-4I-NHE SST39VF010-70-4I-WHE Valid combinations for SST39LF020 SST39LF020-55-4C-NHE SST39LF020-55-4C-WHE Valid combinations for SST39VF020 SST39VF020-70-4C-NHE SST39VF020-70-4C-WHE SST39VF020-70-4I-NHE SST39VF020-70-4I-WHE Valid combinations for SST39LF040 SST39LF040-55-4C-NHE SST39LF040-55-4C-WHE Valid combinations for SST39VF040 SST39VF040-70-4C-NHE SST39VF040-70-4C-WHE SST39VF040-70-4I-NHE SST39VF040-70-4I-WHE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2012 Silicon Storage Technology, Inc. DS25023B 24 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Packaging Diagrams TOP VIEW Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447 2 1 32 SIDE VIEW .112 .106 .020 R. .029 x 30 MAX. .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32-plcc-NH-3 4. Coplanarity: 4 mils. Figure 19:32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH (c)2012 Silicon Storage Technology, Inc. DS25023B 25 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 32-tsop-WH-7 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. Figure 20:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH (c)2012 Silicon Storage Technology, Inc. DS25023B 26 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Table 14: Revision History Number Description Date 01 * 2000 Data Book Feb 2000 02 * Changed speed from 45 ns to 55 ns for the SST39LF020 and SST39LF040 Aug 2000 03 * 2002 Data Book: Reintroduced the 45 ns parts for the SST39LF020 and SST39LF040 Feb 2002 04 * * Added the B3K package for the 2 Mbit devices Added footnote in Table 8 to indicate IDD Write is 30 mA max for Erase operations in the Industrial temperature range. Oct 2002 05 * Changes to Table 8 on page 12 Mar 2003 - Added footnote for MPF power usage and Typical conditions - Clarified the Test Conditions for Power Supply Current and Read parameters - Clarified IDD Write to be Program and Erase - Corrected IDD Program and Erase from 20 mA to 30 mA * Part number changes - see page 23 for additional information 06 * Added new "MM" Micro-Package MPNs for 1M and 2M LF parts- see page 23 Oct 2003 07 * * * 2004 Data Book Added non-Pb MPNs and removed footnote (See page 23) Updated B3K and MM package diagrams Nov 2003 08 * * * Added RoHS Compliant statement. Added 4 MBit to Figure 4. Revised Absolute Max Stress Ratings for Surface Mount Solder Reflow Temperature Removed SST39VFxxx-90 Timing Parameters from Figure 12. Added Footnote and removed Read Access Speed 90 = 90 to Product Ordering Information. Removed 90 part numbers Valid Combinations lists Dec 2005 * * * 09 * Edited page Valid Combinations on page 21. Changed 39LF040-70-4CB3KE to 39LF040-45-4C-B3KE Jan 2006 10 * Removed leaded parts Nov 2008 11 * Added package YME Feb 2009 12 * Revised "Product Ordering Information" on page 23 Apr 2009 13 * Changed endurance from 10,000 to 100,000 in Product Description, page 1 Sep 2009 14 * EOL of SST39LF010-45-4C-YME. Replacement part is SST39LF010-454C-MME in this document. Removed all references to the YME package. Jan 2010 EOL of SST39LF512 and SST39VF512 parts. Replacement parts are SST39LF010 and SST39VF010. Applied new document format. Released document under letter revision system. Updated spec number S71150 to DS25023. Aug 2011 * A * * * * (c)2012 Silicon Storage Technology, Inc. DS25023B 27 06/13 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF010 / SST39LF020 / SST39LF040 SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Table 14: Revision History Number B Description * * * * EOL of 45 ns parts. Removed all 45 ns parts; updated Table 12 on page 13 to reflect this change. EOL of B3KE. Removed the B3KE package. EOL of MME. Removed the MME package. Added 55ns for SST39LF010 and SST39VF010 parts Date June 2013 ISBN:978-1-62077-292-8 (c) 2013 Silicon Storage Technology, Inc-a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners. Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging. Memory sizes denote raw storage capacity; actual usable capacity may be less. SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see www.microchip.com. Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com (c)2012 Silicon Storage Technology, Inc. DS25023B 28 06/13