SST39VF040-70-4C-NHE - MICROCHIP TECHNOLOGY

Data Sheet

www.microchip.com

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Features

• Organized as 128K x8 / 256K x8 / 512K x8

• Single Voltage Read and Write Operations

– 3.0-3.6V for SST39LF010/020/040

– 2.7-3.6V for SST39VF010/020/040

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Activ e Current: 5 mA (typical)

– Standby Current: 1 µA (typical)

• Sec tor-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 55 ns for SST39LF010/020/040

– 70 ns for SST39VF010/020/040

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

2 seconds (typical) for SST39LF/VF010

4 seconds (typical) for SST39LF/VF020

8 seconds (typical) for SST39LF/VF040

• Automatic Write Timing

– Internal VPP Gene ration

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

• All devices are RoHS compli ant

The SST39LF010, SST39LF020, SST39LF04 0 and SST39VF010, SST39VF020,

SST39VF040 are 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash

(MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash

technology. The split-gate cell design and thick-oxid e tunneling injector attain bet-

ter reliability and manufacturability compared with alternate approaches. The

SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power

supply. The SST39VF010/020/040 devices write with a 2.7-3.6V power supply.

The devices conform to JEDEC standard pinouts for x8 memories.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Product Description

The SST39LF010, SST39LF020, SST39LF040 and SST39VF010, SST39VF020, SST39VF040 are

128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprie-

tary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tun-

neling injector attain better reliability and manufacturability compared with alter nate approaches. The

SST39LF010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The

SST39VF010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC

standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39LF010/020/040 and SST39VF010/020/040

devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data#

Polling to indicate the completion of Program operation. To protect against inadvertent write, they have

on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a

wide spectrum of applications , the y ar e offered with a guaranteed typi cal endura nce of 100,000 cycles .

Data retention is rated at greater than 100 years.

The SST39LF010/020/040 and SST39VF010/020/040 devices are suited for applications that require

convenient and economical updating of program, configuration, or data memor y. For all system appli-

cations, they significantly improves performance and reliability, while lowering power consumption.

They inherently use less energy during Erase and Program than alternative flash technologies. The

total energy consumed is a function of the applied voltage, current, and time of application. Since for

any given voltage range, the SuperFlash technology uses less current to program and has a shorter

erase time, the total energy consumed during any Erase or Program operation is less than alternative

flash technologies. These de vices also impro v e fle xibility while lo wering the cost for program, data, and

configuration storage ap p licat ion s.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of

Erase/Program cycles that have occurred. Therefore the system software or hardware does not have

to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-

gram times increase with accumulated Erase/Pro gram cycles.

To meet surface mount requirements, the SST39LF010/020/040 and SST39VF010/020/040 devices

are offered in 32-lead PLCC and 32-lead TSOP packages. See Figures 2 and 3 for pin assignments.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Block Diagram

Figure 1: Functional Block Diagram

Y-Decoder

I/O Buffers and Data Latches

1150 B1.1

Address Buffers & Latches

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Pin Assignments

Figure 2: Pin Assignments for 32-lead PLCC

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

A16

VDD

WE#

A12

A15

A16

VDD

WE#

A17

A12

A15

A16

A18

VDD

WE#

A17

32-lead PLCC

Top View

1150 32-plcc NH P4.4

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)

Table 1: Pin Description

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will

select the sector. During Block-Erase AMS-A16 address lines will select the b lock.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is inter nally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate th e da ta output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF010/020/040

2.7-3.6V for SST39VF010/020/040

VSS Ground

NC No Connection Unconnected pins. T1.1 25023

A11

A13

A14

WE#

VDD

A16

A15

A12

A11

A13

A14

A17

WE#

VDD

A16

A15

A12

A11

A13

A14

A17

WE#

VDD

A18

A16

A15

A12

SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

1150 32-tsop WH P1.1

Standard Pinout

Top Vie w

Die Up

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Device Operation

Commands are used to initiate the memor y operation functions of the device. Commands are written

to the de vice using standard micro processor write sequences. A command is written b y asserting WE#

low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever

occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39LF010/020/040 and SST39VF010/020/040 devices are controlled by

CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for

device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE#

is the output control and is used to gate data from the output pins. The data bu s is in high impedance

state when either CE# or OE# is high. Ref er to the Read cycle timing diagram f or further details (Figure

4).

Byte-Program Operation

The SST39LF010/020/040 and SST39VF010/020/040 are programmed on a byte-by-byte basis.

Before programming, the sector where the byte exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte load sequence for Software Data Protec-

tion. The second step is to load byte address and byte data. During the Byte-Program operation, the

addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is

latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal

Program operation which is initiated af ter the r ising edge of the four th WE# or CE#, which ever occurs

first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for

WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowchar ts. During the

Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program

operation, the host is free to perfor m additional tasks. Any commands written during the internal Pro-

gram operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The

sector architecture is based on unifor m sector size of 4 KByte. The Sector-Erase operation is initiated

by executing a six-byte command sequence with Sector-Erase command (30H) and sector address

(SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse,

while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data#

Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the

Sector-Erase operation will be ignored.

Chip-Erase Operation

The SST39LF010/020/040 and SST39VF010/020/040 devices provide a Chip-Erase operation, which

allows the user to erase the entire memory array to the ‘1’s state . This is useful when the entire device

must be quickly erased.

The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command

sequence with Chip-Er ase command (10H) wit h address 5555H in t he last b yte sequence . The int ernal

Erase oper ation begins with the rising edge of the sixt h WE# or CE#, whiche v e r occurs first. During the

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the com-

mand sequence, Figure 10 for timing diagram, and Figure 18 for the flowchar t. Any commands written

during the Chip-Erase operation will be ignored.

Write Operation Status Detection

The SST39LF010/020/040 and SST39VF010/020/040 devices provide two software means to detect

the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time.

The softw are det ection includes tw o st atus bits : Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of -

Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or

Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Data# Polling (DQ7)

When the SST39LF010/ 020/ 040 an d SST39VF01 0/020/ 040 ar e in the internal Progr am ope r atio n, any

attempt to read DQ7 will produce the complement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately

f ollowing completion of an internal Write oper ation, the remaining data outputs may still be in v alid: v alid

data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs.

During internal Erase operation, any attempt to read DQ7 will produce a “0”. Once the internal Erase

operatio n is comple ted, DQ7 will produce a “1”. The Data# Polling is v alid after the rising edge of f ourth

WE# (or CE#) pulse for Program operation. For Sector - or Chip-Erase, the Data# Polling is valid after

the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure

16 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce

alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation

is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is

valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-

Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle

Bit timing diagram an d Figure 16 for a flowchart.

Data Protection

The SST39LF010/020/040 and SST39VF010/020/ 040 provide both hardware and software features to

protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down .

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Software Data Protection (SDP)

The SST39LF010/020/040 and SST39VF010/020/040 provide the JEDEC approved Software Data

Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation

requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to ini-

tiate the Program operation, providing optimal protection from inadver tent Write operations, e.g., dur-

ing the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load

sequence. These devices are shipped with the Software Data Protection permanently enabled. See

Table 4 for the specific softw a re command codes . During SDP comma nd sequence, inv alid commands

will abort the device to read mode, within TRC.

Product Identification

The Product Identification mode identifies the devices as the SST39LF/VF010, SST39LF/VF020, and

SST39LF/VF040 and manufacturer as SST. This mode may be accessed by software operations.

Users may use the Software Product Identification op eration to identify the p ar t (i.e., using the device

ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software opera-

tion, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 17 for the Software ID

entry command sequence flowchart.

Product Identification Mode Exit/Reset

In order to retu rn to the standard Read mode, t he Softwa re Product Identi fication mode m ust be e xited.

Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to

the Read operation. Please note that the Software ID Exit command is ignored during an internal Pro-

gram or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform,

and Figure 17 for a flowchart.

Table 2: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39LF/VF010 0001H D5H

SST39LF/VF020 0001H D6H

SST39LF/VF040 0001H D7H

T2.1 25023

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Operations

Table 3: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.4 25023

Table 4: Software Command Sequence

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cyc le 6th Bus

Write Cycle

Addr1

1. Address format A14-A0 (Hex),

Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.

AMS = Most significant address

AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2

2. BA = Program Byte address

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX3

3. SAX for Sector-Erase; uses AMS-A12 address lines

30H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID

Entry4,5

4. The device does not remain in Software Product ID mode if powered down.

5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

SST39LF/VF010 Device ID = D5H, is read with A0 = 1,

SST39LF/VF020 Device ID = D6H, is read with A0 = 1,

SST39LF/VF040 Device ID = D7H, is read with A0 = 1.

5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit6

6. Both Software ID Exit operations are equivalent

XXH F0H

Software ID Exit65555H AAH 2AAAH 55H 5555H F0H

T4.2 25023

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Rat ings” ma y cause permanent damage to the de vice . This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sectio ns of this data sheet is not implied. Exposu re to absolute maxim um stress rat ing con-

ditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temper ature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperatur e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest

information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

Table 5: Operating Range SST39LF010/020/040

Range Ambient Temp VDD

Commercial 0°C to +70°C 3.0-3.6V

T5.1 25023

Table 6: Operating Range SST39VF010/020/040

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

T6.1 25023

Table 7: AC Conditio ns of Test1

1. See Figures 13 and 14

Input Rise/Fall Time Output Load

5ns CL = 30 pF for SST39LF010/02 0/040

CL = 100 pF for SST39VF010/020/040

T7.1 25023

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Table 8: DC Operating Character istics -VDD = 3.0-3.6V for SST39LF010/020/040 and 2.7-

3.6V for SST39VF010/020/0401

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min

VDD=VDD Max

Read220 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase330 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 15 µA CE#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T8.7 25023

1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C

(room temperature), and VDD = 3V for VF devices. Not 100% tested.

2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.

3. 30 mA max for Erase operations in the industr ial temperature range.

Table 9: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T9.1 25023

Table 10: Capacitance (Ta = 25°C, f=1 Mhz, other pins open)

P arameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T10.0 25023

Table 11: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating

would result in a higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Sta ndard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T11.3 25023

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

AC Characteristics

Table 12: Read Cycle Timing Parameters - VDD = 3.0-3.6V for SST39LF010/020/040 and

2.7-3.6V for SST39VF010/020/040

Symbol Parameter

SST39LF010-55

SST39LF020-55

SST39LF040-55

SST39VF010-70

SST39VF020-70

SST39VF040-70

UnitsMin Max Min Max

TRC Read Cycle Time 55 70 ns

TCE Chip Enable Access Time 55 70 ns

TAA Address Access Time 55 70 ns

TOE Output Enable Access Time 30 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 15 25 ns

TOHZ1OE# High to High-Z Output 15 25 ns

TOH1Output Hold from Address Change 00ns

T12.2 25023

Table 13: Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Byte-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Wi dt h 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 40 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TSCE Chip-Erase 100 ms

T13.1 25023

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 4: Read Cycle Timing Diagram

Figure 5: WE# Controlled Program Cycle Timing Diagram

1150 F03.0

ADDRESS AMS-0

DQ7-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most significant address

MS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040

1150 F04.0

ADDRESS AMS-0

DQ7-0

TDH

TWPH TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

Note: AMS = Most significant address

MS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 6: CE# Controlled Program Cycle Timing Diagram

Figure 7: Data# Polling Timing Diagram

1150 F05.0

ADDRESS AMS-0

DQ7-0

TDH

TCPH TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

MS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040

1150 F06.0

ADDRESS AMS-0

DQ7DD# D# D

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Note: AMS = Most significant address

MS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 8: Toggle Bit Timing Diagram

Figure 9: WE# Controlled Sector-Erase Timing Diagram

1150 F07.0

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most significant address

MS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040

1150 F08.0

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 3055AA 80 AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minmum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

MS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 10: WE# Controlled Chip-Erase Timing Diagram

Figure 11: Software ID Entry and Read

1150 F17.0

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 1055AA 80 AA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minmum timings are met. (See Table 10)

AMS = Most significant address

MS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

1150 F09.2

Note: Device ID = D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.

ADDRESS A14-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

Three-byte Sequence for

Software ID Entry

TWP

TWPH TAA

Device ID

55AA 90

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 12: Software ID Exit and Reset

Figure 13: AC Input/Output Reference Waveforms

Figure 14: A Test Load Example

1150 F10.0

ADDRESS A

14-0

7-0

IDA

WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

1150 F12.1

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1 ” an d VILT (0.1 VDD) for a logic

“0”. Measurement re ference points for inputs and ou tp uts ar e VIT (0.5 VDD) and VOT (0.5 VDD). Input

rise an d fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1150 F11.1

T O TESTER

TO DUT

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 15: Byte-Program Algorithm

1150 F13.1

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 16: Wait Options

1150 F14.0

W ait TBP,

TSCE, or TSE

Byte-Program/

Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Byte-Program/

Erase

Initiated

Byte-Program/

Erase

Initiated

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 17: Software ID Command Flowchar ts

1150 F15.2

Load data: AAH

Address: 5555H

Software ID Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

W ait TIDA

Read Software ID

Load data: AAH

Address: 5555H

Software ID Exit &

Reset Command Sequence

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Load data: F0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 18: Erase Command Sequence

1150 F16.1

Load data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: AAH

Address: 5555H

W ait TSCE

Chip erased

to FFH

Load data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 30H

Address: SAX

Load data: AAH

Address: 5555H

W ait TSE

Sector erased

to FFH

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Product Ordering Information

SST39VF 010 -55-4C-NHE

XX XX XXX -XX-XX-XXX

Environmental Attribute

E1 = non-Pb

Package Modifier

H = 32 leads

Package Type

N = PLCC

W = TSOP (type 1, die up , 8mm x 14mm)

Temperature Range

C = Commercial = 0°C t o +70°C

I = Industrial = -40°C to +8 5°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

55 = 55 ns

70 = 70 ns

Device Density

040 = 4 Mbit

020 = 2 Mbit

010 = 1 Mbit

Voltage

L = 3.0-3.6V

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are RoHS compliant.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Valid combinations for SST39LF010

SST39LF010-55-4C-NHE SST39LF010-55-4C-WHE

Valid combinations for SST39VF010

SST39VF010-70-4C-NHE SST39VF010-70-4C-WHE

SST39VF010-70-4I-NHE SST39VF010-70-4I-WHE

Valid combinations for SST39LF020

SST39LF020-55-4C-NHE SST39LF020-55-4C-WHE

Valid combinations for SST39VF020

SST39VF020-70-4C-NHE SST39VF020-70-4C-WHE

SST39VF020-70-4I-NHE SST39VF020-70-4I-WHE

Valid combinations for SST39LF040

SST39LF040-55-4C-NHE SST39LF040-55-4C-WHE

Valid combinations for SST39VF040

SST39VF040-70-4C-NHE SST39VF040-70-4C-WHE

SST39VF040-70-4I-NHE SST39VF040-70-4I-WHE

Note:Valid combinations are thos e products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of v alid combinations and to determine av ailability of new combi-

nations.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Packaging Diagrams

Figure 19: 32-lead Plastic Lead Chip Carrier (PLCC)

SST Package Code: NH

.040

.030

.021

.013 .530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

T OP VIEW SIDE VIEW BO TT OM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30°

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 20: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm

SST Package Code: WH

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0°- 5°

DETAIL

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Table 14: Revision History

Number Description Date

01 •2000 Data Book Feb 2000

02 •Changed speed from 45 ns to 55 ns for the SST39LF020 and

SST39LF040 Aug 2000

03 •2002 Data Book: Reintroduced the 45 ns parts for the SST39LF020 and

SST39LF040 Feb 2002

04 •Added the B3K package for the 2 Mbit devices

•Added footnote in Table 8 to indicate IDD Write is 30 mA max for Erase

operations in the Industrial temperature range.

Oct 2002

05 •Changes to Table 8 on page 12

– Added footnote for MPF power usage and Typical conditions

– Clarifi ed the Test Conditions for Power Supply Current and Read parameters

– Clarified IDD Write to be Program and Erase

– Corrected IDD Program and Erase from 20 mA to 30 mA

•Pa rt number chan g es - see pa ge 23 for additiona l inform at ion

Mar 2003

06 •Added new “MM” Micro-Package MPNs for 1M and 2M LF parts- see

page 23 Oct 2003

07 •2004 Data Book

•Added non-Pb MPNs and removed footnote (See page 23)

•Updated B3K and MM package diagrams

Nov 2003

08 •Added RoHS Compliant statement.

•Added 4 MBit to Figure 4.

•Revised Absolute Max Stress Rat ing s for Surface Mount Solder Re flow

Temperature

•Removed SST39VFxxx-90 Timing Parameters from Figure 12.

•Added Footnote and removed Read Access Speed 90 = 90 to Product

Order i n g Information.

•Removed 90 part numbers Valid Combinations lists

Dec 2005

09 •Edited page Valid Combinations on page 21. Changed 39LF040-70-4C-

B3KE to 39LF040-45-4C-B3KE Jan 2006

10 •Removed leaded parts Nov 2008

11 •Added package YME Feb 2009

12 •Revised “Product Ordering Information” on page 23 Apr 2009

13 •Changed endurance from 10,000 to 100 ,000 in Product Description, page

1Sep 2009

14 •EOL of SST39LF010-45-4C-YME. Replacement pa rt is SST39LF010-45-

4C-MME in this document.

•Removed all references to the YME package.

Jan 2010

A•EOL of SST39LF512 and SST39VF5 12 parts. Replacement parts are

SST39LF010 and SST39VF010.

•Applied new document format.

•Released document under letter revision system.

•Updated spec number S71150 to DS25023.

Aug 2011

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

B•EOL of 45 ns parts. Removed all 45 ns parts; updated Tabl e 12 on

page 13 to reflect this change.

•EOL of B3KE. Removed the B3KE package.

•EOL of MME. Remo ved the MME package.

•Added 55ns for SST39LF010 and SST39VF010 parts

June 2013

Table 14: Revision History

Number Description Date

SST, Silicon Stor age Technology, the SST logo, SuperFlash, MTP, and FlashFle x are registered tr ademarks of Silicon Storage Tech-

nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and

registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Ref er to www .microchip .com for the most recent documentation. F or the most current

package dra wings, please see the Pac kaging Specification located at http://www . microchip .com/pac kaging.

Memory sizes denote raw storage capacity; actual usable capacity ma y be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Term s and Conditions of

Sale.

For sales office locations and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

ISBN:978-1-62077-292-8