MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs SYNCHRONOUS DRAM MODULE MT8LSDT864A, MT16LSDT1664A For the latest full-length data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/himl/ datasheet.html FEATURES PC66- and PC100-compliant e JEDEC-standard 168-pin, dual in-line memory module (DIMM) Utilizes 100 MHz and 125 MHz SDRAM components Nonbuffered 64MB (8 Meg x 64) and 128MB (16 Meg x 64) Single +3.3V +0.3V power supply Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal SDRAM banks for hiding row access/ precharge Programmable burst lengths: 1, 2, 4, 8 or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh LVTTL-compatible inputs and outputs Serial presence-detect (SPD) Two-clock WRITE recovery (*WR) version; one-clock WR not supported OPTIONS MARKING Package 168-pin DIMM (gold) G e Frequency/CAS Latency 100 MHz/CL = 2 (8ns, 125 MHz SDRAMs) _ -10E 100 MHz/CL = 3 (8ns, 125 MHz SDRAMs) -10C 66 MHz/CL = 2 (10ns, 100 MHzSDRAMs) _ -662 KEY SDRAM COMPONENT TIMING PARAMETERS MODULE | SPEED CAS ACCESS | SETUP HOLD MARKING | GRADE | LATENCY | TIME TIME TIME -10E -8E 2 6ns 2ns ins -10C -8C 3 6ns 2ns ins -662 -10 2 Ons 3ns ins PIN ASSIGNMENT (Front View) 168-Pin DIMM (H-18; 64MB, 66 MHz), (H-21; 64MB, 100 MHz), (H-22; 128MB) UU LL a) = n =< = 8 rr a) = n =< = 8 rr a) = SYMBOL | PIN | SYMBOL 1 Vss 43 Vss 85 Vss 127 Vss 2 DQO 44 DNU 86 DQ32 128 CKEO 3 bai 45 S2# 87 DQ33 129 S3#* 4 DQ2 46 DQM B2 88 DQ34 130 | DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQM B7 6 Vop 48 DNU 90 Vop 132 RFU 7 DOQ4 49 Vop 91 DQ36 133 Vop 8 DQ5 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ? 52 NC 94 DQ39 136 NC 11 DQ8 53 NC 95 DQ40 137 NC 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQi6 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 Vpp 101 DQ45 143 Vop 18 Vop 60 DQ20 102 Vop 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 NC 63 CKE1* 105 NC 147 NC 22 NC 64 Vss 106 NC 148 Vss 23 Vss 65 DQ?1 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 Vop 68 Vss 110 Vop 152 Vss 27 WE# 69 DQ24 111 CAS# 153 DQ56 28 DQM BO 70 DQ25 112 | DOQMB4 | 154 DQ57 29 DQMBi1 71 DQ26 113 | DQMB5 | 155 DQ58 30 SO# 72 DQ27 114 Si#* 156 DQ59 31 DNU 73 Vop 115 RAS# 157 Vop 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 Al 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 AD 161 DQ63 36 AG 78 Vss 120 A7 162 Vss 37 A8 79 CkK2 121 AQ 163 CkK3 38 Ai0 80 NC 122 BAO 164 NC 39 BAI 81 | NC/WP** | 123 All 165 SAO 40 Vpp 82 SDA 124 Vpp 166 SAI Al Vpp 83 SCL 125 CK1 167 SA2 42 CKO 84 Vpp 126 RFU 168 Vpp *128MB version only **.10E/-10C versions only 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. Micron is a registered trademark of Micron Technology, Inc.MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs PART NUMBERS PART NUMBER CONFIGURATION | SYSTEM BUS SPEED MT8LSDT864AG-662_ 8 Meg x 64 66 MHz MT8LSDT864AG-10C__ 8 Meg x 64 100 MHz MT8LSDT864AG-10E_ 8 Meg x 64 100 MHz MT16LSDT1664AG-662__| 16 Meg x 64 66 MHz MT16LSDT1664AG-10C_| 16 Meg x 64 100 MHz MT16LSDT1664AG-10E_| 16 Meg x 64 100 MHz NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8LSDT864AG-1 0EB4. GENERAL DESCRIPTION The MT8LSDT864A and MT16LSDT1664<A are high-speed CMOS, dynamic random-access, 64MB and 128MB memo- ries organized in a x64 configuration. These modules use internally configured quad-bank SDRAMs with a synchro- nous interface (all signals are registered on the positive edge of the clock signals CKO-CK3). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC- TIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BAO, BAI select the bank, AO-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The modules provide for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compat- ible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The modules are designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to syn- chronously burst data at a high data rate with automatic column-address generation, the ability to interleave be- tweeninternal banks inorder tohide precharge timeand the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 64Mb: x4, x8, x16 SDRAM data sheet. SERIAL PRESENCE-DETECT OPERATION These modules incorporate serial presence-detect (SPD). TheSPD function isimplemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and tim- ing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMMs SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/ EEPROM addresses. 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.MicCr ON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM SDRAM SDRAM CKO ww SDRAM Cage SDRAM tP" SDRAM SDRAM CKe SDRAM t SDRAM T 3.3pF CK1, CK3 vq 10pF T 100 MHz VERSIONS MT8LSDT864A (64MB) SOo# DQ@MBo4 DQMB4, | DQM CS# DQM CS# DQ0 -w;DGQ0 DQ32 -w7 DQO DQ1 -wj4DQ1_ U0 DQ38-~jDQi U4 DQ2 -~4DQ2 DQ34 4 DQ2 DQ3 -~4DQ3 DQ35 4 DQ3 DQ4 -~jDa4 DQ36 -wj DQ4 DQ5 -~4DQ5 DQ37 Ww DQ5 DQ6 ~4DQ6 DQ38 4 DQ6 DQ7 -w4DQ7 DQ39 Ww DQ7 DpaMBi | DQMB5 | DQM CS# DQM CS# Das -~w7DGO0 DQ40 -w7 DQOo DQ9 -wjDQ1 (U1 DQ41-wjDQi- U5 DQ10 -w4 DQ2 DQ42 -w4 DQ2 DQ11 4 DQ3 DQ43 -~4 DQ3 DQ12 -wy DQ4 DQ44-w DQ4 DQ13 4 DQ5 DQ45 -w4 DQ5 DQ14 4 DQ6 DQ46 -~4 DQ6 DQ15 -~ DQ7 DQ47 4 DQ7 S2# DQ@MB2} DQMB6-_ DQM CS# DQM CS# DQ16 w4 DQ0 DQ48 -w4 DQ0 DQ17-wjDQi-U2 DQ49-w~jDQi_ -U6 DQ18 -w4 DQ2 DQ50 -w DQ2 DQ19 -w5 DQ3 DQ51 Ww DQ3 DQ20 -w DQ4 DQ52 -w DQ4 DQ21 -w4 DQ5 DQ53 Ww DQ5 DQ22 -w7 DQ6 DQ54-~ 4 DQ6 DQ23 -~ DQ7 DQ55 -w4 DQ7 bamMB3s_} | D@MB7-_, | DQM CS# DQM CS# DQ24 -w4 DQO DQ56 -vw DO DQ25-~DQ1_U3 DQ57-w~DQ1_sOU7 DQ26 -w4 DQ2 DQ58 -w DQ2 DQ27 4 DQ3 DQ59 -w4 DQ3 DQ28 -w4 DQ4 DQ60 w4 DA4 DQ29 -w DQ5 DQ61 w DQ5 DQ30 -~4 DQ6 DQ62 -w5 DQ6 DQ31 -w+ DQ7 DQ63 -w5 DQ7 RAS# RAS#: SDRAMs U0-U7 Uo CAS# + CAS#: SDRAMs U0-U7 U4 CKEO + CKEO: SDRAMs U0-U7 CKO U4 WE# + WE#: SDRAMs U0-U7 US AO-A11 A0-A11: SDRAMs U0-U7 U2 BAO + BAO: SDRAMs U0-U7 cKI U6 BA1 BA1: SDRAMs U0-U7 US Vpp >. SDRAMs U0-U7 Vss _ __ SDRAMs U0-U7 CK2, CK3 wy 10pF Lt SPD = _ 66 MHz VERSION SCL =< SDA WP AO Al A2 ake | | | + SAO SA1 SA2 NOTE: All resistor values are 10 ohms. U0-U7 = MT48LC8M8A2GT SDRAMs 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.MicCr ON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT16LSDT1664A (128MB) SO# Sil# DQMBO0 _? DQMB4 DQM CS# DQM CS# DQM CS# DQM CS# DQO0 -w1Da0 - Dao DQ32 7 DQO - Dao DQ1 -~j;DQ1i__~U0 rDaQi_ Us DQ33-wjDQi- (U4 -DQ1 U12 DQ2 -w1DQ2 -7 DQ2 DQ34 -w7 DQ2 L DQ2 DQ3 -w{DQ3 - DQ3 DQ35 -w DQ3 t DQ3 DQ4 -wj{DQ4 L DQ4 DQ36 ~~ DQ4 -| DQ4 DQ5 -w7DQ5 L DQ5 DQ37 -w4 DQ5 L DQs DQ6 -w4DQ6 -| DQ6 DQ38 yw DQ6 | DQ6 DQ7 -w4DQ7 H+ DQ7 DQ39 +p, DQ7 }| DQ7 DQMB1 DQMB5 DQM CS# DQM CS# DQM CS# DQM CS# DQ8 -wj{DG0 - 7 DQ0 DQ40 -w4 DGO - Dao DQ9 -wjDQ1 U1 rDQi_ U9 DQ41 -w47DQi-US rDaQi U13 DQ10 1 DQ2 tj DQ2 DQ42 1 DQ2 - DQ2 DQ11 -w4DQ3 L DQ3 DQ43 -w DQ3 L DQ3 DQ12 -w~DOQ4 L DQ4 DQ44 ~~ DO4 - D4 DQ13 ~4 DOS -| DQ5 DQ45 yw DQ5 HL DQ5 DQ14 -w4 DQ6 LJ DQ6 DQ46 yw DQ6 | Das DQ15 -w4 DQ7 H+ DQ7 DQ47 ~w4 DQ7 L| DQ7 S3# DQMB2__-*__r- | DQMB6 _e_ DQM CS# DQM CS# DQM CS# DQM CS# DQ16- 7 DQO - DQo DQ48 7 DQO - Dao DQ17-~7DQi-s U2 FDQ1 U10 DQ49-w7DQi- U6 r Dai U14 DQ18 -~w4 DG2 -7 DQ2 DQ50 -~7 DQ2 - DQ@2 DQ19 -w4 DQ3 L DQ3 DQ51 -~4 DQ3 - DQ3 DQ20 -w 4 DQ4 -j DQ4 DQ52 ~~ DO4 L DQ4 DQ21 -w]DQ5 -| DQ5 DQ53 -~DQ5 L DQ5 DQ22 +, DQ6 1 DQ6 DQ54 4 DQ6 L DQ6 DQ23 4 DQ7 } DQ7 DQ55 4 DQ7 | DQ7 D@MB3@}-_| | DQMB7-9} | DQM CS# DQM CS# DQM CS# DQM CS# DQ24 -w4 DGO - DQo DQ56 -w4 DGO - Dao DQ25 -wjDQi-U3 r Dai U11 DQ57-wjDQiU7 Fr DaQi U15 DQ26 ~ DQ2 tj DQ2 DQ58 4 DQ2 - DQ2 DQ27 ~~ DQ3 - DQ3 DQ59 -w DQ3 - DQ3 DQ28 vw DQ4 -j DQ4 DQ60 ~~ DQ4 - D4 DQ29 +4 DOS 1 DQ5 DQ61 -w4 DQ5 HL DQ5 DQ30 4 DQ6 -| DQ6 DQ62 -~4 DQ6 L DQ6 DQ31 yw DQ7 } DQ7 DQ63 yw DQ7 L| DQ7 Voo 10K: CKE1 KF CKE: SDRAMs U8-U15 SDRAM CKEO CKE: SDRAMs U0-U7 CAS# > CAS#: SDRAMs U0-U15 RAS# + RAS#: SDRAMs U0-U15 WE# >+ WE#: SDRAMs U0-U15 A0-A11 > A0-A11: SDRAMs U0-U15 BAO + BAO: SDRAMs U0-U15 BA1 *BA1: SDRAMs U0-U15 Voo SDRAMs U0-U15 Vss L_____ SDRAMs U0-U15 WP AO Ai A2 47K rT. 0 SPD SCL = SAO SA1 SA2 =~ SDA NOTE: All resistor values are 10 ohms unless otherwise specified. SDRAM oxo fs SORAV SDRAM 1 3.3pF 7 SDRAM SDRAM cK ~w{S SDRAM SDRAM J 3.3pF SDRAM SDRAM SDRAM SDRAM LT 3.3pF 7 SDRAM CK2 SDRAM Ks sw {S$ SORAM SDRAM J 3.3pF U0-U15 = MT48LC8M8A2TG SDRAMs 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE DESCRIPTION 115,111, 27 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS# and WE# (along with SO#-S3#) define the command being entered. 42,79, 125, 163 CKO-CK3 Input Clock: CKO-CK3 are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 63, 128 CKE1, CKEO Input Clock Enable: CKEO-CKE1 activate (HIGH) and deactivate (LOW) the CKO-CKS signals. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER- DOWN (row ACTIVE in any bank) or CLOCK SUSPEND operation (burst access in progress). CKEO-CKE1 are synchronous except after the device enters power-down and self refresh modes, where CKEO-CKE1 become asynchronous until after exiting the same mode. The input buffers, including CKO-CK3, are disabled during power- down and self refresh modes, providing low standby power. 30, 45, 114, 129 SO#-S3# Input Chip Select: SO#-S3# enable (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when SO#-S3# are registered HIGH. SO#-S3# are considered part of the command code. 28-29, 46-47, 112-113, 130-131 DQMB0-DQMB7 Input Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH during a READ cycle. 39, 122 BA1, BAO Input Bank Address: BAO and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. 33-38, 117-121, 123 AO-A11 Input Address Inputs: AO-A11 are sampled during the ACTIVE command (row-address AO-A11) and READ/WRITE command (column-address AO-A8, with A10 defining AUTO PRECHARGE) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BAO, BA1 (LOW). The address inputs also provide the op-code during aLOAD MODE REGISTER command. 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 DQO0-DQ63 Input/ Output Data |/Os: Data bus. 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.: 8, 16 MEG x 64 MICRON SDRAM DIMMs PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE DESCRIPTION 6, 18, 26, 40, 41, 49, 59, Vpp Supply Power Supply: +3.3V +0.3V. 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1,12, 23, 32, 43, 54, 64, Vss Supply Ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 81 WP Input Write Protect: Serial presence-detect hardware write protect. Applies to -10E/-10C versions only. 82 SDA Input/Output | Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 165-167 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 126, 132 RFU - Reserved for Future Use: These pins should be left unconnected. 31, 44, 48 DNU - Do Not Use: These pins are not connected on these modules but are assigned pins on the compatible DRAM version. 8, 16 Meg x 64 SDRAM DIMMs 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ZMO6.p65 Rev. 3/99 1999, Micron Technology, Inc.MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SDA / x DATA STABLE DATA CHANGE DATA STABLE | Figure 1 DATA VALIDITY SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW toacknowledge thatit received the eight bits of data (Figure 3). The SPD device will always respond with an acknowl- edge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an ac- knowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. Ifanacknowledgeis not detected, theslave will terminate further data transmissions and await the stop condition to return to standby power mode. SCL | \ / \ / | SDA | | | | START STOP BIT BIT Figure 2 DEFINITION OF START AND STOP wn QO - 3 3 = D a @ I I re) Data Output - from Transmitter | [ x Data Output from Receiver | | >< oo NSN Acknowledge Figure 3 ACKNOWLEDGE RESPONSE FROM RECEIVER 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.8, 16 MEG x 64 MICRON SDRAM DIMMs TECHNOLOGY, INC. SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION ENTRY (VERSION) | SYMBOL | BIT7| BIT6| BITS} BIT4| BIT3| BIT2} BIT1| BITO| HEX 0 NUMBER OF BYTES USED BY MICRON 128 1 0 0 0 0 0 0 0 80 1 TOTAL NUMBER OF SPD MEMORY BYTES 256 0 0 0 0 1 0 0 0 08 2 MEMORY TYPE SDRAM 0 0 0 0 0 1 0 0 04 3 NUMBER OF ROW ADDRESSES 12 0 0 0 0 1 1 0 0 0c 4 NUMBER OF COLUMN ADDRESSES 9 0 0 0 0 1 0 0 1 09 5 NUMBER OF BANKS 1 (64MB) 0 0 0 0 0 0 0 1 01 2 (128MB) 0 0 0 0 0 0 1 0 02 6 MODULE DATA WIDTH 64 0 1 0 0 0 0 0 0 40 7 MODULE DATA WIDTH (continued) 0 0 0 0 0 0 0 0 0 00 8 MODULE VOLTAGE INTERFACE LEVELS LVTTL 0 0 0 0 0 0 0 1 01 9 SDRAM CYCLE TIME 8 (-10E/-10C) CK 1 0 0 0 0 0 0 0 80 (CAS LATENCY = 3) 10 (-662) 1 0 1 0 0 0 0 0 AO 10 SDRAM ACCESS FROM CLOCK 6 (-10E/-10C) TAC 0 1 1 0 0 0 0 0 60 (CAS LATENCY = 3) 7 (-662) 0 1 1 1 0 0 0 0 70 11 MODULE CONFIGURATION TYPE NONPARITY 0 0 0 0 0 0 0 0 00 12 REFRESH RATE/TYPE 15.6y1s/SELF 1 0 0 0 0 0 0 0 80 13 SDRAM WIDTH (PRIMARY SDRAM) 8 0 0 0 0 1 0 0 0 08 14 ERROR-CHECKING SDRAM DATA WIDTH NONE 0 0 0 0 0 0 0 0 00 15 MINIMUM CLOCK DELAY FROM BACK-TO-BACK 1 ee) 0 0 0 0 0 0 0 1 01 RANDOM COLUMN ADDRESSES 16 BURST LENGTHS SUPPORTED 1, 2, 4, 8, PAGE 1 0 0 0 1 1 1 1 8F 17 NUMBER OF BANKS ON SDRAM DEVICE 4 0 0 0 0 0 1 0 0 04 18 CAS LATENCIES SUPPORTED 2,3 0 0 0 0 0 1 1 0 06 19 CS LATENCY 0 0 0 0 0 0 0 0 1 01 20 WE LATENCY 0 0 0 0 0 0 0 0 1 01 21 SDRAM MODULE ATTRIBUTES NONBUFFERED 0 0 0 0 0 0 0 0 00 22 SDRAM DEVICE ATTRIBUTES: GENERAL OE 0 0 0 0 1 1 1 0 OE 23 SDRAM CYCLE TIME 10 (-10E) CK 1 0 1 0 0 0 0 0 AO (CAS LATENCY = 2) 12 (-10C) 1 1 0 0 0 0 0 0 co 15 (-662) 1 1 1 1 0 0 0 0 FO 24 SDRAM ACCESS FROM CLK 6 (-10E) TAC 1 0 0 1 0 0 0 0 60 (CAS LATENCY = 2) 9 (-10C/-662) 1 0 0 1 0 0 0 0 90 25 SDRAM CYCLE TIME - CK 0 0 0 0 0 0 0 0 00 (CAS LATENCY = 1) 26 SDRAM ACCESS FROM CLK - TAC 0 0 0 0 0 0 0 0 00 (CAS LATENCY = 1) 27 MINIMUM ROW PRECHARGE TIME 20 (-10E/-10C) RP 0 0 0 1 0 1 0 0 14 30 (-662) 0 0 0 1 1 1 1 0 1E 28 MINIMUM ROW ACTIVE TO ROW ACTIVE 20 'RRD 0 0 0 1 0 1 0 0 14 29 MINIMUM RAS# TO CAS# DELAY 20 (-10E/-10C) 'RCD 0 0 0 1 0 1 0 0 14 30 (-662) 0 0 0 1 1 1 1 0 1E 30 MINIMUM RAS# PULSE WIDTH 50 (-10E/-10) 'RAS 0 0 1 1 0 0 1 0 32 60 (-662) 0 0 1 1 1 1 0 0 3C 31 MODULE BANK DENSITY 64MB 0 0 0 1 0 0 0 0 10 32 COMMAND AND ADDRESS SETUP TIME 2 (-10E/-10C) tas, CMS] 0 0 1 0 0 0 0 0 20 0 (-662) 0 0 0 0 0 0 0 0 00 NOTE: 1. 1/0: Serial Data, driven to HIGH/driven to LOW. 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.8, 16 MEG x 64 MICRON SDRAM DIMMs TECHNOLOGY, INC. SERIAL PRESENCE-DETECT MATRIX (continued) BYTE DESCRIPTION ENTRY (VERSION) | SYMBOL | BIT7 | BIT6 | BITS | BIT4 | BIT3|) BIT2 | BIT1 | BITO | HEX 33 COMMAND AND ADDRESS HOLD TIME 1 (-10E/-10C) 'AH, 'CMH] 0 0 0 1 0 0 0 0 10 0 (-662) 0 0 0 0 0 0 0 0 00 34 DATA SIGNAL INPUT SETUP TIME 2 (- 10E/-10C) DS 0 0 1 0 0 0 0 0 20 (-662) 0 0 0 0 0 0 0 0 00 35 DATA SIGNAL INPUT HOLD TIME 1 (-10E/-10C) DH 0 0 0 1 0 0 0 0 10 (-662) 0 0 0 0 0 0 0 0 00 36-61 | RESERVED 0 0 0 0 0 0 0 0 00 62 SPD REVISION REV. 1.2 (-10E/-10C) 0 0 0 1 0 0 1 0 12 REV. 1.0 (-662) 0 0 0 0 0 0 0 1 01 63 CHECKSUM FOR BYTES 0-62 64MB -10E 1 1 1 0 0 1 0 1 E5 64MB -10C 0 0 1 1 0 1 0 1 35 64MB -662 0 1 0 0 0 0 1 0 42 128MB -10E 1 1 1 0 0 1 1 0 E6 128MB -10C 0 0 1 1 0 1 1 0 36 128MB -662 0 1 0 0 0 0 1 1 43 64 MANUFACTURER'S JEDEC ID CODE MICRON 0 0 1 0 1 1 0 0 20 65-71 | MANUFACTURER'S JEDEC ID CODE (CONT. ) 1 1 1 1 1 1 1 1 FF 72 MANUFACTURING LOCATION 0 0 0 0 0 0 0 1 01 0 0 0 0 0 0 1 0 02 0 0 0 0 0 0 1 1 03 0 0 0 0 0 1 0 0 04 0 0 0 0 0 1 0 1 05 0 0 0 0 0 1 1 0 06 73-90 | MODULE PART NUMBER (ASCII) x x x x x x x x xx 91 PCB IDENTIFICATION CODE 1 0 0 0 0 0 0 0 1 01 2 0 0 0 0 0 0 1 0 02 3 0 0 0 0 0 0 1 1 03 4 0 0 0 0 0 1 0 0 04 92 IDENTIFICATION CODE (CONT.} 0 0 0 0 0 0 0 0 0 00 93 YEAR OF MANUFACTURE IN BCD x x x x x x x x XX 94 WEEK OF MANUFACTURE IN BCD x x x x x x x x XX 95-98 | MODULE SERIAL NUMBER x x x x x x x x XX 99-125 | MANUFACTURER-SPECIFIC DATA (RSVD) - - - - - - - - - 126 | SYSTEM FREQUENCY 100 MHz (-10E/-10C) 0 1 1 0 0 1 0 0 64 66 MHz (-662) 0 1 1 0 0 1 1 0 66 127 | SDRAM COMPONENT AND CLOCK DETAIL 64MB (-10E) 1 0 1 0 1 1 1 1 AF 64MB (-10C) 1 0 1 0 1 1 0 1 AD 128MB (-10E) 1 1 1 1 1 1 1 1 FF 128MB (-10C) 1 1 1 1 1 1 0 1 FD (-662) 1 0 0 0 0 1 1 0 06 NOTE: 1. 1/0: Serial Data, driven to HIGH/driven to LOW. 2. x = Variable Data. 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs COMMANDS Truth Table 1 provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 64Mb: x4, x8, x16 SDRAM data sheet. TRUTH TABLE 1 Commands and DQMB Operation (Notes: 1) NAME (FUNCTION) CS# | RAS# | CAS# | WE# |DQMB) ADDR DQs_ | NOTES COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X |Bank/Row}| X 3 READ (Select bank and column, and start READ burst) L H L H | L/H8}Bank/Col| X 4 WRITE (Select bank and column, and start WRITE burst) L H L L | W/H8| Bank/Col | Valid 4 BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or L L L H X X X 6,7 SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER L L L L Op-Code] X 2 Write Enable/Output Enable L Active 8 Write Inhibit/Output High-Z - - - - H - High-Z| 8 NOTE: CKE is HIGH for all commands shown except SELF REFRESH. . A0-A11 define the op-code written to the Mode Register. 1. 2 3. A0O-A11 provide row address, and BAO, BA1 determine which bank is made active. A . AO-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BAO, BA1 determine which bank is being read from or written to. uo BAO, BA1 are Dont Care. NO A10 LOW: BAO, BA1 determine which bank is being precharged. A10 HIGH: all banks are precharged and This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are Dont Care except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 8, 16 MEG x 64 MICRON SDRAM DIMMs Ail A10 AQ ABS A7 AB AB Ad AB AZ Al AD Address Bus Table 1 ' ' BURST DEFINITION Reserved" | we | Op Mode | CAS Latency Burst Length ode Regier Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential | Type = Interleaved *Should program AO to ensure compaty Burst Length 2 0 0-1 0-1 with future devices. we Mimo Ma <0 wet 1 1 -0 1 -0 000 1 1 Ai AO oot 2 2 0 6 (~O 0-1-2-3 0-1-2-3 oie 4 4 Oo 61 1-2-3-0 1-0-3-2 011 8 8 4 100 Reserved Reserved 1 0 2-3-0-1 23-0-1 1041 Reserved Reserved 1 1 3-0-1 2 3-2-1 0 110 Reserved Reserved A2 Al AO 144 Full Page Reserved 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 oO 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 =#0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 M3 Burst Type 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 Sequential 1 0 O | 4-5-6-7-0-1-2-3 | 4-5-6-7-0-1-2-3 1 0 1 | 5-6-7-0-1-23-4 | 5-4-7-6-1-0-3-2 M6 M5 M4 CAS Latency 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 000 Reserved 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 : : : ee Eull n= A0-A8 Cn, Cn+1,Cn+2 Cn +3, Cn + 4... 0414 3 Page Cn-4 Not supported 100 Reserved (y) (location 0-y) wn , 101 Reserved Cn... 1100 Reserved 114 Reserved NOTE: 1. For full-page accesses: y = 512. 2. For a burst length of two, A1-A8 select the block-of- two burst; AO selects the starting column within the M8 M7 M6-MO Operating Mode block. Defined | Standard Operation 3. For a burst length of four, A2-A8 select the block-of- All other states reserved four burst; AO-A1 select the starting column within the block. 4. For a burst length of eight, A3-A8 select the block-of- we Write Burst Mods eight burst; AO-A2 select the starting column within 0 Programmed Burst Length the block. 1 Single Location Access 5. For a full-page burst, the full row is selected, and AO-A8 select the starting column. Figure 1 6. Whenever a boundary of the block is reached within MODE REGISTER DEFINITION a given Seavence above, the following access wraps 7. For a burst length of one, AO-A8 select the unique column to be accessed, and Mode Register bit M3 is ignored. Seave x 64 SDRAM DIMMs 1 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. .p65 Rev. 3/99 1999, Micron Technology, Inc.MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS* Voltage on Vpp Supply Relative to Vss .......... -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to V8S ..cccccescssecsesscsssesseescesseseeeeseees -1V to +4.6V Operating Temperature, T, (ambient) .......... 0C to +70C Storage Temperature (plastic)... -55C to +125C Power Dissipation. ......cccccseeseseeeseseseesseseeneneesesesesesnsseees 8W *Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 6) (Voo = +3.3V +0.3V) PARAM ETER/CONDITION SYMBOL | MIN MAX | UNITS | NOTES SUPPLY VOLTAGE Vop 3 3.6 Vv INPUT HIGH VOLTAGE: Logic 1; All inputs Vin 2 Voo +0.3] V 24 INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.5 0.8 Vv 24 INPUT LEAKAGE CURRENT: DQMB0-DQMB7 li -10 10 LA 22 Any input OV < Vin < Vop CKO-CK3, SO#-S3# li2 -20 20 HA (All other pins not under test = OV) | CKEO-CKE1 lig -40 40 LA RAS#, CAS#, AO-A11, li4 -80 80 LA 22 BAO-BA1, WE# OUTPUT LEAKAGE CURRENT: DQ0-DQ63 loz -10 10 LA 22 DQs are disabled; OV < Vout < Vpp OUTPUT LEVELS: VoH 2.4 - Vv Output High Voltage (lout = -4mA) Output Low Voltage (lout = 4mA) VoL - 0.4 Vv 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs lbp SPECIFICATIONS AND CONDITIONS (Notes: 1, 6, 11, 13) (Vop = +3.3V +0.3V) MAX PARAM ETER/CONDITION SYMBOL| SIZE |-10B-10C | -662 UNITS | NOTES OPERATING CURRENT: Active Mode; 64MB 760 720 3, 18, 19, Burst = 2; READ or WRITE; 'RC ='RC (MIN); Ipp1 mA 30 CAS latency = 3 128MB | 1,040 960 STANDBY CURRENT: Power-Down Mode; Ipb2 64MB 16 24 mA 30 CKE = LOW; All banks idle 128MB 32 48 STANDBY CURRENT: Active Mode; SO#-S3# = HIGH; 64MB 280 240 3, 12, 19, CKE = HIGH; All banks active after RCD met; IpD3 mA 30 No accesses in progress 128MB | 560 480 OPERATING CURRENT: Burst Mode; Continuous burst; 64MB 960 840 3, 12, 19, READ or WRITE; All banks active; Ipp4 mA 30 CAS latency = 3 128MB} 1,240 1,080 AUTO REFRESH CURRENT: Ipps 64MB | 1,520 1,360 mA 3, 12, CKE = HIGH; SO#-S3# = HIGH | RC ='RC (MIN); CL=3 128MB | 1,800 1,600 18, 19, IpD6 64MB 320 280 mA 30 'RC = 15.625us; CL =3 128MB| 640 560 SELF REFRESH CURRENT: CKE < 0.2V IDD7 64MB 8 16 mA 4 128MB 16 32 PARAMETER SYMBOL} MIN MAX MIN MAX | UNITS | NOTES Input Capacitance: AO-A11, BAO, BA1, RAS#, CAS#, WE# CH 22 45 44 88 pF 2 Input Capacitance: CKO-CK3 Ci2 12 18 12 18 pF 2 Input Capacitance: SO#-S3# Cis 12 24 12 24 pF 2 Input Capacitance: CKEO, CKE1 Ci4 22 45 22 45 pF 2 Input Capacitance: DQMBO#-DQMB7# Cis 4 8 7 13 pF 2 Input Capacitance: SCL, SAO-SA2 Cie 6 - 6 pF 2 Input/Output Capacitance: DQ0-DQ63, SDA Cio 6 10 10 15 pF 2 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.: 8, 16 MEG x 64 MICRON SDRAM DIMMs SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 11) AC CHARACTERISTICS -10E -10C -662 PARAMETER SYMBOL| MIN MAX MIN MAX MIN MAX | UNITS | NOTES Access time from CLK (pos. edge) CL=3 tAC 6 6 7 ns CL=2 tAC 6 9 9 ns Address hold time 'AH 1 1 1 ns Address setup time TAS 2 2 3 ns CLK high-level width 1CH 3 3 3.5 ns CLK low-level width tCL 3 3 3.5 ns Clock cycle time CL=3 CK 8 8 10 ns 25 CL=2 CK 10 12 15 ns 25 CKE hold time 'CKH 1 1 1 ns CKE setup time 'CKS 2 2 3 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 1 ns CS#, RAS#, CAS#, WE#, DQM setup time CMS 2 2 3 ns Data-in hold time DH 1 1 1 ns Data-in setup time Ds 2 2 3 ns Data-out high-impedance time CL=3 tHZ 6 6 8 ns 10 CL=2 tHZ 7 7 10 ns 10 Data-out low-impedance time LZ 1 1 2 ns Data-out hold time OH 3 3 3 ns ACTIVE to PRECHARGE command RAS 50 120,000} 50 120,000] 60 120,000] ns AUTO REFRESH, ACTIVE command period tRC 70 70 90 ns ACTIVE to READ or WRITE delay RCD 20 20 30 ns Refresh period (4,096 cycles) 'REF 64 64 64 ms PRECHARGE command period RP 20 20 30 ns ACTIVE bank A to ACTIVE bank B command 'RRD 20 20 20 ns Transition time T 0.3 1.2 0.3 1.2 1 1.2 ns 7 WRITE recovery time twR 11 CLK+ 1 CLK+ 1 CLK+ - 26 8ns 8ns 8ns 15 15 15 ns 27 Exit SELF REFRESH to ACTIVE command XSR 80 80 90 ns 20 *Specifications for the SDRAM components used on the module. 8, 16 Meg x 64 SDRAM DIMMs 1 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ZMO6.p65 Rev. 3/99 1999, Micron Technology, Inc.: 8, 16 MEG x 64 MICRON SDRAM DIMMs AC FUNCTIONAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 11) PARAMETER SYMBOL -10E -10C -662 UNITS | NOTES READ/WRITE command to READ/WRITE command CCD 1 1 1 'CK 17 CKE to clock disable or power-down entry mode 'CKED 1 1 1 CK | 14 CKE to clock enable or power-down exit setup mode 'PED 1 1 1 'CK 14 DQM to input data delay DQD 0 0 0 cK | 17 DQM to data mask during WRITEs DQM 0 0 0 'CK 17 DQM to data high-impedance during READs 'DQZ 2 2 2 'CK 17 WRITE command to input data delay DWD 0 0 0 CK | 17 Data-in to ACTIVE command IDAL 4 4 4 1CK | 15, 21 Data-in to PRECHARGE command 'DPL 2 2 2 'CK 16 Last data-in to burst STOP command BDL 1 1 1 'CK 17 Last data-in to new READ/WRITE command CDL 1 1 1 'CK 17 Last data-in to PRECHARGE command 'RDL 2 2 2 'CK 16 LOAD MODE REGISTER command to ACTIVE or REFRESH command MRD 2 2 2 'CK 28 Data-out to high-impedance from PRECHARGE command CL=3 | 'ROH 3 3 3 CK | 17 CL=2 ROH 2 2 2 1CK 17 SDRAM COMPONENT* ELECTRICAL TIMING CHARACTERISTICS BETWEEN -8 SPEED OPTIONS (Notes: 5, 6, 8, 9, 11) AC CHARACTERISTICS -8E -8D -8C -8B -8A PARAMETER SYMBOL | MIN | MAX} MIN | MAX] MIN | MAX | MIN | MAX | MIN | MAX | UNITS | NOTES Access time from CLK (pos. edge) CL=3 AC 6 6 6 6 6 ns 29 CL=2] tac 6 7 9 9 9 ns 29 CL=1 AC 27 27 27 27 27 | ns 29 Clock cycle time CL=3]| ck 8 8 8 8 8 ns 29 CL=2] ck 10 10 12 12 12 ns 29 CL=1 Ck 30 30 30 30 30 ns 29 ACTIVE to READ or WRITE delay RCD | 20 20 20 20 24 ns 29 PRECHARGE command period 'RP 20 20 20 24 24 ns 29 AUTO REFRESH, ACTIVE command period IRC 70 70 70 80 80 ns 29 WRITE recovery time twR 2 2 2 2 2 cK | 214 100 MHz Speed Reference (CL-'RCD-'RP) 2-2-2 2-2-2 3-2-2 3-2-3 3-3-3 | CLKs *Specifications for the SDRAM components used on the module. 8, 16 Meg x 64 SDRAM DIMMs 1 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ZMO6.p65 Rev. 3/99 1999, Micron Technology, Inc.MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Notes: 1) (Von = +3.3V +0.3V) PARAM ETER/CONDITION SYMBOL MIN MAX UNITS | NOTES SUPPLY VOLTAGE Vpbp 3 3.6 Vv INPUT HIGH VOLTAGE: Logic 1; All inputs VIH Vop x 0.7/Vpp +0.5} V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 Voo x 0.3] V OUTPUT LOW VOLTAGE: lout = 3mA VoL 0.4 Vv INPUT LEAKAGE CURRENT: Vin = GND to Vop IL 10 LA OUTPUT LEAKAGE CURRENT: Vout = GND to Vop ILo 10 LA STANDBY CURRENT: IsB 30 LA SCL = SDA = Vopp - 0.3V; All other inputs = GND or 3.38V +10% POWER SUPPLY CURRENT: Ipp 2 mA SCL clock frequency = 100 KHz SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Notes: 1) (Vop = +3.3V +0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS | NOTES SCL LOW to SDA data-out valid TAA 0.3 3.5 Us Time the bus must be free before a new transition can start BUF 4.7 Us Data-out hold time 'DH 300 ns SDA and SCL fall time tF 300 ns Data-in hold time tHD:DAT 0 Ls Start condition hold time tHD:STA 4 Us Clock HIGH period HIGH 4 us Noise suppression time constant at SCL, SDA inputs {| 100 ns Clock LOW period Low 4.7 us SDA and SCL rise time iR 1 us SCL clock frequency ISCL 100 KHz Data-in setup time 'SU:DAT | 250 ns Start condition setup time 1SU:STA 4.7 Us Stop condition setup time SU:STO 4.7 us WRITE cycle time twRC 10 ms 23 8, 16 Meg x 64 SDRAM DIMMs 1 6 ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.MICRON TECHNOLOGY, INC. 8, 16 MEG x 64 SDRAM DIMMs NOTES 1. All voltages referenced to Vss. 2. This parameter is sampled. Vop = +3.3V; f = 1 MHz. 3. Ipp is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C < T, < 70C) is ensured. 6. An initial pause of 100us is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the 'REF refresh requirement is exceeded. AC characteristics assume 'T = Ins. 8. In addition to meeting the transition rate specifica- N tion, the clock and CKE must transit between Vin and Vit (or between Vit and Vi) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: oT] ~~ 10. HZ defines the time at which the output achieves the open circuit condition; it is not a reference to Von or Vou. The last valid data element will meet OH before going High-Z. 11. AC timing and Ipp tests have Vi. = OV and Vin = 3V, with timing referenced to 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid Vii or Vit levels. 13. Ipp specifications are tested after the device is properly initialized. 14. Timing actually specified by 'CKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by WR plus 'RP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. 18. 19. 20. 21. 22. 23 24. 25. 26. 27. 28. 29. 30. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. The Ipp current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. Address transitions average one transition every two clocks. CLK must be toggled a minimum of two times during this period. Based on 'CK = 100 MHz for -10E/-10C and 66 MHz for -662. 64MB module values will be half of those shown. . The SPD EEPROM WRITE cycle time (WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. Vin overshoot: Vin (MAX) = Vpp + 2V for a pulse width < 10ns, and the pulse width cannot be greater than one third of the cycle rate. Vi. undershoot: Vi. (MIN) = -2V for a pulse width < 10ns, and the pulse width cannot be greater than one third of the cycle rate. The clock frequency must remain constant during access or precharge states (READ, WRITE, including 'WR, and PRECHARGE commands). CKE may be used to reduce the data rate. Auto precharge mode only. The precharge timing budget (RP) begins ns after the first clock delay, after the last WRITE is executed. Precharge mode only. JEDEC and PC100 specify three clocks. These five parameters vary between speed grades and define the differences between the -8 SDRAM speeds: -8A, -8B, -8C, -8D and -8E. All other -8 timing parameters remain constant. 'CK = 10ns for -8E; CK = 15ns for -10. 8, 16 Meg x 64 SDRAM DIMMs ZMO6.p65 Rev. 3/99 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.: 8, 16 MEG x 64 MICRON SDRAM DIMMs SPD EEPROM tr tHIGH tr | tlow SCL | N y \ y \ OY LA K J a tSUSTA ee} THD:STA tHD:DAT ->| |=] tSU-DAT tsusTO SDA IN 1 / | tAA 'DH tBUF SDA OUT OH RXKRRERKRRERKEXRKERKRRERKRRERKR RY RK KKK Red UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL AA F 8, 16 Meg x 64 SDRAM DIMMs 1 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ZMO6.p65 Rev. 3/99 1999, Micron Technology, Inc.: 8, 16 MEG x 64 MICRON SDRAM DIMMs 168-PIN DIMM H-18 (64MB, 66 MHz) FRONT VIEW 5.256 (133.50) .125 (3.18) 5.244 (133.20) MAX .079 (2.00) R 1.255 (31.88 mS C T 245 (31.62) .700 (17.78) 118 (3.00) TYP (2X) oO Od 9 Oo} 9 fe} Od 9 mv [Too ms 118 (8.00) TYP TT Zz +H t | | .250 (6.35) TYP t 054 (1.37) _ __ 128 (8.25) py) 046 (1.17) 118 (3.00) =] J 4 1.661 (42.18) ___ 039 (1.00)8 (2x "116 (3.00) TYP 2.625 (66.68) 039 (1.00)R (2X) 939 (1.00) .050 (1.27) XL TYP TYP PIN 1 (PIN 85 ON BACKSIDE) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) H-21 (64MB, 100 MHz) FRONT VIEW 5.256 (133.50) .125 (3.18) 5.244 (133.20) MAX 079 (2.00) R 1.380 (35.05) Sy C 1.370 (34.80) .700 (17.78) 118 (3.00) TYP (2x) | oO} fe} a {e} | | fe} 118 (3.00) TYP I COT oT DT Yo ~~ t | | -250 (6.35) TYP | oats 25 .054 (1.37) -118 (3.00) > 1.661 (42.18) __,| 089 (1.00)R (2X _ seer 75-00) (2X) .046 (1.17) TYP 2.625 (66.68) 039 (1.00)R (2X) 939 (1.00) 050 (1.27) TYP TYP PIN 1 (PIN 85 ON BACKSIDE) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: 1. All dimensions ini ili MAX or typi : . imensions in inches (millimeters) , or typical where noted. 8, 16 Meg x 64 SDRAM DIMMs 1 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ZMO6.p65 Rev. 3/99 1999, Micron Technology, Inc.: 8, 16 MEG x 64 MICRON SDRAM DIMMs 168-PIN DIMM H-22 (128MB) FRONT VIEW 5.256 (133.50) 487 (4.00) 5244 (133.20) MAX 079 (2.00) R 1.380 (35.05) Sy C T3870 (34.80) 700 (17.78) 118 (3.00) TYP (2x) ol f) | oO fe) ol oO] | mo Oo i .118 (8.00) TYP ITI t | | 250 (6.35) TYP 054 (1.37) | 128 (3.25 046 (1.417 118 (3.00) =} |= \ 1.661 (42.18) __,. 039 (1.00)R (2x Fes o om) TYP 2.625 (66.68) 089 (1.00)R (2X) Q39 (4.00) 050 (1.27) TYP TYP XS PIN 1 (PIN 85 ON BACKSIDE) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) | MAX NOTE: _ 1. All dimensions in inches (millimeters) or typical where noted. MICRON TECHNOLOGY, INC. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http:/Awww.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 8, 16 Meg x 64 SDRAM DIMMs 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ZMO6.p65 Rev. 3/99 1999, Micron Technology, Inc.