©2009 Integrated Device Technology, Inc.
JANUARY 2009
DSC 2621/13
1
IDT71342SA/LA
HIGH SPEED
4K X 8 DUAL-PORT
STATIC RAM
WITH SEMAPHORE
Features
◆High-speed access
– Commercial: 20/25/35/45/55/70ns (max.)
– Industrial: 25/35/55ns (max.)
◆Low-power operation
– IDT71342SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
– IDT71342LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
Functional Block Diagram
2721 drw 01
I/O
CONTROL I/O
CONTROL
MEMORY
ARRAY
ADDRESS
DECODER ADDRESS
DECODER
R/W
R
CE
R
OE
R
I/O
0R
-I/O
7R
A
0R
-A
11R
R/W
L
CE
L
OE
L
A
0L
-A
11L
I/O
0L
-I/O
7L
SEMAPHORE
LOGIC
SEM
R
SEM
L
◆Fully asynchronous operation from either port
◆Full on-chip hardware support of semaphore signalling be-
tween ports
◆Battery backup operation—2V data retention (LA only)
◆TTL-compatible; single 5V (±10%) power supply
◆Available in plastic packages
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
2
2721 drw 02
IDT71342J
J52-1
(4)
52-Pin PLCC
Top View
(5)
INDEX
N/C
GND
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
8
9
10
11
12
13
14
15
16
17
18
19
20
474849505152
1
234567
33323130292827262524232221
SEM
L
A
0L
V
CC
OE
L
R/W
L
CE
R
R/W
R
CE
L
A
10L
A
11L
A
10R
A
11R
SEM
R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52 package body is approximately .79 in x .79 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configura tions(1,2,3)
I
NDEX
71342PF
PN64-1
(4)
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
I/O
6R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
OE
R
N/C
N/C
I/O
2L
A
0L
OE
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
N/C
N/C
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
3L
N/C
N/C
GND
N/C
N/C
A
10R
V
CC
CE
R
CE
L
N/C
N/C
A
10L
N/C
N/C
N/C
A
11L
A
11R
2721 drw 03
SEM
L
R/W
L
SEM
R
R/W
R
,
Description
The IDT71342 is a high-speed 4K x 8 Dual-Port Static RAM with full
on-chip hardware support of semaphore signalling between the two
ports.
The IDT71342 provides two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. To assist in
arbitrating between ports, a fully independent semaphore logic block
is provided. This block contains unassigned flags which can be
accessed by either side; however, only one side can control the flag at any
time. An automatic power down feature, controlled by CE and SEM,
permits the on-chip circuitry of each port to enter a very low standby power
mode (both CE and SEM HIGH).
Fabricated using IDT’s CMOS high-performance technology, this
device typically operates on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery. The device is packaged
in either a 64-pin TQFP or a 52-pin PLCC.
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
3
Absolute Maximum Ra tings(1)
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Maximum Operating
Temperature and Supply Voltage(1,2)
Recommended DC Oper ating
Conditions
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage (VCC = 5V ± 10%)
Symbol Rating Commercial
& Industrial Unit
V
TERM
(2)
Te rminal Vo l tag e
with Re s pe c t
to GND
-0.5 to +7.0 V
T
BIAS
Temperature
Under Bias -55 to +125
o
C
T
STG
Storage
Temperature -65 to +150
o
C
P
T
(3)
Power
Dissipation 1.5 W
I
OUT
DC Outp ut
Current 50 mA
2721 tbl 01
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Outp ut Ca p aci tanc e V
OUT
= 3dV 10 pF
2721 tbl 02
Grade Ambient
Temperature GND Vcc
Commercial 0
O
C to +70
O
C0V5.0V
+
10%
Industrial -40
O
C to +85
O
C0V5.0V
+
10%
2 721 t bl 03
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup pl y Voltag e 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input Hig h Vo ltage 2.2
____
6.0
(2)
V
V
IL
Input Lo w Vo ltage -0.5
(1)
____
0.8 V
2721 tbl 04
Symbol Parameter Test Conditions
71342SA 71342LA
UnitMin. Max. Min. Max.
|I
LI
| Inp ut Le akag e Curre nt
(1)
V
CC
= 5. 5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Outp ut Le ak age Curre nt CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Output Low Vo ltage I
OL
= 6mA
___
0.4
___
0.4 V
I
OL
= 8mA
___
0.5
___
0.5 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2721 t bl 05
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
71342X20
Com'l Only 71342X25
Com'l & Ind 71342X35
Com 'l & Ind
Symbol Parameter Test Condition Version Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Operating Current
(Bo th Ports Ac tive ) CE = V
IL
,
Outputs Disabled
SEM = Do n't Care
f = f
MAX
(3)
COM'L SA
LA 170
170 280
240 160
160 280
240 150
150 260
200 mA
IND SA
LA ____
____
____
____ 160
160 310
260 150
150 300
250
I
SB1
Standby Current
(Bo th Po rts - TTL
Le ve l Inp uts)
CE
L
and CE
R
= V
IH
SEM
L
= SEM
R
> V
IH
f = f
MAX
(3)
COM'L SA
LA 25
25 80
80 25
25 80
50 25
25 75
45 mA
IND SA
LA ____
____
____
____ 25
25 100
80 25
25 75
55
I
SB2
Standby Current
(One Po rt - TTL
Le ve l Inp uts)
CE
"A"
= V
IL
and CE
"B"
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L SA
LA 105
105 180
150 95
95 180
150 85
85 170
140 mA
IND SA
LA ____
____
____
____ 95
95 210
170 85
85 200
160
I
SB3
Ful l Standb y Curre nt (B oth
Ports -
CM OS Lev e l Inp uts )
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
SEM
L
= SEM
R
> V
CC
- 0.2V
f = 0
(3)
COM'L SA
LA 1.0
0.2 15
4.5 1.0
0.2 15
4.0 1.0
0.2 15
4.0 mA
IND SA
LA ____
____
____
____ 1.0
0.2 30
10 1.0
0.2 30
10
I
SB4
Full Stand by Current
(On e P ort -
CM OS Lev e l Inp uts )
One Po rt CE
"A"
or
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
SEM
L
= SEM
R
> V
CC
- 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
COM'L SA
LA 105
105 170
130 95
95 170
120 85
85 150
110 mA
IND SA
LA ____
____
____
____ 95
95 210
190 85
85 190
130
2721 tbl 06a
71342X45
Com'l O nly 71342X55
Com 'l & Ind 71342X70
Com 'l Onl y
Symbol Parameter T est Condition Version Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Operating Current
(Both Po rts Active) CE = V
IL
,
Outputs Disabled
SEM = Do n' t Care
f = f
MAX
(3)
COM'L SA
LA 140
140 240
200 140
140 240
200 140
140 240
200 mA
IND SA
LA ____
____
____
____ 140
140 270
220 ____
____
____
____
I
SB1
Standby Current
(Bo th P orts - TTL
Le v e l Inp uts )
CE
L
and CE
R
= V
IH
SEM
L
= SEM
R
> V
IH
f = f
MAX
(3)
COM'L SA
LA 25
25 70
40 25
25 70
40 25
25 70
40 mA
IND SA
LA ____
____
____
____ 25
25 70
50 ____
____
____
____
I
SB2
Standby Current
(One Po rt - TTL
Le v e l Inp uts )
CE
"A"
= V
IL
and CE
"B "
= V
IH
Active Port Outputs Disable d,
f=f
MAX
(3)
COM'L SA
LA 75
75 160
130 75
75 160
130 75
75 160
130 mA
IND SA
LA ____
____
____
____ 75
75 180
150 ____
____
____
____
I
SB3
Full S tand by Current (Bo th
Ports -
CMOS Le ve l Inp uts)
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0. 2V o r V
IN
< 0.2V
SEM
L
= SEM
R
> V
CC
- 0.2
V
f = 0
(3)
COM'L SA
LA 1.0
0.2 15
4.0 1.0
0.2 15
4.0 1.0
0.2 15
4.0 mA
IND SA
LA ____
____
____
____ 1.0
2.0 30
10 ____
____
____
____
I
SB4
Full Standby Current
(One Po rt -
CMOS Le ve l Inp uts)
One Po rt CE
"A"
or
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0. 2V o r V
IN
< 0.2V
SEM
L
= SEM
R
> V
CC
- 0. 2V
Active Port Outputs Disable d,
f = f
MAX
(3)
COM'L SA
LA 75
75 150
100 75
75 150
100 75
75 150
100 mA
IND SA
LA ____
____
____
____ 75
75 170
120 ____
____
____
____
2721 t bl 06 b
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
5
Data Retention Characteristics
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Data Rention Waveform
AC Test Conditions
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
Figure 1. AC Output Test Load
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
V
DR
V
CC
fo r Data Re tent ion
___
2.0
___
V
I
CCDR
Data Rete ntio n Curre nt V
CC
= 2V, CE > V
HC
COM' L. & IND.
___
100 1500 µA
t
CDR
(3)
Chip De se l e ct to Data Rete ntio n Time SEM > V
HC
V
IN
> V
HC
or < V
LC
0
___ ___
ns
t
R
(3)
Op e ratio n Re co v ery Time t
RC
(2) ___ ___
ns
2721 tbl 07
Inp ut Puls e Le v e ls
Inp ut Ris e /Fal l Time s
Inp ut Timing Re fere nc e Le ve ls
Outp ut Re fe re nc e Le ve l s
Outp ut Load
GND to 3 . 0V
5ns
1.5V
1.5V
Fi g ure s 1 and 2
2721 tbl 08
V
CC
CE
D
A
T
A
R
E
T
E
N
T
I
O
N
M
O
D
E
4.5V4.5V V
DR
>2V
V
DR
V
IH
V
IH
t
CDR
t
R
2721 drw 04
+5V
1250Ω
30pF
775Ω
DATA
OUT
2721 drw 05
,
1250Ω
5pF *
775Ω
DATA
OUT
2721 drw 06
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
6
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Ouput Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (SA or LA).
5. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
71342X20
Com'l Only 71342X25
Com 'l & In d 71342X35
Com 'l & In d
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cyc le Time 20 ____ 25 ____ 35 ____ ns
t
AA
Address Access Time ____ 20 ____ 25 ____ 35 ns
t
ACE
Chip Enable Access Time
(3)
____ 20 ____ 25 ____ 35 ns
t
AOE
Output Enable Acce ss Time ____ 15 ____ 15 ____ 20 ns
t
OH
Output Ho ld from Address Change 0 ____ 0____ 0____ ns
t
LZ
Output Low-Z Time
(1,2)
0____ 0____ 0____ ns
t
HZ
Output High-Z Time
(1,2)
____ 15 ____ 15 ____ 20 ns
t
PU
Chip Enab le to P owe r Up Time
(2)
0____ 0____ 0____ ns
t
PD
Chi p Dis ab le to Po wer Do wn Ti me
(2)
____ 50 ____ 50 ____ 50 ns
t
SOP
SEM Flag Update Pulse (OE or SEM)10 ____ 10 ____ 15 ____ ns
t
WDD
Write Pulse to Data Delay
(4)
____ 40 ____ 50 ____ 60 ns
t
DDD
Write Data Valid to Read Data Del ay
(4)
____ 30 ____ 30 ____ 35 ns
t
SAA
Semaphore Address Access Time ____ ____ ____ 25 ____ 35 ns
2721 tbl 09a
71342X45
Co m' l On l y 71342X55
Com 'l & In d 71342X70
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
tRC Re ad Cy c l e Ti me 45
____
55
____
70
____
ns
tAA Address Access Time
____
45
____
55
____
70 ns
tACE Chip Enab le Access Time
(3)
____
45
____
55
____
70 ns
tAOE Outp ut Enab le A cce s s Time
____
25
____
30
____
40 ns
tOH Outp ut Hold from Address Change 0
____
0
____
0
____
ns
tLZ Output Lo w-Z Tim e
(1,2)
5
____
5
____
5
____
ns
tHZ Outp ut Hi g h-Z Tim e
(1,2)
____
20
____
25
____
30 ns
tPU Chip Enab le to Po wer Up Time
(2)
0
____
0
____
0
____
ns
tPD Chi p Disab le to Po we r Down Time
(2)
____
50
____
50
____
50 ns
tSOP SEM Flag Update Pulse (OE or SEM)15
____
20
____
20
____
ns
tWDD Write Pulse to Data Delay
(4)
____
70
____
80
____
90 ns
tDDD Write Data Valid to Re ad Data Del ay
(4)
____
45
____
55
____
70 ns
tSAA Semaphore Address Access Time
____
45
____
55
____
70 ns
2721 tbl 09b
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
7
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. CE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
Timing Waveform of Write with Port-to-Port Read(2,3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, unless otherwise noted.
4. Start of valid data depends on which timing becomes effective last; tAOE, tACE, or tAA
5. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for SRAM Address Access and tSAA is for Semaphore Address Access.
t
AA or
t
SAA
ADDRESS
DATA
OUT
PREVIOUS DATA VALID DATA VALID
t
OH
t
OH
t
RC
2721 drw 07
2721 drw 08
CE or SEM
DATA
OUT
VALID DATA
t
PD
t
AOE
t
ACE
OE
t
HZ
t
LZ
t
LZ
t
PU
50%50%
I
CC
I
SB
CURRENT
t
HZ
t
SOP
(5)
t
SOP
(1)
(1)
(4) (2)
(2)
(4)
2721 drw 09
R/W
"A"
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
(1)
t
DH
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (SA or LA).
Symbol Parameter
71342X20
Co m' l On l y 71342X25
Com 'l & In d 71342X35
Com'l & Ind
UnitMin. Max. Min. Max. Min. Max.
WR I T E C YC L E
t
WC
Write Cy c le Tim e 20
____
25
____
35
____
ns
t
EW
Chip Enable to End -o f-Write
(3)
15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Puls e Width 15
____
20
____
25
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End -of-Write 15
____
15
____
20
____
ns
t
HZ
Outp ut Hig h-Z Time
(1,2)
____
15
____
15
____
20 ns
t
DH
Da ta Hol d Ti m e
(4)
0
____
0
____
3
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
15
____
20 ns
t
OW
Outp ut Activ e fro m End -o f-Write
(1,2,4)
3
____
3
____
3
____
ns
t
SWR
SEM Flag Write to Read Time 10
____
10
____
10
____
ns
t
SPS
SEM Flag Co nte ntion Windo w 10
____
10
____
10
____
ns
2 721 tbl 10a
Symbol Parameter
71342X45
Co m' l On l y 71342X55
Com 'l & In d 71342X70
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WR I T E C YC L E
t
WC
Write Cy c le Tim e 45
____
55
____
70
____
ns
t
EW
Chip Enable to End -o f-Write
(3)
40
____
50
____
60
____
ns
t
AW
Address Valid to End-of-Write 40
____
50
____
60
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Puls e Width 40
____
50
____
60
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End -of-Write 20
____
25
____
30
____
ns
t
HZ
Outp ut Hig h-Z Time
(1,2)
____
20
____
25
____
30 ns
t
DH
Da ta Hol d Ti m e
(4)
3
____
3
____
3
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
20
____
25
____
30 ns
t
OW
Outp ut Activ e fro m End -o f-Write
(1,2,4)
3
____
3
____
3
____
ns
t
SWR
SEM Flag Write to Read Time 10
____
10
____
10
____
ns
t
SPS
SEM Flag Co nte ntion Windo w 10
____
10
____
10
____
ns
2721 tbl 10b
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
9
CE or SEM
2721 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
WP
t
DH
DATA
OUT
t
WZ
(4) (4)
t
OW
OE
t
HZ
t
LZ
t
HZ
(9)
(6)
(7)
(2)
(3)
(7)
(7)
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/WW
WW
W CONTROLLED TIMING(1,5,8)
Timing Wavef orm of Write Cycle No . 2, CE Controlled Timing(1, 5 )
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of either CE or SEM = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal ( CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t WP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE =V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
2721 drw 11
R/W
t
WC
ADDRESS
DATA
IN
CE or SEM
t
DW
t
WR
t
DH
t
EW
t
AS
t
AW
(9)
(6) (2) (3)
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
10
Timing Wa veform of Semaphore Read After Write Timing, Either Side(1)
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
NOTES:
1. D0R = D0L = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
3. This parameter is measured from the point where R/W "A" or SEM "A" goes HIGH until R/W "B" or SEM "B" goes HIGH.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
Timing Waveform of Semaphore Condition(1,3,4)
A
0
-A
2
VALID ADDRESSVALID ADDRESS
DATA
IN
VALID DATA
OUT
VALID
SEM
R/W
OE
DATA
0
t
AW
t
EW
t
WR
t
DW
t
DH
t
WP
t
AS
t
SWRD
t
SOP
t
AOE
t
ACE
t
SAA
t
OH
t
SOP
Test Cycle
(Read Cycle)
Write Cycle
2721 drw 12
A0"A" -A2"A"
tSPS
R/W"A"
SEM"A"
SIDE(2) "A"
A0"B" -A2"B"
R/W"B"
SEM"B"
SIDE(2) "B"
MATCH
MATCH
2721 drw 13
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
11
FUNCTIONAL DESCRIPTION
The IDT71342 is an extremely fast Dual-Port 4K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an example,
the semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on
the left port in no way slows the access time of the right port. Both ports
are identical in function to standard CMOS Static RAMs and can be
read from or written to at the same time, with the only possible conflict
arising from the simultaneous writing of, or a simultaneous READ/
WRITE of, a non-semaphore location. Semaphores are protected
against such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion of the
Dual-Port SRAM. These devices have an automatic power-down
feature controlled by CE, the Dual-Port SRAM enable, and SEM, the
semaphore enable. The CE and SEM pins control on-chip power down
circuitry that permits the respective port to go into standby mode when
not selected. This is the condition which is shown in Truth Table I
where CE and SEM are both HIGH.
Systems which can best use the IDT71342 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT71342’s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT71342 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or
token, from one port to the other to indicate that a shared resource is
in use. The semaphores provide a hardware assist for a use assignment
method called “Token Passing Allocation.” In this method, the state of
a semaphore latch is used as a token indicating that a shared resource
is in use. If the left processor wants to use this resource, it requests the
token by setting the latch. This processor then verifies its success in
setting the latch by reading it. If it was successful, it proceeds to
assume control over the shared resource. If it was not successful in
setting the latch, it determines that the right side processor had set the
latch first, has the token and is using the shared resource. The left
processor can then either repeatedly request that semaphore’s status
or remove its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the set and
test sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT71342 in a separate
memory space from the Dual-Port RAM. This address space is
accessed by placing a LOW input on the SEM pin (which acts as a chip
select for the semaphore flags) and using the other control pins
(Address, OE, and R/W) as they would be used in accessing
a standard Static RAM. Each of the flags has a unique address
which can be accessed by either side through the address pins A0–A2.
When accessing the semaphores, none of the other address pins has
any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW
level is written into an unused semaphore location, that flag will be set
to a zero on that side and a one on the other (see Truth Table II). That
semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thorough
discussion on the use of this feature follows shortly.) A zero written into
the same location from the other side will be stored in the semaphore
request latch for that side until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data bits
so that a flag that is a one reads as a one in all data bits and a flag
containing a zero reads as all zeros. The read value is latched into one
side’s output register when that side’s semaphore select (SEM) and
output enable (OE) signals go active. This serves to disallow the
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
A sequence of WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as a one, a fact which the processor will verify by the
subsequent read (see Truth Table II). As an example, assume a
processor writes a zero in the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the resource
in question. Meanwhile, if a processor on the right side attempts to
write a zero to the same semaphore flag it will fail, as will be verified
by the fact that a one will be read from that semaphore on the right side
during a subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 3. Two semaphore
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
12
Truth Table I — Non-Contention Read/Write Control(2)
request latches feed into a semaphore flag. Whichever latch is first to
present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will now stay LOW until its
semaphore request latch is written to a one. From this it is easy to
understand that, if a semaphore is requested and the processor which
requested it no longer needs the resource, the entire can hang up until
a one is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to
a resource is secure. As with any powerful programming technique, if
semaphores are misused or misinterpreted, a software error can
easily happen. Code integrity is of the utmost importance when
semaphores are used instead of slower, more restrictive hardware
intensive schemes.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power up. Since any semaphore
request flag which contains a zero must be reset to a one, all
Truth Table II — Example Semaphore Procurement Sequence(1,2,3)
NOTE:
1. AOL = A11L ¹ A0R - A11R.
2. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z" = High-Impedance.
NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
Left or Right Port
(1)
R/WCE SEM OE D
0-7
Function
X H H X Z Po rt Dis ab l e d and in P ower Do wn Mo d e
HHLLDATA
OUT
Data in Semaphore Flag Output on Port
X X X H Z Output Disabled
↑HLXDATA
IN
Port Data Bit D
0
Writte n Into S em apho re Fl ag
HLHLDATA
OUT
Data in Memory Output on Po rt
LLHXDATA
IN
Da ta o n P ort Writte n Into Me mo ry
XLLX
____
No t All o we d
2721 tbl 1
1
Functions D
0
- D
15
Left D
0
- D
15
Ri ght S tatus
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Po rt Write s "0" to Se map ho re 1 0 No chang e . Le ft po rt has no write ac ce ss to se map ho re
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
2721 tbl 12
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
13
SEMAPHORE
REQUEST FLIP FLOP
DQ
SEMAPHORE
REQUEST FLIP FLOP
QD
WRITE
D
0
SEMAPHORE
READ SEMAPHORE
READ
D
0
WRITE
RPORT
LPORT
2721 drw 14
,
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores–Some
examples
Perhaps the simplest application of semaphores is their application
as resource markers for the IDT71342’s Dual-Port RAM. Say the 4K
x 8 RAM was to be divided into two 2K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of the memory.
To take a resource, in this example the lower 2K of Dual-Port RAM,
the processor on the left port could write and then read a zero into
Semaphore 0. If this task were successfully completed (a zero was
read back rather than a one), the left processor would assume control
of the lower 2K. Meanwhile, the right processor would attempt to
perform the same function. Since this processor was attempting to
gain control of the resource after the left processor, it would read back
a one in response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain control of the
second 2K section by writing, then reading a zero into Semaphore 1.
If it succeeded in gaining control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a similar task with Semaphore 0, this protocol would allow the
two processors to swap 2K blocks of Dual-Port RAM with each other.
The blocks do not have to by any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port RAM or other shared resources into eight parts. Semaphores
can even be assigned different meanings on different sides rather than
being given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices had determined
which memory area was “off limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continuously
without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby
guaranteeing a consistent data structure.
Figure 3. IDT71342 Semaphore Logic
6.42
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore Industrial and Commercial Temperature Ranges
14
Ordering Information
2721 drw 15
X
X
X
X
A
9
9
9
A
A
D
evice Type Power Speed Package Process/
Temperature
Range
Blank
I
J
PF
20
25
35
45
55
70
SA
LA
71342
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
Speed in nanoseconds
Standard Power
Low Power
32K (4K x 8-Bit) Dual-Port RAM w/ Semaphore
Commercial Only
Commercial & Industrial
Commercial & Industrial
Commercial Only
Commercial & Industrial
Commercial Only
,
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
1/12/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
6/9/99: Changed drawing format
10/1/99: Added Industrial Temperature Ranges and removed corresponding notes
11/10/99: Replaced IDT logo
12/22/99: Page 1 Made corrections to drawing
6/26/00: Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±500mV to 0mV in notes
1/12/00: Pages 1 and 2 Moved "Description" to page 2 and adjusted page layouts
Page 1 Added "(LA only)" to paragraph
Page 2 Fixed J52 package description in notes
Page 8 Replaced bottom table with correct 10b table
01/29/09: Page 14 Removed "IDT" from orderable part number
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