H D tl 4 HC4 5 4 3 @ BCD-to-Seven Segment Latch/Decoder/Driver This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 output drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (Ph) controls the polarity of the 7 segment outputs. When Ph is low the outputs are true 7 segment, and when Ph is high the outputs are inverted 7 segment. When the Phase input is driven by a liquid crystal display (LCD) backplane waveform the segment pins output the correct segment wave- form for proper LCD AC drive voltages. In addition a Blanking input (BI) is provided, which will blank the display. @ PIN ARRANGEMENT Latch ot 16) Vee Phase {e}~ Ph ri] c Blanking C}H BI bb iol> FEATURES mele i High Speed Operation: tog (A, B, C, D to a~g)=33ns typ. (Cy =50pF) (Top View) @ High Output Current: Fanout of 10 LSTTL Loads @ Wide Operating Voltage: V.-=2~6V Low Input Current: 1uA max. @ Low Quiescent Supply Current: /g (static)=4uA max. (Ta=25C) @ FUNCTION TABLE Inputs Outputs LD) BI |Ph*;}/D|C/]Bi]A]aib|ec/]dt|el | g | Display x H | On ee ee Oe ee ee Blank H L L/LIJL]|L]|LIH|H]|H}|HY|HI] HY] L 0 H L L L{/L]|L|H|L]|H]|H|LILYI LIL 1 H L L{L]|LITH]|L/]H;H]|LIH]|H]|LIH 2 H L L |L]|bL]H|A}]H]|H;|H] HI] LILIA 3 H L L}/LJ/H/]LILIL]/H|H;]| LILI HY] HAH 4 H L L}|L/H;/|L]}H]H]L/|H}]|H]|L]/H/H 5 H L L |L}]}H/;}|H}]}LI]H}L|H}]H| HI] HI] H 6 H L L ]|L]H;H!]}H}]H]AHT|H] LILI LIL 7 H L L/H;I}L/LI]LI]AH}]H|H]H]H)HIH 8 H L L |H|]|L]|L}]H!]H}|H|H|H]| LI] HI] H 9 H L L|HI]LI HI LILY Ly Ly] Ly Ly Lye Blank H L L/H;/L/H/H;| LIL] L]|L|L|L|Lly Blank H 'L L|H]|H;|LILILILYLyILILI LiL Blank H L L H|/H|LI]H]|LIJL}LI|LY]YLY]LyIL Blank H L L|H]|H;|H;I|LIL]ILYILI|LyLy Lil Blank H L L}|H;/|H/H]H/ILYILYILI LILI LIL Blank L L L x | x | x lx OK * * For liquid crystal readouts, apply a square wave to Ph For common cathode LED readouts, select Ph- [.. For common anode LED readouts, select Ph =H * * : Depends upon the BCD coder previously applied when LD= H Er 372HD74HC4543 Doe Phase Blanking Mi LOGIC DIAGRAM -t---- 1.1 an bo ----1,1----, | | | | | | | | | | | | L LL Sys = 1 Fo LL ip 373 B- Ix | | an Latch DisableHD74HC4543 i DC CHARACTERISTICS Te =25C Ta =~-40~ +85C . Item Symbol Test Conditions - - Unit Vec( V) min typ max min max 2.0 1.5 - _ 1.5 - Vin 4.5 3.15 _ | 3.15 _ v Input Volt 6.0 4.2 - _ 4.2 _ mpur womage 2.0 | ] os| | 035 Vin 4.5 ~ _ 1.35 | 1.35 Vv 6.0 _ _ 1.8 - 1.8 2.0 1.9] 2.0 _ 1.9 _ 4.5 Ton =~ 20KA 4.4] 4.5 _ 4.4 _ Vou 6.0 Via=Vin or Vie 5.9] 6.0 _ 5.9 = v 4.5 Ton =4mA 4.18 _ ~ | 4.13 - Output Volt 6.0 Ton=5.2mA 5.68 _ | 5.63 _ epee EE 2.0 foo] oir] | 01 4.5 Tor =20KA | 0.0 0.1 - 0.1 Vou 6.0 Via=Vin or Vin 0.0 0.1 0.1 Vv 4.5 To. =4mA = | 0.26 | 0.33 6.0 Tor =5.2mA = | 0.26 - | 0.33 Input Current Dn 6.0 Vie=Vec or GND _ _ +0.1 | +1.0] #A Quiescent Supply Current Tec 6.0 Vis=Vec or GND, Ior= OKA - _ 4.0 _ 40 | HA Hi AC CHARACTERISTICS (Cz1=50pF, Input -=;=6ns) .. Ta=25C Ta=40~ + 85C . Item Symbol Test Conditions - - Unit Vece(V) min. | typ. | max. | min. | max. 2.0 - _ 400 _ 500 2PLH = 45 A,B, CorDtoa~g _ 33 80 _ 100 ns t PHL 6.0 - _ 68 _ 86 2.0 _ _ 300 - 380 tele . i 45 Blanking to a~g _ 22 60 _ 76 ns > tion Delay T: mm 60 {[ 52] 66 ropagation Delay Tim pag vanme 2.0 | [300 | | 380 tpLy 4.5 Phase toa~g _ 18 60 _ 76 ns t PHL 6.0 - - 52 - 66 2.0 - - 400 _ 500 tpLy . : 45 Latch Disable to a~ g _ 35 80 _ 100 ns ve 6.0 -~T- f ewl | 86 2.0 80 _ _ 100 - Pulse Width te 45 16 5 - 20 _ ns 6.0 14 - - 17 > 2.0 100 _ - 125 - Setup Time bs 45 20 2 _ 25 ~ ns 6.0 17 _ - 21 - 2.0 50 _ - 65 _ Hold Time th 45 10 1 - 13 _ ns 6.0 9 - - ll 2.0 - - 75 - 95 : . trLy Output Rise/Fall Time 45 _ 3 15 _ 19 ns tTHL 7 6.0 | - _ 13 - 16 Input Capacitance Cin _ | _ 5 10 _ 10 pF 374