74ALVC164245 16-bit dual supply translating transceiver; 3-state Rev. 10 -- 9 April 2019 Product data sheet 1. General description The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) VCC(A) (except in suspend mode). 2. Features and benefits * * * * * * * * * * 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range: * 3 V port (VCC(A)): 1.5 V to 3.6 V * 5 V port (VCC(B)): 1.5 V to 5.5 V CMOS low power consumption Direct interface with TTL levels Control inputs voltage range from 2.7 V to 5.5 V Inputs accept voltages up to 5.5 V High-impedance outputs when VCC(A) or VCC(B) = 0 V Complies with JEDEC standard JESD8-B/JESD36 ESD protection: * HBM JESD22-A114F exceeds 2000 V * MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC164245DL -40 C to +125 C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 74ALVC164245DGG -40 C to +125 C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 4. Functional diagram 2DIR 1DIR 2OE 1OE 2A0 1A0 1B0 1A1 2B0 2A1 1B1 1A2 2B1 2A2 1B2 1A3 2B2 2A3 1B3 1A4 2B3 2A4 1B4 1A5 2B4 2A5 1B5 1A6 2B5 2A6 1B6 2B6 2A7 1A7 1B7 2B7 001aaa789 Fig. 1. Logic symbol 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 2 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 1OE 1DIR 2OE 2DIR 1A0 G3 3EN1[BA] 3EN2[AB] G6 6EN4[BA] 6EN5[AB] 1B0 1 2 1A1 1B1 1A2 1B2 1A3 1B3 1A4 1B4 1A5 1B5 1A6 1B6 1A7 1B7 2A0 2B0 4 5 2A1 2B1 2A2 2B2 2A3 2B3 2A4 2B4 2A5 2B5 2A6 2B6 2B7 2A7 001aaa790 Fig. 2. IEC logic symbol 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 3 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 5. Pinning information 5.1. Pinning 1DIR 1 48 1OE 1B0 2 47 1A0 1B1 3 46 1A1 GND 4 45 GND 1B2 5 44 1A2 1B3 6 43 1A3 VCC(B) 7 42 VCC(A) 1B4 8 41 1A4 1B5 9 40 1A5 GND 10 39 GND 1B6 11 38 1A6 1B7 12 37 1A7 74ALVC164245 2B0 13 36 2A0 2B1 14 35 2A1 GND 15 34 GND 2B2 16 33 2A2 2B3 17 32 2A3 VCC(B) 18 31 VCC(A) 2B4 19 30 2A4 2B5 20 29 2A5 GND 21 28 GND 2B6 22 27 2A6 2B7 23 26 2A7 2DIR 24 25 2OE 001aab037 Fig. 3. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1DIR, 2DIR 1, 24 direction control input 1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7 2, 3, 5, 6, 8, 9, 11, 12 data input/output 2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7 13, 14, 16, 17, 19, 20, 22, 23 data input/output GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC(B) 7, 18 supply voltage B (5 V bus) 1OE, 2OE 48, 25 output enable input (active LOW) 1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7 47, 46, 44, 43, 41, 40, 38, 37 data input/output 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7 36, 35, 33, 32, 30, 29, 27, 26 data input/output VCC(A) 31, 42 supply voltage A (3 V bus) 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 4 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. Inputs Outputs nOE nDIR nAn nBn L L nAn = nBn inputs L H inputs nBn = nAn H X Z Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC(B) supply voltage B VCC(B) VCC(A) -0.5 +6.0 V VCC(A) supply voltage A VCC(B) VCC(A) -0.5 +4.6 V IIK input clamping current VI < 0 V -50 - VI input voltage -0.5 +6.0 VI/O input/output voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage output HIGH or LOW [1] -0.5 output 3-state [1] -0.5 +6.0 V - 50 mA 100 mA [1] -0.5 IO(sink/source) output sink or source current V VCC + 0.5 V - VO = 0 V to VCC mA 50 mA VCC + 0.5 V ICC supply current - IGND ground current -100 - mA Tstg storage temperature -65 +150 C Tj junction temperature [2] - +150 C Ptot total power dissipation [3] - 500 mW [1] [2] [3] Tamb = -40 C to +125 C The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. Above 60 C the value of Ptot derates linearly with 5.5 mW/K. 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 5 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC(B) VCC(A) Min Typ Max Unit maximum speed performance 2.7 - 5.5 V low-voltage applications 1.5 - 5.5 V maximum speed performance 2.7 - 3.6 V low-voltage applications 1.5 - 3.6 V VCC(B) VCC(A) supply voltage B VCC(B) VCC(A) supply voltage A VI input voltage control inputs: nOE and nDIR 0 - 5.5 V VI/O input/output voltage nAn port 0 - VCC(A) V nBn port 0 - VCC(B) V VO output voltage nAn port 0 - VCC(A) V nBn port 0 - VCC(B) V -40 - +125 C VCC(A) = 2.7 V to 3.0 V 0 - 20 ns/V VCC(A) = 3.0 V to 3.6 V 0 - 10 ns/V VCC(B) = 3.0 V to 4.5 V 0 - 20 ns/V VCC(B) = 4.5 V to 5.5 V 0 - 10 ns/V Tamb ambient temperature t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions -40 C to +85 C -40 C to +125 C Unit Min Typ [1] Max Min Max 2.0 - - 2.0 - V 2.0 - - 2.0 - V [2] 1.7 - - 1.7 - V VCC(B) = 4.5 V to 5.5 V [2] - - 0.8 - 0.8 V VCC(B) = 3.0 V to 3.6 V [2] - - 0.7 - 0.7 V - - 0.8 - 0.8 V - - 0.7 - 0.7 V nBn port VCC(B) = 3.0 V to 5.5 V [2] nAn port, nOE and nDIR VCC(A) = 3.0 V to 3.6 V VCC(A) = 2.3 V to 2.7 V VIL LOW-level input voltage nBn port nAn port, nOE and nDIR VCC(A) = 3.0 V to 3.6 V VCC(A) = 2.3 V to 2.7 V 74ALVC164245 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 6 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state Symbol Parameter VOH Conditions -40 C to +85 C -40 C to +125 C Unit Min Typ [1] Max Min Max nBn port; VI = VIH or VIL HIGH-level output voltage IO = -24 mA; VCC(B) = 4.5 V VCC(B) - 0.8 - - VCC(B) - 1.2 - V IO = -12 mA; VCC(B) = 4.5 V VCC(B) - 0.5 - - VCC(B) - 0.8 - V IO = -18 mA; VCC(B) = 3.0 V VCC(B) - 0.8 - - VCC(B) - 1.0 - V IO = -100 A; VCC(B) = 3.0 V VCC(B) - 0.2 VCC(B) - VCC(B) - 0.3 - V IO = -24 mA; VCC(A) = 3.0 V VCC(A) - 0.7 - - VCC(A) - 1.0 - V IO = -100 A; VCC(A) = 3.0 V VCC(A) - 0.2 - - VCC(A) - 0.3 - V IO = -12 mA; VCC(A) = 2.7 V VCC(A) - 0.5 - - VCC(A) - 0.8 - V IO = -8 mA; VCC(A) = 2.3 V VCC(A) - 0.6 - - VCC(A) - 0.6 - V IO = -100 A; VCC(A) = 2.3 V VCC(A) - 0.2 VCC(A) - VCC(A) - 0.3 - V nBn port; VI = VIH or VIL LOW-level output voltage IO = 24 mA; VCC(B) = 4.5 V - - 0.55 - 0.80 V IO = 12 mA; VCC(B) = 4.5 V - - 0.40 - 0.60 V IO = 100 A; VCC(B) = 4.5 V - - 0.20 - 0.30 V IO = 18 mA; VCC(B) = 3.0 V - - 0.55 - 0.80 V IO = 100 A; VCC(B) = 3.0 V - - 0.20 - 0.30 V IO = 24 mA; VCC(A) = 3.0 V - - 0.55 - 0.80 V IO = 100 A; VCC(A) = 3.0 V - - 0.20 - 0.30 V IO = 12 mA; VCC(A) = 2.7 V - - 0.40 - 0.60 V IO = 12 mA; VCC(A) = 2.3 V - - 0.60 - 0.60 V IO = 100 A; VCC(A) = 2.3 V - - 0.20 - 0.20 V - 0.1 5 - 10 A - 0.1 10 - 20 A nAn port; VI = VIH or VIL VOL nAn port; VI = VIH or VIL II input leakage current IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND ICC supply current VI = VCC or GND; IO = 0 A - 0.1 40 - 80 A ICC additional per control pin; VI = VCC - 0.6 V; [4] supply current IO = 0 A - 5 500 - 5000 A CI input capacitance - 4.0 - - - pF CI/O input/output capacitance - 5.0 - - - pF [1] [2] [3] [4] VI = 5.5 V or GND nAn and nBn port [3] All typical values are measured at VCC(B) = 5.0 V, VCC(A) = 3.3 V and Tamb = 25 C. If VCC(A) < 2.7 V, the switching levels at all inputs are not TTL compatible. For transceivers, the parameter IOZ includes the input leakage current. VCC(A) = 2.7 V to 3.6 V: other inputs at VCC(A) or GND; VCC(B) = 4.5 V to 5.5 V: other inputs at VCC(B) or GND. 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 7 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; for test circuit see Fig. 6. Symbol Parameter tpd propagation delay Conditions -40 C to +85 C Min Typ [1] Max Min Max VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V to 3.6 V 1.5 3.3 7.6 1.5 9.5 ns VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V 1.0 3.0 5.9 1.0 7.5 ns VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V 1.0 2.9 5.8 1.0 7.5 ns VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V to 3.6 V 1.0 3.0 7.6 1.0 9.5 ns VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V 1.0 4.3 6.7 1.0 8.5 ns VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V 1.2 2.5 5.8 1.2 7.5 ns VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V to 3.6 V 1.5 4.1 11.5 1.5 14.5 ns VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V 1.5 3.6 9.2 1.5 11.5 ns VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V 1.0 3.2 8.9 1.0 12.0 ns VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V to 3.6 V 1.5 4.6 12.3 1.5 15.5 ns VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V 1.5 4.3 9.3 1.5 12.0 ns VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V 1.0 3.2 8.9 1.0 11.5 ns VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V to 3.6 V 2.0 2.7 10.5 2.0 13.5 ns VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V 2.5 4.6 9.0 2.5 11.5 ns VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V 2.1 4.9 8.6 2.1 11.0 ns VCC(A) = 2.3 V to 2.7 V; VCC(B) = 3.0 V to 3.6 V 1.0 2.7 9.3 1.0 12.0 ns VCC(A) = 2.7 V; VCC(B) = 4.5 V to 5.5 V 1.5 3.5 9.0 1.5 11.5 ns VCC(A) = 3.0 V to 3.6 V; VCC(B) = 4.5 V to 5.5 V 2.0 3.2 8.6 2.0 11.0 ns nAn to nBn; see Fig. 4 [2] nBn to nAn; see Fig. 4 ten enable time [2] nOE to nBn; see Fig. 5 [3] nOE to nAn; see Fig. 5 tdis disable time [3] nOE to nBn; see Fig. 5 [4] nOE to nAn; see Fig. 5 74ALVC164245 Product data sheet -40 C to +125 C Unit [4] All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 8 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state Symbol Parameter CPD power dissipation capacitance Conditions -40 C to +85 C Min Typ [1] Max Min Max outputs enabled - 30 - - - pF outputs disabled - 15 - - - pF outputs enabled - 40 - - - pF outputs disabled - 5 - - - pF 5 V port: nAn to nBn; VI = GND to VCC; VCC(B) = 5 V; VCC(A) = 3.3 V [5] 3 V port: nBn to nAn; VI = GND to VCC; VCC(B) = 5 V; VCC(A) = 3.3 V [1] [2] [3] [4] [5] -40 C to +125 C Unit [5] All typical values are measured at nominal voltage for VCC(B) and VCC(A) and at Tamb = 25 C. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in W). 2 2 PD = CPD x VCC x fi x N + (CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 (CL x VCC x fo) = sum of outputs. 10.1. Waveforms and test circuit VI nAn, nBn input VM GND tPHL tPLH VOH nBn, nAn output VM VOL 001aaa792 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 4. Input (nAn, nBn) to output (nBn, nAn) propagation delays 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 9 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs enabled outputs disabled mna362 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with output load. Fig. 5. 3-state enable and disable times Table 8. Measurement points Direction Supply voltage VCC(A) Input VCC(B) VI Output VM VM VX VY VOH(B) - 0.3 V nAn port to nBn port 2.3 V to 2.7 V 2.7 V to 3.6 V VCC(A) 0.5 x VCC(A) 1.5 V VOL(B) + 0.3 V nBn port to nAn port 2.3 V to 2.7 V 2.7 V to 3.6 V 2.7 V 1.5 V 0.5 x VCC(A) VOL(A) + 0.15 V VOH(A) - 0.15 V nAn port to nBn port 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V 1.5 V 0.5 x VCC(B) 0.2 x VCC(B) 0.8 x VCC(B) nBn port to nAn port 2.7 V to 3.6 V 4.5 V to 5.5 V 3.0 V 1.5 V 1.5 V VOL(A) + 0.3 V VOH(A) - 0.3 V VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times. Fig. 6. Test circuit for measuring switching times Table 9. Test data Direction Supply voltage Load VEXT VCC(A) VCC(B) CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ nAn port to nBn port 2.3 V to 2.7 V 2.7 V to 3.6 V 50 pF 500 open GND 2 x VCC nBn port to nAn port 2.3 V to 2.7 V 2.7 V to 3.6 V 50 pF 500 open GND 6.0 V nAn port to nBn port 2.7 V to 3.6 V 4.5 V to 5.5 V 50 pF 500 open GND 2 x VCC nBn port to nAn port 2.7 V to 3.6 V 4.5 V to 5.5 V 50 pF 500 open GND 6.0 V 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 10 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 11. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3 ) pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 Fig. 7. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Package outline SOT370-1 (SSOP48) 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 11 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit max nom min mm A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z 0.8 8 0.4 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 Fig. 8. References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Package outline SOT362-1 (TSSOP48) 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 12 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC164245 v.10 20190409 Product data sheet - Modifications: * 74ALVC164245 v.9 20181112 Modifications: * * * * 74ALVC164245 v.9 Table 6: Typo corrected for VOL(max) at VCC(B) = 4.5 V. Product data sheet - 74ALVC164245 v.8 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74ALVC164245BX (SOT1134-2) removed. Package outline drawing SOT362-1 updated. 74ALVC164245 v.8 20120315 Modifications: * 74ALVC164245 v.7 20111117 Modifications: * 74ALVC164245 v.6 20110616 74ALVC164245 v.5 20100413 74ALVC164245 v.4 Product data sheet - 74ALVC164245 v.7 For type number 74ALVC164245BX the sot code has changed to SOT1134-2. - 74ALVC164245 v.6 Product data sheet - 74ALVC164245 v.5 Product data sheet - 74ALVC164245 v.4 20081111 Product data sheet - 74ALVC164245 v.3 74ALVC164245 v.3 20040914 Product data sheet - 74ALVC164245 v.2 74ALVC164245 v.2 20040601 Product data sheet - 74ALVC164245 v.1 74ALVC164245 v.1 19980826 Product specification - - 74ALVC164245 Product data sheet Product data sheet Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 13 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state 14. 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Right to make changes -- Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74ALVC164245 Product data sheet Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the Nexperia product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). Nexperia does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 14 / 15 74ALVC164245 Nexperia 16-bit dual supply translating transceiver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 4 6. Functional description................................................. 5 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................6 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit........................................ 9 11. Package outline........................................................ 11 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 (c) Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 9 April 2019 74ALVC164245 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 -- 9 April 2019 (c) Nexperia B.V. 2019. All rights reserved 15 / 15