INTEGRATED CIRCUITS DATA SHEET TDA8358J Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier Product specification Supersedes data of 1999 Dec 22 2002 Sep 25 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J FEATURES GENERAL DESCRIPTION * Few external components required The TDA8358J is a power circuit for use in 90 and 110 colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages. * High efficiency fully DC-coupled vertical bridge output circuit * Vertical flyback switch with short rise and fall times * Built-in guard circuit * Thermal protection circuit * Improved EMC performance due to differential inputs The east-west output stage is able to supply the sink current for a diode modulator circuit. * East-west output stage. The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP supply voltage 7.5 12 18 V VFB flyback supply voltage 2 x VP 45 66 V Iq(P)(av) average quiescent supply current during scan - 10 15 mA Iq(FB)(av) average quiescent flyback supply current during scan - - 10 mA Ptot total power dissipation - - 15 W Inputs and outputs Vi(p-p) input voltage (peak-to-peak value) - 1000 1500 mV Io(p-p) output current (peak-to-peak value) - - 3.2 A - - 1.8 A Flyback switch Io(peak) t 1.5 ms maximum (peak) output current East-west amplifier Vo output voltage - - 68 V VI(bias) input bias voltage 2 - 3.2 V Io output current - - 750 mA Thermal data; in accordance with IEC 747-1 Tstg storage temperature -55 - +150 C Tamb ambient temperature -25 - +85 C Tj junction temperature - - +150 C 2002 Sep 25 2 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J ORDERING INFORMATION PACKAGE TYPE NUMBER TDA8358J NAME DESCRIPTION VERSION DBS13P plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6 BLOCK DIAGRAM VP GUARD COMP handbook, full pagewidth 11 13 COMP. CIRCUIT VFB 3 9 GUARD CIRCUIT M5 D2 D3 M2 Vi(p-p) D1 VI(bias) 10 OUTA INA 1 M4 0 Vi(p-p) INB VI(bias) 12 INPUT AND FEEDBACK CIRCUIT FEEDB M1 2 4 0 M3 OUTB TDA8358J Ii(p-p) II(av) M6 INEW 5 8 OUTEW 0 6 VGND Fig.1 Block diagram. 2002 Sep 25 3 7 EWGND MGL866 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier PINNING SYMBOL TDA8358J FUNCTIONAL DESCRIPTION PIN Vertical output stage DESCRIPTION INA 1 positive vertical input INB 2 negative vertical input VP 3 supply voltage OUTB 4 vertical output voltage B INEW 5 east-west input voltage VGND 6 vertical ground EWGND 7 east-west ground OUTEW 8 east-west output voltage VFB 9 flyback supply voltage OUTA 10 vertical output voltage A GUARD 11 guard output voltage FEEDB 12 input measuring resistor COMP 13 input compensation current The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. For processors with output currents, the currents are converted to voltages by the conversion resistors RCV1 and RCV2 (see Fig.3) connected to pins INA and INB. The differential input voltage is compared with the voltage across the measuring resistor RM, thus providing feedback information. The voltage across RM is proportional with the output current. The relationship between the differential input voltage and the output current is defined by: Vi(dif)(p-p) = Io(p-p) x RM; Vi(dif)(p-p) = VINA - VINB The output current should not exceed 3.2 A (p-p) and is determined by the value of RM and RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances. Depending on the value of RM and the internal bondwire resistance (typical value 50 m) the actual value of the current in the deflection coil will be about 5% lower than calculated. handbook, halfpage INA 1 INB 2 VP 3 OUTB 4 INEW 5 VGND 6 Flyback supply The flyback voltage is determined by the flyback supply voltage VFB. The principle of two supply voltages (class G) allows to use an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew rate value of more than 300 V/s. TDA8358J EWGND 7 OUTEW 8 VFB 9 OUTA 10 GUARD 11 FEEDB 12 COMP 13 Protection MGL867 The output circuit contains protection circuits for: * Too high die temperature The die has been glued to the metal block of the package. If the metal block is not insulated from the heatsink, the heatsink shall only be connected directly to pin VGND. * Overvoltage of output A. Fig.2 Pin configuration. 2002 Sep 25 4 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J For that purpose a compensation resistor RCMP is connected between pins OUTA and COMP. The value of RCMP is calculated by: Guard circuit A guard circuit with output pin GUARD is provided. The guard circuit generates a HIGH-level during the flyback period. The guard circuit is also activated for one of the following conditions: ( V FB - V loss ( FB ) - V P ) x R D1 x ( R S + 300 ) R CMP = ------------------------------------------------------------------------------------------------------------( V FB - V loss ( FB ) - I coil ( peak ) x R coil ) x R M * During thermal protection (Tj 170 C) where: * During an open-loop condition. * Rcoil is the coil resistance * Vloss(FB) is the voltage loss between pins VFB and OUTA at flyback. The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller. East-west amplifier The east-west amplifier is current driven. The output can only sink currents of the diode modulator circuit. A feedback resistor (see Fig.4) has to be connected between the input and output of the inverting east-west amplifier in order to convert the east-west correction input current into an output voltage. The output voltage of the east-west circuit at pin OUTEW is given by: Damping resistor compensation HF loop stability is achieved by connecting a damping resistor RD1 (see Fig.4) across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor RM, resulting in a too low deflection coil current at the start of the scan. VOUTEW IINEW x REWF + VINEW The maximum output voltage is Vo(max) = 68 V, while the maximum output current of the circuit is Io(max) = 750 mA. The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time. 2002 Sep 25 5 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage - 18 V VFB flyback supply voltage - 68 V - 0.3 V - 68 V pin OUTB - VP V pins INA, INB, INEW, GUARD, FEEDB, and COMP -0.5 VP V VVGND-EWGND voltage difference between pins VGND and EWGND DC voltage Vn pins OUTA and OUTEW note 1 DC current In pins OUTA and OUTB during scan (p-p) - 3.2 A pins OUTA and OUTB at flyback (peak); t 1.5 ms - 1.8 A -20 +20 mA pins INA, INB, INEW, GUARD, FEEDB, and COMP pin OUTEW Ilu latch-up current input current into any pin; pin voltage is 1.5 x VP; Tj = 150 C - 750 mA - +200 mA - mA +350 V input current out of any pin; -200 pin voltage is -1.5 x VP; Tj = 150 C Ves electrostatic handling voltage machine model; note 2 -350 human body model; note 3 -4000 +4000 V note 4 - 4 W PEW east-west power dissipation Ptot total power dissipation - 15 W Tstg storage temperature -55 +150 C Tamb ambient temperature -25 +85 C Tj junction temperature - +150 C note 5 Notes 1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage. 2. Equivalent to 200 pF capacitance discharge through a 0 resistor. 3. Equivalent to 100 pF capacitance discharge through a 1.5 k resistor. 4. For repetitive time durations of t < 0.1 ms or a non-repetitive time duration of t < 5 ms the maximum (peak) east-west power dissipation PEW(peak) = 15 W. 5. Internally limited by thermal protection at Tj 170 C. THERMAL CHARACTERISTICS In accordance with IEC 747-1. SYMBOL PARAMETER CONDITIONS Rth(j-c) thermal resistance from junction to case Rth(j-a) thermal resistance from junction to ambient 2002 Sep 25 6 in free air VALUE UNIT 4 K/W 40 K/W Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J CHARACTERISTICS VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP operating supply voltage VFB flyback supply voltage Iq(P)(av) average quiescent supply current Iq(P) Iq(FB)(av) 7.5 12 18 V note 1 2 x VP 45 66 V during scan - 10 15 mA quiescent supply current no signal; no load - 45 75 mA average quiescent flyback supply current during scan - - 10 mA - 1000 1500 mV Inputs A and B Vi(p-p) input voltage (peak-to-peak value) note 2 VI(bias) input bias voltage note 2 II(bias) input bias current 100 880 1600 mV - 25 35 A Io = 1.1 A - - 4.5 V Io = 1.6 A - - 6.6 V Io = -1.1 A - - 3.3 V Io = -1.6 A - - 4.8 V - - 3.2 A adjacent blocks - 1 2 % non-adjacent blocks - 1 3 % VI(bias) = 200 mV - - 15 mV VI(bias) = 1 V Outputs A and B Vloss(1) Vloss(2) voltage loss first scan part voltage loss second scan part Io(p-p) output current (peak-to-peak value) LE linearity error Voffset offset voltage note 3 note 4 Io(p-p) = 3.2 A; notes 5 and 6 across RM; Vi(dif) = 0 V - - 20 mV Voffset(T) offset voltage variation with temperature across RM; Vi(dif) = 0 V - - 40 V/K VO DC output voltage Vi(dif) = 0 V - 0.5 x VP - V Gv(ol) open-loop voltage gain notes 7 and 8 - 60 - dB f-3dB(h) high -3 dB cut-off frequency open-loop - 1 - kHz Gv voltage gain note 9 - 1 - Gv(T) voltage gain variation with temperature - - 10-4 K-1 PSRR power supply rejection ratio 80 90 - dB 2002 Sep 25 note 10 7 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier SYMBOL PARAMETER CONDITIONS TDA8358J MIN. TYP. MAX. UNIT Flyback switch Io(peak) maximum (peak) output current t 1.5 ms Vloss(FB) voltage loss at flyback note 11 - - 1.8 A Io = 1.1 A - 7.5 8.5 V Io = 1.6 A - 8 9 V Guard circuit IO(grd) = 100 A 5 6 7 V VO(grd)(max) allowable guard voltage maximum leakage current IL(max) = 10 A - - 18 V IO(grd) VO(grd) = 0 V; not active - - 10 A VO(grd) = 4.5 V; active 1 - 2.5 mA VO(grd) guard output voltage output current East-west amplifier Vo output voltage at pin OUTEW - - 68 V Io = 750 mA; note 12 - - 5 V 2 2.5 3.2 V Io = 100 mA - 2.5 - A Io = 500 mA - 11.5 - A - 30 - dB Vloss voltage loss VI(bias) input bias voltage II(bias) input bias current into pin INEW; note 13 Gv(ol) open-loop voltage gain THD harmonic distortion - 0.5 1 % f-3dB(h) high -3 dB cut-off frequency - - 1 MHz 2002 Sep 25 8 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J Notes 1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA and VFB at the first part of the flyback. 2. Allowable input range for both inputs: VI(bias) + Vi < 1600 mV and VI(bias) - Vi > 100 mV. 3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and between pins OUTB and GND. Specified for Tj = 125 C. The temperature coefficient for Vloss(1) is a positive value. 4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and between pins OUTA and GND. Specified for Tj = 125 C. The temperature coefficient for Vloss(2) is a positive value. 5. The linearity error is measured for a linear input signal without S-correction and is based on the `on screen' measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10, where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum, maximum and average voltages respectively. The linearity errors are defined as: Vk - Vk + 1 a) LE = -------------------------- x 100% (adjacent blocks) V avg V max - V min b) LE = ------------------------------- x 100% (non adjacent blocks) V avg 6. The linearity errors are specified for a minimum input voltage at pin 1 or pin 2 of 300 mV. Lower input voltages lead to voltage dependent S-distortion in the input stage. 7. V OUTA - V OUTB G v ( ol ) = ------------------------------------------V FEEDB - V OUTB 8. Pin FEEDB not connected. 9. V FEEDB - V OUTB G V = ------------------------------------------V INA - V INB 10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM. 11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA. 12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND. 13. Measured for REWF = 10 k; REWL = 30 ; Vo = 6 V. a) For Io = 100 mA and a voltage of 9 V at REWL connected to the line output transformer, the east-west amplifier input current (see Fig.4) is Ii = 300 A. b) For Io = 500 mA and a voltage of 21 V at REWL connected to the line output transformer, the east-west amplifier input current (see Fig.4) is Ii = 350 A. 2002 Sep 25 9 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J APPLICATION INFORMATION handbook, full pagewidth VP RGRD 4.7 k 11 13 COMP. CIRCUIT VFB GUARD VP COMP C1 100 nF VFB 3 9 C2 100 nF GUARD CIRCUIT M5 Vi(p-p) D2 D3 VI(bias) M2 0 D1 I I(bias) 10 OUTA INA 1 RCV1 2.2 k (1%) I i(dif) M4 12 FEEDB INPUT AND FEEDBACK CIRCUIT INB 2 4 II(av) TDA8358J Ii INEW 5 M6 Ii 6 REWF 10 k VGND 8 OUTEW 7 REWL 30 EWGND MGL873 0 Fig.3 Test diagram. 2002 Sep 25 OUTB M3 Vi(p-p) Ii(p-p) CM 10 nF M1 RCV2 2.2 k (1%) 0 RL 3.2 2.7 k I I(bias) VI(bias) RS 10 RM 0.5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 13 Vi(p-p) COMP. CIRCUIT VFB = 30 V VFB C3 100 nF 9 GUARD CIRCUIT C1 47 F (100 V) C4 100 nF C2 220 F deflection coil 5 mH 6 W66ESF CD 47 nF M5 VI(bias) D2 0 D3 RCMP 500 k M2 INA 1 C5 2.2 nF TV SIGNAL PROCESSOR 11 INB 2 C6 2.2 nF D1 RCV1 2.2 k 10 OUTA M4 12 FEEDB INPUT AND FEEDBACK CIRCUIT RS 2.7 k RCV2 2.2 k RM 0.87 M1 4 M3 Vi(p-p) RD1 270 RD2 1.5 Philips Semiconductors GUARD VP 11 3 COMP Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier dbook, full pagewidth 2002 Sep 25 VP = 14 V RGRD 12 k OUTB TDA8358J VI(bias) 0 M6 INEW 5 Ii(p-p) Ii II(av) 6 7 REWL 12 to line output transformer EWGND MGL874 fvert = 50 Hz; tFB = 640 s; II(bias) = 400 A; Ii(p-p) = 475 A; Io(p-p) = 2.4 A. Fig.4 Application diagram. TDA8358J 0 Product specification REWF 82 k VGND 8 OUTEW Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J RM calculation Supply voltage calculation Before calculating the measuring resistor (RM), the differential input voltage [Vi(dif)] has to be known. This voltage can be measured between pins INA and INB. The V i(dif)(p-p) calculation is as follows: R M = --------------------I o(p-p) For calculating the minimum required supply voltage, several specific application parameter values have to be known. These parameters are the required maximum (peak) deflection coil current Icoil(peak), the coil impedance Rcoil and Lcoil and the measuring resistance of RM. The required maximum (peak) deflection coil current should also include the overscan. Most of the TV signal processors from Philips have a current output. This current has to be converted by resistors at the input of the TDA8358J (RCV1 and RCV2). The voltage across these resistors can be calculated. The differential input voltage is given in the following equation (see also Fig 5): Vi(dif)(p-p) = Ii1(p-p) x RCV1 - [-Ii2(p-p)] x RCV2 The deflection coil resistance has to be multiplied by 1.2 in order to take account of hot conditions. Chapter "Characteristics" supplies values for the voltage losses of the vertical output stage. For the first part of the scan the voltage loss is given by Vloss(1). For the second part of the scan the voltage loss is given by Vloss(2). The voltage drop across the deflection coil during scan is determined by the coil impedance. For the first part of the scan the inductive contribution and the ohmic contribution to the total coil voltage drop are of opposite sign, while for the second part of the scan the inductive part and the ohmic part have the same sign. Ii1(p-p) II(bias) 0 For the vertical frequency the maximum frequency occurring must be applied to the calculations. 1 C5 2.2 nF RCV1 2.2 k The required power supply voltage VP for the first part of the scan is given by: TV SIGNAL PROCESSOR V P ( 1 ) = I coil ( peak ) x ( R coil + R M ) - L coil x 2I coil ( peak ) x f vert ( max ) + V loss ( 1 ) 2 C6 2.2 nF The required power supply voltage VP for the second part of the scan is given by: RCV2 2.2 k V P ( 2 ) = I coil ( peak ) x ( R coil + R M ) + L coil x 2I coil ( peak ) x f vert ( max ) + V loss ( 2 ) Ii2(p-p) The minimum required supply voltage VP shall be the highest of the two values VP(1) and VP(2). Spread in supply voltage and component values also has to be taken into account. II(bias) 0 MBL520 Fig.5 Differential input voltage. Flyback supply voltage calculation If the flyback time is known, the required flyback supply voltage can be calculated by the simplified formula: Values for these currents are, for instance: Ii(bias) = 400 A; Ii1(p-p) = Ii2(p-p) = 475 A. R coil + R M V FB = I coil ( p -p ) x -------------------------- t FB x 1-e Therefore the differential input voltage be as follows: Vi(dif)(p-p) = 475 A x 2.2 k - (-475 A x 2.2 k) = 2.09 V where: L coil x = -------------------------R coil + R M 2002 Sep 25 12 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier Power dissipation calculation for the east-west stage The flyback supply voltage calculated this way is approximately 5% to 10% higher than required. In general the shape of the east-west output wave form is a parabola. The output voltage will be higher at the beginning and end of the vertical scan compared to the voltage at the scan middle, while the output current will be higher at the scan middle. This results in an almost uniform power dissipation distribution during scan. Therefore the power dissipation can be calculated by multiplying the average values of the output voltage and the output current of pin OUTEW. Calculation of the power dissipation of the vertical output stage The power dissipation of the vertical output stage is given by the formula: PV = Psup - PL The power to be supplied is given by the formula: When verifying the dissipation the switch-on and switch-off dissipation should also be taken into account. Power dissipation during start-up can be 3 to 5 times higher than during normal operation. I coil ( peak ) P sup = V P x ----------------------- + V P x 0.015 [A] + 0.3 [W] 2 In this formula 0.3 [W] represents the average value of the losses in the flyback supply. Heatsink calculation The average external load power dissipation in the deflection coil and the measuring resistor is given by the formula: The value of the heatsink can be calculated in a standard way with a method based on average temperatures. The required thermal resistance of the heatsink is determined by the maximum die temperature of 150 C. In general we recommend a design for an average die temperature not exceeding 130 C. It should be noted that the heatsink thermal resistance Rth(h-a) found by performing a standard calculation will be lower then normally found for a vertical deflection stand alone device, due to the contribution of the EW power dissipation to this value. 2 ( I coil ( peak ) ) P L = -------------------------------- x ( R coil + R M ) 3 Example Table 1 Application values VALUE UNIT Icoil(peak) SYMBOL 1.2 A Icoil(p-p) Lcoil Rcoil RM fvert 2.4 5 6 0.6 50 A mH Hz tFB 640 s Table 2 EXAMPLE Measured or known values: PEW = 3 W; PV = 6 W; Tamb = 40 C; Tj = 130 C; Rth(j-c) = 4 K/W; Rth(c-h) = 1 K/W. The required heatsink thermal resistance is given by: T j - T amb R th ( h - a ) = ------------------------ - ( R th ( j - c ) + R th ( c - h ) ) P EW + P V Calculated values SYMBOL VP RM + Rcoil (hot) tvert x VFB Psup PL PV 2002 Sep 25 TDA8358J VALUE UNIT When we use the values known we find: 14 7.8 0.02 V s 130 - 40 R th ( h - a ) = ---------------------- - ( 4 + 1 ) = 5 K/W 3+6 0.000641 30 8.91 V W 3.74 5.17 W W The heatsink temperature will be: Th = Tamb + Rth(h-a) x Ptot = 40 + 5 x 9 = 85 C 13 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J Equivalent thermal resistance network EXAMPLE The TDA8358J has two independent power dissipating systems, the vertical output circuit and the east-west circuit. Measured or known values: It is recommended to verify the individual maximum (peak) junction temperatures of both circuits. Therefore the maximum (peak) power dissipations of the circuits and also the heatsink temperature should be measured. The maximum (peak) junction temperatures can be calculated by using an equivalent thermal network (see Fig.6). * The maximum (peak) power dissipation of the most critical transistor: PTRv(peak) = 5 W * The east-west power dissipation: PEW = 3 W * The vertical power dissipation: PV = 6 W * The case temperature: Tc = 85 C. The IC total power dissipation is: Ptot = PEW + PV = 6 + 3 = 9 W The network only includes the contribution of the maximum (peak) power dissipation PTRv(peak), being the dissipation of the most critical transistor internally connected to pins OUTA and VGND. The model assumes equivalent maximum (peak) power dissipations during the different vertical scan stages for all the functionally paired transistors. The calculated maximum (peak) junction temperatures should not exceed Tj = 150 C. It should be noted that the allowed IC total power dissipation is Ptot = 15 W (maximum value). The maximum (peak) temperature TP1(peak) is given by: * TP1(peak) = Tc + (PEW + PTRv(peak)) x Rth(P1-c) = 85 + (3 + 5) x 2.2 = 102.6 C The maximum (peak) junction temperatures for the output circuits are given by: * Tj(EW)(peak) = TP1(peak) + Rth(EW-P1) x PEW = 102.6 + 10.5 x 3 = 134.1 C * Tj(TRv)(peak) = TP1(peak) + Rth(TRv-P1) x PTRv(peak) = 102.6 + 5.2 x 5 = 128.6 C handbook, halfpage TEW(M) TTRv(M) Rth(EW-P1) 10.5 K/W PEW Rth(TRv-P1) 5.2 K/W PTRv(M) TP1(M) Rth(P1-c) 2.2 K/W Ptot Tc MGL872 Fig.6 Equivalent thermal resistance network. 2002 Sep 25 14 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J INTERNAL PIN CONFIGURATION PIN 1 SYMBOL EQUIVALENT CIRCUIT INA 1 300 MBL100 2 INB 2 300 MBL102 3 VP 4 OUTB 6 VGND 9 VFB 10 OUTA 9 3 10 4 6 MGL869 5 INEW 7 EWGND 8 OUTEW 300 5 7 8 MGL868 2002 Sep 25 15 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier PIN 11 SYMBOL TDA8358J EQUIVALENT CIRCUIT GUARD 300 11 MGL870 12 FEEDB 300 12 MGL871 13 COMP 300 13 MGL875 2002 Sep 25 16 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J PACKAGE OUTLINE DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6 non-concave Dh x D Eh view B: mounting base side d A2 B j E A L3 L Q c 1 v M 13 e1 Z e e2 m w M bp 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A2 bp c D (1) d Dh E (1) e e1 e2 Eh j L L3 m Q v w x Z (1) mm 17.0 15.5 4.6 4.4 0.75 0.60 0.48 0.38 24.0 23.6 20.0 19.6 10 12.2 11.8 3.4 1.7 5.08 6 3.4 3.1 12.4 11.0 2.4 1.6 4.3 2.1 1.8 0.8 0.25 0.03 2.00 1.45 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-12-16 99-12-17 SOT141-6 2002 Sep 25 EUROPEAN PROJECTION 17 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction to soldering through-hole mount packages The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 2002 Sep 25 18 Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Sep 25 19 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA74 (c) Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/02/pp20 Date of release: 2002 Sep 25 Document order number: 9397 750 09635