Low Noise, High Speed Amplifier
for 16-Bit Systems
AD8021
Rev. F
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FEATURES
Low noise
2.1 nV/√Hz input voltage noise
2.1 pA/√Hz input current noise
Custom compensation
Constant bandwidth from G = −1 to G = −10
High speed
200 MHz (G = −1)
190 MHz (G = −10)
Low power
34 mW or 6.7 mA typical for 5 V supply
Output disable feature, 1.3 mA
Low distortion
−93 dBc second harmonic, fC = 1 MHz
−108 dBc third harmonic, fC = 1 MHz
DC precision
1 mV maximum input offset voltage
0.5 μV/°C input offset voltage drift
Wide supply range, 5 V to 24 V
Low price
Small packaging
Available in SOIC-8 and MSOP-8
APPLICATIONS
ADC preamps and drivers
Instrumentation preamps
Active filters
Portable instrumentation
Line receivers
Precision instruments
Ultrasound signal processing
High gain circuits
GENERAL DESCRIPTION
The AD8021 is an exceptionally high performance, high speed
voltage feedback amplifier that can be used in 16-bit resolution
systems. It is designed to have both low voltage and low current
noise (2.1 nV/√Hz typical and 2.1 pA/√Hz typical) while operating
at the lowest quiescent supply current (7 mA @ ±5 V) among
today’s high speed, low noise op amps. The AD8021 operates
over a wide range of supply voltages from ±2.25 V to ±12 V, as
well as from single 5 V supplies, making it ideal for high speed,
low power instruments. An output disable pin allows further
reduction of the quiescent supply current to 1.3 mA.
CONNECTION DIAGRAM
8
7
6
5
1
2
3
4
LOGIC
REFERENCE
–IN
+IN
–V
S
DISABLE
+V
S
V
OUT
C
COMP
AD8021
01888-001
Figure 1. SOIC-8 (R-8) and MSOP-8 (RM-8)
The AD8021 allows the user to choose the gain bandwidth
product that best suits the application. With a single capacitor,
the user can compensate the AD8021 for the desired gain with
little trade-off in bandwidth. The AD8021 is a well-behaved
amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast
overload recovery of 50 ns.
The AD8021 is stable over temperature with low input offset
voltage drift and input bias current drift, 0.5 μV/°C and 10 nA/°C,
respectively. The AD8021 is also capable of driving a 75 Ω line
with ±3 V video signals.
The AD8021 is both technically superior and priced considerably
less than comparable amps drawing much higher quiescent
current. The AD8021 is a high speed, general-purpose amplifier,
ideal for a wide variety of gain configurations and can be used
throughout a signal processing chain and in control loops. The
AD8021 is available in both standard 8-lead SOIC and MSOP
packages in the industrial temperature range of −40°C to +85°C.
FREQUENCY (Hz)
0.1M 1G1M 10M 100M
CLOSED-LOOP GAIN (dB)
24
21
–6
18
15
12
9
6
3
0
–3
V
OUT
= 50mV p-p
G = –10, R
F
= 1kΩ, R
G
= 100Ω,
R
IN
= 100Ω, C
C
= 0pF
G = –5, R
F
= 1kΩ, R
G
= 200Ω,
R
IN
= 66.5Ω, C
C
= 1.5pF
G = –2, R
F
= 499Ω, R
G
= 249Ω,
R
IN
= 63.4Ω, C
C
= 4pF
G = –1, R
F
= 499Ω, R
G
= 499Ω,
R
IN
= 56.2Ω, C
C
= 7pF
01888-002
Figure 2. Small Signal Frequency Response
AD8021
Rev. F | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits................................................................................. 17
Applications..................................................................................... 19
Using the Disable Feature.......................................................... 20
Theory of Operation ...................................................................... 21
PCB Layout Considerations...................................................... 21
Driving 16-Bit ADCs................................................................. 22
Differential Driver...................................................................... 22
Using the AD8021 in Active Filters ......................................... 23
Driving Capacitive Loads.......................................................... 23
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
5/06—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Figure 3.......................................................................... 7
Changes to Figure 60...................................................................... 19
Changes to Table 9.......................................................................... 23
3/05—Rev. D to Rev. E
Updated Format..................................................................Universal
Change to Figure 19 ....................................................................... 11
Change to Figure 25 ....................................................................... 12
Change to Table 7 and Table 8 ...................................................... 22
Change to Driving 16-Bit ADCs Section .................................... 22
10/03—Rev. C to Rev. D
Updated Format..................................................................Universal
7/03—Rev. B to Rev. C
Deleted All References to Evaluation Board...................Universal
Replaced Figure 2 ..............................................................................5
Updated Outline Dimensions....................................................... 20
2/03—Rev. A to Rev. B
Edits to Evaluation Board Applications....................................... 20
Edits to Figure 17 ........................................................................... 20
6/02—Rev. 0 to Rev. A
Edits to Specifications.......................................................................2
AD8021
Rev. F | Page 3 of 28
SPECIFICATIONS
VS = ±5 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 1.
AD8021AR/AD8021ARM
Parameter Conditions
Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 355 490 MHz
G = +2, CC = 7 pF, VO = 0.05 V p-p 160 205 MHz
G = +5, CC = 2 pF, VO = 0.05 V p-p 150 185 MHz
G = +10, CC = 0 pF, VO = 0.05 V p-p 110 150 MHz
Slew Rate, 1 V Step G = +1, CC = 10 pF 95 120 V/μs
G = +2, CC = 7 pF 120 150 V/μs
G = +5, CC = 2 pF 250 300 V/μs
G = +10, CC = 0 pF 380 420 V/μs
Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 23 ns
Overload Recovery (50%) ±2.5 V input step, G = +2 50 ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2 VO = 2 V p-p −93 dBc
HD3 VO = 2 V p-p −108 dBc
f = 5 MHz
HD2 VO = 2 V p-p −70 dBc
HD3 VO = 2 V p-p −80 dBc
Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz
Input Current Noise f = 50 kHz 2.1 pA/√Hz
Differential Gain Error NTSC, RL = 150 Ω 0.03 %
Differential Phase Error NTSC, RL = 150 Ω 0.04 Degrees
DC PERFORMANCE
Input Offset Voltage 0.4 1.0 mV
Input Offset Voltage Drift TMIN to TMAX 0.5 μV/°C
Input Bias Current +Input or −input 7.5 10.5 μA
Input Bias Current Drift 10 nA/°C
Input Offset Current 0.1 0.5 ±μA
Open-Loop Gain 82 86 dB
INPUT CHARACTERISTICS
Input Resistance 10 MΩ
Common-Mode Input Capacitance 1 pF
Input Common-Mode Voltage Range −4.1 to +4.6 V
Common-Mode Rejection Ratio VCM = ±4 V −86 −98 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing −3.5 to +3.2 −3.8 to +3.4 V
Linear Output Current 60 mA
Short-Circuit Current 75 mA
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p 15/120 pF
DISABLE CHARACTERISTICS
Off Isolation f = 10 MHz −40 dB
Turn-On Time VO = 0 V to 2 V, 50% logic to 50% output 45 ns
Turn-Off Time VO = 0 V to 2 V, 50% logic to 50% output 50 ns
DISABLE Voltage—Off/On VDISABLE − VLOGIC REFERENCE 1.75/1.90 V
Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA
DISABLE = 4.0 V 2 μA
AD8021
Rev. F | Page 4 of 28
AD8021AR/AD8021ARM
Parameter Conditions
Min Typ Max Unit
Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA
DISABLE = 0.4 V 33 μA
POWER SUPPLY
Operating Range ±2.25 ±5 ±12.0 V
Quiescent Current Output enabled 7.0 7.7 mA
Output disabled 1.3 1.6 mA
+Power Supply Rejection Ratio VCC = 4 V to 6 V, VEE = −5 V −86 −95 dB
−Power Supply Rejection Ratio VCC = 5 V, VEE = −6 V to −4 V −86 −95 dB
VS = ±12 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 2.
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 520 560 MHz
G = +2, CC = 7 pF, VO = 0.05 V p-p 175 220 MHz
G = +5, CC = 2 pF, VO = 0.05 V p-p 170 200 MHz
G = +10, CC = 0 pF, VO = 0.05 V p-p 125 165 MHz
Slew Rate, 1 V Step G = +1, CC = 10 pF 105 130 V/μs
G = +2, CC = 7 pF 140 170 V/μs
G = +5, CC = 2 pF 265 340 V/μs
G = +10, CC = 0 pF 400 460 V/μs
Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 21 ns
Overload Recovery (50%) ±6 V input step, G = +2 90 ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2 VO = 2 V p-p −95 dBc
HD3 VO = 2 V p-p −116 dBc
f = 5 MHz
HD2 VO = 2 V p-p −71 dBc
HD3 VO = 2 V p-p −83 dBc
Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz
Input Current Noise f = 50 kHz 2.1 pA/√Hz
Differential Gain Error NTSC, RL = 150 Ω 0.03 %
Differential Phase Error NTSC, RL = 150 Ω 0.04 Degrees
DC PERFORMANCE
Input Offset Voltage 0.4 1.0 mV
Input Offset Voltage Drift TMIN to TMAX 0.2 μV/°C
Input Bias Current +Input or −input 8 11.3 μA
Input Bias Current Drift 10 nA/°C
Input Offset Current 0.1 0.5 ±μA
Open-Loop Gain 84 88 dB
INPUT CHARACTERISTICS
Input Resistance 10 MΩ
Common-Mode Input Capacitance 1 pF
Input Common-Mode Voltage Range −11.1 to +11.6 V
Common-Mode Rejection Ratio VCM = ±10 V −86 −96 dB
AD8021
Rev. F | Page 5 of 28
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing −10.2 to +9.8 −10.6 to +10.2 V
Linear Output Current 70 mA
Short-Circuit Current 115 mA
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p 15/120 pF
DISABLE CHARACTERISTICS
Off Isolation f = 10 MHz −40 dB
Turn-On Time VO = 0 V to 2 V, 50% logic to 50% output 45 ns
Turn-Off Time VO = 0 V to 2 V, 50% logic to 50% output 50 ns
DISABLE Voltage—Off/On VDISABLE − VLOGIC REFERENCE 1.80/1.95 V
Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA
DISABLE = 4.0 V 2 μA
Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA
DISABLE = 0.4 V 33 μA
POWER SUPPLY
Operating Range ±2.25 ±5 ±12.0 V
Quiescent Current Output enabled 7.8 8.6 mA
Output disabled 1.7 2.0 mA
+Power Supply Rejection Ratio VCC = 11 V to 13 V, VEE = −12 V −86 −96 dB
−Power Supply Rejection Ratio VCC = 12 V, VEE = −13 V to −11 V −86 −100 dB
VS = 5 V, @ TA = 25°C, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 3.
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, CC = 10 pF, VO = 0.05 V p-p 270 305 MHz
G = +2, CC = 7 pF, VO = 0.05 V p-p 155 190 MHz
G = +5, CC = 2 pF, VO = 0.05 V p-p 135 165 MHz
G = +10, CC = 0 pF, VO = 0.05 V p-p 95 130 MHz
Slew Rate, 1 V Step G = +1, CC = 10 pF 80 110 V/μs
G = +2, CC = 7 pF 110 140 V/μs
G = +5, CC = 2 pF 210 280 V/μs
G = +10, CC = 0 pF 290 390 V/μs
Settling Time to 0.01% VO = 1 V step, RL = 500 Ω 28 ns
Overload Recovery (50%) 0 V to 2.5 V input step, G = +2 40 ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2 VO = 2 V p-p −84 dBc
HD3 VO = 2 V p-p −91 dBc
f = 5 MHz
HD2 VO = 2 V p-p −68 dBc
HD3 VO = 2 V p-p −81 dBc
Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz
Input Current Noise f = 50 kHz 2.1 pA/√Hz
AD8021
Rev. F | Page 6 of 28
AD8021AR/AD8021ARM
Parameter Conditions Min Typ Max Unit
DC PERFORMANCE
Input Offset Voltage 0.4 1.0 mV
Input Offset Voltage Drift TMIN to TMAX 0.8 μV/°C
Input Bias Current +Input or −input 7.5 10.3 μA
Input Bias Current Drift 10 nA/°C
Input Offset Current 0.1 0.5 ±μA
Open-Loop Gain 72 76 dB
INPUT CHARACTERISTICS
Input Resistance 10 MΩ
Common-Mode Input Capacitance 1 pF
Input Common-Mode Voltage Range 0.9 to 4.6 V
Common-Mode Rejection Ratio 1.5 V to 3.5 V −84 −98 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing 1.25 to 3.38 1.10 to 3.60 V
Linear Output Current 30 mA
Short-Circuit Current 50 mA
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p 10/120 pF
DISABLE CHARACTERISTICS
Off Isolation f = 10 MHz −40 dB
Turn-On Time VO = 0 V to 1 V, 50% logic to 50% output 45 ns
Turn-Off Time VO = 0 V to 1 V, 50% logic to 50% output 50 ns
DISABLE Voltage—Off/On VDISABLE − VLOGIC REFERENCE 1.55/1.70 V
Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA
DISABLE = 4.0 V 2 μA
Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA
DISABLE = 0.4 V 33 μA
POWER SUPPLY
Operating Range ±2.25 ±5 ±12.0 V
Quiescent Current Output enabled 6.7 7.5 mA
Output disabled 1.2 1.5 mA
+Power Supply Rejection Ratio VCC = 4.5 V to 5.5 V, VEE = 0 V −74 −82 dB
−Power Supply Rejection Ratio VCC = 5 V, VEE = −0.5 V to +0.5 V −76 −84 dB
AD8021
Rev. F | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 26.4 V
Power Dissipation Observed power
derating curves
Input Voltage (Common Mode) ±VS ± 1 V
Differential Input Voltage1±0.8 V
Differential Input Current ±10 mA
Output Short-Circuit Duration Observed power
derating curves
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
1 The AD8021 inputs are protected by diodes. Current-limiting resistors are
not used to preserve the low noise. If a differential input exceeds ±0.8 V, the
input current should be limited to ±10 mA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8021 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit can cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
While the AD8021 is internally short-circuit protected, this can
not be sufficient to guarantee that the maximum junction tem-
perature (150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum
power derating curves.
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
2.0
1.5
1.0
0.5
0.01
–55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75
85
8-LEAD SOIC
8-LEAD MSOP
01888-004
Figure 3. Maximum Power Dissipation vs. Temperature1
1 Specification is for device in free air: 8-lead SOIC: θJA = 125°C/W; 8-lead
MSOP: θJA = 145°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8021
Rev. F | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
8
7
6
5
1
2
3
4
LOGIC
REFERENCE
–IN
+IN
–V
S
DISABLE
+V
S
V
OUT
C
COMP
AD8021
01888-003
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 LOGIC REFERENCE Reference for Pin 81 Voltage Level. Connect to logic low supply.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VSNegative Supply Voltage.
5 CCOMP Compensation Capacitor. Tie to −VS. (See the Applications section for value.)
6 VOUT Output.
7 +VS Positive Supply Voltage.
8 DISABLE Disable, Active Low.
1 When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of
Pin 1, the part is disabled. (See the Specifications tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied to
+VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state.
AD8021
Rev. F | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, RL = 1 kΩ, G = +2, RF = RG = 499 Ω, RS = 49.9 Ω, RO = 976 Ω, RD = 53.6 Ω, CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p,
frequency = 1 MHz, unless otherwise noted.
FREQUENCY (Hz)
0.1M 1G1M 10M 100M
CLOSED-LOOP GAIN (dB)
24
21
–6
18
15
12
9
6
3
0
–3
G = +10, R
F
= 1kΩ, R
G
= 110Ω, C
C
= 0pF
G = +5, R
F
= 1kΩ, R
G
= 249Ω, C
C
= 2pF
G = +2, R
F
= R
G
= 499Ω, C
C
= 7pF
G = +1, R
F
= 75Ω, C
C
= 10pF
01888-005
Figure 5. Small Signal Frequency Response vs. Frequency and Gain,
VOUT = 50 mV p-p, Noninverting (See Figure 48)
FREQUENCY (Hz)
0.1M 1G1M 10M 100M
GAIN (dB)
24
21
–6
18
15
12
9
6
3
0
–3
G = –10, R
F
= 1kΩ, R
G
= 100Ω,
R
IN
= 100Ω, C
C
= 0pF
G = –5, R
F
= 1kΩ, R
G
= 200Ω,
R
IN
= 66.5Ω, C
C
= 1.5pF
G = –2, R
F
= 499Ω, R
G
= 249Ω,
R
IN
= 63.4Ω, C
C
= 4pF
G = –1, R
F
= 499Ω, R
G
= 499Ω,
R
IN
= 56.2Ω, C
C
= 7pF
01888-006
Figure 6. Small Signal Frequency Response vs. Frequency and
Gain, VOUT = 50 mV p-p Inverting (See Figure 48)
FREQUENCY (Hz)
0.1M 1G1M
GAIN (dB)
10M 100M
9
8
–1
7
6
5
4
3
2
1
0C
C
= 9pF
G = +2
C
C
= 7pF
C
C
= 7pF
C
C
= 9pF
C
C
= 5pF
01888-007
Figure 7. Small Signal Frequency Response vs. Frequency and
Compensation Capacitor, VOUT = 50 mV p-p (See Figure 48)
FREQUENCY (Hz)
1G1M
GAIN (dB)
10M 100M
9
8
–1
7
6
5
4
3
2
1
0
G = +2
V
S
= ±5V
V
S
= ±12V
V
S
= ±2.5V
V
S
= ±2.5V
01888-008
Figure 8. Small Signal Frequency Response vs. Frequency and Supply,
VOUT = 50 mV p-p, Noninverting (See Figure 48)
FREQUENCY (Hz)
1G1M
GAIN (dB)
10M 100M
3
2
–7
1
0
–1
–2
–3
–4
–5
–6
V
S
= ±5V
V
S
= ±2.5V
V
S
= ±2.5V
G = –1
V
S
= ±12V
01888-009
Figure 9. Small Signal Frequency Response vs. Frequency and Supply,
VOUT = 50 mV p-p, Inverting (See Figure 50)
FREQUENCY (Hz)
1G1M
GAIN (dB)
10M 100M
9
8
–1
7
6
5
4
3
2
1
0
V
OUT
= 1V p-p
V
OUT
= 4V p-p
V
OUT
= 0.1V AND 50mV p-p
G = +2
01888-010
Figure 10. Frequency Response vs. Frequency and VOUT, Noninverting
(See Figure 48)
AD8021
Rev. F | Page 10 of 28
FREQUENCY (Hz)
0.1M 1G1M
GAIN (dB)
10M 100M
9
8
7
6
5
4
3
2
1
0
10
R
L
= 1kΩ
G = +2
R
L
= 100Ω
01888-011
Figure 11. Large Signal Frequency Response vs. Frequency and
Load, Noninverting (See Figure 49)
FREQUENCY (Hz)
1G1M
GAIN (dB)
10M 100M
9
8
7
6
5
4
3
2
1
0
–1
G = +2 +85°C
–40°C
+25°C
+85°C
V
OUT
=
2V p-p
V
OUT
=
50mV p-p
–40°C
+25°C
01888-012
Figure 12. Frequency Response vs. Frequency, Temperature, and
VOUT, Noninverting (See Figure 48)
FREQUENCY (Hz)
1G1M
GAIN (dB)
10M 100M
15
12
9
6
3
0
–3
–6
–9
–12
18
G = +2 50pF
30pF
20pF
10pF
0pF
01888-013
Figure 13. Small Signal Frequency Response vs.
Frequency and Capacitive Load, Noninverting, VOUT = 50 mV p-p
(See Figure 49 and Figure 71)
FREQUENCY (Hz)
1G0.1M 10M 100M
GAIN (dB)
9
8
7
6
5
4
3
2
1
0
10
1M
R
F
= 1kΩAND C
F
= 2.2pF
G = +2
R
F
= R
G
R
F
= 150Ω
R
F
= 1kΩ
R
F
= 499Ω
R
F
= 250Ω
R
F
= 75Ω
01888-014
Figure 14. Small Signal Frequency Response vs. Frequency and RF,
Noninverting, VOUT = 50 mV p-p (See Figure 48)
FREQUENCY (Hz)
0.1M 1G1M
GAIN (dB)
10M 100M
12
9
6
3
0
–3
–6
–9
–12
–15
15
G = +2
R
S
= 49.9Ω
R
S
= 100Ω
R
S
= 249Ω
01888-015
Figure 15. Small Signal Frequency Response vs. Frequency and RS,
Noninverting, VOUT = 50 mV p-p (See Figure 48)
FREQUENCY (Hz)
100k 1G1M
OPEN-LOOP GAIN (dB)
10M 100M
100
90
80
70
60
50
40
30
20
10
0
PHASE (Degrees)
90
45
0
–45
–90
–135
135
180
10k
01888-016
Figure 16. Open-Loop Gain and Phase vs. Frequency, RG = 100 Ω,
RF = 1 kΩ, RO = 976 Ω, RD = 53.6 Ω, CC = 0 pF (See Figure 50)
AD8021
Rev. F | Page 11 of 28
FREQUENCY (Hz)
1M
GAIN (dB)
10M 100M
6.2
6.0
5.8
5.6
5.4
6.4
G = +2
V
S
= ±12V
V
S
= ±2.5V
01888-017
V
S
= ±5V
Figure 17. 0.1 dB Flatness vs. Frequency and Supply, VOUT = 1 V p-p,
RL = 150 Ω, Noninverting (See Figure 49)
FREQUENCY (Hz)
0.1M
DISTORTION (dBc)
1M
–40
–60
–90
–110
–130
–20
–30
–50
–70
–80
–100
–120
10M 20M
THIRD
SECOND
R
L
= 100Ω
R
L
= 1kΩ
01888-018
Figure 18. Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (Hz)
100k
DISTORTION (dBc)
1M 20M
–40
–60
–90
–110
–130
–30
–50
–70
–80
–100
–120
10M
THIRD SECOND
SECOND
SECOND
THIRD
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±12V
01888-019
Figure 19. Second and Third Harmonic Distortion vs. Frequency and VS
FREQUENCY (MHz)
9.5
P
OUT
(dBm)
10.5
–40
–60
–90
–110
–30
–50
–70
–80
–100
–120
–20
9.7 10.3
10.0
Δf
= 0.2MHz
f
1
f
2
976Ω
53.6Ω50Ω
P
OUT
01888-020
Figure 20. Intermodulation Distortion vs. Frequency
FREQUENCY (MHz)
0
THIRD-ORDER INTERCEPT (dBm)
10 20
45
30
25
40
35
20
50
V
S
= ±5V
V
S
= ±2.5V
515
01888-021
Figure 21. Third-Order Intercept vs. Frequency and Supply Voltage
1
DISTORTION (dBc)
–60
–90
–100
–70
–80
–120
–50
–110
THIRD
SECOND
SECOND
THIRD
V
OUT
(V p-p)
2345
6
R
L
= 100Ω
R
L
= 1kΩ
01888-022
Figure 22. Second and Third Harmonic Distortion vs. VOUT and RL
AD8021
Rev. F | Page 12 of 28
f
C = 5MHz
f
C = 1MHz
1
DISTORTION (dBc)
–60
–90
–100
–70
–80
–120
–50
–110
THIRD
SECOND
SECOND
THIRD
VOUT (V p-p)
2345
01888-023
6
Figure 23. Second and Third Harmonic Distortion vs. VOUT and
Fundamental Frequency (fC), G = +2
1
DISTORTION (dBc)
–50
–80
–90
–60
–70
–110
–40
–100
THIRD
SECOND
SECOND
THIRD
VOUT (V p-p)
23456
f
C = 5MHz
f
C = 1MHz
01888-024
Figure 24. Second and Third Harmonic Distortion vs. VOUT and
Fundamental Frequency (fC), G = +10
0 400 800
–90
–110
–80
200 600 1000
–120
–70
–100
DISTORTION (dBc)
FEEDBACK RESISTANCE (Ω)
f
C
= 1MHz
R
L
= 1kΩ
R
F
= R
G
G = +2
THIRD
SECOND
01888-025
Figure 25. Second and Third Harmonic Distortion vs. Feedback Resistor (RF)
0 800 1600
3.2
2.9
3.4
400 1200 2000
2.8
3.5
3.1
3.3
3.0
–3.4
–3.7
–3.2
–3.8
–3.1
–3.5
–3.3
–3.6
NEGATIVE OUTPUT
POSITIVE OUTPUT
LOAD (
Ω
)
POSITIVE OUTPUT VOLTAGE (V)
NEGATIVE OUTPUT VOLTAGE (V)
01888-026
Figure 26. DC Output Voltages vs. Load (See Figure 48)
–50 –10 30–30 10 50 70 90 110
60
0
100
120
40
80
20
V
S
= ±12V
V
S
= ±5.0V
V
S
= ±2.5V
TEMPERATURE (°C)
SHORT-CIRCUIT CURRENT (mA)
01888-027
Figure 27. Short-Circuit Current to Ground vs. Temperature
G = 2
R
L
= 1kΩ, 150Ω
50
40
30
20
10
–10
–20
–30
–40
–50 120 160 200
TIME (ns)
80400
V
OUT
(mV)
01888-028
Figure 28. Small Signal Transient Response vs.
RL, VO = 50 mV p-p, Noninverting (See Figure 49)
AD8021
Rev. F | Page 13 of 28
R
L
= 150Ω
2.0
1.0
–1.0
–2.0
120 160 200
TIME (ns)
01888-029
R
L
= 1kΩ
V
O
= 4V p-p
G = 2
V
OUT
(V)
80400
Figure 29. Large Signal Transient Response vs. RL, Noninverting
(See Figure 49)
V
OUT
V
IN
5
4
3
2
1
–1
–2
–3
–4
–5
VOLTS
100 150 200 250
TIME (ns)
V
O
= 4V p-p
G = –1
01888-030
500
Figure 30. Large Signal Transient Response, Inverting (See Figure 50)
2.0
1.0
–1.0
–2.0
120 160 200
TIME (ns)
C
L
= 50pF
G = 2
C
L
= 10pF, 0pF
V
O
= 4V p-p
80400
01888-031
V
OUT
(V)
Figure 31. Large Signal Transient Response vs. CL (See Figure 48)
V
OUT
(V)
2.0
1.0
–1.0
–2.0
120 160 200
TIME (ns)
V
O
= 2V p-p
G = 2
V
S
= ±2.5V
V
S
= ±5V
80400
01888-032
Figure 32. Large Signal Transient Response vs. VS (See Figure 48)
V
IN
0 100 200 300 400 500
TIME (ns)
01888-033
V
IN
= ±3V
G = +2
V
IN
= 1V/DIV
V
OUT
= 2V/DIV
V
OUT
, R
L
= 1kΩ
R
L
= 150Ω
Figure 33. Overdrive Recovery vs. RL (See Figure 49)
25ns
–0.01%
+0.01%
HOR = 5ns/DIV
G = 2
OUTPUT SETTLING
01888-034
VERT = 0.2mV/DIV
Figure 34. 0.01% Settling Time, 2 V Step
AD8021
Rev. F | Page 14 of 28
TIME (µs)
12
SETTLING (µV)
20 28
–100 24
–80
–60
–40
–20
0
20
40
60
80
100
04 8 16 32
01888-035
PULSE WIDTH = 300µs
PULSE WIDTH = 120ns
t
1
5V
0V
Figure 35. Long-Term Settling, 0 V to 5 V, VS = ±12 V, G = +13
G = +1
50
40
30
20
10
–10
–20
–30
–40
–50 120 160 200
TIME (ns)
01888-036
80400
V
OUT
(mV)
Figure 36. Small Signal Transient Response, VO = 50 mV p-p, G = +1
(See Figure 48)
10M
FREQUENCY (Hz)
100
10
1
10 100 1k 10k 100k 1M
01888-037
VOLTAGE NOISE (nV/
√
Hz)
2.1nV/
√
Hz
Figure 37. Input Voltage Noise vs. Frequency
FREQUENCY (Hz)
100 10M1k 10k 100k
100
1
10
10 1M
01888-038
INPUT CURRENT NOISE (pA/√Hz)
Figure 38. Input Current Noise vs. Frequency
–25 10025
VOLTAGE OFFSET (mV)
50 75
0.48
0.24
–50 0
0.44
0.40
0.36
0.32
0.28
01888-039
TEMPERATURE (°C)
Figure 39. VOS vs. Temperature
–25 10025
INPUT BIAS CURRENT (
μ
A)
50 75
8.4
6.0
–50 0
8.0
7.6
7.2
6.8
6.4
01888-040
TEMPERATURE (°C)
Figure 40. Input Bias Current vs. Temperature
AD8021
Rev. F | Page 15 of 28
100k 10M 100M
–20
10k 1M
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
01888-041
FREQUENCY (Hz)
CMRR (dB)
Figure 41. CMRR vs. Frequency (See Figure 51)
100k 1G10M 100M
300
10k 1M
100
30
10
3
1
0.3
0.1
0.03
0.01
0.003
01888-042
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
Figure 42. Output Impedance vs. Frequency, Chip Enabled
(See Figure 52)
4V
2V
2V
1V
0 100 200 300 400 500
TIME (ns)
01888-043
V
OUTPUT
t
EN
= 45ns
t
DIS
= 50ns
DISABLE
Figure 43. Enable (tEN)/Disable (tDIS) Time vs. VOUT (See Figure 53)
1M 1G100M
0
0.1M 10M
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
01888-044
DISABLED ISOLATION (dB)
FREQUENCY (Hz)
Figure 44. Input-to-Output Isolation, Chip Disabled (See Figure 54)
01888-045
100k 1G10M 100M
300k
10k 1M
100k
30k
10k
3k
1k
300
100
30
10
3
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
Figure 45. Output Impedance vs. Frequency, Chip Disabled
(See Figure 55)
1M 500M100M10k 10M100k
PSRR (dB)
0
–10
–30
–50
–70
–80
–100
–20
–40
–60
–90
01888-046
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
FREQUENCY (Hz)
–PSRR
+PSRR
Figure 46. PSRR vs. Frequency and Supply Voltage
(See Figure 56 and Figure 57)
AD8021
Rev. F | Page 16 of 28
0 10050
8.5
–50 25
8.0
7.5
7.0
6.5
6.0
5.5
75–25
01888-047
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
Figure 47. Quiescent Supply Current vs. Temperature
AD8021
Rev. F | Page 17 of 28
TEST CIRCUITS
50Ω
–V
S
C
C
+V
S
5
R
S
R
O
R
D
R
F
C
F
R
G
R
IN
49.9Ω
50Ω CABLE
50Ω CABLE
01888-048
Figure 48. Noninverting Gain
FET
PROBE
5
50Ω
–VS
CC
+VS
RS
RL
RF
CF
RG
RIN
49.9Ω
50Ω CABLE
CL
01888-049
Figure 49. Noninverting Gain and FET Probe
5
50Ω
–V
S
C
C
+V
S
R
O
R
F
R
D
R
G
R
IN
49.9Ω
50Ω CABLE
49.9Ω
50Ω CABLE
01888-050
Figure 50. Inverting Gain
01888-051
HP8753D
50Ω
AD8021
499Ω499Ω
55.6Ω
499Ω
499Ω
49.9Ω
NETWORK
ANALYZER
CC
5
+VS
7pF
50Ω
–VS
Figure 51. CMRR
5
HP8753D
AD8021
100Ω
NETWORK
ANALYZER
C
C
+V
S
50Ω
–V
S
7pF
R
G
499ΩR
F
499Ω
01888-052
Figure 52. Output Impedance, Chip Enabled
01888-053
499Ω
AD8021
49.9Ω
49.9Ω
7pF
C
C
5
976Ω
1
8
1.0V
49.9Ω
499Ω
4V
53.6Ω
+V
S
–V
S
LOGIC REF
DISABLE
Figure 53. Enable/Disable
01888-054
7pF
5
1
8
HP8753D
50Ω
AD8021
499Ω499Ω
1kΩ
49.9Ω
NETWORK
ANALYZER
C
C
+V
S
50Ω
–V
S
49.9Ω
50Ω CABLE
FET
PROBE
LOGIC REF
DISABLE
Figure 54. Input-to-Output Isolation, Chip Disabled
AD8021
1
8
5
7pF
HP8753D
50Ω
100Ω
NETWORK
ANALYZER
C
C
+V
S
–V
S
01888-055
Figure 55. Output Impedance, Chip Disabled
AD8021
Rev. F | Page 18 of 28
5
BIAS
BNC HP8753D
NETWORK
ANALYZER
50Ω
50Ω
50ΩCABLE
49.9Ω, 5W
+V
S
+V
S
C
C
7pF
499Ω
976Ω
53.6Ω
–V
S
249Ω
499Ω
01888-056
Figure 56. Positive PSRR
49.9Ω
5W
499Ω
50ΩCABLE
–V
S
+V
S
C
C
7pF
499Ω
976Ω
53.6Ω
–V
S
249Ω
BIAS
BNC HP8753D
NETWORK
ANALYZER
50Ω
50Ω
5
01888-057
Figure 57. Negative PSRR
AD8021
Rev. F | Page 19 of 28
APPLICATIONS
The typical voltage feedback op amp is frequency stabilized
with a fixed internal capacitor, CINTERNAL, using dominant pole
compensation. To a first-order approximation, voltage feedback
op amps have a fixed gain bandwidth product. For example, if
its −3 dB bandwidth is 200 MHz for a gain of G = +1; at a gain
of G = +10, its bandwidth is only about 20 MHz. The AD8021 is
a voltage feedback op amp with a minimal CINTERNAL of about
1.5 pF. By adding an external compensation capacitor, CC, the
user can circumvent the fixed gain bandwidth limitation of
other voltage feedback op amps.
Unlike the typical op amp with fixed compensation, the
AD8021 allows the user to:
• Maximize the amplifier bandwidth for closed-loop gains
between 1 and 10, avoiding the usual loss of bandwidth
and slew rate.
• Optimize the trade-off between bandwidth and phase
margin for a particular application.
• Match bandwidth in gain blocks with different noise gains,
such as when designing differential amplifiers (as shown in
Figure 65).
FREQUENCY (Hz)
1M
OPEN-LOOP GAIN (dB)
100M
110
10k 10M
100
80
60
40
30
10
100k
90
70
50
20
1k 1G 10G
0
–10
180
135
45
90
0
PHASE (Degrees)
(B)
(C)
(A)
(A)
(C)
86
C
C
= 0pF
C
C
= 10pF
01888-058
(B)
Figure 58. Simplified Diagram of Open-Loop Gain and Phase Response
Figure 58 is the AD8021 gain and phase plot that has been
simplified for instructional purposes. Arrow A in Figure 58
shows a bandwidth of about 200 MHz and a phase margin at
about 60° when the desired closed-loop gain is G = +1 and
the value chosen for the external compensation capacitor is
CC = 10 pF. If the gain is changed to G = +10 and CC is fixed at
10 pF, then (as expected for a typical op amp) the bandwidth is
degraded to about 20 MHz and the phase margin increases to
90° (Arrow B). However, by reducing CC to 0 pF, the bandwidth
and phase margin return to about 200 MHz and 60° (Arrow C),
respectively. In addition, the slew rate is dramatically increased,
as it roughly varies with the inverse of CC.
1
2
3
4
5
6
7
8
9
10
0
NOISE GAIN (V/V)
12 3 4 5 6 7 8 91011
01888-059
COMPENSATION CAPACITANCE (pF)
Figure 59. Suggested Compensation Capacitance vs. Gain for
Maintaining 1 dB Peaking
Table 6 and Figure 59 provide recommended values of com-
pensation capacitance at various gains and the corresponding
slew rate, bandwidth, and noise. Note that the value of the
compensation capacitor depends on the circuit noise gain, not
the voltage gain. As shown in Figure 60, the noise gain, GN, of
an op amp gain block is equal to its noninverting voltage gain,
regardless of whether it is actually used for inverting or nonin-
verting gain. Thus,
Noninverting GN = RF/RG + 1
Inverting GN = RF/RG + 1
+
–
–
+
NONINVERTING
AD8021
3
25
6
1
RS
–VS
CCOMP
G = GN = +5
RF
1kΩ
RG
249Ω
AD8021
2
35
6
RF
1kΩ
RG
249Ω
–VS
CCOMP
G = –4
GN = +5
INVERTING
01888-060
Figure 60. The Noise Gain of Both is 5
AD8021
Rev. F | Page 20 of 28
CF = CL = 0, RL = 1 kΩ, RIN = 49.9 Ω (see Figure 49).
Table 6. Recommended Component Values
Noise Gain
(Noninverting
Gain) RS (Ω) RF (Ω) RG (Ω) CCOMP (pF) Slew Rate (V/μs)
−3 dB
SS BW
(MHz)
Output Noise
(AD8021 Only)
(nV/√Hz)
Output Noise
(AD8021 with Resistors)
(nV/√Hz)
1 75 75 NA 10 120 490 2.1 2.8
2 49.9 499 499 7 150 205 4.3 8.2
5 49.9 1 k 249 2 300 185 10.7 15.5
10 49.9 1 k 110 0 420 150 21.2 27.9
20 49.9 1 k 52.3 0 200 42 42.2 52.7
100 49.9 1 k 10 0 34 6 211.1 264.1
With the AD8021, a variety of trade-offs can be made to fine-
tune its dynamic performance. Sometimes more bandwidth
or slew rate is needed at a particular gain. Reducing the
compensation capacitance, as illustrated in Figure 7, increases
the bandwidth and peaking due to a decrease in phase margin.
On the other hand, if more stability is needed, increasing the
compensation capacitor decreases the bandwidth while
increasing the phase margin.
As with all high speed amplifiers, parasitic capacitance and
inductance around the amplifier can affect its dynamic
response. Often, the input capacitance (due to the op amp itself,
as well as the PC board) has a significant effect. The feedback
resistance, together with the input capacitance, can contribute
to a loss of phase margin, thereby affecting the high frequency
response, as shown in Figure 14. A capacitor (CF) in parallel
with the feedback resistor can compensate for this phase loss.
Additionally, any resistance in series with the source creates a
pole with the input capacitance (as well as dampen high
frequency resonance due to package and board inductance
and capacitance), the effect of which is shown in Figure 15.
It must also be noted that increasing resistor values increases
the overall noise of the amplifier and that reducing the feedback
resistor value increases the load on the output stage, thus
increasing distortion (see Figure 22).
USING THE DISABLE FEATURE
When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC
REFERENCE) by approximately 2 V or more, the part is
enabled. When Pin 8 is brought down to within about 1.5 V
of Pin 1, the part is disabled. See Table 1 for exact disable and
enable voltage levels. If the disable feature is not used, Pin 8 can
be tied to VS or a logic high source, and Pin 1 can be tied to
ground or logic low. Alternatively, if Pin 1 and Pin 8 are not
connected, the part is in an enabled state.
AD8021
Rev. F | Page 21 of 28
THEORY OF OPERATION
The AD8021 is fabricated on the second generation of Analog
Devices proprietary High Voltage eXtra-Fast Complementary
Bipolar (XFCB) process, which enables the construction of PNP
and NPN transistors with similar fTs in the 3 GHz region. The
transistors are dielectrically isolated from the substrate (and
each other), eliminating the parasitic and latch-up problems
caused by junction isolation. It also reduces nonlinear capaci-
tance (a source of distortion) and allows a higher transistor, fT,
for a given quiescent current. The supply current is trimmed,
which results in less part-to-part variation of bandwidth, slew
rate, distortion, and settling time.
As shown in Figure 61, the AD8021 input stage consists of an
NPN differential pair in which each transistor operates at a
0.8 mA collector current. This allows the input devices a high
transconductance; thus, the AD8021 has a low input noise of
2.1 nV/√Hz @ 50 kHz. The input stage drives a folded cascode
that consists of a pair of PNP transistors. The folded cascode
and current mirror provide a differential-to-single-ended
conversion of signal current. This current then drives the high
impedance node (Pin 5), where the CC external capacitor is
connected. The output stage preserves this high impedance with
a current gain of 5000, so that the AD8021 can maintain a high
open-loop gain even when driving heavy loads.
Two internal diode clamps across the inputs (Pin 2 and Pin 3)
protect the input transistors from large voltages that could
otherwise cause emitter-base breakdown, which would result in
degradation of offset voltage and input bias current.
+IN
–IN
C
INTERNAL
1.5pF
C
COMP
C
C
–V
S
+V
S
OUTPUT
01888-061
Figure 61. Simplified Schematic
PCB LAYOUT CONSIDERATIONS
As with all high speed op amps, achieving optimum performance
from the AD8021 requires careful attention to PC board layout.
Particular care must be exercised to minimize lead lengths
between the ground leads of the bypass capacitors and between
the compensation capacitor and the negative supply. Otherwise,
lead inductance can influence the frequency response and even
cause high frequency oscillations. Use of a multilayer printed
circuit board, with an internal ground plane, reduces ground
noise and enables a compact component arrangement.
Due to the relatively high impedance of Pin 5 and low values of
the compensation capacitor, a guard ring is recommended. The
guard ring is simply a PC trace that encircles Pin 5 and is
connected to the output, Pin 6, which is at the same potential as
Pin 5. This serves two functions. It shields Pin 5 from any local
circuit noise generated by surrounding circuitry. It also
minimizes stray capacitance, which would tend to otherwise
reduce the bandwidth. An example of a guard ring layout is
shown in Figure 62.
Also shown in Figure 62, the compensation capacitor is located
immediately adjacent to the edge of the AD8021 package, spanning
Pin 4 and Pin 5. This capacitor must be a high quality surface-
mount COG or NPO ceramic. The use of leaded capacitors is
not recommended. The high frequency bypass capacitor(s)
should be located immediately adjacent to the supplies,
Pin 4 and Pin 7.
To achieve the shortest possible lead length at the inverting
input, the feedback resistor RF is located beneath the board and
spans the distance from the output, Pin 6, to inverting input
Pin 2. The return node of Resistor RG should be situated as close
as possible to the return node of the negative supply bypass
capacitor connected to Pin 4.
DISABLE
V
OUT
8
7
6
1
2
3
LOGIC REFERENCE
–IN
+IN
–V
S
4
+V
S
5C
COMP
GROUND
PLANE
BYPASS
CAPACITOR
COMPENSATION
CAPACITOR
GROUND
PLANE
BYPASS
C
APACITO
R
METAL
(TOP VIEW)
01888-062
Figure 62. Recommended Location of
Critical Components and Guard Ring
AD8021
Rev. F | Page 22 of 28
DRIVING 16-BIT ADCs
Low noise and adjustable compensation make the AD8021
especially suitable as a buffer/driver for high resolution ADCs.
As seen in Figure 19, the harmonic distortion is better than 90 dBc
at frequencies between 100 kHz and 1 MHz. This is an
advantage for complex waveforms that contain high frequency
information, because the phase and gain integrity of the sampled
waveform can be preserved throughout the conversion process.
The increase in loop gain results in improved output regulation
and lower noise when the converter input changes state during
a sample. This advantage is particularly apparent when using
16-bit high resolution ADCs with high sampling rates.
Figure 63 shows a typical ADC driver configuration. The
AD8021 is in an inverting gain of −7.5, fC is 65 kHz, and its
output voltage is 10 V p-p. The results are listed in Table 7.
+
–
IN
HI
IN
HI
50Ω
R
G
200Ω
56pF
R
F
1.5kΩ
C
C
10pF
–12V
AD7665
570kSPS
16 BITS
+5V
6
5
3
2
590Ω
+12V
AD8021
01888-063
Figure 63. Inverting ADC Driver, Gain = −7.5, fC = 65 kHz
Table 7. Summary of ADC Driver Performance (fC = 65 kHz,
VOUT = 10 V p-p)
Parameter Measurement Unit
Second Harmonic Distortion −101.3 dBc
Third Harmonic Distortion −109.5 dBc
THD −100.0 dBc
SFDR +100.3 dBc
Figure 64 shows another ADC driver connection. The circuit
was tested with a noninverting gain of 10.1 and an output
voltage of approximately 20 V p-p for optimum resolution and
noise performance. No filtering was used. An FFT was
performed using Analog Devices evaluation software for the
AD7665 16-bit converter. The results are listed in Table 8.
50Ω
+5V
AD8021
+
–
–12V
+12V
AD7665
570kSPS
50Ω
3
2
R
F
750Ω
OPTIONAL C
F
IN
LO
IN
6
50Ω
HI
ADC
C
C
5
R
G
82.5Ω
16 BITS
01888-064
Figure 64. Noninverting ADC Driver, Gain = 10, fC = 100 kHz
Table 8. Summary of ADC Driver Performance
(fC = 100 kHz, VOUT = 20 V p-p)
Parameter Measurement Unit
Second Harmonic Distortion −92.6 dBc
Third Harmonic Distortion −86.4 dBc
THD −84.4 dBc
SFDR +5.4 dBc
DIFFERENTIAL DRIVER
The AD8021 is uniquely suited as a low noise differential driver
for many ADCs, balanced lines, and other applications requiring
differential drive. If pairs of internally compensated op amps are
configured as inverter and follower, the noise gain of the inverter
is higher than that of the follower section, resulting in an
imbalance in the frequency response (see Figure 66).
A better solution takes advantage of the external compensation
feature of the AD8021. By reducing the CCOMP value of the
inverter, its bandwidth can be increased to match that of the
follower, avoiding compromises in gain bandwidth and phase
delay. The inverting and noninverting bandwidths can be
closely matched using the compensation feature, thus
minimizing distortion.
Figure 65 illustrates an inverter-follower driver circuit operating
at a gain of 2, using individually compensated AD8021s. The
values of feedback and load resistors were selected to provide a
total load of less than 1 kΩ, and the equivalent resistances seen
at each op amp’s inputs were matched to minimize offset voltage
and drift. Figure 67 is a plot of the resulting ac responses of
driver halves.
AD8021
+
–
3
2
6
7pF
249Ω
499Ω
G = +2
499Ω
49.9Ω
1kΩ
VOUT1
5
–VS
AD8021
+
–
3
2
6
5pF
232ΩG = –2
664Ω
1kΩ
VOUT2
5
–VS
332Ω
VIN
01888-065
Figure 65. Differential Amplifier
AD8021
Rev. F | Page 23 of 28
G = –2
G = +2
GAIN (dB)
FREQUENCY (Hz)
100k 1M 10M 100M 1G
12
9
6
3
0
–3
–6
–9
–12
–15
–18
01888-066
Figure 66. AC Response of Two Identically Compensated High Speed Op
Amps Configured for a Gain of +2 and a Gain of −2
100k 1M 10M 100M 1G
FREQUENCY (Hz)
12
9
6
3
0
–3
–6
–9
–12
–15
–18
GAIN (dB)
01888-067
G = ±2
Figure 67. AC Response of Two Dissimilarly Compensated AD8021 Op Amps
(Figure 66) Configured for a Gain of +2 and a Gain of −2,
(Note the Close Gain Match)
USING THE AD8021 IN ACTIVE FILTERS
The low noise and high gain bandwidth of the AD8021 make it
an excellent choice in active filter circuits. Most active filter
literature provides resistor and capacitor values for various
filters but neglects the effect of the op amp’s finite bandwidth on
filter performance; ideal filter response with infinite loop gain is
implied. Unfortunately, real filters do not behave in this manner.
Instead, they exhibit finite limits of attenuation, depending on
the gain bandwidth of the active device. Good low-pass filter
performance requires an op amp with high gain bandwidth for
attenuation at high frequencies, and low noise and high dc gain
for low frequency, pass-band performance.
Figure 68 shows the schematic of a 2-pole, low-pass active filter
and lists typical component values for filters having a Bessel-
type response with a gain of 2 and a gain of 5. Figure 69 is a
network analyzer plot of this filter’s performance.
C
C
C2
AD8021
3
2
R
F
6V
OUT
R
G
+V
S
R2R1
V
IN
5
–V
S
C1
01888-068
Figure 68. Schematic of a Second-Order, Low-Pass Active Filter
Table 9. Typical Component Values for Second-Order, Low-
Pass Active Filter of Figure 68
Gain R1
(Ω)
R2
(Ω)
RF
(Ω)
RG
(Ω)
C1
(nF)
C2
(nF)
CC
(pF)
2 71.5 215 499 499 10 10 7
5 44.2 365 365 90.9 10 10 2
1k 10k 100k 1M 10M
FREQUENCY (Hz)
50
40
30
20
10
0
–10
–20
–30
–40
–50
GAIN (dB)
G = 2
G = 5
01888-069
Figure 69. Frequency Response of the Filter Circuit of Figure 68
for Two Different Gains
DRIVING CAPACITIVE LOADS
When the AD8021 drives a capacitive load, the high frequency
response can show excessive peaking before it rolls off. Two
techniques can be used to improve stability at high frequency
and reduce peaking. The first technique is to increase the
compensation capacitor, CC, which reduces the peaking while
maintaining gain flatness at low frequencies. The second
technique is to add a resistor, RSNUB, in series between the output
pin of the AD8021 and the capacitive load, C
B
L. shows
the response of the AD8021 when both C
Figure 70
C and RSNUBB are used to
reduce peaking. For a given CL, Figure 71 can be used to
determine the value of RSNUB that maintains 2 dB of peaking in
the frequency response. Note, however, that using R
B
SNUB attenuates
the low frequency output by a factor of RLOAD/(RSNUBB + RLOAD).
AD8021
Rev. F | Page 24 of 28
OBE
0.1 100010 100
FREQUENCY (MHz)
GAIN (dB)
18
16
14
12
10
8
6
4
2
0
499
Ω
499
Ω
1k
Ω
49.9
Ω
49.9
Ω
C
C
33pF
FET
PR
–V
S
R
SNUB
+V
S
5
6
1.0
01888-070
C
C
= 7pF;
R
SNUB
= 0
Ω
C
C
= 8pF;
R
SNUB
= 0
Ω
C
C
= 8pF;
R
SNUB
= 17.4
Ω
R
L
Figure 70. Peaking vs. RSNUB and CC for CL = 33 pF
20
18
16
14
12
10
8
6
4
2
0
CAPACITIVE LOAD (pF)
0 5 10 20 25 30 35 40 45 5015
R
SNUB
(Ω)
01888-071
Figure 71. Relationship of RSNUB vs. CBL for 2 dB Peaking at a Gain of +2
AD8021
Rev. F | Page 25 of 28
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) × 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 72. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 73. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8021AR −40°C to +85°C 8-Lead SOIC R-8
AD8021AR-REEL −40°C to +85°C 8-Lead SOIC R-8
AD8021AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8
AD8021ARZ1−40°C to +85°C 8-Lead SOIC R-8
AD8021ARZ-REEL1−40°C to +85°C 8-Lead SOIC R-8
AD8021ARZ-REEL71−40°C to +85°C 8-Lead SOIC R-8
AD8021ARM −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 HNA
AD8021ARMZ1−40°C to +85°C 8-Lead MSOP RM-8 HNA#
AD8021ARMZ-REEL1−40°C to +85°C 8-Lead MSOP RM-8 HNA#
AD8021ARMZ-REEL71−40°C to +85°C 8-Lead MSOP RM-8 HNA#
1Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
AD8021
Rev. F | Page 26 of 28
NOTES
AD8021
Rev. F | Page 27 of 28
NOTES
AD8021
Rev. F | Page 28 of 28
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01888-0-5/06(F)
