74LVTH16244MTDX - FAIRCHILD SEMICONDUCTOR

March 1999

Revised June 2005

74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs

74LVT16244 • 74LVTH16244

Low Voltage16-Bit Buffer/Line Driv er

with 3-STATE Outputs

General Descript ion

The LVT16244 and LVTH16244 contain sixteen non-invert-

ing buffers with 3-S TATE outputs designed to b e em ployed

as a memory and address driver, clock driver, or bus ori-

ented trans mitter/receiver. The device is nibb le contro lled.

Individual 3-STATE control inputs can be shorted togeth er

for 8-bit or 16-bit operation.

The LVTH16244 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These buffers an d lin e dr i vers are de signed for low -vo ltage

(3.3V) VCC applications, but with the capability to provide a

TTL interface to a 5V environment. The LVT16244 and

LVTH16244 are fabricated with an advanced BiCMOS

technology to achieve high speed operation similar to 5V

ABT while maintaining a low power dissipation

Features

■Input and output interface capability to systems at

5V VCC

■Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16244),

also availabl e wi tho ut bush old feat ure (74LVT16244 ).

■Live insertion /extracti on per mitt ed

■Power Up/Down high impedance provides glitch-free

bus loading

■Outputs source/sink



32 mA/



64 mA

■Functionally compatible with the 74 series 16244

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human-body model

2000V

Machine model

200V

Charged-drive model

1000V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Ordering Code:

Note 1: Order ing code “G” indicat es T r a ys.

Note 2: Device also av ailable in Tape and R eel. Specify by appending suffix lette r “X” to the ord ering code.

Logic Symbol

Order Number Package

Number Pac kag e Descript ion

74LVT16244G

(Note 1)(Note 2) BGA54A

(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LVT16244MEA

(Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVT16244MTD

(Note 2) MTD48 4 8-Lead Thin Shrink Sm all Outline Pa ckage (TSSOP), JEDEC M O-153, 6.1mm Wide

74LVTH16244G

(Note 1)(Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LVTH16244MEA

(Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LVTH16244MTD

(Note 2) MTD48 4 8-Lead Thin Shrink Sm all Outline Pa ckage (TSSOP), JEDEC M O-153, 6.1mm Wide

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74LVT16244 • 74LVTH16244

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBGA

(Top Thru View)

Logic Diagram

Pin Descriptions

FBGA Pin Assignments

Truth Table

High Voltage Level

Low Voltage Level

Immaterial

High Impedance

Functional Description

The LVT16244 and LVTH16244 contain sixteen non-invert-

ing buffers with 3-STATE outputs. The device is nibble

(4-bits) controlled with each nibble functioning identically,

but independent of the other. The control pins can be

shorted together to obtain full 16-bit operation.

Pin Nam es Descr ipt i on

OEnOutput Enable Inputs (Active LOW)

I0–I15 Inputs

O0–O15 Outputs

NC No Connect

123456

AO0NC OE1OE2NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE4OE3NC I15

Inputs Outputs

OE1I0–I3O0–O3

LL L

LH H

HX Z

Inputs Outputs

OE2I4–I7O4–O7

LL L

LH H

HX Z

Inputs Outputs

OE3I8–I11 O8–O11

LL L

LH H

HX Z

Inputs Outputs

OE4I12–I15 O12–O15

LL L

LH H

HX Z

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74LVT16244 • 74LVTH16244

Absolute Maximum Ratings(Note 3)

Recommended Operating Conditions

Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or cond ition s

beyond th os e indicate d m ay adversely affect device re liability. Fun c ti onal opera t ion under a bs olute ma xi m um rated con dit ions is not implie d.

Note 4: IO Absolu te Maximu m Rating must be observed.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



4.6 V

VIDC Input Vo ltage



0.5 to



7.0 V

VOOutput Voltage



0.5 to



7.0 Output in 3-STATE V



0.5 to



7.0 Output in HIGH or LOW State (Note 4)

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA

IODC Output Current 64 VO

VCC Output at HIGH State mA

128 VO

VCC Output at LOW State

ICC DC Supply Current per Supply Pin

64 mA

IGND DC Ground Current per Ground Pin

128 mA

TSTG Storage Temperature



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage 2.7 3.6 V

VIInput Voltage 0 5.5 V

IOH HIGH Level Output Curr en t



32 mA

IOL LOW Level Output Current 64 mA

TAFree Air Operating Temperature





V Input Edge Rate, VIN

0.8V–2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Min Max

VIK Input Clamp Diode Voltage 2.7



1.2 V II



18 mA

VIH Input HIGH Voltage 2.7–3.6 2.0 V VO

0.1V or

VIL Input LOW Voltage 2.7–3.6 0.8 V VO

VCC



0.1V

VOH Output HIGH Voltage 2.7–3.6 VCC



0.2 VIOH



100

2.7 2.4 IOH



8 mA

3.0 2.0 IOH



32 mA

VOL Output LOW Voltage 2.7 0.2

IOL

100

2.7 0.5 IOL

24 mA

3.0 0.4 IOL

16 mA

3.0 0.5 IOL

32 mA

3.0 0.55 IOL

64 mA

II(HOLD) Bushold Input Minimum Drive 3.0 75

AVI

0.8V

(Note 5)



75 VI

2.0V

II(OD) Bushold Input Over-Drive 3.0 500

A(Note 6)

(Note 5) Current to Change State



500 (Note 7)

IIInput Current 3.6 10

5.5V

Control Pins 3.6

0V or VCC

Data Pins 3.6



VCC

IOFF Power Off Leakage Current 0

100

A0V

VI or VO

5.5V

IPU/PD Power Up/Down 0 – 1.5V

100

AVO

0.5V to 3.0V

3-STATE Current VI

GND or VCC

IOZL 3-STATE Output Leakage Current 3.6



0.5V

IOZH 3-STATE Output Leakage Current 3.6 5

3.0V

IOZH



3-STATE Output Leakage Current 3.6 10



5.5V

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74LVT16244 • 74LVTH16244

DC Electrical Characteristics (Continued)

Note 5: Applies to bushold versions only (LVTH16244).

Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.

Note 7: An external driver m us t s ink at least the sp ec if ied current to switc h f rom H I GH-to-LOW.

Note 8: This is the inc rease in s upply curr ent f or each in put that is at t he s pecified vo lta ge level rath er than VCC or GND.

Dynamic Switching Characteri stics (Note 9)

Note 9: Charact eriz ed in SSOP packa ge. Guaranteed parameter, but not test ed.

Note 10: Max number of ou tp uts defined as (n). n



1 data inpu ts are driven 0V to 3V. Output un der test h eld LOW.

AC Electrical Characteristics

Note 1 1: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specif ic ation ap plies to an y o ut puts switch ing in the same direc t ion, either HIGH-to- LOW (tOSHL) or LO W-to-HIGH (t OSLH).

Cap acitance (Note 12)

Note 12: Capacitance is measured at frequ ency f

1 MHz, per MIL-ST D -883, M et hod 3012 .

Symbol Parameter VCC TA



C to



CUnits Conditions

(V) Min Max

ICCH Power Supply Current 3.6 0.19 mA Outputs High

ICCL Power Supply Current 3.6 5.0 mA Outputs Low

ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled

ICCZ



Power Supply Current 3.6 0.19 mA VCC

5.5V,

Outputs Disabled

ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC



0.6V

(Note 8) Other Inputs at VCC or GND

Symbol Parameter VCC TA

CUnits Conditions

(V) Min Typ Max CL

50 pF, RL

500

VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10)

VOLV Quiet Output Minimum Dynamic VOL 3.3



0.8 V (Note 10)

Symbol Parameter



C to



Units

50 pF, RL

500

VCC

3.3V

0.3V V CC

2.7V

Min Max Min Max

tPLH Propagation Delay Data to Output 1.2 3.5 1.2 3.9 ns

tPHL 1.2 3.5 1.2 3.9

tPZH Output Enable Time 1.2 4.0 1.2 5.0 ns

tPZL 1.2 5.0 1.2 6.5

tPHZ Output Disable Time 2.0 4.7 2.0 5.2 ns

tPLZ 1.5 4.2 1.5 4.4

tOSHL Output to Output Skew 1.0 1.0 ns

tOSLH (Note 11)

Symbol Parameter Conditions Typical Units

CIN Input Capacit ance VCC

0V, VI

0V or VCC 4pF

COUT Output Capacitance VCC

3.0V, VO

0V or VCC 8pF

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74LVT16244 • 74LVTH16244

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA54 A

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74LVT16244 • 74LVTH16244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Packag e Num b er MS48A

7 www.fairchildsemi.com

74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide

Package Number MTD48

Fairchild does not assum e any responsibility for use of any circuitry described, n o circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.