USB5826 6-Port USB 3.1 Gen 1 Smart Hub with Support for Dual USB Type-CTM DFPs Highlights * USB Hub Feature Controller IC Hub with: - 2 USB 3.1 Gen 1 USB Type-CTM downstream ports 2 USB 3.1 Gen 1 legacy downstream ports 2 USB 2.0 downstream ports Legacy upstream port * USB-IF Battery Charger revision 1.2 support on up & downstream ports (DCP, CDP, SDP) * Internal Hub Feature Controller device enables: - USB to I2C/SPI/GPIO bridge endpoint support - USB to internal hub register write and read * USB Link Power Management (LPM) support * Enhanced OEM configuration options available through either OTP or SPI ROM * Available in 100-pin (12mm x 12mm) VQFN RoHS compliant package * Commercial and industrial grade temperature support Target Applications * * * * * Standalone USB Hubs Laptop Docks PC Motherboards PC Monitor Docks Multi-function USB 3.1 Gen 1 Peripherals * Supports battery charging of most popular battery powered devices on all ports - USB-IF Battery Charging rev. 1.2 support (DCP, CDP, SDP) - Apple(R) portable product charger emulation - Chinese YD/T 1591-2006 charger emulation - Chinese YD/T 1591-2009 charger emulation - European Union universal mobile charger support - Support for Microchip UCS100x family of battery charging controllers - Supports additional portable devices * Smart port controller operation - Firmware handling of companion port power controllers * On-chip microcontroller - manages I/Os, VBUS, and other signals * 8 KB RAM, 64 KB ROM * 8 KB One-Time-Programmable (OTP) ROM - Includes on-chip charge pump * Configuration programming via OTP ROM, SPI ROM, or SMBus * PortSwap - Configurable USB 2.0 differential pair signal swap * PHYBoostTM - Programmable USB transceiver drive strength for recovering signal integrity Key Benefits * VariSenseTM * USB 3.1 Gen 1 compliant 5 Gbps, 480 Mbps, 12 Mbps, and 1.5Mbps operation * Port Split - 5V tolerant USB 2.0 pins - 1.32V tolerant USB 3.1 Gen 1 pins - Integrated termination and pull-up/down resistors * Native USB Type-C Support - Integrated Multiplexer on USB Type-C enabled ports - USB 3.1 Gen 1 PHYs are disabled until a valid USB Type-C attach is detected, saving idle power - Programmable USB receive sensitivity - USB2.0 and USB3.1 Gen1 port operation can be split for custom applications using embedded USB3.x devices in parallel with USB2.0 devices. * USB Power Delivery Billboard Device Support - Internal port can enumerate as a Power Delivery Billboard device to communicate Power Delivery Alternate Mode negotiation failure cases to USB host * Compatible with Microsoft Windows 10, 8, 7, XP, Apple OS X 10.4+, and Linux hub drivers * Optimized for low-power operation and low thermal dissipation * Package - 100-pin VQFN (12mm x 12mm) 2016-2018 Microchip Technology Inc. DS00002239D-page 1 USB5826 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00002239D-page 2 2016-2018 Microchip Technology Inc. USB5826 TABLE OF CONTENTS Introduction ........................................................................................................................................................................................... 7 Pin Descriptions and Configuration ....................................................................................................................................................... 6 Functional Descriptions ......................................................................................................................................................................... 9 Operational Characteristics................................................................................................................................................................. 13 System Application ............................................................................................................................................................................. 19 Package Outlines ................................................................................................................................................................................ 26 Revision History ................................................................................................................................................................................... 29 The Microchip Web Site ...................................................................................................................................................................... 30 Customer Change Notification Service ............................................................................................................................................... 30 Customer Support ............................................................................................................................................................................... 30 Product Identification System ............................................................................................................................................................. 31 2016-2018 Microchip Technology Inc. DS00002239D-page 3 USB5826 1.0 PREFACE 1.1 General Terms TABLE 1-1: GENERAL TERMS Term Description ADC Analog-to-Digital Converter Byte 8 bits CDC Communication Device Class CSR Control and Status Registers DWORD 32 bits EOP End of Packet EP Endpoint FIFO First In First Out buffer FS Full-Speed FSM Finite State Machine GPIO General Purpose I/O HS Hi-Speed HSOS High Speed Over Sampling Hub Feature Controller The Hub Feature Controller, sometimes called a Hub Controller for short is the internal processor used to enable the unique features of the USB Controller Hub. This is not to be confused with the USB Hub Controller that is used to communicate the hub status back to the Host during a USB session. I2C Inter-Integrated Circuit LS Low-Speed lsb Least Significant Bit LSB Least Significant Byte msb Most Significant Bit MSB Most Significant Byte N/A Not Applicable NC No Connect OTP One Time Programmable PCB Printed Circuit Board PCS Physical Coding Sublayer PHY Physical Layer PLL Phase Lock Loop RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. SDK Software Development Kit SMBus System Management Bus UUID Universally Unique IDentifier WORD 16 bits DS00002239D-page 4 2016-2018 Microchip Technology Inc. USB5826 1.2 1. 2. 3. 4. 5. Reference Documents UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http:// www.usb.org Universal Serial Bus Revision 3.1 Specification, http://www.usb.org Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org I2C-Bus Specification, Version 1.1, http://www.nxp.com System Management Bus Specification, Version 1.0, http://smbus.org/specs 2016-2018 Microchip Technology Inc. DS00002239D-page 5 USB5826 2.0 INTRODUCTION 2.1 General Description The Microchip USB5826 hub is a low-power, OEM configurable, USB 3.1 Gen 1 hub controller with 6 downstream ports and advanced features for embedded USB applications. The USB5826 is fully compliant with the Universal Serial Bus Revision 3.1 Specification and USB 2.0 Link Power Management Addendum. The USB5826 supports 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB downstream devices on all enabled downstream ports. The USB5826 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the culmination of five generations of Microchip hub controller design and experience with proven reliability, interoperability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 hub controller, decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic. The USB5826 hub feature controller enables OEMs to configure their system using "Configuration Straps." These straps simplify the configuration process, assigning default values to USB 3.1 Gen 1 ports and GPIOs. OEMs can disable ports, enable battery charging, and define GPIO functions as default assignments on power-up, removing the need for OTP or external SPI ROM. The USB5826 supports downstream battery charging via the integrated battery charger detection circuitry, which supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5826 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles: * * * * DCP: Dedicated Charging Port (Power brick with no data) CDP: Charging Downstream Port (1.5A with data) SDP: Standard Downstream Port (0.5A with data) Custom profiles loaded via SMBus or OTP Additionally, the USB5826 includes many powerful and unique features such as: The Hub Feature Controller, which provides an internal USB device dedicated for use as a USB to I2C/UART/SPI/ GPIO interface, allowing external circuits or devices to be monitored, controlled, or configured via the USB interface. PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the PCB. PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity in a compromised system environment. The graphic on the right shows an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in a compromised system environment. VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used. Port Split, which allows for the USB3.1 Gen1 and USB2.0 portions of downstream ports 3 and 4 to operate independently and enumerate two separate devices in parallel in special applications. USB Power Delivery Billboard Device, which allows an internal device to enumerate as a Billboard class device when a Power Delivery Alternate Mode negotiation has failed. The Billboard device will enumerate temporarily to the host PC when a failure occurs, as indicated by a digital signal from an external Power Delivery controller. The USB5826 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow for maximum operational flexibility, and are available as GPIOs for customer specific use. The USB5826 is available in commercial (0C to +70C) and industrial (-40C to +85C) temperature ranges. An internal block diagram of the USB5826 is shown in Figure 2-1. DS00002239D-page 6 2016-2018 Microchip Technology Inc. USB5826 FIGURE 2-1: INTERNAL BLOCK DIAGRAM P0 `B' I2C from Master +3.3 V I2C/SMB AFE0 AFE0 USB3 USB2 +1.2 V Hub Controller Logic 25 Mhz AFE1 AFE1 AFE1 AFE2 AFE1 AFE2 AFE2 AFE3 AFE3 AFE4 AFE4 AFE5 AFE6 AFE7 OTP Hub Feature Controller GPIO P1 `C' 2016-2018 Microchip Technology Inc. P2 `C' P3 `A' P4 `A' P5 `A' SMB SPI P6 `A' DS00002239D-page 7 USB5826 3.0 PIN DESCRIPTIONS 3.1 Pin Diagram HOST_TYPE0/GPIO23 PRT_CTL3/GPIO21 PRT_CTL4/GPIO22 51 VDD33 54 52 HOST_TYPE1/GPIO67 55 53 PRT_CTL6/GANG_PWR/GPIO20 C_ATTACH2/ATTACHMUX2A/GPIO2 56 58 57 VDD12 PRT_CTL2/GPIO19 59 CC_POL/GPIO71 PRT_CTL5/GPIO18 62 GPIO3 ALT_MUX_EN/GPIO70 63 60 VDD33 64 61 SPI_DO/GPIO5 SPI_CLK/GPIO4 65 SPI_DI/GPIO9/CFG_BC_EN 67 66 GPIO69 SPI_CE_N/GPIO7/CFG_NON_REM 68 PRT_CTL1/GPIO17 70 69 VDD33 AB2/ATTACHMUX2B/GPIO66 71 C_ATTACH1/ATTACHMUX1A/GPIO1 73 72 SMBCLK/GPIO8 SMBDATA/GPIO6 74 PIN ASSIGNMENTS (TOP VIEW) 75 FIGURE 3-1: C_ATTACH0/GPIO64 76 50 AB1/ATTACHMUX1B/GPIO65 SUSP_IND/GPIO68 77 49 USB3DN_RXDM3 VDD12 78 48 USB3DN_RXDP3 NC 79 47 VDD12 NC 80 46 USB3DN_TXDM3 NC 81 45 USB3DN_TXDP3 NC 82 44 USB2DN_DM3/PRT_DIS_M3 VDD12 83 43 USB2DN_DP3/PRT_DIS_P3 NC 84 42 VDD33 NC 85 41 USB3DN_RXDM2B 40 USB3DN_RXDP2B USB2DN_DP4/PRT_DIS_P4 86 USB2DN_DM4/PRT_DIS_M4 87 USB3DN_TXDP4 88 USB3DN_TXDM4 89 VDD12 90 36 USB2DN_DM6/PRT_DIS_M6 USB3DN_RXDP4 91 35 USB2DN_DP6/PRT_DIS_P6 USB3DN_RXDM4 92 34 USB3DN_RXDM2A VDD33 93 33 USB3DN_RXDP2A USB2UP_DP 94 32 VDD12 USB2UP_DM 95 31 USB3DN_TXDM2A Microchip USB5826 (Top View 100-VQFN) thermal slug connects to VSS 39 VDD12 38 USB3DN_TXDM2B 37 USB3DN_TXDP2B 23 24 25 TESTEN VBUS_DET/GPIO16 RESET_N 18 22 17 VDD12 USB3DN_RXDP1B 21 16 USB3DN_TXDM1B GPIO72 15 USB3DN_TXDP1B GPIO10 14 USB2DN_DM5/PRT_DIS_M5 20 13 19 12 USB3DN_RXDM1A USB2DN_DP5/PRT_DIS_P5 USB3DN_RXDM1B 11 USB3DN_RXDP1A GPIO12/CFG_STRAP 9 10 VDD12 8 USB3DN_TXDP1A USB3DN_TXDM1A 7 VDD12 6 26 USB2DN_DP1/PRT_DIS_P1 100 USB2DN_DM1/PRT_DIS_M1 VDD33 USB3UP_RXDM 5 27 VDD33 99 4 USB2DN_DP2/PRT_DIS_P2 USB3UP_RXDP 3 28 XTALO 98 XTALI/CLKIN USB2DN_DM2/PRT_DIS_M2 VDD12 2 USB3DN_TXDP2A 29 1 30 97 RBIAS 96 VDD33 USB3UP_TXDP USB3UP_TXDM Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 3.5, Configuration Straps and Programmable Functions DS00002239D-page 8 2016-2018 Microchip Technology Inc. USB5826 3.2 Pin Symbols Pin Num. Pin Name Reset Pin Num. Pin Name Reset 1 RBIAS A/P 51 PRT_CTL4/GPIO22 PD-50k 2 VDD33 A/P 52 PRT_CTL3/GPIO21 PD-50k 3 XTALI/CLKIN A/P 53 HOST_TYPE0/GPIO23 PD-50k 4 XTALO A/P 54 VDD33 A/P 5 VDD33 A/P 55 HOST_TYPE1/GPIO67 Z 6 USB2DN_DP1/PRT_DIS_P1 PD-15k 56 C_ATTACH2/ATTACHMUX2A/GPIO2 Z 7 USB2DN_DM1/PRT_DIS_M1 PD-15k 57 PRT_CTL6/GANG_PWR/GPIO20 PD-50k 8 USB3DN_TXDP1A Z 58 PRT_CTL2/GPIO19 PD-50k 9 USB3DN_TXDM1A Z 59 VDD12 A/P 10 VDD12 A/P 60 GPIO3 Z 11 USB3DN_RXDP1A Z 61 CC_POL/GPIO71 Z 12 USB3DN_RXDM1A Z 62 PRT_CTL5/GPIO18 PD-50k 13 USB2DN_DP5/PRT_DIS_P5 PD-15k 63 ALT_MUX_EN/GPIO70 Z 14 USB2DN_DM5/PRT_DIS_M5 PD-15k 64 VDD33 A/P 15 USB3DN_TXDP1B Z 65 SPI_CLK/GPIO4 Z 16 USB3DN_TXDM1B Z 66 SPI_DO/GPIO5 PD-50k 17 VDD12 A/P 67 SPI_DI/GPIO9/CFG_BC_EN Z 18 USB3DN_RXDP1B Z 68 SPI_CE_N/GPIO7/CFG_NON_REM PU-50k 19 USB3DN_RXDM1B Z 69 GPIO69 Z 20 GPIO12/CFG_STRAP Z 70 PRT_CTL1/GPIO17 PD-50k 21 GPIO10 Z 71 AB2/ATTACHMUX2B/GPIO66 Z 22 GPIO72 Z 72 VDD33 A/P 23 TESTEN Z 73 C_ATTACH1/ATTACHMUX1A/GPIO1 Z 24 VBUS_DET/GPIO16 Z 74 SMBDATA/GPIO6 Z 25 RESET_N R 75 SMBCLK/GPIO8 Z 26 VDD12 A/P 76 C_ATTACH0/GPIO64 Z 27 VDD33 A/P 77 SUSP_IND/GPIO68 Z 28 USB2DN_DP2/PRT_DIS_P2 PD-15k 78 VDD12 A/P 29 USB2DN_DM2/PRT_DIS_M2 PD-15k 79 NC PD-15k 30 USB3DN_TXDP2A Z 80 NC PD-15k 31 USB3DN_TXDM2A Z 81 NC Z 32 VDD12 A/P 82 NC Z 33 USB3DN_RXDP2A Z 83 VDD12 A/P Z 34 USB3DN_RXDM2A Z 84 NC 35 USB2DN_DP6/PRT_DIS_P6 PD-15k 85 NC Z 36 USB2DN_DM6/PRT_DIS_M6 PD-15k 86 USB2DN_DP4/PRT_DIS_P4 PD-15k 37 USB3DN_TXDP2B Z 87 USB2DN_DM4/PRT_DIS_M4 PD-15k 38 USB3DN_TXDM2B Z 88 USB3DN_TXDP4 Z 39 VDD12 A/P 89 USB3DN_TXDM4 Z 40 USB3DN_RXDP2B Z 90 VDD12 A/P 41 USB3DN_RXDM2B Z 91 USB3DN_RXDP4 Z 42 VDD33 A/P 92 USB3DN_RXDM4 Z 43 USB2DN_DP3/PRT_DIS_P3 PD-15k 93 VDD33 A/P 44 USB2DN_DM3/PRT_DIS_M3 PD-15k 94 USB2UP_DP PD-1M 45 USB3DN_TXDP3 Z 95 USB2UP_DM PD-1M 46 USB3DN_TXDM3 Z 96 USB3UP_TXDP Z 47 VDD12 A/P 97 USB3UP_TXDM Z 48 USB3DN_RXDP3 Z 98 VDD12 A/P 49 USB3DN_RXDM3 Z 99 USB3UP_RXDP Z 50 AB1/ATTACHMUX1B/GPIO65 Z 100 USB3UP_RXDM Z 2016-2018 Microchip Technology Inc. DS00002239D-page 9 USB5826 The pin reset state definitions are detailed in Table 3-1. TABLE 3-1: PIN RESET STATE LEGEND Symbol 3.3 Description A/P Analog/Power Input R Reset Control Input Z Hardware disables output driver (high impedance) PU-50k Hardware enables internal 50k pull-up PD-50k Hardware enables internal 50k pull-down PD-15k Hardware enables internal 15k pull-down PD-1M Hardware enables internal 1M pull-down USB5826 Pin Descriptions This section contains descriptions of the various USB5826 pins. The pin descriptions have been broken into functional groups as follows: * * * * * * * * USB 3.1 Gen 1 Pin Descriptions USB 2.0 Pin Descriptions Port Control Pin Descriptions SPI Interface USB Type-C Connector Controls Miscellaneous Pin Descriptions Configuration Strap Pin Descriptions Power and Ground Pin Descriptions The "_N" symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When "_N" is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signal. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive. TABLE 3-2: USB 3.1 GEN 1 PIN DESCRIPTIONS Name Symbol Buffer Type USB 3.1 Gen 1 Upstream D+ TX USB3UP_TXDP I/O-U Upstream USB 3.1 Gen 1 Transmit Data Plus USB 3.1 Gen 1 Upstream D- TX USB3UP_TXDM I/O-U Upstream USB 3.1 Gen 1 Transmit Data Minus USB 3.1 Gen 1 Upstream D+ RX USB3UP_RXDP I/O-U Upstream USB 3.1 Gen 1 Receive Data Plus USB 3.1 Gen 1 Upstream D- RX USB3UP_RXDM I/O-U Upstream USB 3.1 Gen 1 Receive Data Minus DS00002239D-page 10 Description 2016-2018 Microchip Technology Inc. USB5826 TABLE 3-2: USB 3.1 GEN 1 PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type USB 3.1 Gen 1 Ports 4-3 D+ TX USB3DN_TXDP[4:3] I/O-U Downstream Super Speed Transmit Data Plus, ports 4 through 3. USB 3.1 Gen 1 Ports 4-3 D- TX USB3DN_TXDM[4:3] I/O-U Downstream Super Speed Transmit Data Minus, ports 4 through 3. USB 3.1 Gen 1 Ports 4-3 D+ RX USB3DN_RXDP[4:3] I/O-U Downstream Super Speed Receive Data Plus, ports 4 through 3. USB 3.1 Gen 1 Ports 4-3 D- RX USB3DN_RXDM[4:3] I/O-U Downstream Super Speed Receive Data Minus, ports 4 through 3. USB 3.1 Gen 1 Ports 2-1 A D+ TX USB3DN_TXDP[2:1]A I/O-U Downstream USB Type-C "Orientation A" Super Speed Transmit Data Plus, ports 2 through 1. USB 3.1 Gen 1 Ports 2-1 A D- TX USB3DN_TXDM[2:1]A I/O-U Downstream USB Type-C "Orientation A" Super Speed Transmit Data Minus, ports 2 through 1. USB 3.1 Gen 1 Ports 2-1 A D+ RX USB3DN_RXDP[2:1]A I/O-U Downstream USB Type-C "Orientation A" Super Speed Receive Data Plus, ports 2 through 1. USB 3.1 Gen 1 Ports 2-1 A D- RX USB3DN_RXDM[2:1]A I/O-U Downstream USB Type-C "Orientation A" Super Speed Receive Data Minus, ports 2 through 1. USB 3.1 Gen 1 Ports 2-1 B D+ TX USB3DN_TXDP[2:1]B I/O-U Downstream USB Type-C "Orientation B" Super Speed Transmit Data Plus, ports 2 through 1. USB 3.1 Gen 1 Ports 2-1 B D- TX USB3DN_TXDM[2:1]B I/O-U Downstream USB Type-C "Orientation B" Super Speed Transmit Data Minus, ports 2 through 1. USB 3.1 Gen 1 Ports 2-1 B D+ RX USB3DN_RXDP[2:1]B I/O-U Downstream USB Type-C "Orientation B" Super Speed Receive Data Plus, ports 2 through 1. USB 3.1 Gen 1 Ports 2-1 B D- RX USB3DN_RXDM[2:1]B I/O-U Downstream USB Type-C "Orientation B" Super Speed Receive Data Minus, ports 2 through 1. 2016-2018 Microchip Technology Inc. Description DS00002239D-page 11 USB5826 TABLE 3-3: USB 2.0 PIN DESCRIPTIONS Name Symbol Buffer Type Description USB 2.0 Upstream D+ USB2UP_DP I/O-U Upstream USB 2.0 Data Plus (D+) USB 2.0 Upstream D- USB2UP_DM I/O-U Upstream USB 2.0 Data Minus (D-) USB 2.0 Ports 6 D+ USB2DN_DP[6:1] I/O-U Downstream USB 2.0 Ports 6-1 Data Plus (D+) USB 2.0 Ports 6 D- USB2DN_DM[6:1] I/O-U Downstream USB 2.0 Ports 6-1 Data Minus (D-) VBUS Detect VBUS_DET IS This signal detects the state of the upstream bus power. When designing a detachable hub, this pin must be connected to the VBUS power pin of the upstream USB port through a resistor divider (50 k by 100 k) to provide 3.3 V. For self-powered applications with a permanently attached host, this pin must be connected to either 3.3 V or 5.0 V through a resistor divider to provide 3.3 V. In embedded applications, VBUS_DET may be controlled (toggled) when the host desires to renegotiate a connection without requiring a full reset of the device. TABLE 3-4: PORT CONTROL PIN DESCRIPTIONS Name Symbol Port 6 Power Enable / Overcurrent Sense PRT_CTL6 Buffer Type I/OD12 (PU) Description Port 6 Power Enable / Overcurrent Sense. When the downstream port is enabled, this pin is set as an input with an internal pull-up resistor applied. The internal pull-up enables power to the downstream port while the pin monitors for an active low overcurrent signal assertion from an external current monitor on USB port 6. This pin will change to an output and be driven low when the port is disabled by configuration or by the host control. DS00002239D-page 12 2016-2018 Microchip Technology Inc. USB5826 TABLE 3-4: PORT CONTROL PIN DESCRIPTIONS (CONTINUED) Name Symbol Port 5 Power Enable / Overcurrent Sense PRT_CTL5 Buffer Type I/OD12 (PU) Description Port 5 Power Enable / Overcurrent Sense. When the downstream port is enabled, this pin is set as an input with an internal pull-up resistor applied. The internal pull-up enables power to the downstream port while the pin monitors for an active low overcurrent signal assertion from an external current monitor on USB port 5. This pin will change to an output and be driven low when the port is disabled by configuration or by the host control. Port 4 Power Enable / Overcurrent Sense PRT_CTL4 I/OD12 (PU) Port 4 Power Enable / Overcurrent Sense. When the downstream port is enabled, this pin is set as an input with an internal pull-up resistor applied. The internal pull-up enables power to the downstream port while the pin monitors for an active low overcurrent signal assertion from an external current monitor on USB port 4. This pin will change to an output and be driven low when the port is disabled by configuration or by the host control. Port 3 Power Enable / Overcurrent Sense PRT_CTL3 I/OD12 (PU) Port 3 Power Enable / Overcurrent Sense. When the downstream port is enabled, this pin is set as an input with an internal pull-up resistor applied. The internal pull-up enables power to the downstream port while the pin monitors for an active low overcurrent signal assertion from an external current monitor on USB port 3. This pin will change to an output and be driven low when the port is disabled by configuration or by the host control. Port 2 Power Enable / Overcurrent Sense PRT_CTL2 I/OD12 (PU) Port 2 Power Enable / Overcurrent Sense. When the downstream port is enabled, this pin is set as an input with an internal pull-up resistor applied. The internal pull-up enables power to the downstream port while the pin monitors for an active low overcurrent signal assertion from an external current monitor on USB port 2. This pin will change to an output and be driven low when the port is disabled by configuration or by the host control. 2016-2018 Microchip Technology Inc. DS00002239D-page 13 USB5826 TABLE 3-4: PORT CONTROL PIN DESCRIPTIONS (CONTINUED) Name Symbol Port 1 Power Enable / Overcurrent Sense PRT_CTL1 Buffer Type I/OD12 (PU) Description Port 1 Power Enable / Overcurrent Sense. When the downstream port is enabled, this pin is set as an input with an internal pull-up resistor applied. The internal pull-up enables power to the downstream port while the pin monitors for an active low overcurrent signal assertion from an external current monitor on USB port 1. This pin will change to an output and be driven low when the port is disabled by configuration or by the host control. Gang Power GANG_PWR I GANG_PWR becomes the port control (PRTCTL) pin for all downstream ports when the hub is configured for ganged port power control mode. All port power controllers should be controlled from this pin when the hub is configured for ganged port power mode. TABLE 3-5: SPI INTERFACE Name Symbol Buffer Type SPI Chip Enable SPI_CE_N I/O12 This is the active low SPI chip enable output. If the SPI interface is enabled, this pin must be driven high in power-down states. SPI Clock SPI_CLK I/O-U This is the SPI clock out to the serial ROM. If the SPI interface is disabled, by setting the SPI_DIS-ABLE bit in the UTIL_CONFIG1 register, this pin becomes GPIO4. If the SPI interface is enabled this pin must be driven low during reset. SPI Data Output SPI_DO I/O-U SPI data output, when configured for SPI operation. SPI Data Input SPI_DI I/O-U SPI data input, when configured for SPI operation. Note: Description If SPI memory device is not used, these pins may not be simply floated. These pins must be handled per their respective alternate pin functions descriptions (CFG_BC_EN and CFG_NON_REM). DS00002239D-page 14 2016-2018 Microchip Technology Inc. USB5826 TABLE 3-6: USB TYPE-C CONNECTOR CONTROLS Name Symbol USB Type-C Attach Control Input 0-2 C_ATTACH[0:2] Buffer Type I (PD) Description "Type-C Control Mode 1" USB Type-C attach control input. This pin indicates to the hub when a valid USB Type-C attach has been detected. This pin is used by the hub to enable the USB 3.1 Gen 1 PHY when a Type-C connection is present. When there is no USB Type-C connection present, the USB 3.1 Gen 1 PHY is disabled to reduce power consumption. The polarity of this input is controlled via the CC_POL pin. If CC_POL is low, this pin behaves as follows: - 1: USB Type-C attach detected, turn respective USB 3.1 Gen 1 PHY on. - 0: No USB Type-C attach detected, turn respective USB 3.1 Gen 1 PHY off. If CC_POL is high, this pin behaves as follows: - 1: No USB Type-C attach detected, turn respective USB3.1 Gen 1 PHY off. - 0: USB Type-C attach detected, turn respective USB3.1 Gen 1 PHY on. When using legacy USB Type-A and Type-B connectors, pull these pins to 3.3V to permanently enable all USB 3.1 PHYs. USB Type-C Orientation Control Input 1-2 AB[1:2] I (PD) "Type-C Control Mode 1" USB Type-C orientation control input. This pin signals to the hub the orientation of the USB Type-C connector. The hub enables the appropriate USB 3.1 Gen 1 PHY based upon the polarity of this signal, and the assertion of the associated C_ATTACH[0:2] pin. The polarity of this input is controlled via the CC_POL pin. If CC_POL is low, this pin behaves as follows: - 1: Enable USB 3.1 Gen 1 PHY B. - 0: Enable USB 3.1 Gen 1 PHY A. If CC_POL is high, this pin behaves as follows: - 1: Enable USB 3.1 Gen 1 PHY A. - 0: Enable USB 3.1 Gen 1 PHY B. 2016-2018 Microchip Technology Inc. DS00002239D-page 15 USB5826 TABLE 3-6: USB TYPE-C CONNECTOR CONTROLS (CONTINUED) Name Symbol USB Type-C Alternative Orientation A Attach 1-2 ATTACH_MUX[1:2]A Buffer Type Description I (PD) "Type-C Control Mode 2" Alternative USB Type-C attach for "Orientation A" USB Type-C connections. This mode of control is an alternative to the C_ATTACH[0:2] and AB[1:2] pins. To select this mode, the ALT_MUX_EN pin must be high. When this pin asserted, the hub enables the "Orientation A" USB 3.1 Gen 1 PHY of the associated port. When there is no USB Type-C connection present and this pin is not asserted, the associated USB 3.1 Gen 1 PHY is disabled to reduce power consumption. The polarity of this input is controlled via the CC_POL pin. If CC_POL is low, this pin behaves as follows: - 1: USB Type-C attach detected, turn respective "Orientation A" USB 3.1 Gen 1 PHY on. - 0: No USB Type-C attach detected, turn respective "Orientation A" USB 3.1 Gen 1 PHY off. If CC_POL is high, this pin behaves as follows: - 1: No USB Type-C attach detected, turn respective "Orientation A" USB 3.1 Gen 1 PHY off. - 0: USB Type-C attach detected, turn respective "Orientation A" USB 3.1 Gen 1 PHY on. DS00002239D-page 16 2016-2018 Microchip Technology Inc. USB5826 TABLE 3-6: USB TYPE-C CONNECTOR CONTROLS (CONTINUED) Name Symbol USB Type-C Alternative Orientation B Attach 1-2 ATTACH_MUX[1:2]B Buffer Type Description I (PD) "Type-C Control Mode 2" USB Type-C attach for "Orientation B" USB Type-C connections. This mode of control is an alternative to the C_ATTACH[0:2] and AB[1:2] pins.To select this mode, the ALT_MUX_EN pin must be high. When this pin asserted, the hub enables the "Orientation B" USB 3.1 Gen 1 PHY of the associated port. When there is no USB Type-C connection present and this pin is not asserted, the associated USB 3.1 Gen 1 PHY is disabled to reduce power consumption. The polarity of this input is controlled via the CC_POL pin. If CC_POL is low, this pin behaves as follows: - 1: USB Type-C attach detected, turn respective "Orientation B" USB 3.1 Gen 1 PHY on. - 0: No USB Type-C attach detected, turn respective "Orientation B" USB 3.1 Gen 1 PHY off. If CC_POL is high, this pin behaves as follows: - 1: No USB Type-C attach detected, turn respective "Orientation B" USB 3.1 Gen 1 PHY off. - 0: USB Type-C attach detected, turn respective "Orientation A" USB 3.1 Gen 1 PHY on. Attach Polarity Control CC_POL I (PD) USB C_ATTACH polarity control input. If this pin is low, the C_ATTACH[0:2], AB[1:2], ATTACH_MUX[1:2]A, and ATTACH_MUX[1:2]B pins are active high. If this pin is high, the C_ATTACH[0:2], AB[1:2], ATTACH_MUX[1:2]A, and ATTACH_MUX[1:2]B pins are active low. This pin has an internal pull-down enabled. If the desired strapping is to pull this pin low, then this pin may be left unconnected. 2016-2018 Microchip Technology Inc. DS00002239D-page 17 USB5826 TABLE 3-6: USB TYPE-C CONNECTOR CONTROLS (CONTINUED) Name Symbol USB Type-C Control Mode Selection ALT_MUX_EN Buffer Type I (PD) Description USB Type-C control mode selection. If this pin is low, the hub operates in "Type-C Control Mode 1". In "Type-C Control Mode 1", the C_ATTACH[0:2] and AB[1:2] pin functions are used. If this pin is high, the hub operates in "Type-C Control Mode 2". In "Type-C Control Mode 2", the ATTACH_MUX[1:2]A and ATTACH_MUX[1:2]B pin functions are used. This pin has an internal pull-down enabled. If the desired mode is "Type-C Control Mode 1", then this pin may be left unconnected. TABLE 3-7: MISCELLANEOUS PIN DESCRIPTIONS Name Symbol Buffer Type SMBus/I2C Clock SMBCLK I/O12 Description SMBus/I2C Clock The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. For information on how to configure this interface refer to Section 3.5.1, CFG_STRAP Configuration. SMBus/I2C Data SMBDATA I/O12 SMBus/I2C Data The SMBus/I2C interface acts as SMBus slave or I2C bridge dependent on the device configuration. For information on how to configure this interface refer to Section 3.5.1, CFG_STRAP Configuration. USB Host Port 1-0 Speed Indicator HOST_TYPE_[1:0] O12 USB Host Port Speed Indicator Tri-state: Not connected 0: USB 3.1 Gen 1 1: USB 2.0 / USB 1.1 General Purpose I/O USB 2.0 Suspend State Indicator DS00002239D-page 18 GPIO[1:10], GPIO12, GPIO[16:23], GPIO[64:72] I/O12 (PU/ PD) General Purpose Inputs/Outputs SUSP_IND O12 USB 2.0 Suspend State Indicator Refer to Section 3.5.5, General Purpose input/Output Configuration (GPIOx) for details. SUSP_IND can be used as a sideband remote wakeup signal for the host when in USB 2.0 suspend. 2016-2018 Microchip Technology Inc. USB5826 TABLE 3-7: MISCELLANEOUS PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Reset Control Input RESET_N IS Description Reset Control Input This pin places the hub into Reset Mode when pulled low. A 12.0 k (+/- 1%) resistor is attached from ground to this pin to set the transceiver's internal bias settings. Place the resistor as close to the device as possible with a dedicated, low impedance connection to the GND plane. Bias Resistor RBIAS I-R External 25 MHz Crystal Input XTALI ICLK External 25 MHz crystal input External 25 MHz Reference Clock Input CLKIN ICLK External reference clock input. External 25 MHz Crystal Output XTALO OCLK External 25 MHz crystal output Test TESTEN I/O12 Test pin. The device may alternatively be driven by a single-ended clock oscillator. When this method is used, XTALO should be left unconnected. This signal is used for test purposes and must always be connected to ground. No Connect NC - No connect. For proper operation, this signal must be left unconnected. 2016-2018 Microchip Technology Inc. DS00002239D-page 19 USB5826 TABLE 3-8: CONFIGURATION STRAP PIN DESCRIPTIONS Name Symbol Buffer Type Device Mode Configuration Strap CFG_STRAP I Description Device Mode Configuration Strap. This configuration strap is used to set the device mode. Refer to Section 3.5.1, CFG_STRAP Configuration for details. See Note 2 Port 6-1 D+ Disable Configuration Strap PRT_DIS_P[6:1] I Port 6-1 D+ Disable Configuration Strap. These configuration straps are used in conjunction with the corresponding PRT_DIS_M[6:1] straps to disable the related port (6-1). Refer to Section Section 3.5.2, Port Disable Configuration (PRT_DIS_P[6:1] / PRT_DIS_M[6:1]) for more information. See Note 2 Port 6-1 DDisable Configuration Strap PRT_DIS_M[6:1] I Port 6-1 D- Disable Configuration Strap. These configuration straps are used in conjunction with the corresponding PRT_DIS_P[6:1] straps to disable the related port (6-1). Refer to Section 3.5.2, Port Disable Configuration (PRT_DIS_P[6:1] / PRT_DIS_M[6:1]) for more information. See Note 2 Non-Removable Ports Configuration Strap CFG_NON_REM I Configuration strap to control number of reported nonremoval ports. See Section 3.5.3, Non-Removable Port Configuration (CFG_NON_REM) See Note 2 Battery Charging Configuration Strap CFG_BC_EN I Configuration strap to control number of BC 1.2 enabled downstream ports. See Section 3.5.4, Battery Charging Configuration (CFG_BC_EN) See Note 2 Note 2:Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 3.5, Configuration Straps and Programmable Functions for additional information. DS00002239D-page 20 2016-2018 Microchip Technology Inc. USB5826 TABLE 3-9: POWER AND GROUND PIN DESCRIPTIONS Name Symbol Buffer Type +3.3V Power Supply Input VDD33 P Description +3.3 V power and internal regulator input Refer to Section 4.1, Power Connections for power connection information +1.2V Core Power Supply Input VDD12 Ground GND P +1.2 V core power Refer to Section 4.1, Power Connections for power connection information. P Common ground. This exposed pad must be connected to the ground plane with a via array. 3.4 Buffer Type Descriptions TABLE 3-10: USB5826 BUFFER TYPE DESCRIPTIONS BUFFER DESCRIPTION I Input. IS Input with Schmitt trigger. O12 Output buffer with 12 mA sink and 12 mA source. OD12 Open-drain output with 12 mA sink PU 50 A (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups are always enabled. Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled high, an external resistor must be added. PD 50 A (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled. Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled low, an external resistor must be added. ICLK Crystal oscillator input pin OCLK Crystal oscillator output pin I/O-U Analog input/output defined in USB specification. I-R RBIAS. Note: Refer to Section 9.5, DC Specifications for individual buffer DC electrical characteristics. 2016-2018 Microchip Technology Inc. DS00002239D-page 21 USB5826 3.5 Configuration Straps and Programmable Functions Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset (RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various device configuration straps and associated programmable pin functions. Note: 3.5.1 The system designer must guarantee that configuration straps meet the timing requirements specified in Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. CFG_STRAP CONFIGURATION The CFG_STRAP pin is used to place the hub into preset modes of operation. The resistor options are a 200 k pulldown, 200 k pull-up, 10 k pull-down, 10 k pull-up, 10 pull-down, and 10 pull-up as shown in Table 3-11. TABLE 3-11: CFG_STRAP RESISTOR ENCODING CFG_STRAP Resistor Value Config 200 k Pull-Down CONFIG1 Setting I2C Bridging Mode The SMBus interface will operate in Master Mode for use with USB to I2C bridging function. For more information on USB to I2C bridging with the USB5806, refer to the "USB to I2C Using Microchip USB 3.1 Gen 1 Hubs" application note. 200 k Pull-Up CONFIG2 SMBus Slave Mode The SMBus interface will operate in Slave Mode for use with hub configuration. 10 k Pull-Down CONFIG3 Unused, Reserved 10 k Pull-Up CONFIG4 Unused, Reserved 10 Pull-Down CONFIG5 Unused, Reserved 10 Pull-Up CONFIG6 Unused, Reserved 3.5.2 PORT DISABLE CONFIGURATION (PRT_DIS_P[6:1] / PRT_DIS_M[6:1]) The PRT_DIS_P[6:1] and PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1). For PRT_DIS_Px (where x is the corresponding port 6-1): 0 = Port x D+ Enabled 1 = Port x D+ Disabled For PRT_DIS_Mx (where x is the corresponding port 6-1): 0 = Port x D- Enabled 1 = Port x D- Disabled Note: Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.1 Gen 1 port. DS00002239D-page 22 2016-2018 Microchip Technology Inc. USB5826 3.5.3 NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM) The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The resistor options are a 200 k pull-down, 200 k pull-up, 10 k pull-down, 10 k pull-up, 10 pull-down and 10 pullup as shown in Table 3-12. TABLE 3-12: CFG_NON_REM RESISTOR ENCODING CFG_NON_REM Resistor Value 200 k Pull-Down Setting All ports removable 200 k Pull-Up Port 3 non-removable 10 k Pull-Down Port 3, 4 non-removable 10 k Pull-Up Port 3, 4, 5, non-removable 10 Pull-Down Port 3, 4, 5, 6 non-removable 10 Pull-Up Reserved 3.5.4 BATTERY CHARGING CONFIGURATION (CFG_BC_EN) The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor options are a 200 k pull-down, 200 k pull-up, 10 k pull-down, 10 k pull-up, 10 pull-down and 10 pull-up as shown in Table 3-13. TABLE 3-13: CFG_BC_EN RESISTOR ENCODING CFG_BC_EN Resistor Value 200 k Pull-Down Setting No battery charging 200 k Pull-Up Port 1 battery charging 10 k Pull-Down Port 1, 2 battery charging 10 k Pull-Up Port 1, 2, 3, battery charging 10 Pull-Down Port 1, 2, 3, 4 battery charging 10 Pull-Up Port 1, 2, 3, 4, 5, 6 battery charging 3.5.5 GENERAL PURPOSE INPUT/OUTPUT CONFIGURATION (GPIOx) General Purpose Inputs/Outputs may be used for application specific purposes. Any given GPIO may operate as an input or an output. Inputs can apply an internal 50k pull-down or pull-up resistor. Outputs may drive low or drive high (3.3V). GPIOs may be configured and manipulated during runtime (while enumerated to a host) in one of two ways: * SMBus configuration * USB to GPIO bridging 3.5.5.1 SMBus configuration The SMBus slave interface may be used to write to internal registers that configure the state of the GPIO. Refer to the "Configuration Options for Microchip USB58xx and USB59xx Hubs" application note for additional details. 3.5.5.2 USB to GPIO Bridging USB to GPIO Bridging may be used to write to internal registers that configure the state of the GPIO. USB to GPIO bridging operates via host communication to the hub's internal Hub Feature Controller. Refer to the "USB to GPIO Bridging for Microchip USB3.1 Gen 1 Hubs" application note for additional details. 2016-2018 Microchip Technology Inc. DS00002239D-page 23 USB5826 4.0 DEVICE CONNECTIONS 4.1 Power Connections Figure 4-1 illustrates the device power connections. FIGURE 4-1: DEVICE POWER CONNECTIONS +3.3V Supply +1.2V Supply VDD33 3.3V Internal Logic USB5826 4.2 1.2V Internal Logic VDD12 VSS SPI ROM Connections Figure 4-2 illustrates the device SPI ROM connections. Refer to Section 7.1 "SPI Master Interface" for additional information on this device interface. FIGURE 4-2: SPI ROM CONNECTIONS SPI_CE_N CE# SPI_CLK CLK USB5826 4.3 SPI ROM SPI_DO DI SPI_DI DO SMBus Slave Connections Figure 4-3 illustrates the device SMBus slave connections. Refer to Section 7.2 "SMBus Slave Interface" for additional information on this device interface. FIGURE 4-3: SMBUS SLAVE CONNECTIONS +3.3V 10K Clock SMCLK USB5826 +3.3V 10K SMDAT DS00002239D-page 24 SMBus Master Data 2016-2018 Microchip Technology Inc. USB5826 5.0 MODES OF OPERATION The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the RESET_N pin, as shown in Table 5-1. TABLE 5-1: MODES OF OPERATION RESET_N Input Summary 0 Standby Mode: This is the lowest power mode of the device. No functions are active other than monitoring the RESET_N input. All port interfaces are high impedance and the PLL is halted. Refer to Section 8.3.2, External Chip Reset (RESET_N) for additional information on RESET_N. 1 Hub (Normal) Mode: The device operates as a configurable USB hub with battery charger detection. This mode has various sub-modes of operation, as detailed in Figure 5-1. Power consumption is based on the number of active ports, their speed, and amount of data transferred. The flowchart in Figure 5-1 details the modes of operation and how the device traverses through the Hub Mode stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation. FIGURE 5-1: HUB BOOT FLOWCHART RESET_N deasserted SPI Signature Present? YES Run from External ROM NO (SPI_INIT) Load Config from Internal ROM Modify Config Based on OTP (CFG_RD) Do SMBus or I2C initialization YES Load Config from External ROM Modify Config Based on psuedoOTP (Ext_CFG _RD) CFG_STRAP for SMBus Slave? NO (STRAP) No SOC Done? YES (SOC_CFG) Combine OTP Config Data (OTP_CFG) Hub Connect NORMAL operation 2016-2018 Microchip Technology Inc. DS00002239D-page 25 USB5826 5.1 Standby Mode If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode and must be re-initialized after RESET_N is negated high. 5.2 SPI Initialization Stage (SPI_INIT) The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset, the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid signature of "2DFU" (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal ROM (CFG_RD stage). When using an external SPI ROM, a 1 Mbit, 60 MHz or faster ROM must be used. Both 1- and 2-bit SPI operation are supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also supported. If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_RD stage). 5.3 Configuration Read Stage (CFG_RD) In this stage, the internal firmware loads the default values from the internal ROM and then uses the configuration strapping options to override the default values. Refer to Section 3.5, Configuration Straps and Programmable Functions for information on usage of the various device configuration straps. 5.4 Strap Read Stage (STRAP) In this stage, the firmware registers the configuration strap settings and checks the state of CFG_STRAP. If CFG_STRAP is set for CONFIG2, then the hub will check the state of the SMBDATA and SMBCLK pins. If 10k pull-up resistors are detected on both pins, the device will enter the SOC_CFG stage. If 10k pull-up resistors are not detected on both pins, the hub will transition to the OTP_CFG stage instead. 5.5 SOC Configuration Stage (SOC_CFG) In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB device descriptors and port electrical settings. There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When the SOC has completed configuring the device, it must write to register 0xFF to end the configuration. 5.6 OTP Configuration Stage (OTP_CFG) Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is programmed. After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present. Once VBUS is present, and battery charging is enabled, the device will transition to the Battery Charger Detection Stage. If VBUS is present, and battery charging is not enabled, the device will transition to the Connect stage. 5.7 Hub Connect Stage (Hub.Connect) Once the CHGDET stage is completed, the device enters the Hub Connect stage. USB connect can be initiated by asserting the VBUS pin function high. The device will remain in the Hub Connect stage indefinitely until the VBUS pin function is deasserted. DS00002239D-page 26 2016-2018 Microchip Technology Inc. USB5826 5.8 Normal Mode Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the system. 2016-2018 Microchip Technology Inc. DS00002239D-page 27 USB5826 6.0 DEVICE CONFIGURATION The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly function when attached to a USB host controller. The hub can be configured either internally or externally depending on the implemented interface. Microchip provides a comprehensive software programming tool, Pro-Touch2, for configuring the USB5826 functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch2 programming tool. For additional information on the Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5826 product page at www.microchip.com/USB5826. Note: 6.1 Device configuration straps and programmable pins are detailed in Section 3.5, Configuration Straps and Programmable Functions. Refer to Section 7.0, Device Interfaces for detailed information on each device interface. Customer Accessible Functions The following functions are available to the customer via the Pro-Touch2 Programming Tool. Note: 6.1.1 6.1.1.1 For additional programming details, refer to the Pro-Touch2 programming tool User's Guide. USB ACCESSIBLE FUNCTIONS I2C Bridging Access over USB Access to I2C devices is performed as a pass-through operation from the USB Host. The device firmware has no knowledge of the operation of the attached I2C device. For more information, refer to the Microchip USB5826 product page and Pro-Touch2 at www.microchip.com/USB5826. Note: 6.1.1.2 Refer to Section 7.3, I2C Bridge Interface for additional information on the I2C interface. SPI Access over USB Access to an attached SPI device is performed as a pass-through operation from the USB Host. The device firmware has no knowledge of the operation of the attached SPI device. For more information, refer to the Microchip USB5826 product page and SDK at www.microchip.com/USB5826. Note: 6.1.1.3 Refer to Section 7.1, SPI Master Interface for additional information on the SPI. OTP Access The OTP ROM in the device is accessible via the USB bus during normal runtime operation or SMBus during the SOC_CFG stage. For more information, refer to the Microchip USB5826product page or the Pro-Touch2 User's Guide. 6.1.1.4 Battery Charging Access over USB The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than the preprogrammed or OTP programmed behavior is desired. For more information, refer to the Microchip USB5826product page or the Pro-Touch2 User's Guide. 6.1.2 SMBUS ACCESSIBLE FUNCTIONS OTP access and configuration of specific device functions are possible via the USB5826 SMBus slave interface. All OTP parameters can be modified via the SMBus Host. For more information refer to the Microchip USB5826 product page. DS00002239D-page 28 2016-2018 Microchip Technology Inc. USB5826 7.0 DEVICE INTERFACES The USB5826 provides multiple interfaces for configuration and external memory access. This section details the various device interfaces and their usage: * SPI Master Interface * SMBus Slave Interface * I2C Bridge Interface Note: For details on how to enable each interface, refer to Section 3.5, Configuration Straps and Programmable Functions. For information on device connections, refer to Section 4.0, Device Connections. For information on device configuration, refer to Section 6.0, Device Configuration. Microchip provides a comprehensive software programming tool, Pro-Touch2, for configuring the USB5826 functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch2 programming tool. For additional information on the Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5826 product page at www.microchip.com/USB5826. 7.1 SPI Master Interface The device is capable of code execution from an external SPI ROM. When configured for SPI Mode, on power up the firmware looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal ROM. Note: 7.2 For SPI timing information, refer to Section 9.6.7, SPI Timing. SMBus Slave Interface The device includes an integrated SMBus slave interface, which can be used to access internal device run time registers or program the internal OTP memory. SMBus slave detection is accomplished by setting the CFG_STRAP in the correct configuration followed by detection of pull-up resistors on both the SMDAT and SMCLK signals during the hub's bootup sequence. Refer to Section 3.5.1, CFG_STRAP Configuration for additional information. Note: 7.3 All configuration is to be performed via the Pro-Touch2 programming tool. For additional information on the Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5826 product page at www.microchip.com/USB5826. I2C Bridge Interface The I2C Bridge interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The I2C Bridge conforms to the Fast-Mode I2C Specification (400 kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility. The device acts as the master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and generates the START and STOP conditions. The I2C Bridge interface frequency is configurable through the I2C Bridging commands. I2C Bridge frequencies are derived from the formula 626KHz/n, where n is any integer from 1 to 256. Refer to Section 3.5.1, CFG_STRAP Configuration for additional information. Note: Extensions to the I2C Specification are not supported. All configuration is to be performed via the Pro-Touch2 programming tool. For additional information on the Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5826 product page at www.microchip.com/USB5826. 2016-2018 Microchip Technology Inc. DS00002239D-page 29 USB5826 8.0 FUNCTIONAL DESCRIPTIONS This section details various USB5826 functions, including: * * * * * * * * USB Type-C Receptacle Support Battery Charging Resets Link Power Management (LPM) Remote Wakeup Indicator Port Control Interface Port Split 8.1 USB Type-C Receptacle Support The USB5826 has built-in support for the USB Type-C receptacle. There are 3 fundamental configurations: * External USB 3.1 Gen 1 Multiplexer * Internal USB3.1 Gen 1 Multiplexer, "Type-C Control Mode 1" * Internal USB 3.1 Gen 1 Multiplexer, "Type-C Control Mode 2" 8.1.1 EXTERNAL USB 3.1 GEN 1 MULTIPLEXER C_ATTACH[0:2] pins are used to signal to the hub when a valid USB Type-C connection has been detected. This functionality requires an external USB Type-C controller such as a Microchip UTC2000 to monitor the USB Type-C receptacle for a valid attach. This signal is used to enable and disable clocking to the USB 3.1 Gen 1 PHY in order to reduce power consumption when there is no USB Type-C attach. The polarity of the C_ATTACH[0:2] pins are controlled by the CC_POL pin. See Table 3-6 for details. A diagram of a USB Type-C Downstream Facing Port with a USB5826, Microchip UTC2000, and external multiplexer is shown in Figure 8-1. A diagram of a USB Type-C Upstream Facing Port with a USB5826, Microchip UTC2000, and external multiplexer is shown in Figure 8-2. FIGURE 8-1: DFP TYPE-C PORT WITH MICROCHIP UTC2000 AND EXTERNAL MUX USB Type-C External Mux Downstream Port USB Type-C GENERIC PORT PWR CTLR POWER OCS VBUS SSTXA+ SSTXA- SSTXA+ SSTXA- SSTX+ SSTXSSRX+ SSRX- SSTX+ SSRXA+ SSTXSSRXAMUX SSTXB+ SSRX+ SSTXBSSRX- SSRXA+ SSRXASSTXB+ SSTXBSSRXB+ SSRXB- SSRXB+ SSRXB- A/B D+ DPRT_CTLx D+ DPLUG_ ORIENTATION# ENABLE OCS# C_ATTACHx CC1 CC2 CC1 CC2 PPC_EN UTC2000 DFP Mode DS00002239D-page 30 2016-2018 Microchip Technology Inc. USB5826 FIGURE 8-2: UFP TYPE-C PORT WITH MICROCHIP UTC2000 & EXTERNAL MUX USB Type-C USB Type-C External Mux Upstream Port VBUS SSTXA+ SSTXA- SSTXA+ SSTXA- SSRXA+ SSRXA- SSRXA+ SSRXA- SSTXB+ SSTXB- SSTXB+ SSTXB- SSRXB+ SSRXB- SSRXB+ SSRXBA/B VBUS_DET SSTX+ SSTX- SSTX+ SSTX- SSRX+ SSRX- SSRX+ SSRX- MUX D+ DPLUG_ ORIENTATION# CC1 CC2 CC1 CC2 UTC2000 UFP Mode 3.3V D+ D- C_ATTACH0 CONNECTED# 8.1.2 INTERNAL USB3.1 GEN 1 MULTIPLEXER, "TYPE-C CONTROL MODE 1" "Type-C Control Mode 1" is enabled by setting the ALT_MUX_EN signal low or leaving it floating. While in "Type-C Control Mode 1", the C_ATTACH[1:2] and AB[1:2] pins are used together to signal to the hub when a valid USB Type-C connection has been detected and in what orientation the connection has been detected. This functionality requires an external USB Type-C controller such as a Microchip UTC2000 to monitor the USB Type-C receptacle for a valid attach. These signal are used to enable/disable the USB 3.1 Gen 1 PHYs appropriately according to the detected Type-C attach and orientation. Unused USB 3.1 Gen 1 PHYs are disabled to conserve power. The polarity of the C_ATTACH[1:2] pins and AB[1:2] are controlled by the CC_POL pin. See Table 3-6 for details. A diagram of a USB Type-C Downstream Facing Port with the USB5826, Microchip UTC2000, and internal multiplexer operating in "Type-C Control Mode 1" is shown in Figure 8-3. 2016-2018 Microchip Technology Inc. DS00002239D-page 31 USB5826 FIGURE 8-3: UFP TYPE-C PORT WITH MICROCHIP UTC2000 & EXTERNAL MUX (MODE 1) USB Type-C USB Type-C GENERIC PORT PWR CTLR POWER External Mux Downstream Port OCS VBUS SSTXA+ SSTXASSRXA+ SSRXA- SSTXA+ SSTXASSRXA+ SSRXA- SSTXB+ SSTXBSSRXB+ SSRXB- SSTXB+ SSTXBSSRXB+ SSRXB- D+ D- D+ D- PRTCTL 3.3V ENABLE OCS# AB C_ATTACH USB Type-C Control Mode 1 PLUG_OR# PPC_EN CC1 CC2 CC1 CC2 ALT_MUX_EN CC_POL UTC2000 UFP Mode 8.1.3 INTERNAL USB 3.1 GEN 1 MULTIPLEXER, "TYPE-C CONTROL MODE 2" "Type-C Control Mode 2" is enabled by setting the ALT_MUX_EN signal high. While in "Type-C Control Mode 2", the ATTACH_MUX[1:2]A and ATTACH_MUX[1:2]B pins are used to signal to the hub when a valid USB Type-C connection has been detected and in what orientation the connection has been detected. This functionality requires an external USB Type-C controller (this mode not directly supported by UTC2000) to monitor the USB Type-C receptacle for a valid attach. These signal are used to enable/disable the USB 3.1 Gen 1 PHYs appropriately according to the detected TypeC attach and orientation. Unused USB 3.1 Gen 1 PHYs are disabled to conserve power. The polarity of the ATTACH_MUX[1:2]A pins and ATTACH_MUX[1:2]B are controlled by the CC_POL pin. See Table 3-6 for details. A diagram of a USB Type-C Downstream Facing Port with internal multiplexer operating in "Type-C Control Mode 2" with the USB5826 is shown in Figure 8-4. DS00002239D-page 32 2016-2018 Microchip Technology Inc. USB5826 FIGURE 8-4: DFP TYPE-C PORT WITH GENERIC TYPE-C CONTROLLER AND INTERNAL MUX (MODE 2) USB Type-C GENERIC PORT PWR CTLR POWER Internal Mux Downstream Port OCS USB Type-C VBUS SSTXA+ SSTXASSRXA+ SSRXA- SSTXA+ SSTXASSRXA+ SSRXA- SSTXB+ SSTXBSSRXB+ SSRXB- SSTXB+ SSTXBSSRXB+ SSRXB- D+ D- D+ D- PRTCTL ATTACH_MUXA ATTACH_MUXB USB Type-C Control Mode 2 8.2 ALT_MUX_EN CC_POL 3.3V Type-C ENABLE OCS# Controller PPC_EN CC1 ATTACH_MUXA PLUG_OR# CC2 ATTACH_MUXB PPC_EN CC1 CC2 Battery Charging The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub's role in battery charging is to provide acknowledgment to a device's query as to whether the hub system supports USB battery charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the device. Those components must be provided externally by the OEM. FIGURE 8-5: BATTERY CHARGING EXTERNAL POWER SUPPLY INT DC Power SCL Microchip SOC Hub SDA VBUS[n] If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTL[6:1] pins, is on a per port basis. For example, the OEM can configure two ports to support battery charging through high current power FETs and leave the other two ports as standard USB ports. For additional information, refer to the Microchip USB5826 Battery Charging application note on the Microchip.com USB5826 product page www.microchip.com/USB5826. 2016-2018 Microchip Technology Inc. DS00002239D-page 33 USB5826 8.3 Resets * Power-On Reset (POR) * External Chip Reset (RESET_N) * USB Bus Reset 8.3.1 POWER-ON RESET (POR) A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, Power-On and Configuration Strap Timing. 8.3.2 EXTERNAL CHIP RESET (RESET_N) A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the specifications in Section 9.6.3, Reset and Configuration Strap Timing. While reset is asserted, the device (and its associated external circuitry) enters Standby Mode and consumes minimal current. Assertion of RESET_N causes the following: 1. 2. 3. 4. 5. The PHY is disabled and the differential pairs will be in a high-impedance state. All transactions immediately terminate; no states are saved. All internal registers return to the default state. The external crystal oscillator is halted. The PLL is halted. Note: All power supplies must have reached the operating levels mandated in Section 9.2, Operating Conditions**, prior to (or coincident with) the assertion of RESET_N. 8.3.3 USB BUS RESET In response to the upstream port signaling a reset to the device, the device performs the following: 1. 2. 3. 4. Sets default address to 0. Sets configuration to Unconfigured. Moves device from suspended to active (if suspended). Complies with the USB Specification for behavior after completion of a reset sequence. The host then configures the device in accordance with the USB Specification. Note: 8.4 The device does not propagate the upstream USB reset to downstream devices. Link Power Management (LPM) The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1. TABLE 8-1: LPM STATE DEFINITIONS State Description Entry/Exit Time to L0 L2 Suspend Entry: ~3 ms Exit: ~2 ms (from start of RESUME) L1 Sleep Entry: <10 us Exit: <50 us L0 Fully Enabled (On) - DS00002239D-page 34 2016-2018 Microchip Technology Inc. USB5826 8.5 Remote Wakeup Indicator The remote wakeup indicator feature uses SUSP_IND as a side band signal to wake up the host when in USB 2.0 suspend. This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration bit in the hub configuration space register HUB_CFG_3. The only way to control the bit is by configuration EEPROM, SMBus or internal ROM default setting. The state is only modified during a power on reset, or hardware reset. No dynamic reconfiguring of this capability is possible. When HUB_RESUME_INHIBIT = `0', Normal Resume Behavior per the USB 2.0 specification When HUB_RESUME_INHIBIT = `1', Modified Resume Behavior is enabled Note: 8.6 The SUSP_IND signal only indicates the USB2.0 state. Port Control Interface Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled directly from the USB hub, or via the processor. Additionally, smart port controllers can be controlled via the I2C interface. The device can be configured into one of the two following port control modes: * Ganged Mode - A single GANG_PWR pin controls power and detects over-current events for all downstream ports. * Individual Mode - Each port has an individual PRT_CTLx pin for independent port power control and over-current detection. Port connection in various modes are detailed in the following subsections. 8.6.1 PORT CONNECTION IN GANGED MODE Ganged Mode is enabled via SMBus or OTP configuration. GANG_PWR becomes the port control (PRTCTL) pin for all downstream ports when the hub is configured for ganged port power control mode. All port power controllers should be controlled from this pin when the hub is configured for ganged port power mode. While in this mode of operation, an over-current event on any single downstream port will cause all downstream ports to be flagged for over-current. 8.6.2 8.6.2.1 PORT CONNECTION IN INDIVIDUAL MODE Port Power Control using USB Power Switch Individual mode is the default mode of operation. When operating in individual mode, the device will have one port power control and over-current sense pin for each downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation, the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not interfere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up. 2016-2018 Microchip Technology Inc. DS00002239D-page 35 USB5826 FIGURE 8-6: PORT POWER CONTROL WITH USB POWER SWITCH PullUp Enable 5V 50k PRT_CTLx OCS USB Power Switch EN PRTPWR USB Device FILTER OCS When the port is enabled, the PRT_CTLx pin input is constantly sampled. Overcurrent events can be detected in one of two ways: * Single, continuous low pulse (consecutive low samples over tocs_single), as shown in Figure 8-7. * Two short low pulses within a rolling window (two groupings of 1 or more low samples over tocs_double), as shown in Figure 8-8. FIGURE 8-7: SINGLE LOW PULSE OVERCURRENT DETECTION PRT_CTLx IS VIL tocs_single FIGURE 8-8: DOUBLE LOW PULSE OVERCURRENT DETECTION PRT_CTLx IS VIL tocs_double To maximize compatibility with various port power control topologies, the parameters tocs_single and tocs_double are configurable via the Overcurrent Minimum Pulse Width Register and Overcurrent Inactive Timer Register. The pin also has a turn-on "lockout" feature where the state of the pin is ignored for a configured amount of time immediately after port power is turned on. This prevents slow ramp times due to parasitic resistance/capacitance attached to the pin from triggering false overcurrent detections. This parameter is configurable via the Overcurrent Lockout Timer Register. DS00002239D-page 36 2016-2018 Microchip Technology Inc. USB5826 TABLE 8-2: OVERCURRENT MINIMUM PULSE WIDTH REGISTER OCS_MIN_WIDTH (30EAh) Overcurrent Detection Pulse Window BIT Name R/W 7:4 Reserved R 3:0 OCS_MIN_WIDTH R/W Description Reserved The minimum overcurrent detection pulse width (tocs_single) is configured in this register. The range can be configured in 1ms increments from 0ms to 5ms. 0000 - 0ms minimum overcurrent detection pulse width 0001 - 1ms minimum overcurrent detection pulse width 0010 - 2ms minimum overcurrent detection pulse width 0011 - 3ms minimum overcurrent detection pulse width 0100 - 4ms minimum overcurrent detection pulse width 0101 - 5ms minimum overcurrent detection pulse width [Default] TABLE 8-3: OVERCURRENT INACTIVE TIMER REGISTER OCS_INACTIVE_TIMER (30EBh) Overcurrent Inactive Timer After First Overcurrent Detection BIT Name R/W Description 7:0 OCS_INACTIVE_TIMER R/W This register configures the timer within which a double low pulse triggers an overcurrent detection event (tocs_double). The timer can be incremented in 1ms steps. The default value is 20ms (14h). Note: TABLE 8-4: This register should never be set to 00h. OVERCURRENT LOCKOUT TIMER REGISTER START_LOCKOUT_TIMER_REG (30E1h) Start Lockout Timer Register BIT Name R/W 7:0 START_LOCKOUT_TIMER_REG R/W Description The "start lockout timer" blocks an overcurrent event from being detected immediately after port power is turned on. Any overcurrent event within this timer value is ignored. The timer can be incremented in 1ms steps. The default value is 10ms (0Ah). Note: 2016-2018 Microchip Technology Inc. This register should never be set to 00h. DS00002239D-page 37 USB5826 8.6.2.2 Port Power Control using Poly Fuse When using the device with a poly fuse, there is no need for an output power control. To maintain consistency, the same circuit will be used. A single port power control and over-current sense for each downstream port is still used from the Hub's perspective. When disabling port power, the driver will actively drive a '0'. This will have no effect as the external diode will isolate pin from the load. When port power is enabled, it will disable the output driver and enable the pull-up resistor. This means that the pull-up resistor is providing 3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will be at 0.7 volts, and the Schmidt trigger input will register this as a low resulting in an over-current detection. The open drain output does not interfere. Note: The USB 2.0 and USB 3.1 Gen 1 bPwrOn2PwrGood descriptors must be set to 0 when using poly-fuse mode. Refer to the "Configuration Options for the USB58xx and USB59xx" Microchip application note for details on how to change these values. FIGURE 8-9: PORT POWER CONTROL USING A POLY FUSE 5V Pull-Up Enable Poly Fuse 50k PRT_CTLx USB Device PRTPWR OCS 8.6.2.3 FILTER Port Power Control with Single Poly Fuse and Multiple Loads Many customers use a single poly fuse to power all their devices. For the ganged situation, all power control pins must be tied together. DS00002239D-page 38 2016-2018 Microchip Technology Inc. USB5826 FIGURE 8-10: PORT POWER CONTROL WITH GANGED CONTROL WITH POLY FUSE 5V Pull-Up Enable 50k Poly Fuse PRT_CTLz Pull-Up Enable 50k PRT_CTLy Pull-Up Enable 50k PRT_CTLx USB Device PRTPWR USB Device USB Device OCS 8.6.3 PORT CONTROLLER CONNECTION EXAMPLE FIGURE 8-11: GENERIC PORT POWER CONTROLLERS (High Current) PRT_CTLx POWER OCS Generic Port Power Controller POWER OCS Generic Port Power Controller D+ D- Note: VBUS (BC Enabled) D+ D- D+ DPRT_CTLy Port x Connector Port y Connector VBUS (BC Enabled) D+ D- The CFG_BC_EN configuration strap must be properly configured to enable battery charging on the appropriate ports. For more information on the CFG_BC_EN configuration strap, refer to Section 3.5.4, Battery Charging Configuration (CFG_BC_EN). 2016-2018 Microchip Technology Inc. DS00002239D-page 39 USB5826 8.7 8.7.1 Port Split FEATURE OVERVIEW This feature allows the USB 2.0 and USB 3.1 Gen 1 PHYs associated with any downstream port to be operationally separated. The intention of this feature is to allow a system designer to connect an embedded USB 3.x device to the USB 3.1 Gen 1 PHY, while allowing the USB 2.0 PHY to be used as either a standard USB 2.0 port or with a separate embedded USB 2.0 device. This feature operates outside of the provisions of the USB specifications. Operation is intended for specialized applications only. Contact your local sales representative for additional information. In order to maintain a positive end user experience, it is recommended that only permanently attached, embedded USB 3.x devices be connected to the USB 3.1 Gen 1 PHY when enabling the Port Split feature. This prevents end users from attempting to connect USB High-Speed, Full-Speed, or Low-Speed devices to an exposed USB port which only has USB 3.1 Gen 1 connections. FIGURE 8-12: RECOMMENDED PORT SPLITTING CONFIGURATIONS PRTPWRx_USB3_SPLIT (GPIOxx) EN USB58xx/ USB59xx Embedded USB3.x Device PRTCTLx 5V OCS EN PRTPWRx_USB3_SPLIT (GPIOxx) EN Embedded USB3.x Device EN Embedded USB2.0 Device USB58xx/ USB59xx PRTCTLx 8.7.2 USB Power Switch VBUS USB2.0 Device PORT SPLITTING CONFIGURATION Downstream ports 3 and 4 may be configured for Port Splitting. Port Splitting is configured via register configuration through SMBus during the hub configuration stage (SOC_CFG) or via the hub's internal OTP memory. When Port Splitting is enabled, the existing PRT_CTLx pin associated with that port will continue to control the USB 2.0 portion of the port in an identical matter. A new pin function assigned to a GPIOx pin will be activated and configured to control the USB 3.1 Gen 1 portion of the port. This new pin is named PRTPWRx_USB3_SPLIT where x indicates the respective port. Note that overcurrent detection is not supported on the PRTPWRx_USB3_SPLIT pin. These new pins are assigned as shown in Table 8-5. DS00002239D-page 40 2016-2018 Microchip Technology Inc. USB5826 TABLE 8-5: PORT SPLIT PRTPWRX_USB3_SPLIT PIN ASSIGNMENT GPIOx Pin Port Split Assignment GPIO66 PRTPWR3_USB3_SPLIT Option A GPIO6 PRTPWR4_USB3_SPLIT Option A GPIO5 PRTPWR3_USB3_SPLIT Option B GPIO4 PRTPWR4_USB3_SPLIT Option B 8.7.2.1 Enabling Port Splitting In order to enable the Port Splitting feature on downstream ports 3 and/or 4, the following configuration settings must be made. Enabling Port Splitting on Port 3: * Write 0x42 to register 0x416E to select GPIO66 for Option A * Write 0x05 to register 0x416E to select GPIO5 for Option B * Set bit 5 of the USB3_PORT_SPLIT_EN (0x3C48 = 0x20) Enabling Port Splitting on Port 4: * Write 0x06 to register 0x416F to select GPIO6 for Option A * Write 0x04 to register 0x416F to select GPIO4 for Option B * Set bit 6 of the USB3_PORT_SPLIT_EN (0x3C48 = 0x40) TABLE 8-6: USB 3.0 PORT SPLIT ENABLE REGISTER USB3_PORT_SPLIT_EN (0x3C48 - RESET = 0x00) USB 3.0 Port Split Enable BIT Name R/W 7:1 PORT_SPLIT_EN[7:1] R/W Description 0 = Port Splitting on the specified port is disabled 1 = Port Splitting on the specified port is enabled Bit [1] - Reserved [2] - Reserved [3] - Reserved [4] - Reserved [5] - Port 3 [6] - Port 4 [7] - Reserved 0 8.7.2.2 Reserved R Reserved Link Timeout Reset Port Splitting is intended for use with embedded USB 3.x devices only. When Port Splitting is enabled, the hub constantly monitors the USB 3.1 Gen 1 Link to see if a valid USB 3.1 Gen 1 Link is established. If there is no valid USB 3.1 Gen 1 Link for a configured amount of time (see below), then the hub will toggle assertion of the associated "PRTPWRx_USB3_SPLIT" pin in an attempt to reset the embedded USB 3.1 Gen 1 device and re-establish the USB 3.1 Gen 1 Link. The timer is always reset and restarted whenever the timeout occurs. 2016-2018 Microchip Technology Inc. DS00002239D-page 41 USB5826 A valid USB 3.1 Gen 1 link is qualified by the LTSSM_STATE register status for the port. A normal Link will actively switch through many Link states. If the hub detects that the Link is staying in one of the following Link states the entire duration of the timeout timer, then the Link is stuck in an invalid state and PRTPWRx_USB3_SPLIT will be toggled in order to attempt to re-establish the Link. * * * * * * SIS.Disabled(0x4) Rx.Detect(0x5) SS.Inactive(0x6) Polling(0x7) Recovery(0x8) HotReset (0x9) The Link Timeout Reset value is configured via register 0x4171 and can be overridden by OTP. The default value is 0x05, which selects a Timeout value of 1 second. Setting the register to 0x00 will disable the Link Timeout Reset feature. The duration of the Link reset (time which PRTPWRx_USB3_SPLIT signal stays low) can be configured in register 0x4176. The default duration is 400ms with a configurable range of 350ms to 2.9s. 8.8 USB Billboard Device Class Support TABLE 8-7: USB 3.X PORT SPLIT LINK TIMEOUT REGISTER USB3_PORT_SPLIT_TIMEOUT (0X4171 - RESET=0X05) USB 3.X PORT SPLIT LINK TIMEOUT REGISTER BIT NAME R/W DESCRIPTION [7:3] Reserved R/W Always read `0' [2:0] PORT_SPLIT_TIMEOUT[ 2:0] R/W Global USB Port Splitting Link Timeout Value If Port Splitting is enabled on a port and there is no valid USB 3.x Link for the configured amount of time, then the associated "PRTPWRx_USB3_SPLIT" pin will be toggled in an attempt to reset the embedded USB 3.x device and re-establish the USB 3.x Link. The timer is always reset and restarted whenever the timeout occurs. 000b 001b 010b 011b 100b 101b 110b 111b DS00002239D-page 42 - No Timeout, never toggle PRTPWRx_USB3_SPLIT 100ms 250ms 500ms 750ms 1 second 2 second Reserved 2016-2018 Microchip Technology Inc. USB5826 TABLE 8-8: USB 3.X PORT SPLIT TOGGLE TIME REGISTER USB3_PORT_SPLIT_TOGGLE_TIME (0X4176 - RESET=0X05) USB 3.X PORT SPLIT TOGGLE TIME REGISTER BIT NAME R/W DESCRIPTION [7:0] PORT_SPLIT_TOGGLE_ TIME[7:0] R/W The PORT_SPLIT_TOGGLE_TIME is used to control the length of time port power is toggled off. This is specific to the "PRTPWRx_USB3_SPLIT" pin, and is only used in conjunction with 0X4171. The timer is always reset whenever the toggle completes. The minimum toggle time is 350ms and is represented by 00000000b. Each incremental value will add 10ms to the 350ms minimum value. USB Billboard is supported by the USB5826 in conjunction with an external USB Power Delivery capable controller that supports the USB PD stack and alternate mode negotiation. When a USB Type-C enabled product supports alternate modes for enhanced capability beyond what is available through USB connectivity alone, that product must support a USB Billboard endpoint so that a user will be notified by an operating system when the enhanced capability is not enabled due to an alternate mode mismatch. A good example of alternate mode functionality is support for a DisplayPort monitor that many docking stations provide. In this case, the docking station offers DisplayPort (DP) capability over the USB-C connector as an alternate mode.The DP monitor will only function correctly when a successful alternate mode negotiation occurs between the docking station and the notebook PC (this is the USB-C to USB-C connection). In order for the alternate mode negotiation to succeed, the Notebook and the Docking Station must both support DP over USB-C, and have the DP messaging capability enabled to support alternate mode negotiation. If the alternate mode negotiation is successful, then the notebook and the Docking Station both change their multiplexers to enable DP signaling over USB Type-C. In this case, no USB Billboard messages need to be displayed. If the above example instead uses a notebook that doesn't support DP over USB-C, then the alternate mode negotiation will fail. The docking station will not have a way to enable the DP monitor capability, reducing functionality for the customer. For this is the reason, USB Billboard capability is mandated. In this case, a USB Billboard device class endpoint must appear on a hub port within the Docking Station, and it must provide text and or a web site link which will provide information to the user regarding the corrective steps required to use the feature. In the case of the USB5826, all of the above mentioned negotiation capability will occur outside of the USB5826 via an external USB Power Delivery capable device that contains a full USB PD stack and can communicate via USB PD messaging. In an alternate mode failure case, the USB5826 will provide that message by allowing the USB host to enumerate an internal USB Billboard Device Class just after the failure in response to a signal from the external USB PD controller. The Billboard Device descriptors will contain the failure message to the USB Host. The message itself will be prerecorded in the device's OTP memory. 8.8.1 BILLBOARD ENABLE IN OTP AND GPIOx PIN USE Any of the GPIOx pins may be selected to use as the BILLBOARD_EN input. By default, GPIO68 is selected when the Billboard feature is enabled. The BILLBOARD_EN input signal is active low. When the pin is driven low by a Power Delivery controller to indicate an alternate mode negotiation failure, the Billboard functionality will activate. 2016-2018 Microchip Technology Inc. DS00002239D-page 43 USB5826 TABLE 8-9: USB BILLBOARD CONTROL USBBILLBOARDCNTL (OTP ADDR4 - RESET=0X14) USB BILLBOARD CONTROL BIT NAME R/W DESCRIPTION [7:6] Reserved R/W Always read `0' [5:1] BILLBOARD_EN Pin Select R/W 00000= GPIO64 00001= GPIO1 00010= GPIO2 00011= GPIO3 00100= GPIO65 00101= GPIO66 00110= GPIO67 00111= GPIO23 01000= GPIO10 01001= Reserved 01010= GPIO68 (default) 01011= GPIO6 01100= GPIO69 01101= GPIO70 01110= GPIO71 01111= GPIO5 10000= GPIO4 [0] Billboard Support Enable R/W 0 = Billboard support disabled 1 = Billboard support enabled 8.8.2 BILLBOARD ENDPOINT FUNCTIONALITY When the applicable GPIOx pin is 0, which indicates that Billboard device must be displayed, the following sequence of events will occur: 1. 2. 3. 4. 5. 6. 7. USB5826 will force the Hub Feature Controller internal device to disconnect from the USB Hub port (emulating a physical detach) USB5826 will force the Hub Feature Controller to re-connect with descriptors that will show the Hub Feature Controller endpoint is a Billboard device, compliant to version 1.1 of the Billboard device class specification. USB5826 will start a timer (Timer A) when the Host sets the Hub Feature Controller USB address. This timer will be used to ensure that the Billboard endpoint will not remain permanently attached if it is never accessed. The default Timer A timeout is 20 seconds. This implementation will only support Billboard when a failure occurs, therefore the Device Container uses a static list of device capabilities and will only expose the Billboard Device on failure to enter into Modal Operation and will set the bmConfigured descriptor field to "Unspecified Error" (00b) by default. The Hub Feature Controller will Provide the iAlternateModeString when the host requests it, and will start a timer (Timer B). The default Timer B timeout is 20 seconds. When either timer expires, the USB5826 will force the Hub Feature Controller internal device to disconnect from the USB Hub port (emulating a physical detach). USB5826 will force the Hub Feature Controller to re-connect with the standard Hub Feature Controller Functionality. DS00002239D-page 44 2016-2018 Microchip Technology Inc. USB5826 TABLE 8-10: TIMER A: BILLBOARD DETACH TIMER LSB DETACH_TIMER_A_LSB (413Ch) Billboard Detach Timer A LSB BIT Name R/W Description 7:0 TIMEOUT R/W Timer A is started as soon as the Hub Feature Controller's Billboard Class Device address is set by the host. Once the timer expires, the Billboard Class Device will automatically detach from the host and reattach as the default WinUSB device. Increments of 10ms can be set. The default value of 413Ch = D0h, 413Dh = 07h is equivalent to a 20s timeout. (07D0h = 2000d) TABLE 8-11: TIMER A: BILLBOARD DETACH TIMER MSB DETACH_TIMER_A_MSB (413Dh) Billboard Detach Timer A MSB BIT Name R/W Description 7:0 TIMEOUT R/W Timer A is started as soon as the Hub Feature Controller's Billboard Class Device address is set by the host. Once the timer expires, the Billboard Class Device will automatically detach from the host and reattach as the default WinUSB device. Increments of 10ms can be set. Note: TABLE 8-12: The default value of 413Ch = D0h, 413Dh = 07h is equivalent to a 20s timeout. (07D0h = 2000d) TIMER B: BILLBOARD DETACH TIMER LSB DETACH_TIMER_B_LSB (413Eh) Billboard Detach Timer B LSB BIT Name R/W Description 7:0 TIMEOUT R/W Timer B is started as soon as the host requests iAlternateModeString. Once the timer expires, the Billboard Class Device will automatically detach from the host and re-attach as the default WinUSB device. Increments of 10ms can be set. The default value of 413Ch = D0h, 413Dh = 07h is equivalent to a 20s timeout. (07D0h = 2000d) 2016-2018 Microchip Technology Inc. DS00002239D-page 45 USB5826 TABLE 8-13: TIMER B: BILLBOARD DETACH TIMER MSB DETACH_TIMER_B_MSB (413Fh) Billboard Detach Timer A MSB BIT Name R/W Description 7:0 TIMEOUT R/W Timer B is started as soon as the host requests iAlternateModeString. Once the timer expires, the Billboard Class Device will automatically detach from the host and re-attach as the default WinUSB device. Increments of 10ms can be set. Note: 8.8.3 The default value of 413Ch = D0h, 413Dh = 07h is equivalent to a 20s timeout. (07D0h = 2000d) BILLBOARD DEVICE DESCRIPTORS The AlternateModeString and iAdditionalInfoURL descriptors can be configured in the hub to provide the user with additional information about the Alternate Mode failure. TABLE 8-14: BILLBOARD DEVICE DESCRIPTORS Offset: 0 Offset: +1 Offset: +2 Offset: +3 iAdditionalInfoURL Default = 01h bNumberOfAlternateModes bPreferredAlternateMode VCONN Power[0] VCONN Power[1] Default = 00h Default = 00h Default = 80h bmConfigured[0] bmConfigured[1] bmConfigured[2] bmConfigured[3] Default = 00h Default = 00h Default = 00h Default = 00h bmConfigured[4] bmConfigured[5] bmConfigured[6] bmConfigured[7] Default = 00h Default = 00h Default = 00h Default = 00h bmConfigured[8] bmConfigured[9] bmConfigured[10] bmConfigured[11] Default = 00h Default = 00h Default = 00h Default = 00h bmConfigured[12] bmConfigured[13] bmConfigured[14] bmConfigured[15] Default = 00h Default = 00h Default = 00h Default = 00h bmConfigured[16] bmConfigured[17] bmConfigured[18] bmConfigured[19] Default = 00h Default = 00h Default = 00h Default = 00h bmConfigured[20] bmConfigured[21] bmConfigured[22] bmConfigured[23] Default = 00h Default = 00h Default = 00h Default = 00h bmConfigured[24] bmConfigured[25] bmConfigured[26] bmConfigured[27] Default = 00h Default = 00h Default = 00h Default = 00h Default = 01h DS00002239D-page 46 2016-2018 Microchip Technology Inc. USB5826 TABLE 8-14: BILLBOARD DEVICE DESCRIPTORS (CONTINUED) Offset: 0 Offset: +1 Offset: +2 Offset: +3 bmConfigured[28] bmConfigured[29] bmConfigured[30] bmConfigured[31] Default = 00h Default = 00h Default = 00h Default = 00h bcdVersion[0] bcdVersion[1] bAdditonalFailureInfo bReserved Default = 10h Default = 01h Default = 00h Default = 00h wSVID[0] wSVID[1] bAlternateMode Default = 00h Default = FFh Default = 00h 2016-2018 Microchip Technology Inc. DS00002239D-page 47 USB5826 9.0 OPERATIONAL CHARACTERISTICS 9.1 Absolute Maximum Ratings* +1.2 V Supply Voltage (VDD12) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +1.32 V +3.3 V Supply Voltage (VDD33) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V Positive voltage on input signal pins, with respect to ground (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 V Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V Positive voltage on XTALI/CLKIN, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.63 V Positive voltage on USB DP/DM signal pins, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0 V Positive voltage on USB 3.1 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground. . . . . 1.32 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +150oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125oC Lead Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020 HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit. Note 2: This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLKIN, and XTALO *Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 9.2, Operating Conditions**, Section 9.5, DC Specifications, or any other applicable section of this specification is not implied. 9.2 Operating Conditions** +1.2 V Supply Voltage (VDD12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.08 V to +1.32 V +3.3 V Supply Voltage (VDD33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V Input Signal Pins Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V XTALI/CLKIN Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V USB 2.0 DP/DM Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V USB 3.1 Gen 1 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +1.32 V Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 3 +1.2 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 s +3.3 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 s Note 3: 0oC to +70oC for commercial version, -40oC to +85oC for industrial version. **Proper operation of the device is guaranteed only within the ranges specified in this section. Note: Do not drive input signals without power supplied to the device. DS00002239D-page 48 2016-2018 Microchip Technology Inc. USB5826 FIGURE 9-1: SUPPLY RISE TIME MODEL Voltage TRT 3.3 V VDD33 100% 90% 1.2 V VDD12 100% 90% 10% VSS t90% t10% Note: 9.3 The rise time for the 3.3 V supply can be extended to 100ms max if RESET_N is actively driven low, typically by another IC, until 1 s after all supplies are within operating range. Package Thermal Specifications TABLE 9-1: PACKAGE THERMAL PARAMETERS Symbol JA JT JC Note: Time C/W Velocity (Meters/s) 19 0 16 1 0.1 0 0.1 1 1.4 0 1.4 1 Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51. TABLE 9-2: MAXIMUM POWER DISSIPATION Parameter Value Units PD(max) 1.75 W 2016-2018 Microchip Technology Inc. DS00002239D-page 49 USB5826 9.4 Power Consumption The values shown below represent typical power consumption as measured during various modes of operation. Power dissipation is determined by temperature, supply voltage, and external source/sink requirements. The following measurements were taken with VDD33 equal to 3.3V, VDD12 equal to 1.2V, at an ambient temperature of 25C. Note: A USB 3.x hub operates both the USB 3.x and USB 2.0 interfaces in parallel on it's upstream port connection. A port operating under the SS/HS condition indicates that a USB 3.x hub was connected to it. TABLE 9-3: DEVICE POWER CONSUMPTION Typical (mA) Typical Power VDD33 VDD12 (mW) Reset 0.5 27.5 28 No VBUS 0.7 21.5 28 Global Suspend 7.5 24.5 32 4 SS Ports + 2 HS Port 83 685 1,096 4 SS/HS Ports/2 HS Port 123 693 1,238 Note: Actual power consumption will vary depending on the capabilities of the USB host, the devices connected, data type, and data bus utilization. The published data represents typical power consumption of the hub at nominal ambient temperature and supply voltage while large file transfers are active between USB host and USB Mass Storage class devices on all downstream ports. Typical power consumption for specific use cases can be estimated using the formulas below: IVDD33(mA) = 35 + (NPORTSFS)(1)* +(NPORTSHS)(10) + (NPORTSSS)(7) IVDD12(mA) = 245+ (NPORTSFS)(0.1)* +(NPORTSHS)(2) + (NPORTSSS)(109) PTOTAL(mW) = 409.5+ (NPORTSFS)(3.42)* +(NPORTSHS)(35.4) + (NPORTSSS)(153.9) 9.5 DC Specifications TABLE 9-4: I/O DC ELECTRICAL CHARACTERISTICS Parameter Symbol Min Typical Max Units 0.9 V Notes I Type Input Buffer Low Input Level VIL High Input Level VIH 2.1 V IS Type Input Buffer Low Input Level VIL High Input Level VIH 1.9 VHYS 9 Schmitt Trigger Hysteresis (VIHT - VILT) 0.9 V V 20 40 mV 0.4 V IOL = 6 mA V IOH = -6 mA O6 Type Output Buffer Low Output Level VOL High Output Level VOH DS00002239D-page 50 VDD33-0.4 2016-2018 Microchip Technology Inc. USB5826 TABLE 9-4: I/O DC ELECTRICAL CHARACTERISTICS (CONTINUED) Parameter Symbol Min Typical Max Units Notes 0.4 V IOL = 12 mA V IOH = -12 mA V IOL = 12 mA O12 Type Output Buffer Low Output Level VOL High Output Level VOH VDD33-0.4 OD12 Type Output Buffer Low Output Level VOL 0.4 ICLK Type Input Buffer (XTALI Input) Note 4 Low Input Level VIL High Input Level VIH 0.85 0.50 V VDD33 V IO-U Type Buffer (See Note 5) Note 5 Note 4: XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator. Note 5: Refer to the USB 3.1 Gen 1 Specification for USB DC electrical characteristics. 9.6 AC Specifications This section details the various AC timing specifications of the device. 9.6.1 POWER SUPPLY AND RESET_N SEQUENCE TIMING Figure 9-2 illustrates the recommended power supply sequencing and timing for the device. VDD33 should rise after or at the same rate as VDD12. Similarly, RESET_N and/or VBUS_DET should rise after or at the same rate as VDD33. VBUS_DET and RESET_N do not have any other timing dependencies. FIGURE 9-2: POWER SUPPLY AND RESET_N SEQUENCE TIMING VDD12 VDD33 RESET_N/ VBUS_DET TABLE 9-5: POWER SUPPLY AND RESET_N SEQUENCE TIMING Symbol tVDD33 treset Description Min Typ Max Units VDD12 to VDD33 rise time 0 ms VDD33 to RESET_N/VBUS_DET rise time 0 ms 2016-2018 Microchip Technology Inc. DS00002239D-page 51 USB5826 9.6.2 POWER-ON AND CONFIGURATION STRAP TIMING Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in Section 9.2, Operating Conditions**. FIGURE 9-3: POWER-ON CONFIGURATION STRAP VALID TIMING All External Power Supplies Vopp Configuration Straps TABLE 9-6: POWER-ON CONFIGURATION STRAP LATCHING TIMING Symbol Description Min tcsh Configuration strap hold after external power supplies at operational levels 1 Typ Max Units ms Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, Reset and Configuration Strap Timing for additional details. 9.6.3 RESET AND CONFIGURATION STRAP TIMING Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to Section 8.3, Resets for additional information on resets. Refer to Section 3.5, Configuration Straps and Programmable Functions for additional information on configuration straps. FIGURE 9-4: RESET_N CONFIGURATION STRAP TIMING trstia RESET_N tcsh Configuration Straps TABLE 9-7: RESET_N CONFIGURATION STRAP TIMING Symbol Description Min Typ Max Units trstia RESET_N input assertion time 5 s tcsh Configuration strap pins hold after RESET_N deassertion 1 ms Note: The clock input must be stable prior to RESET_N deassertion. Configuration strap latching and output drive timings shown assume that the Power-On reset has finished first otherwise the timings in Section 9.6.2, Power-On and Configuration Strap Timing apply. DS00002239D-page 52 2016-2018 Microchip Technology Inc. USB5826 9.6.4 USB TIMING All device USB signals confirm to the voltage, power, and timing characteristics/specifications as set forth in the Universal Serial Bus Specification. Please refer to the Universal Serial Bus Revision 3.1 Specification, available at http:// www.usb.org/developers/docs. I2C TIMING 9.6.5 All device I2C signals confirm to the 100KHz Standard Mode (Sm) voltage, power, and timing characteristics/specifications as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus Specification, available at http://www.nxp.com/ documents/user_manual/UM10204.pdf. 9.6.6 SMBUS TIMING All device SMBus signals confirm to the voltage, power, and timing characteristics/specifications as set forth in the System Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available at http://smbus.org/specs. 9.6.7 SPI TIMING This section specifies the SPI timing requirements for the device. FIGURE 9-5: SPI TIMING tceh SPI_CE_N tfc tcel SPI_CLK tclq tdh SPI_DI tos toh tov toh SPI_DO TABLE 9-8: SPI TIMING (30 MHZ OPERATION) Symbol tfc Description Min Typ Clock frequency Max Units 30 MHz 13 ns tceh Chip enable (SPI_CE_EN) high time tclq Clock to input data tdh Input data hold time 0 ns tos Output setup time 5 ns toh Output hold time 5 ns tov Clock to output valid 4 ns tcel Chip enable (SPI_CE_EN) low to first clock 12 ns tceh Last clock to chip enable (SPI_CE_EN) high 12 ns TABLE 9-9: ns SPI TIMING (60 MHZ OPERATION) Symbol tfc 100 Description Clock frequency 2016-2018 Microchip Technology Inc. Min Typ Max Units 60 MHz DS00002239D-page 53 USB5826 TABLE 9-9: SPI TIMING (60 MHZ OPERATION) Symbol Description Min Typ Max Units tceh Chip enable (SPI_CE_EN) high time tclq Clock to input data tdh Input data hold time 0 ns 50 ns 9 ns tos Output setup time 5 ns toh Output hold time 5 ns tov Clock to output valid 4 ns tcel Chip enable (SPI_CE_EN) low to first clock 12 ns tceh Last clock to chip enable (SPI_CE_EN) high 12 ns 9.7 Clock Specifications The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (50ppm) input. If the singleended clock oscillator method is implemented, XTALO should be left unconnected and XTALI/CLKIN should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum. It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XTALI/XTALO). The following circuit design (Figure 9-6) and specifications (Table 9-10) are required to ensure proper operation. FIGURE 9-6: 25MHZ CRYSTAL CIRCUIT XTALO Y1 XTALI C2 C1 9.7.1 CRYSTAL SPECIFICATIONS It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XTALI/XTALO). Refer to Table 9-10 for the recommended crystal specifications. TABLE 9-10: CRYSTAL SPECIFICATIONS PARAMETER SYMBOL MIN Crystal Cut NOM MAX UNITS NOTES AT, typ Crystal Oscillation Mode Fundamental Mode Crystal Calibration Mode Parallel Resonant Mode Frequency 25oC Ffund - 25.000 - MHz Ftol - - 50 PPM Frequency Stability Over Temp Ftemp - - 50 PPM Frequency Deviation Over Time Fage - 3 to 5 - PPM Note 6 - - 100 PPM Note 7 - 7 typ - pF Frequency Tolerance @ Total Allowable PPM Budget Shunt Capacitance DS00002239D-page 54 CO 2016-2018 Microchip Technology Inc. USB5826 TABLE 9-10: CRYSTAL SPECIFICATIONS (CONTINUED) PARAMETER SYMBOL MIN NOM MAX UNITS Load Capacitance CL - 20 typ - pF Drive Level PW 100 - - uW Equivalent Series Resistance R1 NOTES - - 60 Note 7 - Note 8 oC XTALI/CLKIN Pin Capacitance - 3 typ - pF Note 9 XTALO Pin Capacitance - 3 typ - pF Note 9 Operating Temperature Range Note 6: Frequency Deviation Over Time is also referred to as Aging. Note 7: 0 C for commercial version, -40 C for industrial version. Note 8: +70 C for commercial version, +85 C for industrial version. Note 9: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this value. The XTALI/CLKIN pin, XTALO pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors. These two external load capacitors determine the accuracy of the 25.000 MHz frequency. 9.7.2 EXTERNAL REFERENCE CLOCK (CLKIN) When using an external reference clock, the following input clock specifications are suggested: * 25 MHz * 50% duty cycle 10%, 100 ppm * Jitter < 100 ps RMS 2016-2018 Microchip Technology Inc. DS00002239D-page 55 USB5826 10.0 PACKAGE INFORMATION 10.1 Package Marking Information 100-VQFN (12x12 mm) PIN 1 Legend: Note: i R nnn e3 YY WW NNN USB5826i e3 Rnnn e3 YYWWNNN Temperature range designator (Blank = commercial, i = industrial) Product revision Internal code Pb-free JEDEC(R) designator for Matte Tin (Sn) Year code (last two digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard device marking consists of Microchip part number, year code, week code and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS00002239D-page 56 2016-2018 Microchip Technology Inc. USB5826 10.2 Package Drawings Note: For the most current package drawings, see the Microchip Packaging Specification at: http://www.microchip.com/packaging. FIGURE 10-1: 100-VQFN PACKAGE (DRAWING) ' 127( $ 6(( '(7$,/$ % 1 ( '$780% '$780$ ; & ; & & 7239,(: ; & & $ % & ' 6($7,1* 3/$1( 6,'(9,(: & $ % ( H 127( . 1 / H %277209,(: 2016-2018 Microchip Technology Inc. ;E & $ % & 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY%6KHHWRI DS00002239D-page 57 USB5826 FIGURE 10-2: 100-VQFN PACKAGE (DIMENSIONS) $ & 6($7,1* 3/$1( $ $ '(7$,/$ Notes: 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI7HUPLQDOV 1 H 3LWFK $ 2YHUDOO+HLJKW 6WDQGRII $ $ 7HUPLQDO7KLFNQHVV 2YHUDOO/HQJWK ' ([SRVHG3DG/HQJWK ' 2YHUDOO:LGWK ( ( ([SRVHG3DG:LGWK E 7HUPLQDO:LGWK 7HUPLQDO/HQJWK / . 7HUPLQDOWR([SRVHG3DG 0,1 0,//,0(7(56 120 %6& 5() %6& %6& 0$; 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5()5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY%6KHHWRI DS00002239D-page 58 2016-2018 Microchip Technology Inc. USB5826 FIGURE 10-3: 100-VQFN PACKAGE (LAND PATTERN) C1 X2 EV 100 1 2 OV C2 Y2 EV G1 Y1 X1 SILK SCREEN E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X100) X1 Contact Pad Length (X100) Y1 Contact Pad to Center Pad (X100) G1 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.40 BSC MAX 8.10 8.10 11.70 11.70 0.20 1.05 0.20 0.33 1.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2407A 2016-2018 Microchip Technology Inc. DS00002239D-page 59 USB5826 APPENDIX A: TABLE A-1: REVISION HISTORY REVISION HISTORY Revision Level & Date Section/Figure/Entry Table 3-6 Added pull-down (PD) to buffer type of C_ATTACH[0:2], AB[1:2], CC_POL, ALT_MUX_EN, ATTACH_MUX[1:2]A, ATTACH_MUX[1:2]B pins. Table 3-6 Corrected the AB[1:2] 0 and 1 state descriptions. Section 8.7.2.1, Enabling Port Splitting Updated section and added USB3_PORT_SPLIT_EN register information. DS00002239D (05-21-18) DS00002239C (08-18-17) Correction Figure 10-1, Figure 10-2, Figure 10-3 Updated package drawings. Cover, Section 2.1, General Description, Section 8.0, Functional Descriptions Removed references to FlexConnect. Section 3.2, Pin Symbols, Figure 3-1, Removed references to FLEX_CMD and Table 3-4 FLEX_STATE pins. DS00002239B (01-20-17) Section 3.2, Pin Symbols, Figure 3-1, Table 3-4 Removed references to PRT_CTL0 pin. Table 9-10 Updated max equivalent series resistance to 60. Table 9-3 Updated values. Figure 4-2, SPI ROM Connections Modified drawing by changing position of DO to DI and DI to DO Table 9-3, Device Power Consumption Typical power consumption formula added below table. Section 8.7.2.1, Enabling Port Splitting Options A and B added. Throughout data sheet Changed 62kOhm to 50kOhm Table 3-1, Pin Reset State Legend In PD-15k, changed "Hardware enables internal 62kOhm pull-down" to "Hardware enables internal 15kOhm pull-down" Section 3.2, Pin Symbols Updated pin names for pin numbers: 51, 52, 57, 58 and 62 Figure 3-1 Pin Assignments (Top View) DS00002239A (10-03-16) DS00002239D-page 60 All Initial Release 2016-2018 Microchip Technology Inc. USB5826 Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2016-2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 9781522431046 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2016-2018 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS00002239D-page 61 USB5826 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device [-X] Tape and Reel Temperature Option Range /XX Package Examples: a) b) c) Device: USB5826 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: Blank I = 0C to = -40C to Package: KD d) = +70C +85C USB5826/KD Tray, Commercial temp., 100-pin VQFN USB5826-I/KD Tray, Industrial temp., 100-pin VQFN USB5826T/KD Tape & reel, Commercial temp., 100-pin VQFN USB5826T-I/KD Tape & reel, Industrial temp., 100-pin VQFN (Commercial) (Industrial) 100-pin VQFN Note 1: DS00002239D-page 62 Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2016-2018 Microchip Technology Inc. USB5826 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support 2016-2018 Microchip Technology Inc. DS00002239D-page 63 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 Israel - Ra'anana Tel: 972-9-744-7705 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 2016-2018 Microchip Technology Inc. Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7289-7561 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 DS00002239D-page 64 10/25/17