MC74HC573A Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The HC573A is identical in function to the HC373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. * * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 218 FETs or 54.5 Equivalent Gates http://onsemi.com MARKING DIAGRAMS 20 PDIP-20 N SUFFIX CASE 738 20 MC74HC573AN AWLYYWW 1 20 1 20 1 SOIC WIDE-20 DW SUFFIX CASE 751D HC573A AWLYYWW 1 20 HC 573A ALYW TSSOP-20 DT SUFFIX CASE 948E 20 1 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC74HC573AN Semiconductor Components Industries, LLC, 2000 May, 2000 - Rev. 9 1 Package Shipping PDIP-20 1440 / Box MC74HC573ADW SOIC-WIDE 38 / Rail MC74HC573ADWR2 SOIC-WIDE 1000 / Reel MC74HC573ADT TSSOP-20 75 / Rail MC74HC573ADTR2 TSSOP-20 2500 / Reel Publication Order Number: MC74HC573A/D MC74HC573A LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LATCH ENABLE OUTPUT ENABLE 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 PIN ASSIGNMENT OUTPUT ENABLE D0 Q0 Q1 Q2 Latch Enable L H L H L L H X X = Don't Care Z = High Impedance Q0 D1 3 18 Q1 17 Q2 16 Q3 Q5 D4 6 15 Q4 Q6 D5 7 14 Q5 Q7 D6 8 13 Q6 D7 9 12 10 11 Q7 LATCH ENABLE Q4 D Q H L X X H L No Change Z GND IIIIIIIIII IIII III IIIIIIIIII IIII III IIIIIIIIII IIII III IIIIIIIIII IIII III IIIIIIIIII IIII III IIIIIIIIII IIII III IIIIIIIIII IIII III IIIIIIIIII IIII III Value Units Internal Gate Count* 54.5 ea. Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 W 0.0075 pJ Speed Power Product 19 5 Output Design Criteria 2 4 PIN 20 = VCC PIN 10 = GND Inputs VCC D2 NONINVERTING OUTPUTS FUNCTION TABLE Output Enable 20 D3 Q3 11 1 1 *Equivalent to a two-input NAND gate. http://onsemi.com 2 MC74HC573A IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 35 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature - 65 to + 150 _C Iin TL Plastic DIP SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, TSSOP or SOIC Package) 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: -6.1 mW/C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII III II III IIII IIIIIIIIIIIIIII IIIII III IIII IIIIIIIII IIIIIIIII IIII IIIIIIIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII IIIIIIIII v v III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII III IIII III v IIII v IIII IIII IIIIIIIII IIIIIIIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 1000 500 400 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C 85_C 125_C Unit VIH Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 18 0.5 0.9 1.35 1.8 V Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 VOH Vin = VIH or VIL |Iout| 2.4mA |Iout| 6.0 mA |Iout| 7.8 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HC573A IIII IIIIIIIII IIIIIIIII IIII IIIIIIIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIIIIIIII v v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III v IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII III IIII III v IIII IIII IIIIIIIII IIIIIIIII IIII III IIII III v IIII IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIIIIIIII III IIII III IIII IIIII IIIIIIIIIIIIIIII IIII IIIIIIIII III IIIII IIIIIIIIIIIIIIII IIII IIII III v IIII v III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIII IIII IIII III IIII III IIIII IIIIIIIIIIIIIIIIIII IIII III IIII III IIIII IIIIIIIIIIIIIIIIIII IIII III IIII III DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VOL Parameter Test Conditions Maximum Low-Level Output Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vin = VIH or VIL |Iout| 2.4mA |Iout| 6.0 mA |Iout| 7.8 mA VCC V - 55 to 25_C 2.0 4.5 6.0 85_C 125_C 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 Unit V Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A IOZ Maximum Three-State Leakage Current Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 - 0.5 - 5.0 - 10 A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND IIoutI = 0 A 6.0 4.0 40 160 A Iin NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C 85_C 125_C Unit tPLH, tPHL Maximum Propagation Delay, Input D to Q (Figures 1 and 5) 2.0 3.0 4.5 6.0 150 100 30 26 190 140 38 33 225 180 45 38 ns tPLH, tPHL Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) 2.0 3.0 4.5 6.0 160 105 32 27 200 145 40 34 240 190 48 41 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) 2.0 3.0 4.5 6.0 60 27 12 10 75 32 15 13 90 36 18 15 ns Maximum Input Capacitance 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) 15 15 15 pF Cin Cout NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 23 pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC573A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIII III III IIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII v v IIII IIIIIIIIIIIII III III IIIII IIIII IIIII II IIIIIIIIIIIII IIII IIIIIIIIIIIII III III III III III III III III II IIIII IIIII IIIII IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III II II IIII IIIIIIIIIIIII III III III III III III III III IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III II II IIII IIIIIIIIIIIII III III III III III III III III IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III II II IIII IIIIIIIIIIIII III III III III III III III III IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III IIII IIIIIIIIIIIII III III III III III III III IIIII II TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter VCC Volts Fig. - 55 to 25_C Min Max 85_C Min Max 125_C Min Max Unit tsu Minimum Setup Time, Input D to Latch Enable 4 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns th Minimum Hold Time, Latch Enable to Input D 4 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Latch Enable 2 2.0 3.0 4.5 6.0 75 60 15 13 95 80 19 16 110 90 22 19 ns tr, tf Maximum Input Rise and Fall Times 1 2.0 3.0 4.5 6.0 http://onsemi.com 5 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns MC74HC573A SWITCHING WAVEFORMS VCC tr LATCH ENABLE tf VCC 90% 50% 10% INPUT D 50% GND tw GND tPLH tPHL 90% 50% 10% Q tPLH tTHL tTLH 50% Q Figure 1. OUTPUT ENABLE Figure 2. 3.0 V VALID 50% GND tPZL Q 10% tPHZ 90% Q GND HIGH IMPEDANCE 50% 1.3 V tSU VOL VOH th VCC 50% LATCH ENABLE GND HIGH IMPEDANCE Figure 3. Figure 4. EXPANDED LOGIC DIAGRAM TEST POINT D0 OUTPUT DEVICE UNDER TEST D1 CL* D2 *Includes all probe and jig capacitance D3 2 3 4 5 Figure 5. Test Circuit D4 D5 TEST POINT OUTPUT VCC 50% INPUT D tPLZ tPZH DEVICE UNDER TEST tPHL 1 k CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. D6 D7 6 7 8 9 LATCH ENABLE *Includes all probe and jig capacitance OUTPUT ENABLE Figure 6. Test Circuit http://onsemi.com 6 11 1 D Q LE 19 D Q LE 18 D Q LE 17 D Q LE 16 D Q LE 15 D Q LE 14 D Q LE 13 D Q LE 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MC74HC573A PACKAGE DIMENSIONS PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E -A- 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C -T- K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M T B M M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 SO-20 DW SUFFIX CASE 751D-05 ISSUE F q A 20 X 45 _ M E h 0.25 1 10 20X B B 0.25 M T A S B S A L H 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE DIM A A1 B C D E e H h L q C T http://onsemi.com 7 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74HC573A PACKAGE DIMENSIONS 20X 0.15 (0.006) T U TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE A K REF 0.10 (0.004) S M T U S V S IIII IIII IIII K K1 2X L/2 20 11 J J1 B -U- L PIN 1 IDENT SECTION N-N 1 10 0.25 (0.010) N 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M A -V- N F DETAIL E -W- C D G H DETAIL E 0.100 (0.004) -T- SEATING DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ PLANE ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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