SLUS507A – JANUARY 2002 – REVISED JUNE 2002
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Terminal Functions
TERMINAL
NAME NO.I/O DESCRIPTION
BOOT 10 O Provides a bootstrapped supply for the topside MOSFET driver, enabling the gate of the topside
MOSFET to be driven above the input supply rail
COMP 3 O Output of the error amplifier
FB 2 I Inverting input of the error amplifier. In normal operation the voltage at this pin is the internal reference
level of 700 mV.
GND 5 –Power supply return for the device. The power stage ground return on the board requires a separate
path from other sensitive signal ground returns.
HDRV 9 O This is the gate drive output for the topside N-channel MOSFET. HDRV is bootstrapped to near 2×VDD
for good enhancement of the topside MOSFET.
ILIM 1 I
A resistor is connected between this pin and VDD to set up the over current threshold voltage. A
15-µA current sink at the pin establishes a voltage drop across the external resistor that represents the
drain-to-source voltage across the top side N-channel MOSFET during an over current condition. The
ILIM over current comparator is blanked for the first 100 ns to allow full enhancement of the top
MOSFET. Set the ILIM voltage level such that it is within 800 mV of VDD; that is, (VDD – 0.8) ≤ IILIM ≤
VDD.
LDRV 6 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET
SS/SD 4 I
Soft-start and overcurrent fault shutdown times are set by charging and discharging a capacitor con-
nected to this pin. A closed loop soft-start occurs when the internal 3-µA current source charges the
external capacitor from 0.17 V to 0.70 V. During the soft-start period, the current sink capability of the
TPS40001 and TPS40003 is disabled. When the SS/SD voltage is less than 0.12 V, the device is shut-
down and the HDRV and LDRV are driven low. In normal operation, the capacitor is charged to 1.5 V.
When a fault condition is asserted, the HDRV is driven low, and the LDRV is driven high. The soft-start
capacitor goes through six charge/discharge cycles, restarting the converter on the seventh cycle.
SW 8 O
Connect to the switched node on the converter. This pin is used for overcurrent sensing in the topside
N-channel MOSFET, zero current sensing in synchronous rectifier N-channel MOSFET, and level
sensing for predictive delay circuit. Overcurrent is determined, when the topside N-channel MOSFET
is on, by comparing the voltage on SW with respect to VDD and the voltage on the ILIM with respect to
VDD. Zero current is sensed, when the rectifier N-channel MOSFET is on, by measuring the voltage
on SW with respect to ground. Zero current sensing applies to the TPS40000/2 devices only.
VDD 7 I Power input for the chip, 5.5-V maximum. Decouple close to the pin with a low-ESR capacitor, 1-µF or
larger.