1
Data sheet acquired from Harris Semiconductor
SCHS167A
Features
• HC/HCT240 Inverting
• HC/HCT241 Non-Inverting
• HC/HCT244 Non-Inverting
• Typical Propagation Delay = 8ns at VCC = 5V,
CL = 15pF, TA = 25oC for HC240
• Three-State Outputs
• Buffered Inputs
• High-Current Bus Driver Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC240 and ’HCT240 are inverting three-state buffers
having two active-low output enables. The CD74HC241,
’HCT241, ’HC244 and ’HCT244 are non-inverting three-
state buffers that differ only in that the 241 has one active-
high and one active-low output enable, and the 244 has two
active-low output enables. All three types have identical
pinouts.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC240F3A -55 to 125 20 Ld CERDIP
CD74HC240E -55 to 125 20 Ld PDIP
CD74HC240M -55 to 125 20 Ld SOIC
CD54HCT240F3A -55 to 125 20 Ld CERDIP
CD74HCT240E -55 to 125 20 Ld PDIP
CD74HCT240M -55 to 125 20 Ld SOIC
CD74HC241E -55 to 125 20 Ld PDIP
CD54HCT241F3A -55 to 125 20 Ld CERDIP
CD74HCT241E -55 to 125 20 Ld PDIP
CD74HCT241M -55 to 125 20 Ld SOIC
CD54HC244F -55 to 125 20 Ld CERDIP
CD54HC244F3A -55 to 125 20 Ld CERDIP
CD74HC244E -55 to 125 20 Ld PDIP
CD74HC244M -55 to 125 20 Ld SOIC
CD54HCT244F -55 to 125 20 Ld CERDIP
CD54HCT244F3A -55 to 125 20 Ld CERDIP
CD74HCT244E -55 to 125 20 Ld PDIP
CD74HCT244M -55 to 125 20 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.
November 1997 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000, Texas Instruments Incorporated
CD54/74HC240, CD54/74HCT240,
CD74HC241, CD54/74HCT241,
CD54/74HC244, CD54/74HCT244
High Speed CMOS Logic
Octal Buffer/Line Drivers, Three-State
[ /Title
(CD74
HC240
,
CD74
HCT24
0,
CD74
HC241
,
CD74
HCT24
1,
CD74
HC244
,
CD74
2
Pinout
CD54HC240, CD54HCT240, CD54HCT241,
CD54HC244, CD54HCT244
(CERDIP)
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241,
CD74HC244, CD74HCT244
(PDIP, SOIC)
TOP VIEW
Functional Diagram
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
1OE
1A0
2Y3
1A1
2Y2
1A2
1A3
2Y1
2Y0
GND
VCC
1Y0
2A3
1Y1
2OE (241)
2A2
1Y2
2A1
1Y3
2A0
241
244 240
VCC
1Y0
2A3
1Y1
2OE (240, 244)
2A2
1Y2
2A1
1Y3
2A0
1OE
1A0
2Y3
1A1
2Y2
1A2
1A3
2Y1
2Y0
GND
241
244240
18
16
14
12
7
3
5
9
21Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2OE
1OE 1
19
6
2OE
1OE
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
240
241
17
4
8
11
13
15
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
240
AND
244
241
AND
244
VCC = 20
GND = 10
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-6 4.5 3.98 - - 3.84 - 3.7 - V
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
6 4.5 - - 0.26 - 0.33 - 0.4 V
7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
4
Three-State Leakage
Current IOZ VIL or
VIH -6--±0.5 - ±0.5 - ±10 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-6 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
6 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC to
GND 0 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆ICC VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
Three-State Leakage
Current IOZ VIL or
VIH - 5.5 - - ±0.5 - ±5-±10 µA
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT UNIT LOADS
HCT240
nA0-A3 1.5
1OE 0.7
2OE 0.7
HCT241
nA0-A3 0.7
1OE 0.7
2OE 1.5
HCT244
nA0-A3 0.7
1OE 0.7
2OE 0.7
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
5
Switching Specifications CL = 50pF, Input tr, tf= 6ns
PARAMETER SYMBOL
TEST
CONDI-
TIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
Propagation Delay tPLH, tPHL CL = 50pF
Data to Outputs
HC240 2 - - 100 - - 125 - - 150 ns
4.5 - - 20 - - 25 - - 30 ns
CL = 15pF 5 - 8 - - - ----ns
CL = 50pF 6 - - 17 - - 21 - - 26 ns
Data to Outputs
HC241 tPLH, tPHL CL = 50pF 2 - - 110 - - 140 - - 165 ns
4.5 - - 22 - - 28 - - 33 ns
CL = 15pF 5 - 9 - - - ----ns
CL = 50pF 6 - - 19 - - 24 - - 28 ns
Data to Outputs
HC244 tPLH, tPHL CL = 50pF 2 - - 110 - - 140 - - 165 ns
4.5 - - 22 - - 28 - - 33 ns
CL = 15pF 5 - 9 - - - ----ns
CL = 50pF 6 - - 19 - - 24 - - 28 ns
Output Enable and Disable
Time tTHL, tTLH CL = 50pF 2 - - 150 - - 190 - - 225 ns
4.5 - - 30 - - 38 - - 45 ns
5-12-------ns
6 - -26- -33- -38ns
Output Transition Time tTLH, tTHL CL = 50pF 2 - - 60 - - 75 - - 90 ns
4.5 - - 12 - - 15 - - 18 ns
6 - -10- -13- -15ns
Input Capacitance CICL = 50pF - 10 - 10 - - 10 - - 10 pF
Three-State Output
Capacitance COCL = 50pF - - - 20 - - 20 - - 20 pF
Power Dissipation Capacitance
(Notes 5, 6) CPD CL = 15pF
HC240 5 - 38 - - - ----pF
HC241 5 - 34 - - - ----pF
HC244 5 - 46 - - - ----pF
HCT TYPES
Propagation Delay
Data to Outputs
HCT240 tPHL, tPLH CL = 50pF 4.5 - - 22 - - 28 - - 33 ns
CL = 15pF 5 - 9 - - - ----ns
Data to Outputs
HCT241 tPHL, tPLH CL = 50pF 4.5 - - 25 - - 31 - - 38 ns
CL = 15pF 5 - 10 - - - ----ns
Data to Outputs
HCT244 tPHL, tPLH CL = 50pF 4.5 - - 25 - - 31 - - 38 ns
CL = 15pF 5 - 10 - - - ----ns
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
6
Output Enable and Disable
Times tTLH, tTHL CL = 50pF 4.5 - - 30 - - 38 - - 45 ns
Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 12 - - 15 - - 18 ns
Input Capacitance CICL = 50pF - 10 - 10 - - 10 - - 10 pF
Power Dissipation Capacitance
(Notes 5, 6)) CPD
HCT240 - 5 - 40 - - - ----pF
HCT241 - 5 - 38 - - - ----pF
HCT244 - 5 - 40 - - - ----pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per channel.
6. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDI-
TIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
50% 10%
90%
GND
VCC
10%
90% 50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
0.3
2.7
GND
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
tr6ns
tPZH
tPHZ
tPZL
tPLZ
6ns tf
1.3
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
7
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto
VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
OUTPUT
RL = 1kΩ
CL
50pF
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Customers are responsible for their applications using TI components.
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Copyright 2000, Texas Instruments Incorporated
