PHILIPS INTERNATIONAL Philips Semiconductors Zero standby power universal PAL devices Se ee DESCRIPTION The PLC18V8Z is a universal PAL-type devices featuring high performance and virtually zero-standby power for power sensitive applications. They are reliable, user-configurable substitutes for discrete TTUCMOS logic. While compatible with TTL and HCT logic, the PLC 18V8Z can also replace HC logic over the Vcc range of 4.5 to 5.5V. The PLC 18V8Z is a two-level logic element comprised of 10 inputs, 74 AND gates (product terms) and 8 output Macro cells. Each output features an Output Macro Cell which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. As a result, the PLC 18V8Z is capable of emulating all common 20-pin PAL devices to reduce documentation, inventory, and manufacturing costs. A power-up reset function and a Register Preload function have been incorporated in the PLC18V8Z architecture to facilitate state machine design and testing. With a standby current of less than 100pA and active power consumption of 1.5mA/MHz, the PLC 18V8Z is ideally suited for power sensitive applications in battery operated/backed portable instruments and computers, The PLC18V82Z is also processed to industrial requirements for operation over an extended temperature range of -40C to +85C and supply voltage of 4.5V to 5.5V. Ordering information can be found below. FEATURES 20-pin Universal Programmable Array Logic . Virtually Zero-Standby-power Functional replacement for Series 20 PAL devices lo = 24mA High-performance CMOS EPROM cell technology - Erasable Reconfigurable 100% testable 25ns Max propagation delay (comm) Up to 18 inputs and 8 input/output macro cells Programmable output polarity Power-up reset on all registers Register Preload capability @ Synchronous Preset/Asynchronous Reset Security fuse to prevent duplication of proprietary designs Design support provided using AMAZE software development package and other CAD tools for PLDs Available in 300mil-wide DIP with quartz window, plastic DIP (OTP) or PLCC (OTP) APPLICATIONS Battery powered instruments Laptop and pocket computers industrial contro! Medical instruments Portable communications equipment WSE D 7110826 0031446 5 ESPHIN T~4bo-19-\3_ ; Product specificatio ee Sec ee PIN CONFIGURATIONS N and FA Packages to/CLK od Vf Voc 1 [2] [19] F7 2 [3] 13] FS 13 [4] 7] Fs 4} 7N fe is [6] VL J 45] F3 te (7 14} F2 7 [8] a3) FA is [9] [13] Fo GND (35) [a3] 19/0 N = Plastic DIP (300mi-wide) FA = Ceramic DIP with Quartz Window (300mi-wide) A Package to/ 12. 11 CLKVgg FF? lon 0 Yi 13 [4] [16] F6 4 [5] 7] FS is [5] 6] F4 15] F3 fre ta GND I/ FO Ft OE A = Plastic Leaded Chip Carrler PIN LABEL DESCRIPTIONS I Dedicated input B Bidirectional input/output oO Dedicated output D Registered output (D-type flip-fiop) F Macrocell Input/Output GLK Clock Input OE Output Enable Veco Supply Voltage GND | Ground ORDERING INFORMATION ; DESCRIPTION OPERATING CONDITIONS ORDER CODE 20-Pin Plastic Dual In-Line Package 300mil-wide (tpp = 25ns) Commercial PLO18V8Z25N 20-Pin Ceramic Dual In-Line Package 300mil-wide with quartz window (tpp = 25ns) Temperature Range PLO1SV8Z25FA 20-Pin Plastic Leaded Chip Carrier 350mil square (tpp = 25ns) cE 5% Power Supplies PLCi8V8Z25A 20-Pin Plastic Dual In-Line Package 300mil-wide (tpp = 30ns) Industrial PLC 18V8ZIAN 20-Pin Ceramic Dual tn-Line Package 300mil-wide with quartz window (tpp = 30ns) Temperature Range PLO18V8ZIAFA 20-Pin Plastic Leaded Chip Carrier 350mil square (tpp = 30ns) + 5% Power Supplies PLC18V8ZIAA @PAL is a registered trademark of Monolithic Memories, inc., a wholly owned subsidiary of Advancd Micro Devices, Inc. October 17, 1991 2 853-1580 04372PHILIPS INTERNATIONAL SED) & 71L06b OO31447 2 EXPHIN T-Alo -19-13 Philips Semiconductors . Product specification Zero standby power universal PAL devices LOGIC DIAGRAM PLC18V8Z25/PLC18V8ZIA fO/CLK {1 F3 FI 11) 1s/OE SUSE SASS QE! ASS SP S28 rir BABS 9.2919 CELL NOTES: . In the unprogrammed or virgin state: Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell, The clock and OE functions are disabled. Alt cells are in a conductive state, All output macro calls (OMG) are contigured as bidirectional VO, with the outputs disabled via the All AND gate bocations are pulled to a logic *0* (Low). direction term. Output polarity is inverting. Denotes a programmable cell location, October 17, 1991 3PHILIPS INTERNATIONAL USE D EA 7130826 0030448 9 KEPHIN THbo 19-13 Philips Semiconductors Product specification Zero standby power universal PAL@devices PLC18V8Z25/PLC18V8ZIA PAL DEVICE TO PLC18V8Z OUTPUT PIN CONFIGURATION FUNCTIONAL DIAGRAM CROSS REFERENCE , 16L8 PIN | PLC | 16Hs | 16R4 | t6R6 | tena | 16L2 | ALA | 12h ee NO. 18V8Z ters 46RP4 | 16RP6 | 16RP8 i6p2 | 14p4 | 12P]6 | i0P8 1 Ip/CLK l CLK CLK CLK I [ 1 | 19 F7 B B B D | oO zy - tf 18 F6 B B D D 1 | oO oO 2 a5 Qo 17 F5 B D D D | oO oO oO . WS . tS 16 F4 B D D D O Oo O Oo . S3 = 15 F3 B D D D fe) oO oO O Vv Be FI 14 F2 B D D D I oO Oo Oo = 8 13 Fi B B D D I | Oo Oo 12 FO B B B Oo 8 Fo 1 1/OE 1 OE OE OE l | I I * IgE The Signetics state-of-the-art Floating-Gate devices prior to shipment to the customer. CMOS EPROM process yields bipolar Additionally, this allows Signetics to equivalent performance at less than extensively stress test, as well as ensure the one-quarter the power consumption. The threshold voltage of each individual EPROM erasable nature of the EPROM process cell. 100% programming yield is subsequently enables Signetics to functionally test the guaranteed. OUTPUT MACRO CELL (OMC) THE OUTPUT MACRO CELL (OMC) The PLC18V8Z series devices have 8 FROM AND individually programmable Output Macro ARRAY 4 10 ALL OMCs Cells. The 72 AND inputs (or product terms) _ tet from the programmable AND array are \ 1 connected to the 8 OMCs in groups of 9. DIRECTION CONTROL TERM i | Eight of the AND terms are dedicated to logic Veo! " OF functions; the ninth is for asynchronous ; 50 MUX direction control, which enables/disables the alo: 10 | respective bidirectional 1/0 pin. Two product as Lo | terms are dedicated for the Synchronous - | Preset and Asynchronous Reset functions. FROM | ! Each OMC can be independently AND a, o1 programmed via 16 architecture contro! bits, ARRAY D it MUX " ACi, and AC2, (one pair per macro cell), | E CuTPuT ak-t+eoo | Similarly, each OMC has a programmable | ~ ontaoe | tk I _ I output polarity control bit (Xn). By configuring i ACt pte >> | the pair of architecture control bits according | | I to the configuration cell table, 4 different | Acai De configurations may be implemented, Note | = | that the configuration cell is automatically $. } ! 1 ! Fp 10 programmed based on the OMC ! ' i MUX a ! configuration. | if Li L-~ Pmt 4 = 4 DESIGN SECURITY wat A The PLC18V8Z series devices have a CE programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved. NOTE: = Denotes a programmable cell location. October 17, 1991 4PHILIPS INTERNATIONAL Philips Semiconductors 4SE D ES 7130826 0031449 O KGPHIN T= 40-19-13 Product specification Zero standby power universal PAL devices PLC18V8Z25/PLC18V8ZIA CONFIGURATION CELL A single configuration cell controls the functions of Pins 1 and 11. Refer to Functional Diagram. When the configuration cell is programmed, Pin 1 is a dedicated for all registered OMCs is common-from Pin 11 only, Output enable control of the bidirectional I/O OMCs is provided from the AND array via the direction product term. If any one OMC is configured as registered, enabled on Pins 1 and 11, respectively. if none of the OMCs are registered, the configuration cell will be programmed such that Pins 1 and 11 are dedicated inputs. The programming codes are as follows: anaes the confouraioncalte., the configuration cell wil be automatically Pin 1 =CLK, Pin 11 = OE L onerogrammed, Fins Yang taro oth thatthe clockand output enable functions are L_Pis.1and Pin tf = Input H CONTROL CELL CONFIGURATIONS FUNCTION ACt, AC2y CONFIG. CELL COMMENTS Registered mode Programmed Programmed Programmed pede ae skond OMOs tern OE tren. Bidirectional I/O mode! Unprogrammed Unprogrammed Unprogrammed Bins 1 and 11 are decicated inp only. Fixed input mode Unprogrammed Programmed Unprogrammed Pins 1 and 11 are dedicated inputs. Fixed output mode Programmed Unprogrammed Unprogrammed foodbeck bath ite Poe deetied NOTE: . 1. This is the virgin state as shipped from the factory. ARCHITECTURE CONTROLAC1 and AC2 11] OE F(D), F (D) OMC CONFIGURATION CODE REGISTERED (0-TYPE) D s ) >_-- F(B), F (8) OMC CONFIGURATION BIDIRECTIONAL 1/0! B (COMBINATORIAL) s = ) >__ FO), F ) OMG CONFIGURATION | CODE FIXED OUTPUT y++_- rw OMC CONFIGURATION CODE FIXED INPUT { Vv se} Kal-+f>o- ro. Fo AR ; OE CONFIGURATION CELL | CODE PIN t= CLK L PIN 11 = DE Nc sp AR CONFIGURATION CELL | CODE PIN 1 = INPUT H8 PIN 11 = INPUT NOTE: Output polarity is inverting. Aahonwn A factory shipped unprogrammed device is configured such that: . This is the initial unprogrammed state. All cells are in a conductive state. All AND gates are pulled to a fogic 0 (Low). Pins 1 and 11 are configured as inputs 0 and 9. The clock and OE functions are disabled. All Output Macro Cells (OMCs) are configured as bidirectional 1/O, with the outputs disabled via the direction term. This configuration cannot be used if any OMCs are configured as registered (Code = D). The configuration cell will be automatically configured to ensure that the clock and output enable functions are enabled on Pins 1 and 11, respectively, if any one OMC is programmed as registered, October 17, 1991- PHILIPS INTERNATIONAL HSE) 7110626 OO3L4S5O 7 ESPHIN T= Alo - 19-13 Philips Semiconductors . Product specification Zero standby power universal PLC18V8Z25/PLC18V8ZIA PAL devices ABSOLUTE MAXIMUM RATINGS! : THERMAL RATINGS SYMBOL PARAMETER RATINGS UNIT TEMPERATURE Vec Supply voltage 0.5 to +7 Vpc Maximum junction 160C : 4.5 to .5 (Industrial Maximum ambient 75C Veo Operating supply voltage 4.75 10 528 (Commercal) Voc Allowable thermal rise 75C VIN Input voltage -0.5 to Vog + 0.5 Voc ambient to junction Vout Output voltage -0.5 to Veg + 0.8 Voc lin Input currents "=10 to +10 mA lout Output currents +24 mA Tamp Operating temperature range on 78 (Commaraah C Ts1g Storage temperature range -85 to +150 C NOTE: 1, Stresses above those listed may cause malfuncion or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. AC TEST CONDITIONS VOLTAGE WAVEFORMS +3.0V Voc? | +V Ss C2 at J INPUTS , I el 19 DUT AAA VV E:) = oT Bw I ot ___+ B Bz : x GND OUTPUTS => : ~ MEASUREMENTS: 4 All circuit delays are measured at the +1.5V level of = inputs and outputs, unless otherwise specified. NOTE: Cy and Co are to bypass Vcc to GND. Input Pulses October 17, 1991 6PHILIPS INTERNATIONAL HSE D 7110826 0032451 9 EAPHIN Philips Semiconductors Zero standby power universal PAL devices T-Ab (9-13 Product specification PLC18V8Z25/PLC18V8ZIA DC ELECTRICAL CHARACTERISTICS Commercial = 0C < Tamp < +75C, 4.75V < Voc = 5.25V; Industrial = 40C < Tay < +85C, 4.5V < Voc < 5.5V LIMITS SYMBOL PARAMETER TEST CONDITION MIN TYP! MAX UNIT input voltage Vit Low Voc = MIN 0.3 0.8 Vv Output voltage? V L Voc = MIN, lo, = 20pA 0.100 Vv OL ow Voce = MIN, lo, = 24mA 0.500 Vv i Voc = MIN, loy =3.2mA 2.4 Vv Vou High Voc = MIN, loy = 202A Veo - 0.1V Vv Input current Ie Low Vin= GND 10 pA hy High Vin = Veo 10 HA Output current : Vout = V 10 lo(orr) Hi-Z state Vour = GND ~10 A los Short-circuit$ : Vout = GND 130 mA loc Voc supply current (Standby) Voc = MAX, Vin = 0 or Voc 100 pA lec/f Vcc supply current (Active)4 Voc = MAX (CMOS inputs)5 6 1.5 mA/MHz Capacitance Voc = 5V Cy Input Vin = 2,0V 12 pF Cg vo . Vp = 2.0V 15 pF NOTES: 1. All typical values are at Veg = 5V, Tam = +25C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short-circuit should not exceed one second. Test one at a time. 4. Tested with TTL input levels: Vi, = 0.45V, Vin = 2.4V, Measured with all outputs switching. 5. Alcc/TTL input = 2mA. , 6. Alce vs frequency (registered configuration) = 2mA/MHz. 7. Ty for Pin 1 (lo/CLK) is + 104 with Vin = 0.4V. 8. Vin includes CLK and OE if applicable, 15 10 L < Va E / Oo 2 N Atpp YY won| /| 0 0 2 4 6 8 10 0 20 40 60 80 100 120 140 160 180 200 f{MHz) OUTPUT CAPACITANCE LOADING (pF) Figure 1. icg vs Frequency Figure 2. Atpp vs Output Capacitance (Worst Case) Loading (Typical) October 17, 1991 7PHILIPS INTERNATIONAL USE D 7410826 OO3L452 0 ESPHIN T-4lo- 19-13 Philips Semiconductors . Product specification Zero standby power universal PAL devices AC ELECTRICAL CHARACTERISTICS Commercial = 0C < Tam < +75C, 4.75V < Voc < 5.25V; Industrial = 40C < Tamp < +85C, 4.5V < Voc < 5.5V; Ro = 3902 PLC18V8Z25/PLC18V8ZIA PLC18V8Z25 PLC18V8ZIA TEST CONDITION! (Commercial) (Industrial) SYMBOL PARAMETER FROM TO Ry (0) CL MIN MAX | MIN MAX UNIT (pF) Pulse width Clock period tcxp (Minimum tis + texo) CLK + CLK + | 200 50 33 40 ns toKH Clock width High CLK + CLK 200 50 15 20 ns teKL Clock width Low CLK= CLK + 200 50 16 20 ns tanw Async reset pulse width I+, Ft 14, FF 25 30 ns Hold time ty tor feedback CLK+ | Inputs 200 50 0 0 ns Setup time tis Quacaten tine It,Ft | CLK+ 200 so | 18 22 ns Propagation delay Delay from input tpp to active output I+, Ft. F+ 200 50 25 30 ns texo | Clock High to outputvalid | cin, | Fe 200 50 15 18 | ns Product term enable to Active-High R = 1.5k 3 : toes outputs off 1, Fe Fa Active-LowR=550 | 5 25 30 ns Product term disable to From Voy R =e 2 OH oor outputs off It, Fe Ft From Vo, R = 200 5 25 30 ns Pin 11 output disable High From Voy R = 2 tone to outputs off OE - Ft From Vo. R = 200 5 20 26 ns Pin 11 output enable to Active-High R = 1.5k 3 og2 active output OE + Ft Active-LowR=550 | 20 a ns tarp Async reset delay It, Ft Fe : 30 35 ns tarRR Async reset recovery time tt, Ft CLK + 20 25 ns tspa Sync preset recovery time t+, Ft CLK + 20 25 ns tppR Power-up reset Veo + Fe 25 30 ns Frequency of operation fax Maximum frequency Vhs + toxo) 200 | 50 | | 30 | | 26 | MHz NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit) 2. For 3-State output; output enable times are tested with C, = 50pF to the 1.5V level, and.S; is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with C, = 5pF. High-to-High impedance tests are made to an output voltage of V7 = (Voy 0.5V) with S; open, and Low-to-High impedance tests are made to the V7 = (Vo, + 0.5V) level with S, closed. 3. Resistor values of 1.5k and 550Q provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level. 4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns. : October 17, 1991 8PHILIPS INT ERNATIONAL Philips Semiconductors Zero standby power universal PAL devices USE D El 7110826 0031453 2 BAPHIN T-4lo-A-13 Product specification PLC18V8Z25/PLC18V8ZIA POWER-UP RESET In order to facilitate state machine design and testing, a power-up reset function has been incorporated in the PLC18V8Z. All internal registers will reset to Active-Low (logical 0") after a specified period of time (tepr). Therefore, any OMC that has been configured as a registered output will always produce an Active-High on the associated output pin because of the inverted output buffer. The internal feedback (Q) of a registered OMC will also be set Low. The programmed polarity of OMC will not affect the Active-High output condition during a system power-up condition. TIMING DIAGRAMS VO, REG. VALID INPUT VAUD INPUT FEEDBACK . - H# t's >e tH -K tokH ICKL CLK PIN 11 OE _|_S tckep PN . = REGISTERED OUTPUTS + tcKo 3-STATE ANY INPUT 4, OIRECTION CONTROL NOTE: Cp COMBINATORIAL OUTPUTS Veo 7 F bay 4 (OUTPUTS) 7 , y / y y , sen ZILLI XX Switching Waveforms ton1 toe1 y 3-STATE +5V ov Vou VoL [ LB +V ov be 'CKL oH 4s 'CKH i {KL tcKp Power-Up Reset Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled). October 17, 1991T= 4h -(943 PHILIPS INTER NATIONAL NSE D E@ 7110826 0031454 4 EEPHIN Philips Semiconductors Product specification Zero standby power universal PAL devices PLC18V8Z25/PLC18V8ZIA TIMING DIAGRAMS (Continued) | ASYNCHRONOUS RESET INPUT tARD REGISTERED OUTPUT " 'ARR CLOCK . . 7 Asynchronous Reset 4s oH tsPR SYNCHRONOUS : . PRESET INPUT om NY tcKo REGISTERED OUTPUT Synchronous Preset October 17, 1991 10 5 xega SeayPHILIPS INTERNATIONAL Philips Semiconductors Zero standby power universal PAL devices HSE D 7410826 0032455 b ESPHIN TW -19-13 Product specification PLC18V8Z25/PLC18V8ZIA REGISTER PRELOAD FUNCTION (DIAGNOSTIC MODE ONLY) In order to facilitate the testing of state machine/controller designs, a diagnostic mode register preload feature has been incorporated into the PLC18V8Z series device. This feature enables the user to load the registers with predetermined states while a super voltage is applied to Pins 11 and 6 (I9/OE and I5). (See diagram for timing and sequence.) . To read the data out, Pins 11 and 6 must be returned to normal TTL levels. The outputs, FO F7, must be enabled in order to read REGISTER PRELOAD (DIAGNOSTIC MODE) data out. The Q outputs of the registers will reflect data in as input via FO F7 during preload. Subsequently, the register Q output via the feedback path will reflect the data in as input via FO F7. Refer to the voltage waveform for timing and voltage references. tp, = 10psec. 120V 12.0 (WOE (PIN 11) 5.0V 5.0V tL, tel tpt LPL) tPL tp EVOL) 12.0 15 | (PIN 6) | 5.0V | _ _ | tol ae CLK iCLK ~ ~ Y (PIN 4} | / L roe tcKL HICK: 50-7 4 PRELOAD DATAIN }_____ PRELOAD DATA OUT DATA OUT FO-7 LY se WLI. 1X 1-4, 6-8 October 17, 1991 11PHILIPS INTERNATIONAL Philips Semiconductors Zero standby power universal PAL devices USE D Ea 71108cb OO3L45b 4 ES PHIN THA 19-13 Product specification PLC18V8Z25/PLC18V8ZIA LOGIC PROGRAMMING The PLC18V8Z series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Signetics AMAZE, SLICE and SNAP design software packages. ABEL CUPL and PALASM 90 design software packages also support the PLC18V8Z architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. OUTPUT POLARITY - (0, B) PLC18V8Z logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by AMAZE and SLICE only. Both AMAZE and SLICE design packages are available, free of charge, to qualified. users. With Logic programming, the AND/OR/Ex-OR gate input connections necessary to implement the desired logic function are coded directly from logic equations using the ACTIVE LEVEL INVERTING! L ACTIVE LEVEL CODE NONANVERTING H AND ARRAY - (I, B) Program Table. Similarly, various OMC configurations are implemented by programming the Architecture Control bits AC1 and AC2., Note that the configuration cell is automatically programmed based on the ONC configuration. In this table, the logic state of Variables I, P and B associated with each Sum Term S is assigned a symbol which results in the proper fusing pattem of corresponding link pairs, defined as follows: i 1,5 poly | i LB L 1B .po_ 1B P STATE CODE STATE woe T | i 1B upol | 1B CODE STATE DON'T CARE - INACTIVE! o LB CODE STATE CODE H 18 L NOTE: 1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state. ee ABEL is a trademark of Data VO Cop. CUPL is a trademark of Logical Devices, Inc. PALASM Is a registered trademark of AMD Corp. October 17, 1991 12PHILIPS INTERNATIONAL Philips Semiconductors Zero standby power universal PAL devices HSE D El 7110826 0033457 T EPHIN T* Yo 49-13 Product specification PLC18V8Z25/PLC18V8ZIA ERASURE CHARACTERISTICS (For Quartz Window Packages Only) The erasure characteristics of the PLC18V8Z Series devices are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lighting could erase a typical PLC18V8Z in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the PROGRAMMING PLC18V8Z is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure. The recommended erasure procedure for the PLC18V8Z is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15Wsec/cm?. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000,W/cm? power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm?). Exposure of these CMOS EPLDs to high intensity UV tight for longer periods may cause permanent damage. The maximum number of guaranteed erase/write cycles is 50. Data retention exceeds 20 years. The PLC 18V8Z25 is programmable on conventional programmers for 20-pin PAL devices. Refer to the following charts for qualified manufacturers of programmers and software tools: PROGRAMMER MODEL PROGRAMMER MANUFACTURER FAMILY/PINOUT CODES System 29B, LogicPak 303A-011A; VO9 (DIL). DATA VO CORPORATION 303A-011B; 04 (PLCC) 10525 WILLOWS ROAD, N.E. UNISITE 40/48 - REDMOND, WASHINGTON 98073-9746 V2.6 (DIL) B6/4F Chipsite (PLCC) - v2.8 (800)247-5700 MODEL 60 360A001 (DIL) 360A006 (PLCC) STAG MICROSYSTEMS, INC. ZL30/30A PROGRAMMER 1600 WYATT DRIVE REV. 30434 (DIL) SUITE 3 30A001 Adaptor (PLCC) 12/205 SANTA CLARA, CALIFORNIA 95054 PPZ PROGRAMMER (408)988-1118 TBA SOFTWARE MANUFACTURER DEVELOPMENT SYSTEM SIGNETICS COMPANY SNAP 811 EAST ARQUES AVENUE REV. 1.6 AND LATER P.O. BOX 3409 SUNNYVALE, CALIFORNIA 94088-3409 SLICE REV. 1.0 AND LATER (408)891-2000 AMAZE SOFTWARE REV. 1.8 AND LATER DATA /0 10525 WILLOWS ROAD, N.E. ABEL SOFTWARE P.O. BOX 97046 REDMOND, WASHINGTON 98073-9746 (800)247-5700 LOGICAL DEVICES, INC. 1201 NORTHWEST 65TH PLACE CUPL SOFTWARE FORT LAUDERDALE, FLORIDA 33309 (800)331-7766 17, 1991 13PHILIPS INTERNATIONAL Philips Semiconductors 45E D 7410826 0033458 1 ESPHIN TMlo- 14-13 Product specification Zero standby power universal PAL devices PLC18V8Z25/PLC18V8ZIA PROGRAM TABLE October 17, 1991 the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as combinatorial Pins 1 and 11 are configured as inputs 0 and 9, respectively, via with the outputs disabled via the direction control term. *All AND gate locations are pulled to a logic 0 (Low). In the unprogrammed or virgin state: Output polarity is inverting. NOTES: CF(XXXX) CUSTOMER NAME PURCHASE ORDER # SIGNETICS DEVICE # CUSTOMER SYMBOLIZED PART # TOTAL NUMBER OF PARTS PROGRAM TABLE # VARIABLE NAME CONFIGURATION CELL ARCH, CONTROL BITS ARD ARRAY CONTROL OR ARRAY (AXED) ORC ARCH OUTPUT POLARTY DATA CANNOT BE ENTERED WTO THE OR ARRAY FIELD REGISTERED p || (NONINVERTING H] | DUE To THE FIXED NATURE AD-TWPE INVERTING L || OF THE DEVICE ARCHITEC. FAXED INPUT { TURE, CONAG. CELL* FAXEO OUTPUT oO PINT = CLK: PN DE OIRECTION CONTROL] D BIOIRECTIONAL1O [8 | | | PN ; an ; or ACTWE OUTPUT | A + = NOT USED * THE CONFIGURATION CELL iS AUTOMATICALLY PROGRAMMED BASED ON THE OMC ARCHITECTURE. **FOR SP, AR: ~" IS NOT ALLOWED. 14PHILIPS INTERNATIONAL USE ) @ 7130826 0032459 3 BAPHIN T=Ylo -\9- \3 Philips Semiconductors Product specification Zero standby power universal ' PAL devices PLC18V8Z25/PLC18V8ZIA SNAP RESOURCE SUMMARY DESIGNATIONS by/CLK SDINVE:! 0 CONFIG. CELL ENINVS: 3 {4 SOKENS: "Te a BFE ano, [Sh ox zo oer rz SNOUTVa: la Te] a5 ome FG z . 3 e a -Shy, e ~ ax 9 ttt zo SNOUT Va: 7 Te Sie omc Fi o = PH, 2 . {) SNOUTVR: 13 one Fo I _ {88 J UCCONHG. 7 AR__loet cette | IgE fe SEE st Ie FROM AND ARRAY A TOALLOMs pow ee ee | | _ DIRECTION CONTROL TERM | | a} & | ae | | FROM ASE DFR: Soe LF] ARRAY D | OUTPUT = POLARITY tICOLK | CONTROL ] ACI ot 1 it ni rt KORINE: 1 a 1 | AC2p ~ i I 1 4 = t 14 | i tt ~<] { t 4 | ' iG | Poot | 1 i i bee NOTE: \ 1 # Denotes a programmabie cell location. Y YY TO ALL OMCs October 17, 1991 15Product specification To lo -19-73 PLC18V8Z25/PLC18V8ZIA 74110826 OO314460 T KEIPHIN 4S5E D Zero standby power universal PAL devices 20-PIN (300 mils wide) PLASTIC DUAL IN-LINE (N) PACKAGE Philips Semiconductors (z9"z } o0'0 (sz"0) o100 | (cooL) s6e'o. (g0) $100 ( BL0N) fue(292) 006'0 am| |} ty ose i Wa cy poe (150) oz0'0 \ (680) Se00 | t (262) Sito (Eve) Seto (S 310N) ea O0c'O @ te) oze0 do} OUy WOdy PAMAIA USYM OZ# Ul 0} SSIMYOOPOIJOJUNDD SNURUOD pUe L# Uld YUM ULIS SIsqWINU Uig 9 | aueyd oO} sejnoIpUadsed 8q 0] PSUIENSUCO SpE] Sy] YIM Paunseaw SUOISUaLUIP ASA! Ss apis Aue uo (Wwtugz9) You! 010 pasoxa jou yeYys sualsnjold Jo Ysel} ploy] SuoIsnsjold JO Ysey plow apnjoul you Op pue Apog pepjow auj uo stunjep soualajal ese .3, pue iq, VL. P Z8GL - WS 'PLA ISN Jad Bulouesajo} pue uolsuawiq (S@/Z g anss}) spe9] oz (oyse|d) Bupeds moi youl 00g'o eBeyoed (4jq) aur7-uy jenq puepuEys 10} AV-LO0-SW YonesyHedg Q3AQAP O} wWojuCS suo|suawIp aBeyoeg Z sesoujuased ul UMOYS Ose OLS S@YOUl :UOISUeWIP BuyjouoD *| SALON (so'e) ozt'0 (19"e) seto (er'e) Selo (90r} o910 y (@uccroo]Oa[s [1S] | (vs92) Spo" (vit) sro'o (69!) 7900 (se92z) zSo't Osa (ys"2) coLo A (e2'9) Spz"o (ape) ss2"0 ! Te ae yy oy PHILIPS INTERNATIONAL NL1 (er'0) 2100 (90) ezoo 16 E] tL | AS 853-0408B 02880 October 17, 1991PHILIPS INTERNATIONAL Philips Semiconductors USE D o 721082b 00 Zero standby power universal PAL devices 3u4bi 1 ESIPHIN Ts Ylo- 19-13 Product specification PLC18V8Z25/PLC18V8ZIA 20-PIN (300 mils wide) CERAMIC DUAL IN-LINE WITH WINDOW (FA) PACKAGE SEE NOTE 6 853-0584 88099 078 (1.98) ___ 078 (1.98) O12 (.30) | 012 (30) RAR AAA Ss A ds fr 306. (7.77) _/ ,285 (7.24) [Pin # 1}- eee el L100 (2.64) BSC 975 (24.73) aE 940 (23.68) oy (e088 (1.47) ob 070 (1.78) 030 (76) "(050 (1.27) | .200 (5.08) 7} Lt 1465 (4.19) ' | EcaNe | 165 (4.19) 125 (3.18) ar an WUE G.o10 54S & O10 (.254 {L_ 2 _ pea a0 aai_S | NOTES: 1. 2. 3. 4. . Pin numbers start with pin #1 and continue . Denotes window location for EPROM products. Controlling dimension: inches. Millimeters. ara shown in parentheses. Dimensions and tolerancing per ANSI Y14.5M - 1962. "T", "D", and "E" are reference datums on the body and include allowance for glass overrun and meniscus on +4 saal line, and lid to base mismatch. tes dimensions me red with the leads constrained to be perpendicular t. alane T. counterclockwise to pin #20 when viewed from the top, 320 (8.13) {~ .290 (7.37) 475 (4.45) 145 (3.68) 035 (.89) 020 (51) 018 (98) -010 (25) _| BSC .300 (7.62) (NOTE 4) 395 (10.03) (NOTE 4) | Yd aan ot 1T 300 (7.62) October 17, 1991 17PHILIPS INTERNATIONAL 4YSE D Ea 7110826 OO39L4b2 3 EEPHIN FAL -19-(3 Philips Semiconductors : Product specification Zero standby power universal PAL devices 20-PIN PLASTIC LEADED CHIP CARRIER (A) PACKAGE PLC18V8Z25/PLC18V8ZIA oT 007 018 1 6 @]0-E ] [002 Ns NIB 39511003) [6] 007 1018 1 O[AGIF-6 ) -A-J AN 305.0976 1 : 1. PACKAGE DHENSIONS CONFORM TO JEDEC SPECIFICATION {200 15081) HO-047-AA FOR PLASTIC LEADED CHIP CARRIER 20 LEADS, 050 INCH LEAD SPACING. SQUARE. USSUE A, 10/31/84). mee! CJA BLOT OWTSTEOD ED) 2 contRoLtns DMENSIONS RCHES. METRIC DHENSIONS IN mm 3 PLACES ARE SHOWN IN PARENTHESES, dboondh 3 OMENS'ONNG AND TOLERANCING PER ANS! 14.5M-1982 i t Affe] g ZX DATUM PLANE [EEEJLOCATED AT THE TOP OF HOLD PARTING PLS q | . LINE AND CONCIOENT WITH TOP OF LEAO. WHERE LEAD Exits PN 1--=}0 n 200 (508 J 395 1003) PLASTIC BOOY ] q Pp 305 9787 ] u A LOCATION TO DATUH(-A-]AND([-5-]TO BE OETERMNED AT PLANE | =E-] A | [HE]. THESE DATUMS 00 NOT INCLUDE HOLO FLASH. HOLO FLASH 7 PROTRUSION SHALL NOT EXCEED .006' (015 mm) ON ANY SIDE. 4 dee , 068 1 422 Vy p05 1 & A DATUM (0-E] AND [F-G] ARE DETERMINED WHERE THESE CENTER 042 (107) LEADS EXT FROM THE BOOY AT PLANE[-AZ). (sora SIDES 7. PIN NUMBERS CONTINUE COUNTERCLOEKWISE TO PA 20 (TOP 060 (152) VIEW) O] 007 1 08 TO[A@IF-G @]_ | 3561 9023 - HN cL joo2 N7 NTA 3501689) /. 8 SIGNETICS ORDER CODE FOR PRODUCT PACKAGED IN A PLC 1S 05611421 Vee 032 o81) THE SUFFIX 'A' APTER THE PROOUCT NUMBER. 0421107) 0261066) 025 (0645 HN. A\ APPLICABLE TO PACKAGES WITH PEDESTAL ONLY. 120 305) 090 (2293 os (038) | A e038) 4020 05) HN. & ao 457) PEDESTAL | CLEARANCE W/O t=}-_______-____ - PEDESTAL | STLET CLEARANCE EDESTAL SEATING Toor 1010 7 seatnG I A TT 7 PLANE A PLANE | 0214 053) {Gf 007 (018 1O]O-E .F-GG] 1981503) [dfot 025 Ts) XO) ETS)| 013 (033) . BACKIID O45 1 192) R = 0251 649 330.833) CECE BTS) EXO)} 330 (838) _ [blo (036 1@f0-E 20 PLACES Bov73a7y 3007371 853-0400 93885 Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheat contains the design target or goal specifications for product development. Specifications may change in any manner without notios, This data sheet contains proliminary data, and supplementary data will be published at a later date. Pretiminary Specification Preproduction Product Signetics reserves the right to make changes at any time without notice.in ordet to Improve design and Supply the best possible product. Product Specification Full Production This data sheet contains Fina! Specifications. Signetics reserves the tight to make changes at any time without notice, in order to Improve design and supply the best possible product. LIFE SUPPORT APPLICATIONS Signetics Products are not designed for use in life support appliances, devices, or systems where malfunction ofa Signetics Product can reasonably be expected to result in a personal injury. Signetics customers using or selling Signetics Products for use in such applications do so at their own risk, and agree to fully indemnify Signetics for any damages resulting from such improper use or sale. October 17, 1991 18