Dual Very Low Noise Precision
Operational Amplifier
OP270
Rev. E
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FEATURES
Very low noise density of 5 nV/√Hz at 1 kHz maximum
Excellent input offset voltage of 75 μV maximum
Low offset voltage drift of 1 μV/°C maximum
Very high gain of 1500 V/mV minimum
Outstanding CMR of 106 dB minimum
Slew rate of 2.4 V/μs typical
Gain bandwidth product of 5 MHz typical
Industry-standard 8-lead dual pinout
FUNCTIONAL BLOCK DIAGRAMS
00325-001
–IN A
1
+IN A
2
NC
3
V–
4
OUT A
16
NC
15
NC
14
V+
13
NC
5
NC
12
+IN B
6
NC
11
–IN B
7
OUT B
10
NC
8
NC
9
NC = NO CONNECT
OP270
Figure 1. 16-Lead SOIC
(S-Suffix)
00325-002
OP270
OUT A
AB
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead CERDIP
(Z-Suffix)
GENERAL DESCRIPTION
The OP270 is a high performance, monolithic, dual operational
amplifier with exceptionally low voltage noise density (5 nV/√Hz
maximum at 1 kHz). It offers comparable performance to the
industry-standard OP27 from Analog Devices, Inc.
The OP270 features an input offset voltage of less than 75 μV
and an offset drift of less than 1 μV/°C, guaranteed over the full
military temperature range. Open-loop gain of the OP270 is more
than 1,500,000 into a 10 kΩ load, ensuring excellent gain accuracy
and linearity, even in high gain applications. The input bias
current is less than 20 nA, which reduces errors due to signal
source resistance. With a common-mode rejection (CMR) of
greater than 106 dB and a power supply rejection ratio (PSRR)
of less than 3.2 μV/V, the OP270 significantly reduces errors
due to ground noise and power supply fluctuations. The power
consumption of the dual OP270 is one-third less than two OP27
devices, a significant advantage for power conscious applications.
The OP270 is unity-gain stable with a gain bandwidth product
of 5 MHz and a slew rate of 2.4 V/μs.
The OP270 offers excellent amplifier matching, which is
important for applications such as multiple gain blocks, low
noise instrumentation amplifiers, dual buffers, and low noise
active filters.
The OP270 conforms to the industry-standard 8-lead DIP
pinout. It is pin compatible with the MC1458, SE5532/A,
RM4558, and HA5102 dual op amps, and can be used to
upgrade systems using those devices.
For higher speed applications, the ADA4004-2 or the AD8676 are
recommended. For a quad op amp, see the OP470 data sheet.
OP270
Rev. E | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits ..................................................................................... 11
Applications Information .............................................................. 12
Voltage and Current Noise ........................................................ 12
Total Noise and Source Resistance ........................................... 12
Noise Measurements .................................................................. 14
Capacitive Load Driving and Power Supply Considerations .. 15
Unity-Gain Buffer Applications ............................................... 15
Low Phase Error Amplifier ....................................................... 16
Five-Band, Low Noise, Stereo Graphic Equalizer .................. 16
Digital Panning Control ............................................................ 17
Dual Programmable Gain Amplifier ....................................... 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
2/10—Rev. D to Rev. E
Change to General Description Section ........................................ 1
Change to Input Noise Current Density Parameter, Table 1 ...... 3
Change to Figure 18 ......................................................................... 8
Changes to Total Noise and Source Resistance Section ............ 13
Changes to Figure 41 ...................................................................... 16
2/09—Rev. C to Rev. D
Updated Format .................................................................. Universal
Reorganized Layout ............................................................ Universal
Changes to Figure 7 .......................................................................... 6
Changes to Figure 22 ........................................................................ 9
Deleted Applications Heading ...................................................... 11
Changes to Figure 44 ...................................................................... 17
Changes to Figure 46 ...................................................................... 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
4/03—Rev. B to Rev. C
Deletion of OP270A model ............................................... Universal
Edits to Features ................................................................................. 1
Changes to Specifications ................................................................. 2
Deletion of Wafer Limits and Dice Characteristics ...................... 4
Changes to Absolute Maximum Ratings ........................................ 4
Changes to Ordering Guide ............................................................. 4
Changes to Equations in Noise Measurements section ............. 10
Change to Figure 10 ....................................................................... 11
Updated Outline Dimensions ....................................................... 14
11/02—Rev. A to Rev. B
Updated Ordering Guide .............................................................. 15
9/02—Rev. 0 to Rev. A
Edits to Absolute Maximum Ratings .............................................. 5
Edits to Ordering Guide ................................................................ 15
2/01—Revision 0: Initial Version
OP270
Rev. E | Page 3 of 20
SPECIFICATIONS
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions
OP270E OP270F OP270G
Unit Min Typ Max Min Typ Max Min Typ Max
Input Offset Voltage VOS 10 75 20 150 50 250 μV
Input Offset Current IOS V
CM = 0 V 1 10 3 15 5 20 nA
Input Bias Current IB V
CM = 0 V 5 20 10 40 15 60 nA
Input Noise Voltage1 e
n p-p 0.1 Hz to 10 Hz 80 200 80 200 80 nV p-p
Input Noise Voltage Density2 e
n f
O = 10 Hz 3.6 6.5 3.6 6.5 3.6 nV/√Hz
e
n f
O = 100 Hz 3.2 5.5 3.2 5.5 3.2 nV/√Hz
e
n f
O = 1 kHz 3.2 5.0 3.2 5.0 3.2 nV/√Hz
Input Noise Current Density in f
O = 10 Hz 1.1 1.1 1.1 pA/√Hz
i
n f
O = 100 Hz 0.7 0.7 0.7 pA/√Hz
i
n f
O = 1 kHz 0.6 0.6 0.6 pA/√Hz
Large-Signal Voltage Gain AVO VO = ±10 V,
RL = 10 kΩ
1500 2300 1000 1700 750 1500 V/mV
VO = ±10 V,
RL = 2 kΩ
750 1200 500 900 350 700 V/mV
Input Voltage Range3 IVR ±12 ±12.5 ±12 ±12.5 ±12 ±12.5 V
Output Voltage Swing VO R
L ≥ 2 kΩ ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 V
Common-Mode Rejection CMR VCM = ±11 V 106 125 100 120 90 110 dB
Power Supply Rejection
Ratio
PSRR VS = ±4.5 V
to ±18 V
0.56 3.2 1.0 5.6 1.5 5.6 μV/V
Slew Rate SR 1.7 2.4 1.7 2.4 1.7 2.4 V/μs
Supply Current
(All Amplifiers)
ISY No load 4 6.5 4 6.5 4 6.5 mA
Gain Bandwidth Product GBP 5 5 5 MHz
Channel Separation1 CS
VO = ±20 V p-p,
fO = 10 Hz
125 175 125 175 175 dB
Input Capacitance CIN 3 3 3 pF
Input Resistance
Differential Mode RIN 0.4 0.4 0.4 MΩ
Common Mode RINCM 20 20 20 GΩ
Settling Time tS AV = +1, 10 V,
step to 0.01%
5 5 5 μs
1 Guaranteed but not 100% tested.
2 Sample tested.
3 Guaranteed by CMR test.
OP270
Rev. E | Page 4 of 20
ELECTRICAL SPECIFICATIONS
VS = ±15 V, −40°C ≤ TA ≤ 85°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions
OP270E OP270F OP270G
Unit Min Typ Max Min Typ Max Min Typ Max
Input Offset Voltage VOS 25 150 45 275 100 400 μV
Average Input Offset
Voltage Drift
TCVOS 0.2 1 0.4 2 0.7 3 μV/°C
Input Offset Current IOS V
CM = 0 V 1.5 30 5 40 15 50 nA
Input Bias Voltage IB V
CM = 0 V 6 60 15 70 19 80 nA
Large-Signal Voltage Gain AVO VO = ±10 V,
RL = 10 kΩ
1000 1800 600 1400 400 1250 V/mV
A
VO VO = ±10 V,
RL = 2 kΩ
500 900 300 700 225 670 V/mV
Input Voltage Range1IVR ±12 ±12.5 ±12 ±12.5 ±12 ±12.5 V
Output Voltage Swing VO R
L ≥ 2 kΩ ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 V
Common-Mode Rejection CMR VCM = ±11 V 100 120 94 115 90 100 dB
Power Supply Rejection
Ratio
PSRR VS = ±4.5 V to ±18 V 0.7 5.6 1.8 10 2.0 1.5 μV/V
Supply Current
(All Amplifiers)
ISY No load 4.4 7.2 4.4 7.2 4.4 7.2 mA
1 Guaranteed by CMR test.
OP270
Rev. E | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 18 V
Differential Input Voltage1 1.0 V
Differential Input Current1 ±25 mA
Input Voltage Supply voltage
Output Short-Circuit Duration Continuous
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) 300°C
Junction Temperature (TJ) −65°C to +150°C
Operating Temperature Range −40°C to +85°C
1 The OP270 inputs are protected by back-to-back diodes. To achieve low noise
performance, current-limiting resistors are not used. If the differential voltage
exceeds +10 V, the input current should be limited to ±25 mA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For military processed devices, refer to the Standard Micro-
circuit Drawing (SMD) available at the Defense Logistics
Agency website.
Table 4. Analog Devices Equivalent to SMD
SMD Part Number Analog Devices Equivalent
5962-8872101PA OP270AZMDA
ESD CAUTION
OP270
Rev. E | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
00352-004
10
3
4
5
6
7
8
9
2
1
1 10 100 1k
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
T
A
= 25°C
V
S
= ±15V
1/f CORNER = 5Hz
Figure 3. Voltage Noise Density vs. Frequency
00352-005
5
3
4
2
1
0 ±5 ±10 ±15 ±20
VOLTAGE NOISE DENSITY (nV/√Hz)
SUPPLY VOLTAGE (V)
T
A
= 25°C
AT 1kHz
AT 10kHz
Figure 4. Voltage Noise Density vs. Supply Voltage
00352-006
NOISE VOLTAGE (100nV/DIV)
TIME (1 sec/DIV)
0.1Hz TO 10Hz NOISE
T
A
= 25°C
T
S
= ±15V
Figure 5. 0.1 Hz to 10 Hz Input Voltage Noise
00352-007
10
1
0.1
10 100 1k 10k
CURRENT NOISE DENSITY (pA/√Hz)
FREQUENCY (Hz)
TA = 25°C
VS = ±15V
1/f CORNER = 200Hz
Figure 6. Current Noise Density vs. Frequency
00352-008
40
0
10
20
30
–30
–20
–10
–75 –50 –25 25 50 75 100 1250
VOLTAGE (µV)
TEMPERATURE (°C)
V
S
= ±15V
Figure 7. Input Offset Voltage vs. Temperature
00352-009
5
4
0
1
2
3
02341
CHANGE IN OFFSET VOLTAGE (µA)
TIME (Minutes)
5
T
A
= 25°C
V
S
= ±15V
Figure 8. Warm-Up Offset Voltage Drift
OP270
Rev. E | Page 7 of 20
00352-010
7
6
2
3
4
5
INPUT BIAS CURRENT (nA)
TEMPERATURE (°C)
V
S
= ±15V
V
CM
= 0V
–75 –50 –25 25 50 75 100 1250
Figure 9. Input Bias Current vs. Temperature
00352-011
5
4
0
1
2
3
INPUT OFFSET CURRENT (nA)
TEMPERATURE (°C)
V
S
= ±15V
V
CM
= 0V
–75 –50 –25 25 50 75 100 1250
Figure 10. Input Offset Current vs. Temperature
00352-012
7
6
2
3
4
5
INPUT BIAS CURRENT (nA)
COMMON-MODE VOLTAGE (V)
–12.5 –7.5 –2.5 2.5
–10.0 –5.0 0 5.0 7.5 12.5
10.0
T
A
= +25°C
V
S
= ±15V
Figure 11. Input Bias Current vs. Common-Mode Voltage
00352-013
130
100
110
120
10
20
30
40
50
60
70
80
90
CMR (dB)
FREQUENCY (Hz)
1 10 1k 10k 100k 1M100
T
A
= 25°C
V
S
= ±15V
Figure 12. CMR vs. Frequency
00352-014
6
4
5
3
2
0 ±5 ±10 ±15 ±20
TOTAL SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
+125°C
+25°C
–55°C
Figure 13. Total Supply Current vs. Supply Voltage
00352-015
8
7
2
1
0
3
4
5
6
TOTAL SUPPLY CURRENT (mA)
TEMPERATURE (°C)
V
S
= ±15V
–75 –50 –25 25 50 75 100 1250
Figure 14. Total Supply Current vs. Temperature
OP270
Rev. E | Page 8 of 20
00352-016
140
100
120
0
20
40
60
80
PSR (dB)
FREQUENCY (Hz)
1 10 1k 10k 100k 1M 10M 100M100
T
A
= 25°C
–PSR
+PSR
Figure 15. PSR vs. Frequency
00352-017
140
100
120
0
20
40
60
80
OPEN-LOOP GAIN (dB)
FREQUENCY (Hz)
1 10 1k 10k 100k 1M 10M 100M100
T
A
= 25°C
V
S
= ±15V
Figure 16. Open-Loop Gain vs. Frequency
00352-018
80
60
–20
0
20
40
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
1k 10k 100k 1M 10M
T
A
= 25°C
V
S
= ±15V
Figure 17. Closed-Loop Gain vs. Frequency
00352-019
25
15
20
–10
–5
0
5
10
OPEN-LOOP GAIN (dB)
FREQUENCY (MHz)
12345678910
T
A
= 25°C
V
S
= ±15V
PHASE SHIFT (Degrees)
180
160
140
120
100
80
PHASE
MARGIN = 62°
GAIN
PHASE
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency
00352-020
5000
1000
2000
3000
4000
0
0 ±5 ±10 ±15 ±20 ±25
OPEN-LOOP GAIN (V/mA)
SUPPLY VOLTAGE (V)
Figure 19. Open-Loop Gain vs. Supply Voltage
00352-021
80
70
40
50
60
PHASE MARGIN (Degrees)
TEMPERATURE (°C)
–75 –50 –25 25 50 75 100 125 1500
GAIN BANDWIDTH PRODUCT (MHz)
4
5
6
7
8
GBP
Ф
Figure 20. Phase Margin and Gain Bandwidth Product vs. Temperature
OP270
Rev. E | Page 9 of 20
00352-022
28
20
24
0
4
8
12
16
MAXIMUM OUTPUT SWING (V)
FREQUENCY (Hz)
1k 10k 100k 1M 10M
T
A
= 25°C
V
S
= ±15V
THD = 1%
Figure 21. Maximum Output Swing vs. Frequency
00352-023
15
12
13
14
5
6
7
8
9
10
11
MAXIMUM OUTPUT VOLTAGE (V)
LOAD RESISTANCE (Ω)
100 1k 10k
T
A
= 25°C
V
S
= ±15V POSITIVE
SWING
NEGATIVE
SWING
Figure 22. Maximum Output Voltage vs. Load Resistance
00352-024
50
40
0
10
20
30
SMALL-SIGNAL OVERSHOOT (%)
CAPACITIVE LOAD (pF)
0 200 400 600 800 1000
T
A
= 25°C
V
S
= ±15V
V
IN
= 100mV
A
V
= +1
Figure 23. Small-Signal Overshoot vs. Capacitive Load
00352-025
100
75
0
25
50
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
1k 10k 100k 1M 10M
T
A
= 25°C
V
S
= ±15V
A
V
= 100
A
V
= 10
A
V
= 1
Figure 24. Output Impedance vs. Frequency
00352-026
2.2
2.3
2.4
2.5
2.6
2.7
2.8
SLEW RATE (V/µs)
TEMPERATURE (°C)
V
S
= ±15V
–75 –50 –25 25 50 75 100 1250
–SR
+SR
Figure 25. Slew Rate vs. Temperature
00352-027
190
150
160
170
180
70
80
90
100
110
120
130
140
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
1 10 1k 10k 100k 1M100
TA = 25°C
VS = ±15V
VO = 20V p-p TO 10kHz
Figure 26. Channel Separation vs. Frequency
OP270
Rev. E | Page 10 of 20
00352-028
0.1
0.01
0.001
10 100 1k 10k
TOTAL HARMONIC DISTORTION (%)
FREQUENCY (Hz)
T
A
= 25°C
V
S
= ±15V
V
O
= 20V p-p
R
L
= 2kΩ
A
V
= 10
A
V
= 1
Figure 27. Total Harmonic Distortion vs. Frequency
00352-029
TA = 25°C
VS = ±15V
AV = +1
RL = 2kΩ
5V 20µs
Figure 28. Large-Signal Transient Response
00352-030
TA = 25°C
VS = ±15V
AV = +1
RL = 2kΩ
50mV 200ns
Figure 29. Small-Signal Transient Response
OP270
Rev. E | Page 11 of 20
TEST CIRCUITS
00325-031
1/2
OP270
500Ω
5kΩ
V
1
20V
p-p
1/2
OP270
CHANNEL SEPARATION = 20 LOG
50Ω
5kΩ
V
2
V
1
V
2
/1000
Figure 30. Channel Separation Test Circuit
00325-032
1/2
OP270
100kΩ
1/2
OP270
+18
V
–18V
200kΩ
100kΩ
2
1
7
3
6
5
4
8
Figure 31. Burn-In Circuit
OP270
Rev. E | Page 12 of 20
APPLICATIONS INFORMATION
VOLTAGE AND CURRENT NOISE Figure 33 also shows the relationship between total noise and
source resistance, but at 10 Hz. Total noise increases more
quickly than shown in Figure 32 because current noise is
inversely proportional to the square root of frequency. In
Figure 33, the current noise of the OP270 dominates the total
noise when RS is greater than 5 kΩ.
The OP270 is a very low noise dual op amp, exhibiting a typical
voltage noise density of only 3.2 nV/√Hz at 1 kHz. Because the
voltage noise is inversely proportional to the square root of the
collector current, the exceptionally low noise characteristic of
the OP270 is achieved in part by operating the input transistors
at high collector currents. Current noise, however, is directly
proportional to the square root of the collector current. As a
result, the outstanding voltage noise density performance of the
OP270 is gained at the expense of current noise performance,
which is normal for low noise amplifiers.
Figure 32 and Figure 33 show that to reduce total noise, source
resistance must be kept to a minimum. In applications with a
high source resistance, the OP200, with lower current noise
than the OP270, can provide lower total noise.
00352-034
100
10
1
100 1k 10k 100k
TOTAL NOISE (nV/
√
Hz)
SOURCE RESISTANCE (Ω)
RESISTOR
NOISE ONLY
OP200
OP270
To obtain the best noise performance in a circuit, it is vital to
understand the relationships among voltage noise (en), current
noise (in), and resistor noise (et).
TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calculated by
222 )()()( tsnnn eRieE ++=
where:
En is the total input-referred noise.
en is the op amp voltage noise.
in is the op amp current noise.
et is the source resistance thermal noise.
RS is the source resistance. Figure 33. Total Noise vs. Source Resistance
(Including Resistor Noise) at 10 Hz
The total noise is referred to the input and at the output is
amplified by the circuit gain. Figure 34 shows peak-to-peak noise vs. source resistance over
the 0.1 Hz to 10 Hz range. At low values of RS, the voltage noise
of the OP270 is the major contributor to peak-to-peak noise,
with current noise becoming the major contributor as RS
increases. The crossover point between the OP270 and the
OP200 for peak-to-peak noise is at a source resistance of 17 kΩ.
Figure 32 shows the relationship between total noise at 1 kHz
and source resistance. When RS is less than 1 kΩ, the total noise
is dominated by the voltage noise of the OP270. As RS rises
above 1 kΩ, total noise increases and is dominated by resistor
noise rather than by the voltage or current noise of the OP270.
When RS exceeds 20 kΩ, the current noise of the OP270
becomes the major contributor to total noise.
00352-035
1k
100
10
100 1k 10k 100k
PEAK-TO-PEAK NOISE (nV)
SOURCE RESISTANCE (Ω)
RESISTOR
NOISE ONLY
OP200
OP270
00352-033
100
10
1
100 1k 10k 100k
TOTAL NOISE (nV/
√
Hz)
SOURCE RESISTANCE (Ω)
RESISTOR
NOISE ONLY
OP200
OP270
Figure 34. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source Resistance
(Including Resistor Noise)
Figure 32. Total Noise vs. Source Resistance
(Including Resistor Noise) at 1 kHz
OP270
Rev. E | Page 13 of 20
For reference, typical source resistances of some signal sources are listed in Table 5.
Table 5. Typical Source Resistances
Device Source Impedance Comments
Strain Gage <500 Ω Typically used in low frequency applications.
Magnetic Tapehead, Microphone <1500 Ω Low IB is very important to reduce self-magnetization problems when
direct coupling is used. OP270 IB can be disregarded.
Magnetic Phonograph Cartridge <1500 Ω Low IB is important to reduce self-magnetization problems in direct-coupled
applications. OP270 does not introduce any self-magnetization problems.
Linear Variable Differential Transformer <1500 Ω Used in rugged servo-feedback applications. The bandwidth of interest is
400 Hz to 5 kHz.
00325-036
OP270
DUT
R1
5Ω
R2
5Ω
R3
1.24kΩ
OP27E
R5
909Ω
R4
200Ω
R13
5.9kΩ
R12
10kΩ
OP27E
OP42E
R9
306Ω
R10
65.4kΩR11
65.4kΩ
R8
10kΩ
C1
2µF
C4
0.22µF
D1, D2
1N4148
R6
600Ω
C2
0.032µF
C3
0.22µF C5
1µF
R14
4.99kΩe
OUT
GAIN = 50,000
V
S
= ±15V
Figure 35. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
OP270
Rev. E | Page 14 of 20
NOISE MEASUREMENTS
Peak-to-Peak Voltage Noise
The circuit of Figure 35 is a test setup for measuring peak-to-
peak voltage noise. To measure the 200 nV peak-to-peak noise
specification of the OP270 in the 0.1 Hz to 10 Hz range, the
following precautions must be observed:
• The device has to be warmed up for at least five minutes.
As shown in the warm-up drift curve (see Figure 8), the
offset voltage typically changes 2 μV due to increasing chip
temperature after power-up. In the 10 sec measurement
interval, these temperature-induced effects can exceed tens
of nanovolts.
• For similar reasons, the device has to be well shielded from
air currents. Shielding also minimizes thermocouple effects.
• Sudden motion in the vicinity of the device can also feed
through to increase the observed noise.
• The test time to measure noise of 0.1 Hz to 10 Hz should
not exceed 10 sec. As shown in the noise-tester frequency
response curve of Figure 36, the 0.1 Hz corner is defined by
only one pole. The test time of 10 sec acts as an additional
pole to eliminate noise contribution from the frequency
band below 0.1 Hz.
• A noise voltage density test is recommended when measuring
noise on several units. A 10 Hz noise voltage density mea-
surement correlates well with a 0.1 Hz to 10 Hz peak-to-peak
noise reading because both results are determined by the
white noise and the location of the 1/f corner frequency.
• Power should be supplied to the test circuit by well bypassed
low noise supplies, such as batteries. Such supplies will min-
imize output noise introduced via the amplifier supply pins.
00352-037
100
60
80
0
20
40
GAIN (dB)
FREQUENCY (Hz)
0.01 0.1 1 10 100
Figure 36. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise
Test Circuit Frequency Response
Noise Measurement—Noise Voltage Density
The circuit of Figure 37 shows a quick and reliable method for
measuring the noise voltage density of dual op amps. The first
amplifier is in unity gain, with the final amplifier in a noninverting
gain of 101. Because the noise voltages of the amplifiers are
uncorrelated, they add in rms to yield
(
)
(
)
(
)
2
2
101 nB
nA
OUT eee +=
The OP270 is a monolithic device with two identical amplifiers.
Therefore, the noise voltage densities of the amplifiers match,
giving
(
)
(
)
nn
OUT eee 21012101 2==
00325-038
e
OUT
(nV/√Hz) ≈ 101 (√2e
n
)
V
S
= ±15V
TO SPECTRUM ANALYZER
e
OUT
R1
100ΩR2
10kΩ
1/2
OP270
1/2
OP270
Figure 37. Noise Voltage Density Test Circuit
Noise Measurement—Current Noise Density
The test circuit shown in Figure 38 can be used to measure current
noise density. The formula relating the voltage output to the current
noise density is
()
S
nOUT
nR
HznV
G
e
i
2
2
/40−
⎟
⎠
⎞
⎜
⎝
⎛
=
where:
G is a gain of 10,000.
RS = 100 kΩ source resistance.
00325-039
OP270
DUT
R1
5ΩR2
100kΩ
R3
1.24kΩ
OP27E
R5
8.06kΩ
R4
200Ω
e
nOUT
GAIN = 10,000
V
S
= ±15V
TO SPECTRUM ANALYZER
Figure 38. Current Noise Density Test Circuit
OP270
Rev. E | Page 15 of 20
CAPACITIVE LOAD DRIVING AND POWER SUPPLY
CONSIDERATIONS
The OP270 is unity-gain stable and capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves the
capacitive load driving capability of the OP270.
In the standard feedback amplifier, the output resistance of the
op amp combines with the load capacitance to form a low-pass
filter that adds phase shift in the feedback network and reduces
stability. A simple circuit to eliminate this effect is shown in
Figure 39. The components C1 and R3 decouple the amplifier
from the load capacitance and provide additional stability. The
values of C1 and R3 shown in Figure 39 are for a load capacitance
of up to 1000 pF when used with the OP270.
00325-040
C1
200pF
V
IN
V
OUT
PLACE SUPPLY DECOUPLING
CAPACITOR AT OP270
OP270
V
+
R1
C3
0.1µF
C2
10µF
C1
1000pF
R2
C4
10µF
C5
0.1µF
R3
50Ω
+
V–
+
Figure 39. Driving Large Capacitive Loads
UNITY-GAIN BUFFER APPLICATIONS
When Rf ≤ 100 Ω and the input is driven with a fast, large signal
pulse (>1 V), the output waveform looks like the one in Figure 40.
During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and
a current, limited only by the output short-circuit protection, is
drawn by the signal generator. With Rf ≥ 500 Ω, the output is
capable of handling the current requirements (IL ≤ 20 mA at 10 V);
the amplifier stays in its active mode and a smooth transition occurs.
When Rf > 3 kΩ, a pole created by Rf and the input capacitance
(3 pF) of the amplifier creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 50 pF) in parallel with
Rf helps eliminate this problem.
00325-041
OP270
2.4V/µs
Rf
Figure 40. Pulsed Operation
OP270
Rev. E | Page 16 of 20
LOW PHASE ERROR AMPLIFIER
The simple amplifier depicted in Figure 41 utilizes a monolithic
dual operational amplifier and a few resistors to substantially
reduce phase error compared with conventional amplifier
designs. At a given gain, the frequency range for a specified
phase accuracy is more than a decade greater than that of a
standard single op amp amplifier.
The low phase error amplifier performs second-order fre-
quency compensation through the response of Op Amp A2 in
the feedback loop of A1. Both op amps must be extremely well
matched in frequency response. At low frequencies, the A1
feedback loop forces V2/(K1 + 1) = VIN. The A2 feedback loop
forces VO/(K1 + 1) = V2/(K1 + 1), yielding an overall transfer
function of VO/VIN = K1 + 1. The dc gain is determined by the
resistor divider at the output, VO, and is not directly affected by
the resistor divider around A2. Note that, like a conventional
single op amp amplifier, the dc gain is set by resistor ratios only.
Minimum gain for the low phase error amplifier is 10.
00325-042
1/2
OP270E
A2
1/2
OP270E
A1
R1
V
O
V
2
V
IN
R1
K1
R2 R2 = R1
ω
T
s
R2
K2
V
O
= (K
1
+ 1)V
IN
ASSUME A1 AND A2 ARE MATCHED.
A
O
(s) =
Figure 41. Low Phase Error Amplifier
Figure 42 compares the phase error performance of the low
phase error amplifier with a conventional single op amp
amplifier and a cascaded two-stage amplifier. The low phase
error amplifier shows a much lower phase error, particularly for
frequencies where ω/βωT < 0.1. For example, a phase error of
−0.1° occurs at 0.002 ω/βωT for the single op amp amplifier, but
at 0.11 ω/βωT for the low phase error amplifier.
00352-043
–7
–6
–5
–4
–3
–2
–1
0
PHASE SHIFT (Degrees)
FREQUENCY RATIO (1/βω)(ω/ω
T
)
0.001 0.005 0.01 0.1 1
LOW PHASE ERROR
AMPLIFIER
CASCADED
(TWO STAGES)
SINGLE OP AMP.
CONVENTIONAL DESIGN
0.05 0.5
Figure 42. Phase Error Comparison
FIVE-BAND, LOW NOISE, STEREO GRAPHIC
EQUALIZER
The graphic equalizer circuit shown in Figure 43 provides 15 dB
of boost or cut over a five-band range. Signal-to-noise ratio over
a 20 kHz bandwidth is better than 100 dB and referred to a 3 V
rms input. Larger inductors can be replaced by active inductors,
but consequently reduces the signal-to-noise ratio.
00325-044
1/2
OP270E 1/2
OP270E
R2
3.3kΩ
R1
47kΩ
R4
1kΩ
60Hz
TANTALUM
V
OUT
V
IN
R14
100Ω
R13
3.3kΩ
C2
6.8µF L1
1H
C1
0.47µF
R3
680Ω
200Hz
R6
1kΩ
800Hz
R8
1kΩ
3kHz
R10
1kΩ
10kHz
R12
1kΩ
+
TANTALUM
C3
1µF L2
600mH
R5
680Ω+
C4
0.22µF L3
180mH
R7
680Ω+
C5
0.047µF L4
60mH
R9
680Ω+
C6
0.022µF L5
10mH
R11
680Ω+
Figure 43. Five-Band, Low Noise Graphic Equalizer
OP270
Rev. E | Page 17 of 20
0
0325-045
1/2
OP270GP
V
IN
NC
R
FBA
1
1
23
2422
18
19 CS
WR
WRITE
CONTROL 20
6
5
7
3
24
3
21
V
DD
DAC8221P
28
4
0.01µF
+15V
–15V
OUT
I
OUT
A
I
OUT
B
AGND
DGND
5
1/2
OP270GP
DAC B
DAC A
+5V
10µF
–
+
10µF
–
+
0.1µF
R
FBB
V
REF
A
V
REF
B
DAC A/DAC B
DAC DATA BUS
PINS 6 (MSB) TO 17 (LSB)
OUT
DIGITAL PANNING CONTROL
Figure 44 uses a DAC8221 (a dual 12-bit CMOS DAC) to pan a
signal between two channels. One channel is formed by the
current output of DAC A driving one-half of an OP270 in a
current-to-voltage converter configuration. The other channel
is formed by the complementary output current of DAC A,
which normally flows to ground through the AGND pin. This
complementary current is converted to a voltage by the other
half of the OP270, which also holds AGND at virtual ground.
Gain error due to mismatching between the internal DAC
ladder resistors and the current-to-voltage feedback resistors is
eliminated by using feedback resistors internal to the DAC8221.
Only DAC A passes a signal; DAC B provides the second
feedback resistor. With VREFB unconnected, the current-to-
voltage converter, using RFBB, is accurate and not influenced by
digital data reaching DAC B. Distortion of the digital panning
control is less than 0.002% over the 20 Hz to 20 kHz audio
range. Figure 45 shows the complementary outputs for a 1 kHz
input signal and a digital ramp applied to the DAC data input.
DUAL PROGRAMMABLE GAIN AMPLIFIER Figure 44. Digital Panning Control
The dual OP270 and the DAC8221 (a dual 12-bit CMOS DAC)
can be combined to form a space-saving, dual programmable
amplifier. The digital code present at the DAC, which is easily
set by a microprocessor, determines the ratio between the internal
feedback resistor and the resistance that the DAC ladder presents
to the op amp feedback loop. Gain of each amplifier is
00352-046
5V5V 1ms
A
OUT
A
OUT
nV
V
IN
O4096
−=
where n is the decimal equivalent of the 12-bit digital code
present at the DAC.
If the digital code present at the DAC consists of all 0s, the
feedback loop opens, causing the op amp output to saturate. A
20 MΩ resistor placed in parallel with the DAC feedback loop
eliminates this problem with only a very small reduction in gain
accuracy.
Figure 45. Digital Panning Control Output
OP270
Rev. E | Page 18 of 20
00325-047
V
IN
B
1
19
18
WRITE
CONTROL 20
6
5
7
3
23
21
V
DD
DAC8221P
28
4
DGND
5
1/2
OP270GP
1/2
OP270EZ
DAC B
DAC A
+5V
0.01µF
+15
V
10µF
–
+
–15V
10µF
–
+
0.1µF
24
22
1
I
OUT
B
2
I
OUT
A
AGND
V
REF
B
4
V
REF
A
V
OUT
B
V
OUT
A
20MΩ
20MΩ
DAC DATA BUS
PINS 6 (MSB) TO 17 (LSB)
R
FBB
V
IN
A3R
FBA
Figure 46. Dual Programmable Gain Amplifier
BIAS
00325-003
V–
–
IN
V
+
OUT
+IN
Figure 47. Simplified Schematic
(One of Two Amplifiers Is Shown)
OP270
Rev. E | Page 19 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13)
MIN 0.055 (1.40)
MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
14
58
Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP]
Z-Suffix
(Q-8)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 49. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
OP270
Rev. E | Page 20 of 20
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013- AA
032707-B
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
Figure 50. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
S-Suffix
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
TA = +25°C
VOS Max (μV)
θJC
(°C/W)
θJA1
(°C/W) Temperature Range Package Description
Package
Option
OP270EZ 75 12 134 −40°C to +85°C 8-Lead CERDIP Q-8 (Z-Suffix)
OP270FZ 150 12 134 −40°C to +85°C 8-Lead CERDIP Q-8 (Z-Suffix)
OP270GP 250 37 96 −40°C to +85°C 8-Lead PDIP N-8 (P-Suffix)
OP270GPZ2
−40°C to +85°C 8-Lead PDIP N-8 (P-Suffix)
OP270GS 250 27 92 −40°C to +85°C 16-Lead SOIC_W RW-16 (S-Suffix)
OP270GS-REEL −40°C to +85°C 16-Lead SOIC_W RW-16 (S-Suffix)
OP270GSZ2
−40°C to +85°C 16-Lead SOIC_W RW-16 (S-Suffix)
OP270GSZ-REEL2
−40°C to +85°C 16-Lead SOIC_W RW-16 (S-Suffix)
1 θJA is specified for worst-case mounting conditions, that is, θJA is specified for device in socket for CERDIP and PDIP packages; θJA is specified for device soldered to
printed circuit board for SOIC package.
2 Z = RoHS Compliant Part.
©2001–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00325-0-2/10(E)