19-1309; Rev 0; 10/97 5-Tap Silicon Delay Line ____________________________Features Improved Second Source to DS1005 Available in Space-Saving 8-Pin MAX Package 17mA Supply Current vs. Dallas' 40mA Low Cost Delay Tolerance of 2ns or 3%, whichever is Greater TTL/CMOS-Compatible Logic Leading- and Trailing-Edge Accuracy Custom Delays Available ________________________Applications ______________Ordering Information Clock Synchronization Digital Systems PART MXD1005C/D__ _________________Pin Configurations TOP VIEW IN 1 8 VCC 7 TAP1 3 6 TAP3 GND 4 5 TAP5 TAP2 2 TEMP. RANGE PIN-PACKAGE 0C to +70C Dice* MXD1005PA__ MXD1005PD__ MXD1005SA__ -40C to +85C -40C to +85C -40C to +85C 8 Plastic DIP 14 Plastic DIP 8 SO MXD1005SE__ MXD1005UA__ -40C to +85C -40C to +85C 16 Narrow SO 8 MAX *Dice are tested at TA = +25C. Note: To complete the ordering information, fill in the blank with the part number extension from the Part Number and Delay Times table to indicate the desired delay per output. MXD1005 TAP4 DIP/SO/MAX _____Part Number and Delay Times PART NUMBER EXTENSION (MXD1005_ _ __) TAP1 TAP2 TAP3 TAP4 TAP5 60 DELAY (tPHLTAP4 , tPLH) PER OUTPUT (ns) IN 1 14 VCC 60 12 24 36 48 2 13 N.C. 75 15 30 45 60 75 12 TAP1 100 20 40 60 80 100 125 25 50 75 100 125 150 30 60 90 120 150 175 35 70 105 140 175 200 40 80 120 160 200 250 50 100 150 200 250 N.C. N.C. 3 TAP2 4 MXD1005 N.C. 5 11 N.C. 10 TAP3 TAP4 6 9 N.C. GND 7 8 TAP5 DIP Pin Configurations continued at end of data sheet. Note: Contact factory for characterization data. Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MXD1005 _______________General Description The MXD1005 silicon delay line offers five equally spaced taps with delays ranging from 12ns to 250ns and a nominal accuracy of 2ns or 3%, whichever is greater. Relative to hybrid solutions, this device offers enhanced performance and higher reliability, and reduces overall cost. Each tap can drive up to ten 74LS loads. The MXD1005 is available in multiple versions, each offering a different combination of delay times. It comes in the space-saving 8-pin MAX package, as well as an 8-pin SO or DIP, allowing full compatibility with the DS1005 and other delay line products. MXD1005 5-Tap Silicon Delay Line ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.5V to +6V All Other Pins..............................................-0.5V to (VCC + 0.5V) Short-Circuit Output Current (1sec) ....................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.1mW/C above +70C) ......727mW 14-Pin Plastic DIP (derate 10.0mW/C above +70C) ..800mW 8-Pin SO (derate 5.9mW/C above +70C)..................471mW 16-Pin Narrow SO (derate 8.7mW/C above +70C) ....696mW 8-Pin MAX (derate 4.1mW/C above +70C) .............330mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5.0V 5%, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) MIN TYP MAX UNITS Supply Voltage PARAMETER VCC (Note 2) 4.75 5.00 5.25 V Input Voltage High VIH (Note 2) 2.2 Input Voltage Low VIL (Note 2) IL 0V VIN VCC Input Leakage Current SYMBOL CONDITIONS V 0.8 -1 Active Current ICC VCC = 5.25V, period = minimum (Notes 3, 4) Output Current High IOH VCC = 4.75V, VOH = 4.0V Output Current Low IOL VCC = 4.75V, VOL = 0.5V Input Capacitance CIN TA = +25C (Note 5) 17 V 1 A 70 mA -1 mA 12 mA 5 10 pF TIMING CHARACTERISTICS (VCC = +5.0V 5%, TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS TYP MAX 40% of TAP5 tPLH UNITS Input Pulse Width tWI Input-to-Tap Delay (leading edge) tPLH (Notes 7-10) See Part Number and Delay Times table ns Input-to-Tap Delay (trailing edge) tPHL (Notes 7-10) See Part Number and Delay Times table ns Power-Up Time tPU Period Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: 2 (Note 6) MIN ns 100 (Note 6) 4(tWI) ms ns Specifications to -40C are guaranteed by design, not production tested. All voltages referenced to GND. Measured with outputs open. ICC is a function of frequency and TAP5 delay. Only an MXD1005_ _60 operating with a 40ns period and VCC = +5.25V will have a maximum ICC of 70mA. For example, an MXD1005_ _100 will not exceed 30mA. See Supply Current vs. Input Frequency graph in Typical Operating Characteristics. Guaranteed by design. Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling, etc.). VCC = +5V at +25C. Typical delays are accurate on both rising and falling edges within 2ns or 3%. See Test Conditions section. The combination of temperature variations from +25C to 0C or +25C to +70C and voltage variation from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional typical input-to-tap delay shift of 1.5ns or 4%, whichever is greater. All taps and outputs delays tend to vary unilaterally with temperature or supply variations. For example, if TAP1 slows down, all other taps will also slow down; TAP3 cannot be faster than TAP2. _______________________________________________________________________________________ 5-Tap Silicon Delay Line 50% DUTY CYCLE 16 15 14 13 12 MXD1005_ _75 1.5 tPLH 0.5 tPLH 0 tPHL -0.5 -1.0 -1.5 11 MXD1005_ _200 0.001 RELATIVE TO NOMINAL (+25C) -2.0 10 0.01 0.1 1 -40 10 -20 0 20 40 60 80 FREQUENCY (MHz) TEMPERATURE (C) MXD1005_ _100 TO MXD1005_ _200 PERCENT CHANGE IN DELAY vs. TEMPERATURE MXD1005_ _250 PERCENT CHANGE IN DELAY vs. TEMPERATURE 1.5 1.0 tPHL 0.5 tPHL 0 tPLH -0.5 tPLH -1.0 -1.5 2.0 1.5 % CHANGE IN DELAY (TAP2) MXD1005 TOC2 2.0 % CHANGE IN DELAY (TAP2) tPHL 1.0 1.0 0.5 tPLH tPHL 0 tPHL -0.5 tPLH -1.0 -1.5 RELATIVE TO NOMINAL (+25C) 100 MXD1005 TOC3 ACTIVE CURRENT (mA) 17 2.0 % CHANGE IN DELAY (TAP2) MXD1005 TOC4 18 MXD1005 TOC1 MXD1005_ _75 PERCENT CHANGE IN DELAY vs. TEMPERATURE ACTIVE CURRENT vs. FREQUENCY RELATIVE TO NOMINAL (+25C) -2.0 -2.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) _______________________________________________________________________________________ 3 MXD1005 __________________________________________Typical Operating Characteristics (VCC = +5V, TA = +25C, unless otherwise noted.) MXD1005 5-Tap Silicon Delay Line ______________________________________________________________Pin Description PIN NAME FUNCTION 8-PIN DIP/SO/MAX 14-PIN DIP 16-PIN SO 1 1 1 IN 2 4 4 TAP2 40% of specified maximum delay 3 6 6 TAP4 80% of specified maximum delay 4 7 8 GND Device Ground 5 8 9 TAP5 100% of maximum specified delay 6 10 11 TAP3 60% of specified maximum delay 7 12 13 TAP1 20% of specified maximum delay 8 14 16 VCC Power-Supply Input -- 2, 3, 5, 9, 11, 13 2, 3, 5, 7, 10, 12, 14, 15 N.C. No Connection. Not internally connected. Signal Input Note: Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information. _______________Definitions of Terms Period: The time elapsed between the first pulse's leading edge and the following pulse's leading edge. Pulse Width (t WI): The time elapsed on the pulse between the 1.5V level on the leading edge and the 1.5V level on the trailing edge, or vice-versa. Input Rise Time (tRISE): The time elapsed between the 20% and 80% points on the input pulse's leading edge. Input Fall Time (tFALL): The time elapsed between the 80% and 20% points on the input pulse's trailing edge. Time Delay, Rising (tPLH): The time elapsed between the 1.5V level on the input pulse's leading edge and the corresponding output pulse's leading edge. Time Delay, Falling (tPHL): The time elapsed between the 1.5V level on the input pulse's trailing edge and the corresponding output pulse's trailing edge. 4 ____________________Test Conditions Ambient Temperature: Supply Voltage (VCC): Input Pulse: +25C 3C +5V 0.01V High = 3.0V 0.1V Source Impedance: Low = 0.0V 0.1V 50 max Rise and Fall Times: Pulse Width: 3.0ns max 500ns max Period: 1s Each output is loaded with a 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edges. The time delay due to the 74F04 is subtracted from the measured delay. _______________________________________________________________________________________ 5-Tap Silicon Delay Line VIH IN VIL (+5V) 0.1F PERIOD TIME MEASUREMENT UNIT tFALL tRISE 2.4V 1.5V 2.4V 1.5V 1.5V 0.6V 0.6V MXD1005 VCC IN 20% TAP1 20% TAP2 20% TAP3 20% TAP4 20% TAP5 50 tWI MXD1005 tPHL tPLH 1.5V 1.5V OUT 74FO4 Figure 2. Test Circuit Figure 1. Timing Diagram __________Applications Information Supply and Temperature Effects on Delay Variations in supply voltage may affect the MXD1005's fixed tap delays. Supply voltages beyond the specified range may result with larger variations. The devices are internally compensated to reduce the effects of temperature variations. Although these devices might vary with supply and temperature, the delays vary unilaterally, which suggests that TAP3 can never be faster than TAP2. Capacitance and Loading Effects on Delay The output load can affect the tap delays. Larger capacitances tend to lengthen the rising and falling edges, thus increasing the tap delays. As the taps are loaded with other logic devices, the increased load will increase the tap delays. Board Layout Considerations/Decoupling The device should be driven with a source that can deliver the required current for proper operation. A 0.1F ceramic bypassing capacitor could be used. The board should be designed to reduce stray capacitance. _______________________________________________________________________________________ 5 MXD1005 5-Tap Silicon Delay Line _________________________________________________________Functional Diagram TAP1 20% IN TAP2 TAP3 20% 20% TAP4 20% TAP5 20% MXD1005 ____Pin Configurations (continued) ___________________Chip Information TRANSISTOR COUNT: 824 TOP VIEW IN 1 16 VCC N.C. 2 15 N.C. N.C. 3 14 N.C. TAP2 4 MXD1005 13 TAP1 N.C. 5 12 N.C. TAP4 6 11 TAP3 N.C. 7 10 N.C. GND 8 9 TAP5 SO 6 _______________________________________________________________________________________ 5-Tap Silicon Delay Line 8LUMAXD.EPS _______________________________________________________________________________________ 7 MXD1005 ________________________________________________________Package Information ___________________________________________Package Information (continued) SOICN.EPS MXD1005 5-Tap Silicon Delay Line Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.