T4-LDS-0305-3, Rev. 1 (7/30/13) ©2013 Microsemi Corporation Page 1 of 6
2N5415UA – 2N5416UA
Compliant
PNP Silicon Low-Power Transistor
Qualified per MIL-PRF-19500/485
Qualified Levels:
JAN, JANT X, JANTXV
and JANS
DESCRIPTION
This family of 2N5415UA and 2N5416UA epitaxial planar transistors are military qualified up to
a JANS level for high-re lia bility appl ic ations . The UA package is hermetically sealed and
provides a low profile for minimizing board height. These devices are also available in the
long-leaded TO-5, short-leaded TO-39 and low profile U4 packaging.
UA Package
Also available in:
TO-5 package
(long-leaded)
2N5415 – 2N5416
TO-39 (TO-205AD)
package
(short-leaded)
2N5415S – 2N5416S
U4 package
(surface mount)
2N5415U4 – 2N5416U4
Important: For the latest information, visit our website http://www.microsemi.com.
FEATURES
• JEDEC registered 2N5415 thr ough 2N 5416 series
• JAN, JANTX, JANTXV, and JANS qualifications are available per MIL-PRF-19500/485.
(See part nomenclature for all available options.)
• RoHS compliant
APPLICATIONS / BENEFITS
• General purpo se tr an si stors for low power applications requiring high frequency switching.
• Low package profile
• Military and other high-reliability applications
MAXIMUM RATINGS @ TA = +25 ºC unless otherwise noted
MSC – Lawrence
6 Lake Street,
Lawrence, MA 01841
Tel: 1-800-446-1158 or
(978) 620-2600
Fax: (978) 689-0803
MSC – Ireland
Gort Road Business Park,
Ennis, Co. Clare, Ireland
Tel: +353 (0) 65 6840044
Fax: +353 (0) 65 6822298
Website:
www.microsemi.com
Parameters / Test Conditions Symbol 2N5415UA 2N5416UA Unit
Collector-Emitter Voltage VCEO 200 300 V
Collector-Base Voltage VCBO 200 350 V
Emitter-Base Voltage VEBO 6.0 6.0 V
Collector Current
IC
1.0
1.0
A
Operating & Storage Jun cti on T emperature Range TJ, Tstg -65 to +200 °C
Thermal Resi stan ce Jun cti on-to-Ambient
R
ӨJA
234
oC/W
Thermal Resi stan ce Jun cti on-to-Solder Pad RӨJSP 80
o
C/W
Total Power Dissipation
@ TA = +2 5 °C (1)
@ TSP = +25 °C (2) PT 0.75
2 W
Notes: 1. Derate linearly 4.29 mW/°C for TA > +25°C
2. Derate linearly 12.5 mW/°C for TSP > +25 °C
T4-LDS-0305-3, Rev. 1 (7/30/13) ©2013 Microsemi Corporation Page 2 of 6
2N5415UA – 2N5416UA
MECHANICAL and PACKAGING
• CASE: Hermetically sealed ceramic package
• TERMINALS: Gold plate over nickel
• MARKING: Manufacturer's ID, date code, part number
• POLARITY: PNP (see package outline)
• TAPE & REEL option: Per EIA-481 (consult factory for quantities)
• WEIGHT: Approximately 0.12 grams
• See Package Dimensions on last page.
PART NOMENCLATURE
JAN 2N5415 UA
Reliability Level
JAN = JAN Level
JANTX = JANTX Level
JANTXV = JANTXV Level
JANS = JANS level
Blank = Commercial
Surface Mount pack ag e
JEDEC type number
(see Electrical Characteristics
table)
SYMBOLS & DEFINITIONS
Symbol
Definition
Cobo
Common-base open-circuit output capacitance
ICEO
Collector cutoff current, base open
ICEX
Collector cut of f curr ent, circuit bet ween bas e and emitter
IEBO
Emitter cutoff current, collector open
hFE
Common-emitter static forward current transfer ratio
VCEO
Collector-emitter voltage, base open
VCBO
Collector-emitter voltage, emitter open
VEBO
Emitter-base voltage, collector open
T4-LDS-0305-3, Rev. 1 (7/30/13) ©2013 Microsemi Corporation Page 3 of 6
2N5415UA – 2N5416UA
ELECTRICAL CHARACTERISTICS @ TA = +25 °C, unless otherwise noted
OFF CHARACTERISTICS
Parameters / Test Conditions
Symbol
Min.
Max.
Unit
Collector-Emitter Breakdown Voltage
V(BR)CEO
200
300
V
I
C
= 50 mA, I
B
= 5 mA,
L = 25 mH; f = 30 – 60 Hz
2N5415UA
2N5416UA
Emitter-Base Cutoff Current
VEB = 6.0 V
IEBO 20 µA
Collector-Emitter Cutoff Current
ICEX 50 µA
V
CE
= 200 V, V
BE
= 1.5 V
VCE = 300 V, VBE = 1.5 V
2N5415UA
2N5416UA
Collector-Emitter Cutoff Current
ICEO1 50 µA
V
CE
= 150 V
VCE = 250 V
2N5415UA
2N5416UA
Collector-Emitter Cutoff Current
ICEO2 1 mA
V
CE
= 200 V
VCE = 300 V
2N5415UA
2N5416UA
Collector-Base Cutoff Current
ICBO1 50 µA
V
CB
= 175 V
VCB = 280 V
2N5415UA
2N5416UA
V
CB
= 200 V
VCB = 350 V
2N5415UA
2N5416UA
ICBO2 500 µA
V
CB
= 175 V, T
A
= +150 ºC
VCB = 280 V, TA = +150 ºC
2N5415UA
2N5416UA
ICBO3 1 mA
ON CHARACTERISTICS
Parameters / Test Conditions Symbol Min. Max. Unit
Forward-Current Transfer Ratio
IC = 50 mA, VCE = 10 V
IC = 1 mA, VCE = 10 V
IC = 50 mA, VCE = 10 V, TA = +150 ºC
hFE
30
15
15
120
Collector-Emitter Saturation Voltage
I
C
= 50 mA, I
B
= 5 mA
VCE(sat) 2.0 V
Base-Emitter Voltage Non-Saturation
I
C
= 50 mA, V
CE
= 10 V
VBE 1.5 V
DYNAMIC CHA RACTERISTICS
Parameters / Test Conditions Symbol Min. Max. Unit
Magnitude of Common Emitter Small-Signal Short-
|hfe| 3 15
Circuit Forward Current Transfer Ratio
IC = 10 mA, VCE = 10 V, f = 5 MHz
Small-signal short Circuit Forward-Current
hfe
25
Transfer Ratio
IC = 5 mA, VCE = 10 V, f ≤ 1 kHz
Output Capac ita nc e
VCB = 10 V, IE = 0, 100 kHz ≤ f ≤ 1 MHz
Cobo 15 pF
T4-LDS-0305-3, Rev. 1 (7/30/13) ©2013 Microsemi Corporation Page 4 of 6
2N5415UA – 2N5416UA
ELECTRICAL CHARACTERISTICS @ TA = +25 °C unless otherwise noted. (continued)
SWITCHING CHARACTERISTICS
Parameters / Test Conditions Symbol Min. Max. Unit
Turn-On Time
VCC = 200 V, IC = 50 mA, IB1 = 5 mA
ton
1 µs
Turn-Off Time
VCC = 200 V, IC = 50 mA, IB1 = IB2 = 5 mA
toff
10 µs
SAFE OPERATING AREA
(See SOA graph below and MIL-STD-750, method 3053)
DC Tests
TC = +25 °C, tP = 0.4 s, 1 Cycle
Test 1
VCE = 10 V, IC = 0.3 A
Test 2
VCE = 100 V, IC = 30 mA
Test 3 (2N5415UA only)
VCE = 200 V, IC = 12 mA
Test 4 (2N5416UA only)
VCE = 300 V, IC = 5 mA
VCE – COLLECTOR – EMITTER VOLTAGE – V
Maximum Safe Operating Area (TJ = 200 ºC)
I
C
– COLLECTOR CURRE NT - A
T4-LDS-0305-3, Rev. 1 (7/30/13) ©2013 Microsemi Corporation Page 5 of 6
2N5415UA – 2N5416UA
GRAPHS
Time (s)
FIGURE 1
Thermal impedance graph (RӨJA)
Theta (oC/W)
T4-LDS-0305-3, Rev. 1 (7/30/13) ©2013 Microsemi Corporation Page 6 of 6
2N5415UA – 2N5416UA
PACKAGE DIMENSIONS
NOTES:
1. Dimensions are in inches.
2. Millimeters are given for information only.
3. Dimension "CH" controls the overall package thickness. W hen a
window lid is used, dimension "CH" must increase by a minimum
of 0.010 inch (0.254 mm) and a maximum of 0.040 inch (1.020
mm).
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing.
5. Dimensions " L W2" minimu m and "L3" minim um and the
appropriate castellation length define an unobstructed three-
dimensional space traversing all of the ceramic layers in which a
castellation was designed. (Castellations are required on bottom
two layers, optional on top ceramic layer.) Dimension " LW2"
maximum and "L3" maximum define the maximum width and
depth of the castellation at any point on its surface.
Measurement of these dimensions may be made prior to solder
dipping.
6. The co-planarity deviation of all terminal contact points, as
defined by the device seating plane, shall not exceed 0.006 i nch
(0.15mm) for solder dipped leadless chip carriers.
7. In accordance with ASME Y14.5M, diameters are equivalent to
Φx symbology.
Dimensions
Symbol
Inches
Millimeters
Note
Min
Max
Min
Max
BL
0.215
0.225
5.46
5.71
BL2
-
0.225
-
5.71
BW
0.145
0.155
3.68
3.93
BW2
-
0.155
-
3.93
CH
0.061
0.075
1.55
1.90
3
L3
0.003
0.007
0.08
0.18
5
LH
0.029
0.042
0.74
1.07
LL1
0.032
0.048
0.81
1.22
LL2
0.072
0.088
1.83
2.23
LS
0.045
0.055
1.14
1.39
LW
0.022
0.028
0.56
0.71
LW2
0.006
0.022
0.15
0.56
5
Pin no.
1
2
3
4
Transistor
Collector
Emitter
Base
N/C
