2N5415UA - 2N5416UA Qualified Levels: JAN, JANTX, JANTXV and JANS PNP Silicon Low-Power Transistor Compliant Qualified per MIL-PRF-19500/485 DESCRIPTION This family of 2N5415UA and 2N5416UA epitaxial planar transistors are military qualified up to a JANS level for high-reliability applications. The UA package is hermetically sealed and provides a low profile for minimizing board height. These devices are also available in the long-leaded TO-5, short-leaded TO-39 and low profile U4 packaging. Important: For the latest information, visit our website http://www.microsemi.com. FEATURES * JEDEC registered 2N5415 through 2N5416 series * JAN, JANTX, JANTXV, and JANS qualifications are available per MIL-PRF-19500/485. UA Package (See part nomenclature for all available options.) * RoHS compliant Also available in: TO-5 package (long-leaded) 2N5415 - 2N5416 APPLICATIONS / BENEFITS * * * General purpose transistors for low power applications requiring high frequency switching. Low package profile Military and other high-reliability applications TO-39 (TO-205AD) package (short-leaded) 2N5415S - 2N5416S U4 package (surface mount) 2N5415U4 - 2N5416U4 MAXIMUM RATINGS @ T A = +25 C unless otherwise noted Parameters / Test Conditions Symbol 2N5415UA 2N5416UA Unit Collector-Emitter Voltage V CEO 200 300 V Collector-Base Voltage V CBO 200 350 V Emitter-Base Voltage V EBO 6.0 6.0 V IC 1.0 1.0 A Collector Current Operating & Storage Junction Temperature Range T J , T stg -65 to +200 Thermal Resistance Junction-to-Ambient R JA 234 o C/W Thermal Resistance Junction-to-Solder Pad R JSP 80 o C/W PT 0.75 2 Total Power Dissipation (1) @ T A = +25 C (2) @ T SP = +25 C Notes: 1. Derate linearly 4.29 mW/C for TA > +25C 2. Derate linearly 12.5 mW/C for T SP > +25 C T4-LDS-0305-3, Rev. 1 (7/30/13) (c)2013 Microsemi Corporation C W MSC - Lawrence 6 Lake Street, Lawrence, MA 01841 Tel: 1-800-446-1158 or (978) 620-2600 Fax: (978) 689-0803 MSC - Ireland Gort Road Business Park, Ennis, Co. Clare, Ireland Tel: +353 (0) 65 6840044 Fax: +353 (0) 65 6822298 Website: www.microsemi.com Page 1 of 6 2N5415UA - 2N5416UA MECHANICAL and PACKAGING * * * * * * * CASE: Hermetically sealed ceramic package TERMINALS: Gold plate over nickel MARKING: Manufacturer's ID, date code, part number POLARITY: PNP (see package outline) TAPE & REEL option: Per EIA-481 (consult factory for quantities) WEIGHT: Approximately 0.12 grams See Package Dimensions on last page. PART NOMENCLATURE JAN 2N5415 UA Reliability Level JAN = JAN Level JANTX = JANTX Level JANTXV = JANTXV Level JANS = JANS level Blank = Commercial Symbol C obo I CEO I CEX I EBO h FE V CEO V CBO V EBO Surface Mount package JEDEC type number (see Electrical Characteristics table) SYMBOLS & DEFINITIONS Definition Common-base open-circuit output capacitance Collector cutoff current, base open Collector cutoff current, circuit between base and emitter Emitter cutoff current, collector open Common-emitter static forward current transfer ratio Collector-emitter voltage, base open Collector-emitter voltage, emitter open Emitter-base voltage, collector open T4-LDS-0305-3, Rev. 1 (7/30/13) (c)2013 Microsemi Corporation Page 2 of 6 2N5415UA - 2N5416UA ELECTRICAL CHARACTERISTICS @ T A = +25 C, unless otherwise noted OFF CHARACTERISTICS Parameters / Test Conditions Collector-Emitter Breakdown Voltage I C = 50 mA, I B = 5 mA, L = 25 mH; f = 30 - 60 Hz Emitter-Base Cutoff Current V EB = 6.0 V Collector-Emitter Cutoff Current V CE = 200 V, V BE = 1.5 V V CE = 300 V, V BE = 1.5 V Collector-Emitter Cutoff Current V CE = 150 V V CE = 250 V Collector-Emitter Cutoff Current V CE = 200 V V CE = 300 V Collector-Base Cutoff Current V CB = 175 V V CB = 280 V V CB = 200 V V CB = 350 V V CB = 175 V, T A = +150 C V CB = 280 V, T A = +150 C 2N5415UA 2N5416UA Symbol Min. V (BR)CEO 200 300 Max. Unit V I EBO 20 A 2N5415UA 2N5416UA I CEX 50 A 2N5415UA 2N5416UA I CEO1 50 A 2N5415UA 2N5416UA I CEO2 1 mA 2N5415UA 2N5416UA 2N5415UA 2N5416UA 2N5415UA 2N5416UA I CBO1 50 A I CBO2 500 A I CBO3 1 mA Min. Max. Unit 30 15 15 120 ON CHARACTERISTICS Parameters / Test Conditions Forward-Current Transfer Ratio I C = 50 mA, V CE = 10 V I C = 1 mA, V CE = 10 V I C = 50 mA, V CE = 10 V, T A = +150 C Collector-Emitter Saturation Voltage I C = 50 mA, I B = 5 mA Base-Emitter Voltage Non-Saturation I C = 50 mA, V CE = 10 V Symbol h FE V CE(sat) 2.0 V V BE 1.5 V Unit DYNAMIC CHARACTERISTICS Parameters / Test Conditions Magnitude of Common Emitter Small-Signal ShortCircuit Forward Current Transfer Ratio I C = 10 mA, V CE = 10 V, f = 5 MHz Small-signal short Circuit Forward-Current Transfer Ratio I C = 5 mA, V CE = 10 V, f 1 kHz Output Capacitance V CB = 10 V, I E = 0, 100 kHz f 1 MHz T4-LDS-0305-3, Rev. 1 (7/30/13) Symbol Min. Max. |h fe | 3 15 h fe 25 C obo (c)2013 Microsemi Corporation 15 pF Page 3 of 6 2N5415UA - 2N5416UA ELECTRICAL CHARACTERISTICS @ T A = +25 C unless otherwise noted. (continued) SWITCHING CHARACTERISTICS Parameters / Test Conditions Turn-On Time V CC = 200 V, I C = 50 mA, I B1 = 5 mA Turn-Off Time V CC = 200 V, I C = 50 mA, I B1 = I B2 = 5 mA Symbol Min. Max. Unit t on 1 s t off 10 s IC - COLLECTOR CURRENT - A SAFE OPERATING AREA (See SOA graph below and MIL-STD-750, method 3053) DC Tests T C = +25 C, t P = 0.4 s, 1 Cycle Test 1 V CE = 10 V, I C = 0.3 A Test 2 V CE = 100 V, I C = 30 mA Test 3 (2N5415UA only) V CE = 200 V, I C = 12 mA Test 4 (2N5416UA only) V CE = 300 V, I C = 5 mA V CE - COLLECTOR - EMITTER VOLTAGE - V Maximum Safe Operating Area (T J = 200 C) T4-LDS-0305-3, Rev. 1 (7/30/13) (c)2013 Microsemi Corporation Page 4 of 6 2N5415UA - 2N5416UA o Theta ( C/W) GRAPHS Time (s) FIGURE 1 Thermal impedance graph (R JA ) T4-LDS-0305-3, Rev. 1 (7/30/13) (c)2013 Microsemi Corporation Page 5 of 6 2N5415UA - 2N5416UA PACKAGE DIMENSIONS NOTES: 1. Dimensions are in inches. 2. Millimeters are given for information only. 3. Dimension "CH" controls the overall package thickness. When a window lid is used, dimension "CH" must increase by a minimum of 0.010 inch (0.254 mm) and a maximum of 0.040 inch (1.020 mm). 4. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 5. Dimensions " LW2" minimum and "L3" minimum and the appropriate castellation length define an unobstructed threedimensional space traversing all of the ceramic layers in which a castellation was designed. (Castellations are required on bottom two layers, optional on top ceramic layer.) Dimension " LW2" maximum and "L3" maximum define the maximum width and depth of the castellation at any point on its surface. Measurement of these dimensions may be made prior to solder dipping. 6. The co-planarity deviation of all terminal contact points, as defined by the device seating plane, shall not exceed 0.006 inch (0.15mm) for solder dipped leadless chip carriers. 7. In accordance with ASME Y14.5M, diameters are equivalent to x symbology. T4-LDS-0305-3, Rev. 1 (7/30/13) Symbol BL BL2 BW BW2 CH L3 LH LL1 LL2 LS LW LW2 (c)2013 Microsemi Corporation Dimensions Inches Millimeters Min Max Min Max 0.215 0.225 5.46 5.71 0.225 5.71 0.145 0.155 3.68 3.93 0.155 3.93 0.061 0.075 1.55 1.90 0.003 0.007 0.08 0.18 0.029 0.042 0.74 1.07 0.032 0.048 0.81 1.22 0.072 0.088 1.83 2.23 0.045 0.055 1.14 1.39 0.022 0.028 0.56 0.71 0.006 0.022 0.15 0.56 Pin no. Transistor 1 Collector 2 Emitter 3 Base Note 3 5 5 4 N/C Page 6 of 6