SEMICONDUCTOR TECHNICAL DATA High-Performance Silicon-Gate CMOS The MC74HC4024 is identical in pinout to the standard CMOS MC14024. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 7 master-slave flip-flops. The output of each flip-flop feeds the next and the frequency at each output is half that of the preceding one. The state of the counter advances on the negative going edge of the Clock input. Reset is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4024 for some designs. N SUFFIX PLASTIC PACKAGE CASE 646-06 14 1 1 ORDERING INFORMATION * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 206 FETs or 51.5 Equivalent Gates MC74HCXXXXN MC74HCXXXXD 11 9 CLOCK 1 6 5 4 3 RESET CLOCK 1 14 VCC RESET 2 13 NC Q7 3 12 Q1 Q6 4 11 Q2 Q5 5 10 NC Q1 Q4 6 9 Q3 Q2 GND 7 8 NC Q3 NC = NO CONNECTION Q4 Q5 Q6 FUNCTION TABLE Q7 2 Clock Reset Output State X L L H No Change Advance to Next State All Outputs are Low PIN 14 = VCC PIN 7 = GND PINS 8, 10 AND 13 = NO CONNECTION 10/95 Motorola, Inc. 1995 Plastic SOIC PIN ASSIGNMENT LOGIC DIAGRAM 12 D SUFFIX SOIC PACKAGE CASE 751A-03 14 1 REV 6 IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII v v IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIII IIII IIIIIIIIIIIIII IIIIII IIIIII IIIIIIIII IIIIIIIIIIIII IIIIIIIII IIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III v v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII v IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MC74HC4024 MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) - 1.5 to VCC + 1.5 Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air 750 500 mW Tstg Storage Temperature - 65 to + 150 _C Iin TL Plastic DIP SOIC Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 1000 500 400 ns DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C 85_C 125_C Unit VIH Minimum High-Level Input Voltage Vout = VCC - 0.1 V |Iout| 20 A 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 VOH Vin = VIH or VIL |Iout| |Iout| VOL Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| |Iout| Iin ICC 4.0 mA 5.2 mA 4.0 mA 5.2 mA V Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 A 6.0 8 80 160 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). MOTOROLA 2 High-Speed CMOS Logic Data DL129 -- Rev 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII v IIII v III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MC74HC4024 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC V - 55 to 25_C 85_C 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 4.5 6.0 5.4 27 32 4.4 22 26 3.6 18 21 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q1* (Figures 1 and 4) 2.0 4.5 6.0 210 42 36 265 53 45 315 63 54 ns tPHL Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4) 2.0 4.5 6.0 210 42 36 265 53 45 315 63 54 ns tPLH, tPHL Maximum Propagation Delay, QN to QN + 1 (Figures 3 and 4) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance -- 10 10 10 pF Symbol Cin Parameter NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * For TA = 25_C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: VCC = 2.0 V: tP = [205 + 100(N - 1)] ns VCC = 4.5 V: tP = [41 + 20(N - 1)] ns VCC = 6.0 V: tP = [35 + 17(N - 1)] ns Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* pF 30 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III v IIII v III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit VCC V - 55 to 25_C Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 tw Minimum Pulse Width, Clock (Figure 1) tw 85_C 125_C 100 20 17 125 25 21 150 30 26 ns 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns Symbol trec tr, tf Parameter Unit NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 3 MOTOROLA MC74HC4024 PIN DESCRIPTIONS INPUTS input resets the counter to its zero state, thus forcing all Q outputs low. Clock (Pin 1) Negative edge triggering clock input. A High to low transition of this input advances the state of the counter. OUTPUTS Reset (Pin 2) Active-high outputs. Each QN output divides the Clock input frequency by 2N. Q1 - Q7 (Pins 12, 11, 9, 6, 5, 4, 3) Active high asynchronous reset. A high level applied to this SWITCHING WAVEFORMS tw tf 90% 50% 10% CLOCK tr RESET VCC GND tPHL GND tw Q1 50% Q 1/fmax tPLH VCC 50% tPHL trec VCC 90% 50% 10% 50% CLOCK tTLH GND tTHL Figure 1. Figure 2. TEST POINT OUTPUT DEVICE UNDER TEST VCC QN 50% GND tPHL tPLH QN + 1 50% * Includes all probe and jig capacitance Figure 4. Test Circuit Figure 3. MOTOROLA CL* 4 High-Speed CMOS Logic Data DL129 -- Rev 6 MC74HC4024 TIMING DIAGRAM 1 2 3 4 8 16 32 64 128 CLOCK RESET Q1 Q2 Q3 Q4 Q6 Q7 EXPANDED LOGIC DIAGRAM Q1 12 1 Q2 11 Q3 9 Q4 6 Q5 5 Q6 4 Q7 3 C Q C Q C Q C Q C Q C Q C C Q C Q C Q C Q C Q C Q C Q CLOCK R R R R R R R 2 RESET High-Speed CMOS Logic Data DL129 -- Rev 6 5 MOTOROLA MC74HC4024 OUTLINE DIMENSIONS 14 8 1 7 N SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L C J N H G D SEATING PLANE K M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 1 P 7 PL 0.25 (0.010) 7 G D 0.25 (0.010) M T F J M K 14 PL B S M R X 45 C SEATING PLANE B M A S MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 -B- INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 6 *MC74HC4024/D* MC74HC4024/D High-Speed CMOS Logic Data DL129 -- Rev 6