W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 1 - Revision 1.0
W83601R/W83601G/
W83602R/W83602G
Winbond GPI/O IC
W83601R/G/W83602R/G
- 2 -
Table of Contents-
1. GENERAL DESCRIPTION......................................................................................................... 3
2. FEATURES................................................................................................................................. 3
3. PACKAGE................................................................................................................................... 3
5. PIN CONFIGURATION F OR W 83601R/602R............................................................................ 4
6.1 W83602R/G Universal General Purp ose I/O Port for I2C BUS & ACPI Power Control.6
7. REGISTERS ...............................................................................................................................7
7.1 Brief of register contents................................................................................................. 7
7.2 W83601R/G/W83 602R/G Regi ste rs Descriptio ns.......................................................... 8
8. FUNCTION DESCRIPTIONS.................................................................................................... 12
8.1 ACCESS INTERFACE.................................................................................................. 12
8.1.1 Write a data into W83601R/G/W83602R/G register.......................................................12
8.1.2 Read a data from W83601R/G/W83602R/G register......................................................12
8.2 CTLSTRV Timing Waveforms (Only for W83602R/G) ................................................. 13
8.3 CTL3VSB Timing Waveforms (Only for W83602R/G).................................................. 13
8.4 GPI/O Output Mode :.................................................................................................... 14
8.4.1 GPO output ....................................................................................................................14
8.4.2 INT output.......................................................................................................................14
8.4.3 GPI interrupt status.........................................................................................................14
9. DC AND AC SPECIFICATION.................................................................................................. 15
9.1 Absolute Maximum Ratings.......................................................................................... 15
9.2 DC Characteristics........................................................................................................ 15
9.3 AC Characteristics........................................................................................................ 16
9.3.1 Serial Bus Timing Diagram.............................................................................................16
10. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 17
11. REVISION HISTORY................................................................................................................ 21
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 3 - Revision 1.0
1. GENERAL DESCRIPTION
W83601R/G/W83602R/G are general purpose input/output ICs with SMBusTM( I2C ). W83601R/G
provides 15 GPI/O pins. W83602R/G provides 10 GPI/O pins and ACPI power control function for STR.
W83601R/G/W83602R/G both provides SMBusTM (I2C) address setting pins to set the address during
power- on reset or from external reset.
W83601R/G SMBusTM Address is: 0 0 1 1 A2 A1 A0 R/W
W83602R/G SMBusTM Address is: 0 0 1 1 0 A1 A0 R/W
W83601R/G/W83 602R/G also p rovides a interrupt to inform system that a trans ition occurs on Gene ral
Purpose (GP) input pins.
2. FEATURES
y SMBus compliance with 3.3V voltage levels
y Two ports GPI/O which provides more flexibility
y Issue interrup ts to notify system that an event occurs
y GP output can be level or pulse mode
y Interrupt output can be level or pulse mode
y Internal power-on reset or external RST# pin reset
y Programmable POWER LED output
y ACPI power management for Suspend to Ram (STR) (only for W83602R/G )
3. PACKAGE
y 20-pin SSOP
4. 4. KEY SPECIFICATIONS
y Supply Voltage 5V
y Operating Supply Current 1 mA typ.
y Operating Temperature 0 - 70 °C
W83601R/G/W83602R/G
- 4 -
5. PIN CONFIGURATION FOR W83601R/602R
1
2
3
4
5
6
7
8
9
10
20
18
17
16
15
14
13
12
11
19
W83601R
SCLK
SDAT
GP20/A0
GP21/A1
GP22/A2
GP10
GP11
GP23
GP24
VSS
VDD
RST#
GP17/INT
GP16
GP15
GP14
GP13
GP12
GP26/INT
GP25
1
2
3
4
5
6
7
8
9
10
20
18
17
16
15
14
13
12
11
19
W83602R
SCLK
SDAT
GP20/A0
GP21/A1
CTL3VSB
GP10
GP11
CTLSTRV
S5IN#
VSS
VDD
RST#
GP17/INT
GP16
GP15
GP14
GP13
GP12
PWCTLIN#
PS_ON#
20SSOP 20SSOP
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 5 - Revision 1.0
6. PIN DESCRIPTION
I/OD24t - TTL level bi-directiona l pin open drain output with 24 mA sink capability
I/OD12ts - TTL level bi-directional pin open drain output with 12 mA sink capability and schmitt-trigger level input
I/O21 - CMOS level bi-directional pin with 21 mA source-sink capability
INt - TTL level input pin
INcd - CMOS level input pin with internal pull down resistor
INts - TTL level Schmitt-trigger input pin
OD24 - Open drain output pin with 24 mA sink capability
W83601R/G Universal General Purpose I/O Port for I2C BUS
PIN SYMBOL I/O FUNCTION
1 SCL INts SMBus Clock. (I2C clock)
2 SDA I/OD12ts SMBus bi-directional Data.(I2C data)
3 GP20
A0 I/O21
INcd General Purpose I/O. This pin is a setting pin for SMBus (I2C)
address bit 0 during power-on reset or RST# pin reset.
4 GP21
A1 I/O21
INcd General Purpose I/O. This pin is a setting pin for SMBus (I2C)
address bit 1 during power-on reset or RST# pin reset.
5 GP22
A2 I/O21
INcd General Purpose I/O. This pin is a setti ng pin for SMBus (I2C)
address bit 2 during power-on reset or RST# pin reset.
6 GP10 I/OD24t General Purpose I/O default input.
7 GP11 I/OD24t General Purpose I/O default input.
8 GP23 I/OD24t General Purpose I/O default input.
9 GP24 I/OD24t General Purpose I/O default input.
10 VSS PWR Ground Pin.
11 GP25 I/OD24t General Purpose I/O defau lt input.
12 GP26
INT I/OD24t
OD24
General Purpose I/O default input.
Auto-generate Interrupt sig nal when detecting a transition on GPI
inputs. This interrupt is either on pin1 2 or pin18.
13 GP12 I/OD24t General Purpose I/O defau lt input.
14 GP13 I/OD24t General Purpose I/O defau lt input.
15 GP14 I/OD24t General Purpose I/O defau lt input.
16 GP15 I/OD24t General Purpose I/O defau lt input.
17 GP16 I/OD24t General Purpose I/O defau lt input.
18 GP17
INT I/OD24t
OD24
General Purpose I/O default input.
Auto-generate Interrupt sig nal when detecting a transition on GPI
inputs. This interrupt is either on pin1 2 or pin18
19 RST# Ints Reset signal input.
20 VDD PWR Power Pin.
W83601R/G/W83602R/G
- 6 -
6.1 W83602R/G Universal General Purpose I/O Port for I2C BUS & ACPI Power
Control
PIN SYMBOL I/O FUNCTION
1 SCL INts SMBus Clock. (I2C clock)
2 SDA I/OD12ts SMBus bi-directional Data.(I2C data)
3 GP20
A0 I/O21
INcd General Purpose I/O. This pin is a setting pin for SMBus (I2C)
address bit 0 during power-on reset or RST# pin reset.
4 GP21
A1 I/O21
INcd General Purpose I/O. This pin is a setting pin for SMBus (I2C)
address bit 1 during power-on reset or RST# pin reset.
5 CTL3VSB OD24 Control 3VSB and 3VCC power source for ACPI features.
6 GP10 I/OD24t General Purpose I/O default input.
7 GP11 I/OD24t General Purpose I/O default input.
8 CTLSTR OD24 Suspend to RAM power control output.
9 S5IN# INt S5# signal input.
10 VSS PWR Ground Pin.
11 PS_ON# OD24 ATX power on_off control.
12 PWCTLIN# INt Connected to W83627F/ H F power control output.
13 GP12 I/OD24t General Pu rpose I/O default input.
14 GP13 I/OD24t General Pu rpose I/O default input.
15 GP14 I/OD24t General Pu rpose I/O default input.
16 GP15 I/OD24t General Pu rpose I/O default input.
17 GP16 I/OD24t General Pu rpose I/O default input.
18 GP17
INT I/OD24t
OD24 General Purpose I/O default input.
Auto-generate Interrupt sig nal when detecting a transition on GPI
inputs.
19 RST# INts Reset signal input.
20 VDD PWR Power Pin.
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 7 - Revision 1.0
7. REGISTERS
7.1 Brief of register conte nts
INDEX R/W DEFAULT REGISTERS DESCRIPTION
00h R - GP Port 1: Input Port Data Register
01h R/W 00 GP Port 1: Output Port Data Register
02h R/W f0 GP Port 1: Polarity Inversion Register
03h R/W ff GP Port 1: Input/Output Configuration Register
04h R/W 00 GP Port 1: Output style control Register.
05h R - GP Port 1: Input Latched Data Register.
06-07h - - Reserved Register
08h R - GP Port 2: Input Port Register
09h R/W 00 GP Port 2: Output Port Register
0Ah R/W 70 GP Port 2: Polarity Inversion Register
0Bh R/W 7f GP Port 2: Input/Output Configuration Register
0Ch R/W 00 GP Port 2: Output style control Register.
0Dh R - GP Port 2: Input Latched Data Register.
0E-0F
h - - Reserved Register
10h R 00 GP Port 1: Interrupt Status Register.
11h R 00 GP Port 2: Interrupt Status Register
12h R/W 00 GP Port 1: Interrupt Enable Register
13h R/W 00 GP Port 2: Interrupt Enable Register
14h R/W 00 Mode Configuration Register
15h R/W 00 Power LED Configuration Register
16-1F
h - - Reserved Register
20h R 60 Chip ID High Byte Register
21h R 12
22 Chip ID Low Byte Register (W83601R/G)
Chip ID Low Byte Register (W83602R/G)
W83601R/G/W83602R/G
- 8 -
7.2 W83601R/G/W83602R/G Registers Descriptions
CR00 (GP Port 1: Input port Data Regi ster, Default 0x--, Read Only)
This register is a data port for input only. It reflects the incoming logic levels of the pins whether the pin is
defined as an input mode by CR03. It will be inverted data by CR02.
Bit 7 ~ 0: GP17 ~ GP10 Input Data Port.
CR01 (GP Port 1: Output port Data Register, Default 0x00, Read/Write)
This register is a d ata port for output only. It reflec ts the outgoing logic level s of the pins whether the pin
is defined as an output mode by CR03. This register will reflect the value of output Flip-flop while read
access. The output data will be inverted or changed output style by CR02 or CR04.
Bit 7 ~ 0: GP17 ~ GP10 Output Data Port.
CR02 (GP Port 1: Polarity Inversion Register, Default 0xf0, Read / Write)
This register enables p ola rity inversion of pins defined as input or output by CR03.
When set to a "1", the incoming/outgoing port value is inverted.
When set to a "0", the incoming/outgoing port value is the same as in data register.
Bit 7 ~ 0: GP17 ~ GP10 Polarity Iversion Register.
CR03 (GP Port 1: Input/Output Configuration Register, Default 0xff, Read / Write)
This register selects Input or Outp ut mode of pins.
When set to a "1", respective GPIO port is programmed as an input port.
When set to a "0", respective GPIO port is programmed as an output port.
Bit 7 ~ 0: GP17 ~ GP10 Input/Output Configuration Register.
CR04 (GP Port 1: Output Style Contr ol Register, Default 0x00, Read / Write)
This register selects Outpu t style of pins as level or pulse.
When set to a "1", respective GPIO port is progra mmed as a pulse signal.
When set to a "0", respective GPIO port is progra mmed as a level signal.
Bit 7 ~ 0: GP17 ~ GP10 Output Style Control Register.
CR05 (GP Port 1: Input latched da ta Register, Default 0x--, Re ad Only)
This register will latch Port 1 data while power on or RST# pin low, which is controlled by CR14h bit 0.
Bit 7 ~ 0: GP17 ~ GP10 Input latched data.
CR06-07 Reserved Register
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 9 - Revision 1.0
CR08 (GP Port 2: Input port Data Regi ster, Default 0x--, Read Only)
This register is a data port for input only. It reflects the incoming logic levels of the pins whether the pin is
defined as an input mode by CR0B. It will be inverted data by CR0 A .
Bit 7: Reserved.
Bit 6 ~ 0: GP26 ~ GP20 Input Data Port.
CR09 (GP Port 2: Output port Data Register, Default 0x00, Read / Write)
This register is a d ata port for output only. It reflec ts the outgoing logic level s of the pins whether the pin
is defined as an output mode by CR0B. This register will reflect the value of output Flip-flop while read
access. The output data will be inverted or changed output style by CR0A or CR0C.
Bit 7: Reserved.
Bit 7 ~ 0: GP26 ~ GP20 Output Data Port.
CR0A (GP Port 2: Polarity Inversion Register, Default 0x70, Read / Write )
This register enables p ola rity inversion of pins defined as input or output by CR0B.
When set to a "1", the incoming/outgoing port value is inverted.
When set to a "0", the incoming/outgoing port value is the same as in data register.
Bit 7: Reserved.
Bit 6 ~ 0: GP26 ~ GP20 Polarity Inversion Register.
CR0B (GP Port 2: Input/Output Configuration Register, Default 0x7f, Read / Write)
This register selects Input or Outp ut mode of pins.
When set to a "1", respective GPIO port is programmed as an input port.
When set to a "0", respective GPIO port is programmed as an output port.
Bit 7: Reserved.
Bit 6 ~ 0: GP26 ~ GP20 Input/Output Configuration Register.
CR0C (GP Port 2: Output Styl e Control Register, Default 0x00, Read / Write)
This register selects Outpu t style of pins as level or pulse.
When set to a "1", respective GPIO port is progra mmed as a pulse signal.
When set to a "0", respective GPIO port is progra mmed as a level signal.
Bit 7: Reserved.
Bit 6 ~ 0: GP26 ~ GP20 Output Style Control Register.
CR0D (GP Port 2: Input latched data Register, Default 0 x- -, Read Only)
This register will latch Port 2 data while power on or RST# pin low, which is controlled by CR14h bit 1.
Bit 7: Reserved.
Bit 6 ~ 0: GP26 ~ GP20 Input latched data, which bit 2-0 are SMBus ad dress bit A2-A0.
CR0E-0F Reserved Register
W83601R/G/W83602R/G
- 10 -
CR10 (GP Port1: Interrupt Status Register, Default 0x00, Read Only)
Bit 7-0: = 1, a transition occurs at pin GP17-GP 10.
If GP17/INT is selected as interrupt function, bit 7 of this register will always be 0.
A read to this register will clear this register.
CR11 (GP Port2: Interrupt Status Register, Default 0x00, Read Only)
Bit 7: = Reserved.
Bit 6-0: = 1, a transition occurs at pin GP26-GP 20.
If GP26/INT is selected as interrupt function, bit 6 of this register will always be 0.
A read to this register will clear this register.
CR12 (GP Port 1: Interrupt Enable Register, Default 0x00, Read / Write)
Bit 7-0: = 0, disable GP17-GP10 interrupt output when interrupt function is selected.
CR13 (GP Port 2: Interrupt Enable Register, Default 0x00, Read / Write)
Bit 7-5: = Reserved.
Bit 6-0: = 0, disable GP26-GP20 interrupt output when interrupt function is selected.
CR14 Mode Configuration Register (Default 0x00, Read / Write)
Bit 7: = 1, Set GP/INT pin as INT function. 0, Set GP/INT pin as GP function.
Bit 6: = 1, Set INT function at GP26 (pin 12). 0, Set INT function at GP17 (pin 1 8).
W83602R/G INT function is only at GP17.
Bit 5: = 1, Set INT output pin as pulse mode. 0, set INT output pin as level mod e.
Bit 4: = 1, Set INT output pin polarity is 1 (normal high) . 0, set INT output pin polarity is 0 (normal low).
This bit is only for W83601R.
Bit 3: = 1, Port 2 (CR09h-CR0Ch, CR11h, CR13h) re gisters ca n be reset to def ault data by RST# pin. 0
Port 2 (CR09h-CR0Ch) can not be reset by RST# pin.
Bit 2: = 1, Port 1 (CR01h-CR04h, CR10h, CR1 2h) regist ers can be reset to defaul t data by RST# pin. 0,
Port 1 (CR01h-CR04h) can not be reset by RST# pin.
Bit 1: = 1, Port 2 CR0Dh can be latched not only by RST# pin but also power-on period. 0, Port 2
CR0Dh can only be latched by power-on period.
Bit 0: = 1, Port 1 CR05h can be latched not only by RST# pin but also power-on period. 0, Port 1
CR05h can only be latched by power-on period.
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 11 - Revision 1.0
CR15 Power LED Configuration Register (Default 0 x00, Read/Write)
Priority of LED function is highest.
Bit 7: = 1, Enable LED function. 0, Disable LED funciton.
When LED function is enabled, GP function is ignore d despite of input or output.
Bit 6-4: LED frequency selection.
= 111, LED pin is tri-state (OD pin) or drived high (O pin).
= 110, LED pin is a 1 Hz toggle pulse with 50 duty cycle.
= 101, LED pin is a 1/2 Hz toggle pulse with 50 duty cycle.
= 100, LED pin is a 1/4 Hz toggle pulse with 50 duty cycle.
= 000, LED pin is drived low.
Bit 3: GP port selection.
0, Select GP port 1 as LED function if bit 7 is set to 1.
1, Select GP port 2 as LED function if bit 7 is set to 1.
As W83602R/G, setting this bit 1 is meaningless.
Bit 2-0: GP pin selection.
=110-000, GP16-GP10 can be selected as LED output when bit 3 is 0.
=101-011, GP25-GP23 can be selected as LED output when bit 3 is 1.
As W83602R/G, only GP16-GP10 can be sel ecte d as LED output.
CR16-1F Reserved Register
CR20 (Chip ID High Byte, Read Only)
Bit 7-0: = 0x60.
CR21 (Chip ID Low Byte, Read Only)
Bit 7-0: = 0x13 (for W83601R/G).
= 0x23 (for W83602R/G).
NOTE: W83602R/G has no GP22-GP26. All the corresponding register has no effect on
W83602R/G.
W83601R/G/W83602R/G
- 12 -
8. FUNCTION DESCRIPTIONS
8.1 ACCESS INTERFACE
W83601R/G/W83602R/G provides a two-wired serial interface which is compliant with SMBusTM 1.0
Write Byte and Read Byte protocol.
8.1.1 Write a data into W83601R/G/W83602R/G register
0
Start By
Master
0101A2A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Ack
by
601R
R/W
Ack
by
601R
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
Ack
by
601R
Stop
by
Master
SCL
SDA (Continued)
780 78
0
78
Frame 2
Internal Index Register Byte
(Continued)
Frame 3
Data Byte
Frame 1
Serial Bus Address Byte
8.1.2 Read a data from W83601R/G/W83602R/G register
0
Repea
Start
By
Master
D7 D5 D4
Ack
by
601R
SCL (Cont..)
SDA (Cont..)
780
Frame 4
MSB Data Byte
Frame 3
Serial Bus Address Byte
D2 D1 D0
7
Stop by
Master
No Ack
by
Master
0
Start By
Master
0011A2A1 A0 R/W
Ack
by
601R
SCL
SDA
780
Frame 1
Serial Bus Address Byte
4
Ack
by
601R
Frame 2
Pointer Byte
0 0 1 1 A2 A1 A0 R/W
...
...
D6 D3
8
78
D7 D5 D4 D2 D1 D0
D6 D3
0
1
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 13 - Revision 1.0
8.2 CTLSTRV Timing Waveforms (Only for W83602R/G)
8.3 CTL3VSB Timing Waveforms (O nly for W83602R/G)
5VSB
PWRCTL#
PS_ON#
CTL3VSB
First AC On
~ S5 state ~
Power On
~ S0 state ~
t1= 5+1ms
Suspend to RAM Resume from S3
~ S0 state ~
T2=500+125MS
Soft OFF
~ S5 state ~
3VSB_Voltage 3VCC 3VSB 3VCC
T2=500+125MS
t1= 5+1ms
3VSB 3VSB
~ S3 STATE ~
5VSB
S5IN#
PWRCTL# POWER
*NOTE1
PS_ON#
FIRST AC ON PO
~ S5 STATE ~
CTLSTRV
WER ON
~ S0 STATE ~
T1= 5+1MS
STR *NOTE2
SUSPEND
to RAM
RESUME
from S3
T2=500+125MS
SOFT OFF
~ S5 STATE ~
DRAM_VOLTAG 3VCC 3VSB 3VCC
*
NOTE 1: IT CAN WAKE
UP POWER FROM POWER
BUTTON, KEYBOARD/MO
USE,
*NOTE 2: IT CAN SUSPEND TO RAM BY OS OR SPECIAL DEFINED
~ S0 STATE ~
~~
S3 STATE
T1
=
5
+
1MS
W83601R/G/W83602R/G
- 14 -
8.4 GPI/O Output Mode :
8.4.1 GPO output
Tow output modes for GPO. One is LEVEL and the other is PULSE.
GPO OUTPUT
STYLE POLARITY OUTPUT PORT
REGISTER OUTPUT VALUE
AT PIN WAVE
0 0 0
1 1
Level 1 0 1
1 0
Pulse 0 write 1 Active
1 write 1 Active
8.4.2 INT output
Two output modes for INT pin. One is LEVEL mode and the other is PULSE.
INT OUTPUT
MODE POLARITY OUTPUT WAVE
Level 0(normal low) 1
1(normal high) 0
Pulse 0(normal low) High Pulse
1(normal high) Low Pulse
In Level mode, if INT is activated, it will be de-activated when interrupt status registers are read.
In Pulse mode, interrupt will be activated again unless all enabled interrupt status registers are rea d.
8.4.3 GPI interrupt status
Once a transition occurs at GPI input pins, interrupt status registers (CR10, CR11) will be set. At the
mean time, if interrupt function is enable, INT pin will generate an interrupt. Reading these interrupt
registers will clear themselves and reset interrupt. If an interrupt occurs but no read to interrupt status
registers, interrupt will not be generated again.
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 15 - Revision 1.0
9. DC AND AC SPECIFICATION
9.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage -0.5 to 7.0 V
Input Voltage -0.5 to VDD+0.5 V
Operating Temperature 0 to +70 ° C
Storage Temperature -55 to +150 ° C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
9.2 DC Characteristics
(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/OD12ts - TTL level bi-directional pin open drain with source-sink capability of 12 mA and
schmitt-trigger level input
Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V
Input High Threshol d Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V
Hysteresis VTH 0.5 1.2 V VDD = 5 V
Output Low Voltage VOL 0.4 V IOL = 12 mA
Input High Leakage ILIH +10
μA VIN = VDD
Input Low Leakage ILIL -10
μA VIN = 0V
INt - TTL level input pin
Input Low Voltage VIL 0.8 V
Input High Voltage VIH 2.0 V
Input High Leakage ILIH +10
μA VIN = VDD
Input Low Leakage ILIL -10
μA VIN = 0 V
INts - TTL level Schmitt-triggered input pin
Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V
Input High Threshol d Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V
Hysteresis VTH 0.5 1.2 V VDD = 5 V
Input High Leakage ILIH +10
μA VIN = VDD
Input Low Leakage ILIL -10
μA VIN = 0 V
W83601R/G/W83602R/G
- 16 -
DC Characteristics, continued
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
INcd - CMOS level input pin with internal pull down
Input Low Voltage VIL 0.3 VDD V VDD = 5 V
Input High Voltage VIH 0.7VDD V VDD = 5 V
Input High Leakage ILIH +10
μA VIN = VDD
Input Low Leakage ILIL -10
μA VIN = 0 V
I/O21 - CMOS level bi-direction pin with 21mA source-sink capability
Input Low Voltage VIL 0.3 VDD V VDD = 5 V
Input High Voltage VIH 0.7VDD V VDD = 5 V
Output Low Voltage VOL 0.4 V IOL = 21 mA
Output High Voltage VOH 3.5 V IOH = 21 mA
Input High Leakage ILIH +10
μA VIN = VDD
Input Low Leakage ILIL -10
μA VIN = 0 V
I/OD24t - TTL level bi-direction pin open-drain output with 24mA sink capability
Input Low Voltage VIL 0.8 V
Input High Voltage VIH 2.0 V
Output Low Voltage VOL 0.4 V IOL = 24 mA
Input High Leakage ILIH +10
μA VIN = 5 V
Input Low Leakage ILIL -10
μA VIN = 0 V
OD24 - open-drain output pin with 24mA sink capability
Input Low Voltage VIL 0.4 V IOL = 24 mA
9.3 AC Characteristics
9.3.1 Serial Bus Timing Diagram
VALID DATA
SCL
SDA IN
SDA OUT
tHD;STA
tSCL
tSU;DAT tSU;STO
tHD;DAT
Serial Bus Timing Diagram
tR
tF
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 17 - Revision 1.0
Serial Bus Timing
PARAMETER SYMBOL MIN. MAX. UNIT
SCL clock period t-SCL 10 uS
Start condition hold time tHD;STA 4.7 uS
Stop condition setup-up time tSU;STO 4.7 uS
DATA to SCL setup time tSU;DAT 120 nS
DATA to SCL hold time tHD;DAT 5 nS
SCL and SDA rise time tR 1.0 uS
SCL and SDA fall time tF 300 nS
10. PACKAGE DRAWING AND DIMENSIONS
20 SSOP-209 mil
1
2
D
E
e
YbA1
A2 A
SEATING PLANE
DTEAIL A
L
L1
θ
DETAIL A
SEATING PLANE
E
H
10
11
0
0.002
0.197
0.291
7.80
0
7.40
8
8.20
5.30
b
E
D
c6.90
5.00
A1
A2
A
5.60
7.50
7.20
2.00
1.85
8
0.3230.307
0.073
0.079
0.220
0.272 0.2950.283
0.209
MIN.
DIMENSION IN INCH
SYMBOL DIMENSION IN MM
MIN. NOM MAX. MAX.NOM
0.05
e
L
L1
Y
θ
0.009 0.015
0.004 0.010
0.021 0.030
0.050
0.004
0.22 0.38
0.09 0.25
0.65 0.0256
0.55 0.75
1.25
0.10
HE
0.95 0.037
1.75
1.65 0.065 0.069
W83601R/G/W83602R/G
- 20 -
11. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
n.a. All the version before 0.30 are for internal use.
0.3 99/08 n.a. First publication.
0.31 99/08 P.4,5
P.6
P.10
P.13
Change Pin Description of W83601R pin
3,4,5.
Change Pin Description of W83602R pin 3,4.
Update Register Table.
CR16 is a reserved register. Please ignore it.
Change INT output description.
0.32 99/09 P.10 CR15 bit 3 description.
0.33 01/02 P.11 Insert 8.1 section – Access interface
0.34 01/02 P.10 Update CR21 Chip ID.
0.35 01/03 P.4
Update pin characteristic.
Update application schematic to version 0.3.
0.4 01/06 P.15 Add chapter 9 DC and AC specification.
0.5 01/08 P.15 Update chapter 9.2 DC specification
0.6 05/04 n.a. Add Pb-free package
1.0 May 26, 2005 20 ADD Important Notice
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
W83601R/G/W83602R/G
Publication Release Date: May 26, 2005
- 21 - Revision 1.0