Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
1
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8305I is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8305I has selectable clock inputs that accept
either differential or single ended input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A sepa-
rate output enable pin controls whether the outputs are in the
active or high impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
HiPerClockS™
ICS
BLOCK DIAGRAM PIN ASSIGNMENT
GND
OE
VDD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
GND
ICS8305I
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
FEATURES
• 4 LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
•Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
LVCMOS_CLK
CLK
nCLK
CLK_SEL
Q0
Q1
Q2
Q3
0
1
CLK_EN
OE
D
Q
LE
0
1
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
2
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaM stinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
C
DP
ecnaticapaCnoitapissiDrewoP
)tuptuorep( 11Fp
R
TUO
ecnadepmItuptuO 57 21Ω
rebmuNemaNepyTnoitpircseD
31,9,1DNGrewoP.dnuorgylppusrewoP
2EOtupnIpulluP .etatsecnadepmiHGIHnierastuptuo,WOLnehW
.elbanetuptuO
.slevelecafretniLTTVL/SOMCVL.evitcaerastuptuo,HGIHnehW
3V
DD
rewoP.nipylppuseroC
4NE_KLCtupnIpulluP
eraskcolctuptuoeht,WOLnehW.elbanekcolcgnizinorhcnyS
.delbaneeraskcolc
tuptuo,HGIHnehW.delbasid
.slevelecafretniLTTVL/SOMCVL
5KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
6KLCntupnI /pulluP
nwodlluP V.tupnikcolclaitnereffidgnitrevnI
DD
.gnitaolftfelnehwtluafed2/
7LES_KLCtupnIpulluP
.stupniKLCn,KLCstceles,HGIHnehW.tupnitceleskcolC
.tupniKLC_S
OMCVLstceles,WOLnehW
.slevelecafretniLTTVL/SOMCVL
8KLC_SOMCVLtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
61,41,21,0
10Q,1Q,2Q,3QtuptuO.slevelecafretniLTTVL/SOMCVL.stuptuokcolC
51,11V
ODD
rewoP.snipylppustuptuO
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
3
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
EONE_KLCLES_KLCecruoSdetceleS3Q:0Q
10 0 KLC_SOMCVLWOL;delbasiD
10 1 KLCn,KLCWOL;delbasiD
11 0 KLC_SOMCVLdelbanE
11 1 KLC
n,KLCdelbanE
0X X ZiH
egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_
KLCretfA:ETON
.1erugiFninwohssa
FIGURE 1. CLK_EN TIMING DIAGRAM
Enabled
Disabled
nCLK
CLK,
LVCMOS_CLK
CLK_EN
Q0:Q3
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
4
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC531.33.3564.3V
V
ODD
egatloVylppuStuptuO
531.33.3564.3V
573.25.2526.2V
56.18.159.1V
I
DD
tnerruCylppuSrewoP 12Am
I
ODD
tnerruCylppuStuptuO 5Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
tupnI
egatloVhgiH
EO,LES_KLC,NE_KLC2V
DD
3.0+V
KLC_SOMCVL2V
DD
3.0+V
V
LI
tupnI
egatloVwoL
EO,LES_KLC,NE_KLC3.0-8.0V
KLC_SOMCVL3.0-3.1V
I
HI
tupnI
tnerruChgiH
EO,LES_KLC,NE_KLCV
DD
V=
NI
V564.3=5Aµ
KLC_SOMCVLV
DD
V=
NI
V564.3=051Aµ
I
LI
tupnI
tnerruCwoL
EO,LES_KLC,NE_KLCV
DD
V,V564.3=
NI
V0=051-Aµ
KLC_SOMCVLV
DD
V,V564.3=
NI
V0=5-Aµ
V
HO
1ETON;egatloVhgiHtuptuO
V
ODD
%5±V3.3=6.2V
V
ODD
%5±V5.2=8.1V
V
ODD
V51.0±V8.1=V
ODD
3.0-V
V
LO
1ETON;egatloVwoLtuptuO
V
ODD
%5±V3.3=5.0V
V
ODD
%5±V5.2=5.0V
V
ODD
V51.0±V8.1=4.0V
I
LZO
woLtnerruCetatsirTtuptuO 5-Aµ
I
HZO
hgiHtnerruCetatsirTtuptuO 5Aµ
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
.tiucriCtseTdaoLtuptuO,noitamrofnItnemerusaeMretemaraPeeS.2/
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, V
O-0.5V to VDDO + 0.5V
Package Thermal Impedance, θ
JA 89°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
5
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCnV
NI
V=
DD
V564.3=051Aµ
KLCV
NI
V=
DD
V564.3=051Aµ
I
LI
tnerruCwoLtupnI KLCnV
NI
V,V0=
DD
V564.3=051-Aµ
KLCV
NI
V,V0=
DD
V564.3=5-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC
2,1ETON 5.0+DNGV
DD
58.0-V
snoitacilppadedneelgnisroF:1ETON ,VsiKLCn,KLCrofegatlovtupnimumixameht
DD
.V3.0+
VsadenifedsiegatlovedomnommoC:2ETON
HI
.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO KLCn/KLC=feR053zHM
KLC_SOMCVL=feR003zHM
pt
HL
,yaleDnoitagaporP
hgiHotwoL
;KLC_SOMCVL
A1ETON
;KLCn,KLC
B1ETON
57.18.2sn
t
)o(ks6,2ETON;wekStuptuOegdEgnisiRehtnoderusaeM04sp
t
)pp(ks6,3ETON;wekStraP-ot-traP 007sp
t
tij
;SMR,rettiJesahPevitiddAreffuB
,noitcesrettiJesahPevitiddAotrefer
5ETON
40.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02001007sp
cdoelcyCytuDtuptuO IJzHM0025455%
zHM002>ƒ2485%
t
NE
4ETON;emiTelbanEtuptuO 5sn
t
SID
4ETON;emiTelbasiDtuptuO 5sn
VehtmorfderusaeM:A1ETON
DD
Vottupniehtfo2/
ODD
.tuptuoehtfo2/
VottniopgnissorctupnilaitnereffidehtmorfderusaeM:B1ETON
ODD
.tuptuoehtfo2/
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
Vtade
rusaeM
ODD
.2/
dnasegatlovylppusemasehtagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
Vtaderusaemsituptuoeht,ecivedhcaenotupnifoepytemasehtgnisU.snoitidnocdaollauqehtiw
ODD
.2/
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:4ETON
.kcolctupnienoylnognivi
rD:5ETON
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:6ETON
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
6
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± -0.15V, TA = -40°C TO 85°C
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO KLCn/KLC=feR053zHM
KLC_SOMCVL=feR003zHM
pt
HL
,yaleDnoitagaporP
hgiHotwoL
;KLC_SOMCVL
A1ETON
;KLCn,KLC
B1ETON
57.159.2sn
t
)o(ks6,2ETON;wekStuptuOegdEgnisiRehtnoderusaeM04sp
t
)pp(ks6,3ETON;wekStraP-ot-traP 008sp
ttij
;SMR,rettiJesahPevitiddAreffuB
,noitcesrettiJesahPevitiddAotrefer
5ETON
40.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02001007sp
cdoelcyCytuDtuptuO IJzHM6615455%
zHM661>f2485%
t
NE
4ETON;emiTelbanEtuptuO 5sn
t
SID
4ETON;emiTelbasiDtuptuO 5sn
VehtmorfderusaeM:A1ETON
DD
Vottupniehtfo2/
ODD
.tuptuoehtfo2/
VottniopgnissorctupnilaitnereffidehtmorfderusaeM:B1ETON
ODD
.tuptuoehtfo2/
VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD
:2ETON
ODD
.2/
dnasegatlovylppusemasehtagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
Vtaderusaemsi
tuptuoeht,ecivedhcaenotupnifoepytemasehtgnisU.snoitidnocdaollauqehtiw
ODD
.2/
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:4ETON
.kcolctupnienoylnognivi
rD:5ETON
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:6ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO KLCn/KLC=feR053zHM
KLC_SOMCVL=feR003zHM
pt
HL
,yaleDnoitagaporP
hgiHotwoL
;KLC_SOMCVL
A1ETON
;KLCn,KLC
B1ETON
57.17.3sn
t
)o(ks6,2ETON;wekStuptuOegdEgnisiRehtnoderusaeM54sp
t
)pp(ks6,3ETON;wekStraP-ot-traP 009sp
tj ti
;SMR,rettiJesahPevitiddAreffuB
,noitcesrettiJesahPevitiddAotrefer
5ETON
40.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02001007sp
cdoelcyCytuDtuptuO IJzHM6615455%
zHM661>f2485%
t
NE
4ETON;emiTelbanEtuptuO 5sn
t
SID
4ETON;emiTelbasiDtuptuO 5sn
.B5elbaTees,setonroF
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
7
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.04ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
8
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
VDD
tsk(pp)
V
DDO
2
V
DDO
2
Qx
Qy
PART 1
PART 2
-1.65V±5%
1.65V±5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
-1.25V±5%
1.25V±5%
SCOPE
Qx
LVCMOS
-0.9V±0.075V
0.9V±0.075V
VDD
VDDO
2.4V±0.09V
SCOPE
Qx
LVCMOS
VDD
VDDO
2.05V±5%
VDD,
VDDO
GND
GND
GND
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
9
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
PROPAGATION DELAY OUTPUT RISE/FALL TIME
Clock
Outputs
20%
80% 80%
20%
t
R
t
F
nCLK
CLK
Q0:Q3
t
PD
V
DDO
2
➤
➤
V
DD
2
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
tPW
Q0:Q3
LVCMOS_CLK
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
10
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Clock Input CLK
nCLK
VDD
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
11
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A,
the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driver
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
12
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8305I is: 459
TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
LVCMOS Rec eiv er
R1
43
VDD
R5
1K
LVCMOS Rec eiv er
VDD=3.3V
VDD
R4
1K
Zo = 50
(U1,11)
Ro ~ 7 Ohm
3,.3V LVCMOS (U1,15)(U1,3) VDD
R3 43
R2
43
C2
0.1u
U1
ICS8305
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
GND
OE
VDD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK GND
Q3
VDDO
Q2
GND
Q1
VDDO
Q0
Zo = 50
VDD
Zo = 50
C1
0.1u
R6
1K
C3
0.1u
SCHEMATIC EXAMPLE
This application note provides general design guide using
ICS8305I LVCMOS buffer.
Figure 4
shows a schematic example
of the ICS8305I LVCMOS clock buffer. In this example, the input
FIGURE 4. EXAMPLE ICS8305I LVCMOS CLOCK OUTPUT BUFFER SCHEMATIC
is driven by an LVCMOS driver. CLK_EN is set at logic low to
select LVCMOS_CLK input.
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
13
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N61
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.401.5
ECISAB04.6
1E03.405.4
eCISAB56.0
L5
4.057.0
α°0°8
aaa--01.0
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
14
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
Integrated
Circuit
Systems, Inc.
8305AGI www.icst.com/products/hiperclocks.html REV. B MAY 19, 2005
15
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
TEEHSYROTSIHNOISIVER
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