2014 Microchip Technology Inc. DS40001744B-page 1
PIC16(L)F183XX
Description
PIC16(L)F183XX microcontrollers feature Analog, Core Independent Peripherals and communication peripherals,
combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The
Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,
PWM and communications) to add flexibility to the application design.
Core Features
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operati ng Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-Bit Timers
• Up to Three 16-Bit Timers
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR) with Fast Recovery
• Low-Power BOR (LPBOR) Option
• Extended Watchd og Timer (WD T) wi th D e dic ate d
On-Chip Os ci llator for Reliabl e Oper ation
• Programmable Code Protection
Memory
• Up to 14KB Program Flash Memory (PFM)
• Up to 1KB Data SRAM Memory
• 256B of EEPROM Data Flash Memory (DFM)
• Direct, Indirect and Relative Addressing modes
Operating Characteristics
• Operati ng Voltage Range:
- 1.8V to 3.6V (PIC16LF183XX)
- 2.3V to 5.5V (PIC16F183XX)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
eXtreme Low-Power (XLP) Features
• Sleep mode: 50 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operati ng Curren t:
- 8 uA @ 32 kHz, 1.8V, typical
- 32 uA/MHz @ 1.8V, typical
Power-Saving Functionality
• Doze mode: Ability to run the CPU core slower
than the system clock used by the internal
peripherals
• Idle mode: Ability to put the CPU core to sleep
while inte rna l peri ph eral s conti nu e ope rati ng from
the system clock
• Sleep mode: Lowest Power Consumption
• Peripheral Module Disable: Peripheral power
disable hardware module to minimize power
consumption of unused peripherals
Digital Peripherals
• Configurable Logic Cell (CLC):
- Up to four CLCs
- Integrated combinational and sequential logic
• Complem entary Wav efo rm Ge nera tor (CW G ):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Up to two CWGs
- Multiple signal sources
• Up to Four Capture/Compare/PWM (CCP)
modules
• PWM: Two 10-bit Pulse-Width Modulators
• Numerically Controlled Oscillator (NCO):
- Precision linear frequency generator (@50%
duty cycle) with 0.0001% step size of source
input clock
- Input Clock: 0 Hz < FNCO < 32 MHz
- Resolution: FNCO/220
• Serial Communications:
- SPI, I2C™, EUSART
- RS-232, RS-485, LIN co mpatible
• Data Signal Modulator (DSM):
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms.
Full-Featured, Low Pin Count Microcontrollers with XLP Product Brief
PIC16(L)F183XX
DS40001744B-page 2 2014 Microchip Technology Inc.
• Peripheral Pin Select (PPS):
- I/O pin remapping of digital peripherals
• Up to 18 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-c han ge with edg e-s ele ct
Analog Peripherals
• 10-Bit Analog-to-Digital Converter (ADC):
- Up to 17 external channels
- Conversion available during Sleep
• Comparator:
- Up to two comparators
- Low and High-Speed modes
- Fixed Voltage Reference at inverting/non-
inverting input(s)
- Compar ator outputs ext ern ally accessible
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Refere nce Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Volta ge Refere nc e:
- Fixed V olt age Refer ence with 1.02 4V, 2 .048V
and 4.096V output levels
Clocking Structure
• High-Precision Internal Oscillator:
- Selectab le freq uen cy range up to 32 MHz
• x2/x4 PLL with Internal and External Sources
• Low -Power Internal 32 kHz Oscill ator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOCS )
• External High-Speed Crystal Oscillators
2014 Microchip Technology Inc. DS40001744B-page 3
PIC16(L)F183XX
TABLE 1: PIC16(L)F183XX Family Types
Device
Data Sheet Index
Program Flash
Memory (K words)
Program Memory
Flash (K bytes)
Data Memory
(bytes)
Data SRAM
(bytes)
I/Os(1)
10-bit ADC (ch)
5-bit DAC
Comparators
CWG
Clock R ef
Timers
(8/16-bit)
CCP
PWM
NCO
EUSART
MSSP (I2C™/SPI)
CLC
DSM
PPS
XLP
PMD
Idle & Doze
Debug(2)
PIC16(L)F18313 (A) 2 3.5 256 256 6 9 1 1 1 1 2/1 2 2 1 1 1 2 1 Y Y Y Y I/E
PIC16(L)F18323 (A) 2 3.5 256 256 12 15 1 2 1 1 2/1 2 2 1 1 1 2 1 Y Y Y Y I/E
PIC16(L)F18324 (B) 4 7 256 512 12 15 1 2 2 1 4/3 4 2 1 1 1 4 1 Y Y Y Y I/E
PIC16(L)F18325 (C) 8 14 256 1K 12 15 1 2 2 1 4/3 4 2 1 1 2 4 1 Y Y Y Y I/E
PIC16(L)F18344 (B) 4 7 256 512 18 21 1 2 2 1 4/3 4 2 1 1 1 4 1 Y Y Y Y I/E
PIC16(L)F18345 (C) 8 14 256 1K 18 21 1 2 2 1 4/3 4 2 1 1 2 4 1 Y Y Y Y I/E
Note 1: One pin i s inpu t-onl y.
2: Debugging Methods: (I) – Integrated on Chip; E – using Emulation Header.
Data Sheet Index: (Unshaded device s are described in this document.)
Note A: Future Release PIC16(L)F18313/18323 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP
B: Future Release PIC16 (L)F183 24/18 344 D at a Sheet, Full-Feat ur ed, Low Pin Cou nt Microco ntrol le rs with XLP
C: Future Release PIC16(L )F1832 5/1834 5 Dat a She et, Full- Featured , Low Pin Count Micr ocon troll ers wi th XLP
Note: For other small form-factor pac kage availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
PIC16(L)F183XX
DS40001744B-page 4 2014 Microchip Technology Inc.
TABLE 2: PACKAGES
Packages PDIP SOIC DFN/UDFN TSSOP QFN/UQFN SSOP
PIC16(L)F18313 X X X
PIC16(L)F18323 X X X X
PIC16(L)F18324 X X X X
PIC16(L)F18325 X X X X
PIC16(L)F18344 X X X X
PIC16(L)F18345 X X X X
Note: Pin details are subject to change.
2014 Microchip Technology Inc. DS40001744B-page 5
PIC16(L)F183XX
PIN DIAGRAMS
Pin Diagram – 8-Pin PDIP, SOIC, DFN/UDFN
Pin Diagram – 14-Pin PDIP, SOIC, TSSOP
Pin Diagram – 16-Pin QFN/UQFN
1
2
3
4
VDD
RA5
RA4
VPP/MCLR/RA3
RA0/ICSPDAT
RA1/ICSPCLK
RA2
VSS
8
7
6
5
PIC16(L)F18313
Note: See Table 3 for location of all peripheral functions.
1
2
3
4
5
6
7
VDD
RA5
RA4
VPP/MCLR/RA3
RC5
RC4
RC3
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
14
13
12
11
10
9
8
VSS
PIC16(L)F18323
PIC16(L)F18324
PIC16(L)F18325
Note: See Table 4, Table 5 and Table 6 for location of all peripheral functions.
2
3
1
9
10
11
12
RC4
4
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
NC
NC
VDD
RA5
RA4
RA3/MCLR/VPP
RC5
RC3
RC2
RC1
6758
15 14
16 13
PIC16(L)F18323
PIC16(L)F18324
PIC16(L)F18325
Note 1: See Table 4, Table 5 and Table 6 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS.
PIC16(L)F183XX
DS40001744B-page 6 2014 Microchip Technology Inc.
Pin Diagram – 20-Pin PDIP, SOIC, SSOP
Pin Diagram – 20-Pin QFN/UQFN (4x4)
PIC16(L)F18344
PIC16(L)F18345
1
2
3
4
20
19
18
17
5
6
7
16
15
14
VDD
RA5
RA4
MCLR/VPP/RA3
RC5
RC4
RC3
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
8
9
10
13
12
11
RC6
RC7
RB7
RB4
RB5
RB6
Note: See Table 7 and Table 8 for location of all peripheral functions.
-
89
2
3
114
15
16
10
11
6
12
13
17181920
7
5
4
PIC16(L)F18344
PIC16(L)F18345
RA3/MCLR/VPP
RC5
RC4
RC3
RC6
RC7
RB7
RB4
RB5
RB6
RC1
RC0
RA2
RA1/ICSPCLK
RA0/ICSPDAT
Vss
VDD
RA4
RA5
RC2
Note 1: See Table 7 and Table 8 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS.
2014 Microchip Technology Inc. DS40001744B-page 7
PIC16(L)F183XX
PIN ALLOCATION TABLES
TABLE 3: 8-PIN ALLOCATION TABLE (PIC16( L)F18 313 )
I/O(2)
8-Pin PDIP/SOIC/DFN/UDFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0 7ANA0 —C1IN0+ —DAC1OUT MDCIN1(1) — — — — — TX(1)
CK(1) CLCIN3(1) —IOCA0 YICDDAT/
ICSPDAT
RA1 6ANA1 VREF+C1IN0- — DAC1REF+MDMIN
(1) ————SCK
(1)
SCL(1,3,4) RX(1)
DT(1,3) CLCIN2(1) —IOCA1 YICDCLK/
ICSPCLK
RA2 5ANA2 VREF- — — DAC1REF- — T0CKI(1) — — CWG1(1) SDA(1,3,4)
SDO(1) — — — INT(1)
IOCA2 Y —
RA3 4 — — — — — — ————SS
(1) —CLCIN0
(1) —IOCA3 YMCLR
VPP
RA4 3ANA4 —C1IN1- — — — T1G(1)
SOSCO — — — — — — — IOCA4 YCLKOUT
OSC2
RA5 2ANA5 —— — — MDCIN2(1) T1CKI(1)
SOSCIN
SOSCI
CCP1(1)
CCP2(1) ————CLCIN1(1) —IOCA5 YCLKIN
OSC1
VDD 1— — — — — — — — — — — — — —— — VDD
VSS 8——— — — — ——————————VSS
OUT(2)
— — — C1OUT NCO —DSM TMR0 CCP1 PWM5 CWG1A SDA(3) CK CLC1OUT CLKR — — —
— — — — — — — — CCP2 PWM6 CWG1B SCL(3) DT(3) CLC2OUT — — — —
— — — — — — — — — — CWG1C SDO TX — — — — —
— — — — — — — — — — CWG1D SCK — — — — — —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
PIC16(L)F183XX
DS40001744B-page 8 2014 Microchip Technology Inc.
TABLE 4: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18323)
I/O(2)
14/16-P in PDIP /SOIC/T S SOP
16-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0 13 12 ANA0 —C1IN0+ —DAC1OUT — — — — — — — — —IOCA0 YICDDAT/
ICSPDAT
RA1 12 11 ANA1 VREF+C1IN0-
C2IN0- —DAC1REF+— —— — — ————IOCA1 YICDCLK/
ICSPCLK
RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) — — CWG1(1) — — — — INT(1)
IOCA2 Y —
RA3 4 3 — — — — — — —— — — ————IOCA3 YMCLR
VPP
RA4 3 2 ANA4 — — — — — T1G(1)
SOSCO — — — — — — — IOCA4 YCLKOUT
OSC2
RA5 2 1 ANA5 ——— — —T1CKI(1)
SOSCIN
SOSCI
—— ———
CLCIN3(1) —IOCA5 YCLKIN
OSC1
RC0 10 9ANC0 —C2IN0+ — — — — — — — SCK(1)
SCL(1,3,4) — — — IOCC0 Y —
RC1 9 8 ANC1 —C1IN1-
C2IN1- —— —————SDI
(1)
SDA(1,3,4) —CLCIN2(1) —IOCC1 Y —
RC2 8 7 ANC2 —C1IN2-
C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y —
RC3 7 6 ANC3 —C1IN3-
C2IN3- ——MDMIN
(1) —CCP2(1) ——SS
(1) —CLCIN0(1) —IOCC3 Y —
RC4 6 5 ANC4 — — — — — — — — — — TX(1)
CK(1) CLCIN1(1) —IOCC4 Y —
RC5 5 4 ANC5 —— — — MDCIN2(1) —CCP1(1) ———RX
(1)
DT(1,3) ——IOCC5 Y —
VDD 116 — — — — — — — — — — — — — — — — VDD
VSS 1413——— — — — —— — — ——————VSS
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
2014 Microchip Technology Inc. DS40001744B-page 9
PIC16(L)F183XX
OUT(2)
— — — — C1OUT NCO —DSM TMR0 CCP1 PWM5 CWG1A SDA(3) CK CLC1OUT CLKR — — —
— — — — C2OUT — — — — CCP2 PWM6 CWG1B SCL(3) DT(3) CLC2OUT — — — —
— — — — — — — — — — — CWG1C SDO TX — — — — —
————— — — — —— —CWG1DSCK——————
TABLE 4: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18323)
I/O(2)
14/16-P in PDIP /SOIC/T S SOP
16-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
PIC16(L)F183XX
DS40001744B-page 10 2014 Microchip Technology Inc.
TABLE 5: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18324)
I/O(2)
14/16-P in PDIP /SOIC/T S SOP
16-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0 13 12 ANA0 —C1IN0+ —DAC1OUT — — — — — — — — —IOCA0 YICDDAT/
ICSPDAT
RA1 12 11 ANA1 VREF+C1IN0-
C2IN0- —DAC1REF+— —— — — ————IOCA1 YICDCLK/
ICSPCLK
RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) CCP3(1) —CWG1(1)
CWG2(1) —— — — INT(1)
IOCA2 Y —
RA3 4 3 — — — — — — —— — — ————IOCA3 YMCLR
VPP
RA4 3 2 ANA4 — — — — — T1G(1)
SOSCO — — — — — — — IOCA4 YCLKOUT
OSC2
RA5 2 1 ANA5 ——— — —T1CKI(1)
SOSCIN
SOSCI
—— ———
CLCIN3(1) —IOCA5 YCLKIN
OSC1
RC0 10 9ANC0 —C2IN0+ — — — T5CKI(1) — — — SCK(1)
SCL(1,3,4) — — — IOCC0 Y —
RC1 9 8 ANC1 —C1IN1-
C2IN1- — — — — CCP4(1) ——SDI
(1)
SDA(1,3,4) —CLCIN2(1) —IOCC1 Y —
RC2 8 7 ANC2 —C1IN2-
C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y —
RC3 7 6 ANC3 —C1IN3-
C2IN3- ——MDMIN
(1) T5G(1) CCP2(1) ——SS
(1) —CLCIN0(1) —IOCC3 Y —
RC4 6 5 ANC4 — — — — — T3G(1) — — — — TX(1)
CK(1) CLCIN1(1) —IOCC4 Y —
RC5 5 4 ANC5 —— — — MDCIN2(1) T3CKI(1) CCP1(1) ———RX
(1)
DT(1,3) ——IOCC5 Y —
VDD 116 — — — — — — — — — — — — — — — — VDD
VSS 1413——— — — — —— — — ——————VSS
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
2014 Microchip Technology Inc. DS40001744B-page 11
PIC16(L)F183XX
OUT(2)
— — — — C1OUT NCO —DSM TMR0 CCP1 PWM5 CWG1A
CWG2A SDA(3) CK CLC1OUT CLKR — — —
— — — — C2OUT — — — — CCP2 PWM6 CWG1B
CWG2B SCL(3) DT(3) CLC2OUT — — — —
— — — — — — — — — CCP3 —CWG1C
CWG2C SDO TX CLC3OUT — — — —
— — — — — — — — — CCP4 — CWG1D
CWG2D SCK — CLC4OUT — — — —
TABLE 5: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18324) (CONTINUED)
I/O(2)
14/16-P in PDIP /SOIC/T S SOP
16-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
PIC16(L)F183XX
DS40001744B-page 12 2014 Microchip Technology Inc.
TABLE 6: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18325)
I/O(2)
14/16-P in PDIP /SOIC/T S SOP
16-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0 13 12 ANA0 —C1IN0+ —DAC1OUT — — — — — SS2(1) — — —IOCA0 YICDDAT/
ICSPDAT
RA1 12 11 ANA1 VREF+C1IN0-
C2IN0- —DAC1REF+— — — — — — — — —IOCA1 YICDCLK/
ICSPCLK
RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) CCP3(1) —CWG1(1)
CWG2(1) —— — — INT(1)
IOCA2 Y —
RA3 4 3 — — —— — ——— — — ————IOCA3 YMCLR
VPP
RA4 3 2 ANA4 — — — — — T1G(1)
SOSCO — — — — — — — IOCA4 YCLKOUT
OSC2
RA5 2 1 ANA5 ——— — —T1CKI(1)
SOSCIN
SOSCI
—————
CLCIN3(1) —IOCA5 YCLKIN
OSC1
RC0 10 9ANC0 —C2IN0+ — — — T5CKI(1) — — — SCK1(1)
SCL1(1,3,4) — — — IOCC0 Y —
RC1 9 8 ANC1 —C1IN1-
C2IN1- — — — — CCP4(1) ——SDI1
(1)
SDA1(1,3,4) —CLCIN2(1) —IOCC1 Y —
RC2 8 7 ANC2 —C1IN2-
C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y —
RC3 7 6 ANC3 —C1IN3-
C2IN3- ——MDMIN
(1) T5G(1) CCP2(1) — — SS1(1) —CLCIN0(1) —IOCC3 Y —
RC4 6 5 ANC4 — — — — — T3G(1) — — — SCK2(1)
SCL2(1,3,4) TX(1)
CK(1) CLCIN1(1) —IOCC4 Y —
RC5 5 4 ANC5 —— — — MDCIN2(1) T3CKI(1) CCP1(1) ——SDI2
(1)
SDA2(1,3,4) RX(1)
DT(1,3) ——IOCC5 Y —
VDD 116 — — — — — — — — — — — — — — — — VDD
VSS 14 13 — — — — — — — — — — — — — — — — VSS
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
2014 Microchip Technology Inc. DS40001744B-page 13
PIC16(L)F183XX
OUT(2)
— — — — C1OUT DDS —DSM TMR0 CCP1 PWM5 CWG1A
CWG2A SDA1(3)
SDA2(3) CK CLC1OUT CLKR — — —
— — — — C2OUT — — — — CCP2 PWM6 CWG1B
CWG2B SCL1(3)
SCL2(3) DT(3) CLC2OUT — — — —
— — — — — — — — — CCP3 —CWG1C
CWG2C SDO1
SDO2 TX CLC3OUT — — — —
— — — — — — — — — CCP4 — CWG1D
CWG2D SCK1
SCK2 — CLC4OUT — — — —
TABLE 6: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18325) (Continued)
I/O(2)
14/16-P in PDIP /SOIC/T S SOP
16-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
PIC16(L)F183XX
DS40001744B-page 14 2014 Microchip Technology Inc.
TABLE 7: 20-PIN ALLOCATION TABLE (PIC16(L)F18344)
I/O(2)
20-Pin PDIP/SOIC/SSOP
20-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0 19 16 ANA0 —C1IN0+ —DAC1OUT — — — — — — — — —IOCA0 YICDDAT/
ICSPDAT
RA1 18 15 ANA1 VREF+C1IN0-
C2IN0- —DAC1REF+— — — — — — — — —IOCA1 YICDCLK/
ICSPCLK
RA2 17 14 ANA2 VREF- — — DAC1REF- — T0CKI(1) CCP3(1) —CWG1(1)
CWG2(1) ——CLCIN0(1) —INT(1)
IOCA2 Y —
RA3 4 1 — — —— — ——— — — ————IOCA3 YMCLR
VPP
RA4 320 ANA4 — — — — — T1G(1)
T3G(1)
T5G(1)
SOSCO
CCP4(1) — — — — — — IOCA4 YCLKOUT
OSC2
RA5 219 ANA5 ——— — —T1CKI(1)
T3CKI(1)
T5CKI(1)
SOSCIN
SOSCI
——————
—IOCA5 YCLKIN
OSC1
RB4 13 10 ANB4 — — — — — — — — — SDI(1)
SDA(1,3,4) —CLCIN2(1) —IOCB4 Y —
RB5 12 9ANB5— — — — — — — — — — RX
(1)
DT(1) CLCIN3(1) —IOCB5Y —
RB6 11 8ANB6 — — — — — — — — — SCK(1)
SCL(1,3,4) — — — IOCB6 Y —
RB7 10 7ANB7— — — — — — — — — — TX(1)
CK(1) ——IOCB7Y—
RC0 16 13 ANC0 —C2IN0+ — — — — — — — — — — — IOCC0 Y —
RC1 15 12 ANC1 —C1IN1-
C2IN1- ———————————IOCC1 Y —
RC2 14 11 ANC2 —C1IN2-
C2IN2- — — MDCIN1(1) — — — — — — — — IOCC2 Y —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be stan dard
TTL/ST as selected by the INLVL register.
2014 Microchip Technology Inc. DS40001744B-page 15
PIC16(L)F183XX
RC3 7 4 ANC3 — C1IN3-
C2IN3- ——MDMIN
(1) — CCP2(1) — — — — CLCIN1(1) — IOCC3 Y —
RC4 6 3 ANC4 — — — — — — — — — —— — —IOCC4 Y —
RC5 5 2 ANC5 —— — — MDCIN2(1) —CCP1(1) ——————IOCC5 Y —
RC6 8 5 ANC6 — — — — — — — — — SS(1) — — — IOCC6 Y—
RC7 9 6 ANC7 — — — — — — — — — — — — — IOCC7 Y —
VDD 118 — — — — — — — — — — — — — — — — VDD
VSS 20 17 — — — — — — — — — — — — — — — — VSS
OUT(2)
— — — — C1OUT NCO —DSM TMR0 CCP1 PWM5 CWG1A
CWG2A SDO DT(3) CLC1OUT CLKR — — —
— — — — C2OUT — — — — CCP2 PWM6 CWG1B
CWG2B SCK CK CLC2OUT — — — —
— — — — — — — — — CCP3 —CWG1C
CWG2C SCL(3) TX CLC3OUT — — — —
— — — — — — — — — CCP4 — CWG1D
CWG2D SDA(3) — CLC4OUT — — — —
TABLE 7: 20-PIN ALLOCATION TABLE (PIC16(L)F18344) (Continued)
I/O(2)
20-Pin PDIP/SOIC/SSOP
20-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be stan dard
TTL/ST as selected by the INLVL register.
PIC16(L)F183XX
DS40001744B-page 16 2014 Microchip Technology Inc.
TABLE 8: 20-PIN ALLOCATION TABLE (PIC16(L)F18345)
I/O(2)
20-Pin PDIP/SOIC/SSOP
20-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0 19 16 ANA0 —C1IN0+ —DAC1OUT — — — — — — — — —IOCA0 YICDDAT/
ICSPDAT
RA1 18 15 ANA1 VREF+C1IN0-
C2IN0- —DAC1REF+— — — — — SS2(1) ———IOCA1 YICDCLK/
ICSPCLK
RA2 17 14 ANA2 VREF- — — DAC1REF- — T0CKI(1) CCP3(1) —CWG1(1)
CWG2(1) ——CLCIN0(1) —INT(1)
IOCA2 Y —
RA3 4 1 — — —— — ——— — — ————IOCA3 YMCLR
VPP
RA4 320 ANA4 — — — — — T1G(1)
T3G(1)
T5G(1)
SOSCO
CCP4(1) — — — — — — IOCA4 YCLKOUT
OSC2
RA5 219 ANA5 ——— — —T1CKI(1)
T3CKI(1)
T5CKI(1)
SOSCIN
SOSCI
——————
—IOCA5 YCLKIN
OSC1
RB4 13 10 ANB4 — — — — — — — — — SDI1(1)
SDA1(1,3,4) —CLCIN2(1) —IOCB4 Y —
RB5 12 9ANB5— — — — — — — — — SDI2
(1)
SDA2(1,3,4) RX(1)
DT(1) CLCIN3(1) —IOCB5Y —
RB6 11 8ANB6 — — — — — — — — — SCK1(1)
SCL1(1,3,4) — — — IOCB6 Y —
RB7 10 7 ANB7 — — — — — — — — — SCK2(1)
SCL2(1,3,4) TX(1)
CK(1) ——IOCB7Y—
RC0 16 13 ANC0 —C2IN0+ — — — — — — — — — — — IOCC0 Y —
RC1 15 12 ANC1 —C1IN1-
C2IN1- ———————————IOCC1 Y —
RC2 14 11 ANC2 — C1IN2-
C2IN2- — — MDCIN1(1) —— — — ————
IOCC2 Y —
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be stan dard
TTL/ST as selected by the INLVL register.
2014 Microchip Technology Inc. DS40001744B-page 17
PIC16(L)F183XX
RC3 7 4 ANC3 — C1IN3-
C2IN3- ——MDMIN
(1) — CCP2(1) — — — — CLCIN1(1) — IOCC3 Y —
RC4 6 3 ANC4 — — — — — — — — — — — — —IOCC4 Y —
RC5 5 2 ANC5 —— — — MDCIN2(1) —CCP1(1) ——————IOCC5 Y —
RC6 8 5 ANC6 — — — — — — — — — SS(1) — — — IOCC6 Y—
RC7 9 6 ANC7 — — — — — — — — — — — — — IOCC7 Y —
VDD 118 — — — — — — — — — — — — — — — — VDD
VSS 20 17 — — — — — — — — — — — — — — — — VSS
OUT(2)
— — — — C1OUT NCO —DSM TMR0 CCP1 PWM5 CWG1A
CWG2A SDO1
SDO2 DT(3) CLC1OUT CLKR — — —
— — — — C2OUT — — — — CCP2 PWM6 CWG1B
CWG2B SCK1
SCK2 CK CLC2OUT — — — —
— — — — — — — — — CCP3 —CWG1C
CWG2C SCL1(3)
SCL2(3) TX CLC3OUT — — — —
— — — — — — — — — CCP4 — CWG1D
CWG2D SDA1(3)
SDA2(3) — CLC4OUT — — — —
TABLE 8: 20-PIN ALLOCATION TABLE (PIC16(L)F18345)
I/O(2)
20-Pin PDIP/SOIC/SSOP
20-Pin QFN/UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registe rs.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS outp ut selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be stan dard
TTL/ST as selected by the INLVL register.
DS40001744B-page 18 2014 Microchip Technology Inc.
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer ,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoL yzer , PIC, PICSTART, PIC32 logo, RightTouch, S pyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporat ed in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsP ICDEM. net, ECA N, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLA B Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewS pan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Mic r o chip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63276-629-8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that i t s family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopp ing
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2014 Microchip Technology Inc. DS40001744B-page 19
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PIC16F18345-I/ML PIC16F18344T-I/ML PIC16F18345T-I/SO PIC16F18344-I/SO PIC16F18344T-I/SO
PIC16F18325-I/ST PIC16F18344-E/SS PIC16F18345-E/ML PIC16F18324-I/ST PIC16F18325-E/ST PIC16F18325-
I/ML PIC16F18324-I/ML PIC16F18344-E/ML PIC16F18325T-I/ST PIC16F18345-I/SO PIC16F18345T-I/SS
PIC16F18345T-I/ML PIC16F18324-I/P PIC16F18324-E/ML PIC16F18324-E/ST PIC16F18324T-I/SL PIC16F18324-
E/P PIC16F18324T-I/ST PIC16F18325-E/SL PIC16F18344-I/P PIC16F18325-E/P PIC16F18325T-I/SL
PIC16F18344-I/ML PIC16F18344T-I/SS PIC16F18345-E/P PIC16F18345-E/SO PIC16F18345-I/P PIC16F18344-
E/SO PIC16F18324T-I/ML PIC16F18344-E/P PIC16F18344-I/SS PIC16F18324-E/SL PIC16F18325T-I/ML
PIC16F18345-E/SS PIC16F18325-E/ML PIC16F18325-I/P PIC16F18324-I/SL PIC16F18325-I/SL PIC16F18345-I/SS
