PCA9534PW/DG,118 - NXP Semiconductors

1. General description

The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel

Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to

enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improveme nts

include higher drive capa bility, 5 V I/O tolerance, lower supply current, individual I/O

configuration, 400 kHz clock frequency, and smaller packaging. I/O expander s provide a

simple solution when additional I/O is needed for ACPI power switches, sensors,

push buttons, LEDs, fans, etc.

The PCA9534 consists of an 8-bit Configu ration register (Input or Output selection); 8-bit

Input register, 8-bit Output register and an 8-bit Polarity Inversion register (active HIGH or

active LOW operation). The system master can enable the I/Os as either inputs or outputs

by writing to the I/O configuration bits. The data for each input or output is kept in the

corresponding Input or Output register. The polarity of the Input Port register can be

inverted with the Polarity Inversion register. All registers can be read by the system

master. Although pin-to-pin and I2C-bus address compatible with the PCF8574 series,

softwar e changes are required due to the enhancement s and are di scussed in Application

Note AN469.

The PCA9534 is identical to the PCA9554 except for the removal of the internal I/O

pull-up resistor which greatly reduces power consumption when the I/Os are held LOW.

The PCA9534 open- drain interrupt ou tput is activated when any input state differs from its

corresponding input port register state and is used to indicate to the system master that

an input state has changed. The power-on reset sets the registers to their default value s

and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allo w up to eight

devices to share the same I2C-bus/SMBus.

2. Features and benefits

8-bit I2C-bus GPIO

Operating power supply voltage range of 2.3 V to 5.5 V

5 V tolerant I/Os

Polarity Inversion register

Active LOW interrupt output

Low standby current

Noise filter on SCL/SDA inputs

No glitch on power-up

Internal powe r- on res et

PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

Rev. 4 — 7 November 2017 Product data sheet

Product data sheet Rev. 4 — 7 November 2017 2 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

8 I/O pins which default to 8 inputs

0 Hz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Offered in four dif f erent p ackag es: SO16, TSSOP16, and HVQFN16 ( 4 40.85 mm

and 3 30.85 mm versions)

3. Ordering information

3.1 Ordering options

Table 1. Ordering information

Tamb =





Cto+85



Type number Topside

mark Package

Name Description Version

PCA9534D PCA9534D SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

PCA9534PW PCA9534 TSSOP16 plastic thin shrink small outline package; 16 l eads;

body width 4.4 mm SOT403-1

PCA9534BS 9534 HVQFN16 plastic thermal enhanced very thin quad flat package;

no leads; 16 terminals; body 4 40.85 mm SOT629-1

PCA9534BS3 P34 HVQFN16 plastic thermal enhanced very thin qua d flat package;

no leads; 16 terminals; body 3 30.85 mm SOT758-1

Table 2. Ordering options

Type number Orderable

part number Package Packing method Minimum

order quantity Temperature

PCA9534D PCA9534D,112 SO16 STANDARD

MARKING * IC'S

TUBE - DSC BULK

PACK

1920 Tamb =40 C to +85 C

PCA9534D,118 SO16 REEL 13" Q1/T1

*STANDARD MARK

SMD

1000 Tamb =40 C to +85 C

PCA9534D,512 SO16 STANDARD

MARKING * TUBE

DRY PACK

1920 Tamb =40 C to +85 C

PCA9534D,518 SO16 REEL 13" Q1/T1

*STANDARD MARK

SMD DP

1000 Tamb =40 C to +85 C

Product data sheet Rev. 4 — 7 November 2017 3 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

4. Block diagram

PCA9534PW PCA9534PW,112 TSSOP16 STANDARD

MARKING * IC'S

TUBE - DSC BULK

PACK

2400 Tamb =40 C to +85 C

PCA9534PW,118 TSSOP16 REEL 13" Q1/T1

*STANDARD MARK

SMD

2500 Tamb =40 C to +85 C

PCA9534 BS PCA9534BS,118 HVQFN16 REEL 13" Q1/T1

*STANDARD MARK

SMD

6000 Tamb =40 C to +85 C

PCA9534BS3 PCA9534BS3,118 HVQFN16 REEL 13" Q1/T1

*STANDARD MARK

SMD

6000 Tamb =40 C to +85 C

Table 2. Ordering options …continued

Type number Orderable

part number Package Packing method Minimum

order quantity Temperature

All I/Os are set to inputs at reset.

Fig 1. Block diagram of PCA9534

PCA9534

POWER-ON

RESET

002aac469

I2C-BUS/SMBus

CONTROL

INPUT

FILTER

SCL

SDA

VDD

INPUT/

OUTPUT

PORTS

IO0

VSS

8-bit

write pulse

read pulse

IO2

IO4

IO6

IO1

IO3

IO5

IO7

FILTER

VDD

INT

Product data sheet Rev. 4 — 7 November 2017 4 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16

Fig 4. Pin configura tio n for HVQFN1 6

(SOT629-1; 4 40.85 mm) Fig 5. Pin configur ation for HVQFN16

(SOT758-1; 3 30.85 mm)

PCA9534D

A0 VDD

A1 SDA

A2 SCL

IO0 INT

IO1 IO7

IO2 IO6

IO3 IO5

VSS IO4

002aac465

PCA9534PW

A0 VDD

A1 SDA

A2 SCL

IO0 INT

IO1 IO7

IO2 IO6

IO3 IO5

VSS IO4

002aac466

002aac467

PCA9534BS

Transparent top view

IO2 IO6

IO1 IO7

IO0 INT

A2 SCL

IO3

VSS

IO4

IO5

VDD

SDA

4 9

3 10

2 11

1 12

terminal 1

index area

002aac468

PCA9534BS3

Transparent top view

IO2 IO6

IO1 IO7

IO0

A2 SCL

IO3

VSS

IO4

IO5

VDD

SDA

4 9

3 10

2 11

1 12

terminal 1

index area

INT

Table 3. Pin description

Symbol Pin Description

SO16, TSSOP16 HVQFN16

A0 1 15 address input 0

A1 2 16 address input 1

A2 3 1 address input 2

IO0 4 2 input/output 0

IO1 5 3 input/output 1

IO2 6 4 input/output 2

IO3 7 5 input/output 3

VSS 86

[1] ground supply voltage

IO4 9 7 input/output 4

IO5 10 8 i nput/output 5

Product data sheet Rev. 4 — 7 November 2017 5 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

[1] HVQFN package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be

connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level

performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the

board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in

the thermal pad region.

6. Functional description

Refer to Figure 1 “Block diagram of PCA9534”.

6.1 Registers

6.1.1 Command byte

The command byte is the first byte to follow the address byte during a write tra nsmission.

It is used as a pointer to determine which of the following registers will be written or read.

6.1.2 Register 0 - Input Port register

This register is a read-only port. It reflect s the incomin g logic levels of the pins, regardless

of whether the pin is defined as an input or an output by Register 3. Writes to this register

have no effect.

The default ‘X’ is determined by the externally applied logic level.

IO6 11 9 i nput/output 6

IO7 12 10 input/output 7

INT 13 11 interrupt output (open-drain)

SCL 14 12 serial clock line

SDA 15 13 serial data line

VDD 16 14 supply voltage

Table 3. Pin description …continued

Symbol Pin Description

SO16, TSSOP16 HVQFN16

Table 4. Command byte

Command Protocol Function

0 read byte Input Port register

1 read/write byte Output Port register

2 read/write byte Polarity Inversion register

3 read/write byte Configuration register

Product data sheet Rev. 4 — 7 November 2017 6 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

6.1.3 Register 1 - Output Port register

This register reflect s the outgo ing logic levels of the pins d efined as output s by Re gister 3.

Bit values in this register have no ef fect on pins defined as input s. Reads from this register

return the value that is in the flip-flop controlling the output selection, not the actual pin

value.

6.1.4 Register 2 - Polarity Inversion register

This register allows the user to invert the polarity of the Input Port register data. If a bit in

this register is set (written with ‘1’), the corresponding Input Port dat a is inverted. If a bit in

this register is cleared (written with a ‘0’) , the Input Port data polarity is retained.

Table 5. Register 0 - Input Port register bit description

Bit Symbol Access Value Description

7 I7 read only X determined by externally applied logic level

6 I6 read only X

5 I5 read only X

4 I4 read only X

3 I3 read only X

2 I2 read only X

1 I1 read only X

0 I0 read only X

Table 6. Register 1 - Output Port register bit description

Legend: * default value.

Bit Symbol Access Value Description

7 O7 R 1* reflects outgoing logic levels of pins defined as

outputs by Register 3

6O6 R 1*

5O5 R 1*

4O4 R 1*

3O3 R 1*

2O2 R 1*

1O1 R 1*

0O0 R 1*

Table 7. Register 2 - Polarity Inversion register bit description

Legend: * default value.

Bit Symbol Access Value Description

7 N7 R/W 0* inverts polarity of Input Port register data

0 = Input Port register data retained (default value)

1 = Input Port register data inverted

6N6 R/W 0*

5N5 R/W 0*

4N4 R/W 0*

3N3 R/W 0*

2N2 R/W 0*

1N1 R/W 0*

0N0 R/W 0*

Product data sheet Rev. 4 — 7 November 2017 7 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

6.1.5 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver . If a bit in

this register is cleared, the corr esponding port pin is enabled as an output. At reset, th e

I/Os are configu re d as inpu ts.

6.2 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9534 in

a reset condition until VDD has reached VPOR. At that point, the reset condition is released

and the PCA9534 registers and state machine will initialize to their default states.

Thereafter, VDD must be lowered below 0.2 V to reset the device.

For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the

operating voltage.

6.3 Interrupt output

The open-drain interrupt output is activated when one of the port pins change state and

the pin is configured as an input. The interrupt is deactivated when the input returns to its

previous state or the Input Port register is read.

Note that changing an I/O from and output to an inp ut may cause a false interrupt to occur

if the sta te of the pin does not match the contents of the Input Port register.

6.4 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a

high-impedance in put. The inpu t volt age may be raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depen ding on the

state of th e Output Port register. Care should be exercised if an exte rnal voltage is applied

to an I/O configured as an output be cause of the low-impedance paths that exist between

the pin and either VDD or VSS.

Table 8. Register 3 - Configuration register bit description

Legend: * default value.

Bit Symbol Access Value Description

7 C7 R/W 1* confi gures the directions of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin configured as input

(default value)

6C6 R/W 1*

5C5 R/W 1*

4C4 R/W 1*

3C3 R/W 1*

2C2 R/W 1*

1C1 R/W 1*

0C0 R/W 1*

Product data sheet Rev. 4 — 7 November 2017 8 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

6.5 Device address

6.6 Bus transactions

Data is tran smitted to the PCA9534 registers using the Write mode as shown in Figure 8

and Figure 9. Data is read from the PCA9534 r egister s using the Read mod e as sh own in

Figure 10 and Figure 11. These devices do not implement an auto-increment function, so

once a command byte has been sent, the register which was addressed will continue to

be accessed by reads until a new command byte has been sent.

Remark: At power-on reset, all registers return to default values.

Fig 6. Simplified schematic of IO0 to IO7

VDD

IO0 to IO7

output port

configuration

CK Q

data from

shift register

write configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity inversion

002aac470

data from

shift register

VSS

to INT

Fig 7. PCA9534 device address

002aac471

0 1 0 0 A2 A1 A0 R/W

fixed

slave address

hardware

selectable

Product data sheet Rev. 4 — 7 November 2017 9 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

Fig 8. Write to Output Port register

1 0 0 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

002aac472

acknowledge

from slave

SCL

SDA A

write to port

data out

from port

v(Q)

987654321

command byte

acknowledge

from slave

data to port

DATA 1

slave address

00000010

STOP

condition

data 1 valid

Fig 9. Write to Configuration register or Polarity Inversion register

1 0 0 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

002aac473

acknowledge

from slave

SCL

SDA A

data to

987654321

command byte

acknowledge

from slave

data to register

DATA

slave address

0000011/00

STOP

condition

Fig 10. Read from register

1 0 0 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

002aac474

acknowledge

from slave

SDA

A P

command byte

acknowledge

from master

data from register

DATA (first byte)

slave address

STOP

condition

(repeated)

START condition

(cont.)

(cont.) 1 0 0 A2 A1 A0 1 A0

R/W

acknowledge

from slave

slave address

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

no acknowledge

from master

data from register

DATA (last byte)

Product data sheet Rev. 4 — 7 November 2017 10 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

This figure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any moment by a STOP condition.

Fig 11. Read Input Port register

1 0 0 A2 A1 A0 1 AS0

START condition R/W

acknowledge

from slave

002aac475

acknowledge

from master

SCL

SDA NA

read from

port

data into

port

th(D)

987654321

data from port

no acknowledge

from master

data from port

DATA 4

slave address

DATA 1

STOP

condition

DATA 2 DATA 3 DATA 4

tsu(D)

INT

tv(INT_N) trst(INT_N)

Product data sheet Rev. 4 — 7 November 2017 11 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

7. Application design-in information

7.1 Minimizing IDD when the I/O us used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to VDD through a

resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the

I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes

lower than VDD.

Designs needing to minimize current consumption, such as battery power applications,

should consider maint aining the IOn pins greater than or equa l to VDD when the LED is off.

Figure 13 shows a high value resistor in parallel with the LED. Figure 14 shows VDD less

than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI

at or above VDD and prevents additional supply current consumption when the LED is off.

Device address configured as 0100 100X for this example.

IO0, IO1, IO2 configured as outputs.

IO3, IO4, IO5 configured as inputs.

IO6, IO7 are not used and must be configured as outputs.

Fig 12. Typical application

PCA9534

IO0

IO1

SCL

SDA

VDD

002aac476

SCL

SDA IO2

IO3

VDD

VSS

MASTER

CONTROLLER

VSS

VDD (5 V)

2 kΩ

SUBSYSTEM 1

(e.g., temp. sensor)

INT

SUBSYSTEM 2

(e.g., counter)

RESET

controlled switch

(e.g., CBT device)

enable

INT

5 V

INT

10 kΩ10 kΩ

SUBSYSTEM 3

(e.g., alarm system)

ALARM

IO4

IO5

VDD

IO6

IO7

100 kΩ

(× 3)

10 kΩ10 kΩ

Product data sheet Rev. 4 — 7 November 2017 12 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

8. Limiting values

Fig 13. High value resistor in parallel with

the LED Fig 14. Device supplied by a lower voltage

002aac660

LED

VDD

IOn

100 kΩ

VDD

002aac661

LED

IOn

3.3 V 5 V

Table 9. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +6.0 V

IIinput current - 20 mA

VI/O voltage on an input/output pin VSS 0.5 5.5 V

IO(IOn) output current on pin IOn - 50 mA

IDD supply current - 85 mA

ISS ground supply current - 100 mA

Ptot total power dissipation - 200 mW

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +85 C

Product data sheet Rev. 4 — 7 November 2017 13 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

9. Static characteristics

Table 10. Static characteristics

VDD = 2.3 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 2.3 - 5.5 V

IDD supply current operating mode; VDD =5.5V;

no load; fSCL = 100 kHz - 104 175 A

Istb standby current Standby mode; VDD = 5.5 V; no load;

fSCL = 0 kHz; I/O = inputs

VI=V

SS -0.251 A

VI=V

DD -0.251 A

VPOR power-on reset voltage no load; VI=V

DD or VSS [1] -1.72.2V

Input SCL; input/outpu t S DA

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -5.5V

IOL LOW-level output current VOL =0.4V 3 6 - mA

ILleakage current VI=V

DD =V

SS 1- +1 A

Ciinput capacitance VI=V

SS - 5 10 pF

I/Os

VIL LOW-level input voltage 0.5 - +0.8 V

VIH HIGH-level input voltage 2.0 - 5.5 V

IOL LOW-level output current VOL =0.5V; V

DD =2.3V [2] 810- mA

VOL =0.7V; V

DD =2.3V [2] 10 13 - mA

VOL =0.5V; V

DD =3.0V [2] 814- mA

VOL =0.7V; V

DD =3.0V [2] 10 19 - mA

VOL =0.5V; V

DD =4.5V [2] 817- mA

VOL =0.7V; V

DD =4.5V [2] 10 24 - mA

VOH HIGH-level output voltage IOH =8mA; V

DD =2.3V [3] 1.8 - - V

IOH =10 mA; VDD =2.3V [3] 1.7 - - V

IOH =8mA; V

DD =3.0V [3] 2.6 - - V

IOH =10 mA; VDD =3.0V [3] 2.5 - - V

IOH =8mA; V

DD =4.75V [3] 4.1 - - V

IOH =10 mA; VDD =4.75V [3] 4.0 - - V

ILI input leakage curren t VI=V

DD =V

SS 1- +1 A

Ciinput capacitance - 5 10 pF

Interrupt INT

IOL LOW-level output current VOL =0.4V 3 - - mA

Select input s A0, A1, A2

VIL LOW-level input voltage 0.5 - 0.8 V

VIH HIGH-level input voltage 2.0 - 5.5 V

ILI input leakage curren t 1- 1 A

Product data sheet Rev. 4 — 7 November 2017 14 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

[1] VDD must be lowered to 0.2 V in order to reset part.

[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.

[3] The total current sourced by all I/Os must be limited to 85 mA.

10. Dynamic characteristics

[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.

[3] Cb= total capacitance of one bus line in pF.

Table 11. Dynamic characteristics

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

fSCL SCL clock frequency 0 100 0 400 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - s

tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - s

tSU;STO set-up time for STOP condition 4.0 - 0.6 - s

tHD;DAT data hold time 0 - 0 - s

tVD:ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s

tVD;DAT data valid time [2] 300 - 50 - ns

tSU;DAT data set-up time 250 - 100 - ns

tLOW LOW period of the SCL clock 4.7 - 1.3 - s

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s

trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns

tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 s

tSP pulse width of spikes that must be

suppressed by the input filter - 50 - 50 ns

Port timing

tv(Q) data output valid time - 200 - 200 ns

tsu(D) data input setup time 100 - 100 - ns

th(D) data input hold time 1 - 1 - s

Interrupt timing

tv(INT_N) valid time on pin INT -4 - 4s

trst(INT_N) reset time on pin INT -4 - 4s

Product data sheet Rev. 4 — 7 November 2017 15 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

Fig 15. Definition of timing

BUF

HD;STA

PP S

LOW

HD;DAT

HIGH

SU;DAT

SU;STA

HD;STA

SU;STO

SDA

SCL

002aaa986

0.7 × V

0.3 × V

0.7 × V

0.3 × V

Rise and fall times refer to VIL and VIH.

Fig 16. I2C-bus timing diagram

002aab175

protocol START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6) bit 0

(R/W) acknowledge

(A)

STOP

condition

(P)

SCL

SDA

tHD;STA tSU;DAT tHD;DAT

tBUF

tSU;STA tLOW tHIGH

tVD;ACK tSU;STO

1 / fSCL

tVD;DAT

0.3 × VDD

0.7 × VDD

0.3 × VDD

0.7 × VDD

Product data sheet Rev. 4 — 7 November 2017 16 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

11. Test information

RL = load resistor.

CL = load capacitance includes jig and probe capacitance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generators.

Fig 17. Test circu itr y for switching times

Fig 18. Test circ u it

Table 12. Test data

Test Load Switch

CLRL

tv(Q) 50 pF 500 2VDD

PULSE

GENERATOR

50 pF

500 Ω

002aab393

VDD

DUT

6.0 V

open

VSS

50 pF

500 Ω

002aab881

open

from output

under test

500 Ω

Product data sheet Rev. 4 — 7 November 2017 17 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

12. Package outline

Fig 19. Package outline SOT162-1 (SO16)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 10.5

10.1 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT162-1

detail X

0.25

075E03 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.41

0.40 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

vMA

(A )

0 5 10 mm

scale

SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

99-12-27

03-02-19

Product data sheet Rev. 4 — 7 November 2017 18 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

Fig 20. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 4 — 7 November 2017 19 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

Fig 21. Package outline SOT629-1 (HVQFN16)

terminal 1

index area

0.651

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.25

1.95

4.1

3.9 2.25

1.95

0.38

0.23

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT629-1 MO-220 - - -- - -

0.75

0.50

0.1

0.05

0 2.5 5 mm

scale

SOT629-1

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

16 13

01-08-08

02-10-22

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 4 — 7 November 2017 20 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

Fig 22. Package outline SOT758-1 (HVQFN16)

terminal 1

index area

0.51

A1Eh

UNIT y

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.75

1.45

3.1

2.9 1.75

1.45

1.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT758-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT758-1

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 3 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

16 13

02-03-25

02-10-21

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 4 — 7 November 2017 21 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

13. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you mu st take no rmal precautions appropria te to handling

integrated circuits.

14. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orie ntation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus PbSn soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 4 — 7 November 2017 22 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

14.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 23) than a PbSn process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 13 and 14

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 23.

Table 13. SnPb eutec t ic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 14. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 4 — 7 November 2017 23 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

15. Abbreviations

MSL: Moisture Sensitivity Level

Fig 23. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 15. Abbreviations

Acronym Description

ACPI Advanced Configuration and Power Interface

CDM Charged Device Model

DUT Device Under Test

ESD ElectroStatic Discharge

FET Field-Effect Transistor

GPIO General Purpose Input/Output

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

I/O Input/Output

LED Light-Emitting Diode

MM Machine Model

POR Power-On Reset

SMBus System Management Bus

Product data sheet Rev. 4 — 7 November 2017 24 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

16. Revision history

Table 16. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9534 v.4 20171107 Product data sheet 201710002I PCA9534_3

Modifications: •Table 10 “Static characteristics”: Corrected VPOR typ and max limit

•Added Section 3.1 “Ordering opti ons”

PCA9534_3 20061106 Product data sheet - PCA9534_2

Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•pin names I/O0 through I/O7 changed to IO0 through IO7

•added HVQFN16 (SOT758-1) package

•symbol (tpv and tPV) changed to tv(Q)

•symbol (tph and tPH) changed to th(D)

•symbol (tps and tPS) changed to tsu(D)

•symbol (tiv and tIV) changed to tv(INT_N)

•symbol (tir and tIR) changed to trst(INT_N)

•Figure 6 “Simplified schematic of IO0 to IO7”: removed ESD diodes

•Table 9 “Limiting values”: symbol “II/O, DC output current on an I/O” changed to “IO(IOn), output

current on pin IOn”

•Table 10 “Static characteristics”, sub-section “I/Os”: symbol IIL changed to ILI

•added Section 15 “Abbreviations”

PCA9534_2

(9397 750 13506) 20040930 Product data sheet - PCA9534_1

PCA9534_1

(9397 750 12454) 20031202 Product da ta ECN 853-2319 01-A14517

of 14 Nov 2003 -

Product data sheet Rev. 4 — 7 November 2017 25 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support , life-critical or

safety-critical systems or equipme nt, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 7 November 2017 26 of 27

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for aut omo tive use. It i s neither qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifi ca tions, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims result ing from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

Translations — A non-English (translated) version of a docume nt is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

17.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9534

8-bit I2C-bus and SMBus low power I/O port with interrupt

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 November 2017

Document identifier: PCA9534

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

6.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.1.1 Command byte. . . . . . . . . . . . . . . . . . . . . . . . . 5

6.1.2 Register 0 - Input Port register . . . . . . . . . . . . . 5

6.1.3 Register 1 - Output Port register. . . . . . . . . . . . 6

6.1.4 Register 2 - Polarity Inversion register . . . . . . . 6

6.1.5 Register 3 - Configuration register . . . . . . . . . . 7

6.2 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.3 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.4 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.5 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 8

6.6 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . . 8

7 Application design-in information . . . . . . . . . 11

7.1 Minimizing IDD when the I/O us used to control

LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12

9 Static characteristics. . . . . . . . . . . . . . . . . . . . 13

10 Dynamic characteristics . . . . . . . . . . . . . . . . . 14

11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 16

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17

13 Handling information. . . . . . . . . . . . . . . . . . . . 21

14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 21

14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 21

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21

14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

18 Contact information. . . . . . . . . . . . . . . . . . . . . 26

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27