3936
A3936-DS Rev. 2
Designed for pulse-width modulated (PWM) current control of three-
phase brushless dc motors, the A3936SED is capable of peak output currents
to ± 3 A and operating voltages to 50 V. Internal fixed off-time PWM current-
control timing circuitry can be configured to operate in slow-, fast- and mixed-
decay modes.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, and crossover current protection. Special power up sequencing is
not required.
The A3936 is supplied in a 44-pin plastic PLCC with internally
fused leads (three on each side) for enhanced heat dissipation. These leads
are at ground potential and need no electrical isolation. This device is also
available in a lead (Pb) free version, with 100% matte tin leadframe plating.
Features
±3 A, 50 V Continuous Output Rating
Low rDS(on) Outputs (typically 500 mΩ source, 315 mΩ sink)
Configurable Mixed, Fast and Slow Current-Decay Modes
Synchronous Rectification for Low Power Dissipation
Internal UVLO and Thermal Shutdown Circuitry
Crossover-Current Protection
Tachometer Output for External Speed Control Loop
Always order by complete part number
Part Number Package
A3936SED 44-pin PLCC
A3936SED-T 44-pin PLCC, Pb-free
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB ........................... 50 V
Output Current, IOUT................................... ±3 A*
Logic Supply Voltage, VDD......................... 7.0 V
Logic Input Voltage Range, VIN
(tW>30 ns).......... -0.3 V to VDD + 0.3 V
(tW<30 ns)................ -1.0V to VDD +1V
Sense Voltage, VSENSE................................. 0.5 V
Reference Voltage, VREF ................................VDD
Package Power Dissipation,
P
D............................................... 3.9 W
Operating Temperature Range,
T
A................................-20°C to +85°C
Junction Temperature, TJ.........................+150°C
Storage Temperature Range,
T
S...............................-55°C to +150°C
* Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating or a
junction temperature of 150°C.
DMOS THREE-PHAS
E
PWM MOTOR DRIVER
3936 Three Phase PWM Motor Driver
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
REF
HA-
SENSE
CURRENT
SENSE
+-
ZERO
CURRENT
DETECT
+-
.1uF
RS
REGULATOR CHARGE PUMP
VREG
CP1
CP2
BANDGAP
.22uf/100V
.22uf/50V
.22uf/50V
GATE
DRIVE
HA+
HB-
PWM
TIMER
OSC
TACH
OUTA
OUTB
OUTC
OVERVOLTAGE
UNDERVOLTAGE
AND FAULT
DETECT
BUFFER/
DIVIDER
VCPVREG
HB+
HC-
HC+
HALL
HALL
HALL
Comm
Logic
DIR
SLEEP
Control
Logic
VCP
VBB1
ENABLE
EXTMODE
BRAKE
SR
BLANK
HBIAS
PFD1
PFD2
VDD
VBB2
LSS1
LSS2
3936 Three Phase PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TJ= +25°C, VBB = 50 V, VDD =5.0V,f
PWM < 50KHz (unless noted otherwise)
Limits
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Output Drivers
Load Supply Voltage Range VBB Operating 9 – 50 V
During Sleep Mode 0 50 V
Output Leakage Current IDSS VOUT =V
BB –<1.020 µA
V
OUT = 0 V – <–1.0 -20 µA
Output On Resistance RDSON Source Driver, IOUT = -3A – .55 Ω
Sink Driver, IOUT =3A – .35 Ω
Body Diode Forward Voltage VFSource Diode, IF= -3A – – 1.4 V
Sink Diode, IF=3A – – 1.3 V
Motor Supply Current IBB fPWM <50kHz – 4 7 mA
Charge Pump On, Outputs Disabled – 2 5 mA
Sleep Mode – – 20 uA
IDD fPWM <50kHz – 10 mA
Outputs Off – 8 mA
Logic Supply Current
Sleep Mode (Inputs below .5V) 100 µA
Control Logic
Logic Supply Voltage Range VDD Operating 3 5.0 5.5 V
Logic Input Voltage VIN(1) VDD*.5 – – V
VIN(0) ––V
DD*.2 V
Logic Input Current IIN(1) VIN =V
DD*.5 -20 <1.0 20 µA
(except ENABLE) IIN(0) VIN =V
DD*.2 -20 <-1.0 20 µA
Logic Input Current IIN(1) VIN =V
DD*.5 – 100 µA
ENABLE Input IIN(0) VIN =V
DD*.2 – 30 µA
OSC shorted to GND 3 4 5 MHzInternal Oscillator fOSC
ROSC= 51K 3.4 4 4.6 MHz
3936 Three Phase PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TJ= +25°C, VBB =50V,V
DD = 5.0 V, fPWM < 50KHz (unless noted
otherwise)
Limits
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Control Logic
Buffer Input Offset Volt. VIO ±10 mV
VREF Input Voltage Range Operating 0.0 – VDD V
Reference Input Current IREF VREF =V
DD ,VBB=0 to 50V -.5 0 0.5 µA
Comparator Input Offset Volt. VIO VREF =0V ±5 mV
V
REF =V
DD -4 4 %GMError VERR
(Note 3) VREF =.5V -14 14 %
Propagation Delay Times tpd 50% TO 90%, SR Enabled
PWM CHANGE TO SOURCE ON 600 750 1000 ns
PWM CHANGE TO SOURCE OFF 50 150 350 ns
PWM CHANGE TO SINK ON 600 750 1000 ns
PWM CHANGE TO SINK OFF 50 100 150 ns
Crossover Delay tCOD SR Enabled 300 600 1000 ns
Thermal Shutdown Temp. TJ– 165 – °C
Thermal Shutdown Hysteresis ∆TJ–15– °C
UVLO Enable Threshold Rising VDD 2.45 2.7 2.95 V
UVLO Hysteresis 0.05 0.10 – V
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device pin.
3. VERR =((VREF/10) – VSENSE)/(VREF/10)
3936 Three Phase PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA= +25°C, VBB =50V,V
DD =5.0Vf
PWM < 50KHz (unless noted
otherwise)
Limits
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Hall Logic
Hall Input Current IHALL VIN =1.2V -1 0 1 µA
Common Mode Input Range VCMR .3 2.5 V
AC Input Voltage Range VHALL .120 Vp-p
Hysteresis VHYS TA= -20 to 85 deg C. 10 30 mV
Pulse Reject Filter 35.58 µs
Hall Bias Output Sat Voltage VHB IOUT=40mA, TA= -20 to 85 deg C. .4 .5 V
IHB 40 mA
Tach Output VOL IOUT= 500uA .5 V
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device pin.
Commutation Truth Table
120 spacing Outputs
HA HB HC DIR OUTA OUTB OUTC
1+-+FOR HI LO Z
2+- - FOR HI Z LO
3++- FOR Z HI LO
4-+-FOR LO HI Z
5-++FOR LO Z HI
6--+FOR Z LO HI
1+-+REV LO HI Z
2 + - - REV LO Z HI
3 + + - REV Z LO HI
4-+- REV HI LO Z
5-++REV HI Z LO
6 - - + REV Z HI LO
--- X Z Z Z
+++ X Z Z Z
3936 Three Phase PWM Motor Driver
Functional Description
VREG. The VREG pin should be decoupled with a 0.22
µF capacitor to ground. This supply voltage is used to run
the sink side DMOS outputs. VREG is internally monitored
and in the case of a fault condition, the outputs of the device
are disabled.
Charge Pump. The Charge Pump is used to generate a
supply above VBB to drive the source side DMOS gates. A
0.22 uF ceramic monolithic capacitor should be connected
between CP1and CP2for pumping purposes. A 0.22 uF
ceramic monolithic capacitor should be connected between
VCP and VBB to act as a reservoir to run the high side
DMOS devices. The VCP Voltage is internally monitored
and in the case of a fault condition the outputs of the device
are disabled.
Shutdown. In the event of a fault due to excessive
junction temperature, or low voltage on VCP or VREG,the
outputs of the device are disabled until the fault condition is
removed. At power up, and in the event of low VDD,the
UVLO circuit disables the drivers.
Current Regulation. Load current is regulated by an
internal fixed off time PWM control circuit. When the
outputs of the DMOS H-bridge are turned on, current
increases in the motor winding until it reaches a value given
by:
ITRIP =V
REF/(10*RSENSE)
At the trip point, the sense comparator resets the source
enable latch, turning off the source driver. At this point,
load inductance causes the current to recirculate for the
fixed off time period. The current path during recirculation
is determined by the configuration of slow/mixed decay
mode and the synchronous rectification control setting.
Enable Logic. The Enable input terminal allows
external PWM. ENABLE high turns ON the selected sink-
source pair, enable low switches off the appropriate drivers
and the load current decays. If the ENABLE pin is held
high, the current will rise until it reaches the level set by the
internal current control circuit.
ENABLE Outputs
0 Source
Chopped
1ON
Extmode Logic. When using external PWM current
control, the EXTMODE input determines the current path
during the chopped cycle. With EXTMODE set low, fast
decay mode, both the source and sink drivers are chopped
OFF during the decay time (ENABLE=0). With
EXTMODE high, slow decay mode, only the source driver
turns off during the current decay time.
EXTMODE Decay
0Fast
1Slow
Sleep Mode. The input pin SLEEP is dedicated to put
the device into a minimum current draw mode. When
asserted low, all circuits are disabled.
Fixed Off-Time. The 3936 is set for a fixed off time of
96 counts of the internal oscillator, typically 24 µs with
4Mhz oscillator.
Internal Current Control Mode. Input pins PFD1
and PFD2 determine the current decay method after an
overcurrent event is detected at sense input. In slow decay
mode both sink side drivers are turned on for the fixed off
time period. Mixed decay mode starts out in fast decay
mode for the selected percentage of the fixed off time, and
then is followed by slow decay for the rest of the period.
PFD2 PFD1 % tOFF Decay
00 0Slow
0 1 15 Mixed
1 0 48 Mixed
1 1 100 Fast
3936 Three Phase PWM Motor Driver
PWM Blank Timer. When a source driver turns on, a
current spike occurs due to the reverse recovery currents of
the clamp diodes and/or switching transients related to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source enable latch, the
sense comparator is blanked. The blank timer runs after the
off time counter to provide the blanking function. The blank
timer is reset when ENABLE is chopped or DIR is changed.
For external PWM control, a DIR change or ENABLE ON
will trigger the blanking function. The duration is adjusted
by control input BLANK.
BLANK tBLANK
06/f
OSC
1 12/fOSC
Synchronous Rectification. Logic high applied to
the SR terminal enables synchronous rectification. When a
PWM off cycle is triggered, either by an ENABLE chop
command or internal fixed off time cycle, load current will
recirculate according to the decay mode selected by control
logic. The A3936 synchronous rectification feature will turn
on the appropriate MOSFET(s)during the current decay and
effectively short out the body diodes with the low Rdson
driver. This will lower power dissipation significantly and
can eliminate the need for external schottky diodes.
Reversal of load current is prevented by turning off
synchronous rectification when a zero current level is
detected.
Brake. Logic high to the brake terminal activates the
brake function, logic low allows normal operation. Brake
will turn all three sink drivers ON and effectively shorts out
the motor generated BEMF. It is important to note that the
internal PWM current control circuit will not limit the
current when braking, since the current does not flow
through the sense resistor. The maximum current can be
approximated by VBEMF/RL. Care should be taken to insure
that the maximum ratings of the device are not exceeded in
worse case braking situations of high speed and high
inertial loads.
Oscillator. The PWM timer is based on an internal
oscillator set by a resistor connected from the OSC terminal
to VDD. Typical value of 4Mhz is set with 51k resistor.
FOSC = 204E9/ROSC.
Tach. A tachometer signal is available for speed
measurement. This open collector output toggles at each
Hall transition.
3936
Terminal List
Pin No. Pin Name Pin Description
1GND
2GND
3 HA+ Hall input
4 HA- Hall input
5 HB+ Hall input
6 HB- Hall input
7 HC+ Hall input
8 HC- Hall input
9V
DD Logic Supply Voltage
10 REF GmReference Input Voltage
11 GND
12 GND
13 GND
14 BRAKE Logic Input
15 SENSE Sense Resistor Connection
16 SR Logic Input (Disabled = Low, Active SR = High)
17 OUTA DMOS H – Bridge A
18 HBIAS Connection for hall element neg side
19 VBB1 Load Supply Voltage
20 LSS1 Low Side Source connection
21 OUTB DMOS H – Bridge B
22 GND
23 GND
24 GND
25 LSS2 Low Side Source connection
26 VBB2 Load Supply Voltage
27 TACH Speed output
28 OUTC DMOS H – Bridge C
29 VCP Reservoir Capacitor Terminal
30 CP1 Charge Pump Capacitor Terminal
31 CP2 Charge Pump Capacitor Terminal
32 SLEEP Logic input for SLEEP mode
33 GND
34 GND
35 GND
36 OSC Oscillator Terminal
37 VREG Regulator decoupling Terminal
38 DIR Logic Input
39 ENABLE Logic Input
40 EXTMODE Logic Input
41 BLANK Logic Input
42 PFD2 Logic Input
43 PFD1 Logic Input
44 GND Power Ground Tab
3936
