PRODUCT DATA SHEET
PAC5223
Power Application Controller®
Multi-Mode Power ManagerTM
Configurable Analog Front EndTM
Application Specific Power DriversTM
ARM® Cortex®-M0 Controller Core
www.active-semi.com
Copyright © 2017 Active-Semi, Inc.
PAC5223
Power Application Controller
TABLE OF CONTENTS
1. General Description........................................................................................................................................... 7
2. PAC Family Applications.................................................................................................................................... 8
3. Product Selection Summary............................................................................................................................... 9
4. Ordering Information.......................................................................................................................................... 9
5. Absolute Maximum Ratings.............................................................................................................................. 10
6. Architectural Block Diagram............................................................................................................................. 11
7. Pin Configuration.............................................................................................................................................. 12
7.1. PAC5223QM............................................................................................................................................ 12
8. Features........................................................................................................................................................... 13
9. Pin Description................................................................................................................................................. 14
10. Multi-Mode Power Manager (MMPM)............................................................................................................ 20
10.1. Features................................................................................................................................................. 20
10.2. Block Diagram........................................................................................................................................ 20
10.3. Functional Description............................................................................................................................ 20
10.3.1. Multi-Mode Switching Supply (MMSS) Controller...........................................................................20
10.3.2. Linear Regulators........................................................................................................................... 22
10.3.3. Power Up Sequence...................................................................................................................... 23
10.3.4. Hibernate Mode.............................................................................................................................. 23
10.3.5. Power and Temperature Monitor.................................................................................................... 24
10.3.6. Voltage Reference.......................................................................................................................... 24
10.4. Electrical Characteristics........................................................................................................................ 25
10.5. Typical Performance Characteristics...................................................................................................... 28
11. Configurable Analog Front End (CAFE)..........................................................................................................29
11.1. Block Diagram........................................................................................................................................ 29
11.2. Functional Description............................................................................................................................ 30
11.2.1. Differential Programmable Gain Amplifier (DA)..............................................................................30
11.2.2. Single-Ended Programmable Gain Amplifier (AMP).......................................................................30
11.2.3. General Purpose Comparator (CMP).............................................................................................30
11.2.4. Phase Comparator (PHC)..............................................................................................................30
11.2.5. Protection Comparator (PCMP)......................................................................................................30
11.2.6. Analog Output Buffer (BUF)............................................................................................................31
11.2.7. Analog Front End I/O (AIO)............................................................................................................ 31
11.2.8. Push Button (PBTN)....................................................................................................................... 31
11.2.9. HP DAC and LP DAC..................................................................................................................... 31
11.2.10. ADC Pre-Multiplexer..................................................................................................................... 32
11.2.11. Configurable Analog Signal Matrix (CASM)..................................................................................32
11.2.12. Configurable Digital Signal Matrix (CDSM)...................................................................................32
11.3. Electrical Characteristics........................................................................................................................ 33
11.4. Typical Performance Characteristics......................................................................................................37
12. Application Specific Power Drivers (ASPD).................................................................................................... 39
12.1. Features................................................................................................................................................. 39
12.2. Block Diagram........................................................................................................................................ 39
12.3. Functional Description............................................................................................................................ 39
12.3.1. Low-Side Gate Driver..................................................................................................................... 40
12.3.2. High-Side Gate Driver.................................................................................................................... 40
12.3.3. High-Side Switching Transients......................................................................................................40
12.3.4. Power Drivers Control.................................................................................................................... 41
12.3.5. Gate Driver Fault Protection...........................................................................................................41
12.4. Electrical Characteristics........................................................................................................................ 42
12.5. Typical Performance Characteristics...................................................................................................... 43
13. ADC with Auto-Sampling Sequencer.............................................................................................................. 45
- 2 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
13.1. Block Diagram........................................................................................................................................ 45
13.2. Functional Description............................................................................................................................ 45
13.2.1. ADC................................................................................................................................................ 45
13.2.2. Auto-Sampling Sequencer............................................................................................................. 45
13.2.3. EMUX Control................................................................................................................................ 46
13.3. Electrical Characteristics........................................................................................................................ 46
14. Memory System............................................................................................................................................. 47
14.1. Features................................................................................................................................................. 47
14.2. Block Diagram........................................................................................................................................ 47
14.3. Functional Description............................................................................................................................ 47
14.3.1. Program and Data FLASH............................................................................................................. 47
14.3.2. SRAM............................................................................................................................................. 47
14.4. Electrical Characteristics........................................................................................................................ 48
15. Clock Control System..................................................................................................................................... 49
15.1. Features................................................................................................................................................. 49
15.2. Block Diagram........................................................................................................................................ 49
15.3. Functional Description............................................................................................................................ 50
15.3.1. Free Running Clock (FRCLK)........................................................................................................ 50
15.3.2. Fast Clock (FCLK).......................................................................................................................... 50
15.3.3. High-Speed Clock (HCLK).............................................................................................................50
15.3.4. Auxiliary Clock (ACLK)................................................................................................................... 50
15.3.5. Clock Gating................................................................................................................................... 50
15.3.6. Ring Oscillator (ROSC).................................................................................................................. 50
15.3.7. Trimmed 4MHz RC Oscillator......................................................................................................... 50
15.3.8. Internal Slow RC Oscillator............................................................................................................ 50
15.3.9. Crystal Oscillator Driver................................................................................................................. 50
15.3.10. External Clock Input..................................................................................................................... 50
15.3.11. PLL............................................................................................................................................... 50
15.4. Electrical Characteristics........................................................................................................................ 51
16. ARM Cortex-M0 Microcontroller Core............................................................................................................ 52
16.1. Features................................................................................................................................................. 52
16.2. Block Diagram........................................................................................................................................ 52
16.3. Functional Description............................................................................................................................ 52
16.4. Electrical Characteristics........................................................................................................................ 53
16.5. Typical Performance Characteristics...................................................................................................... 53
17. I/O Controller.................................................................................................................................................. 54
17.1. Features................................................................................................................................................. 54
17.2. Block Diagram........................................................................................................................................ 54
17.3. Functional Description............................................................................................................................ 54
17.4. Electrical Characteristics........................................................................................................................ 55
18. Serial Interface............................................................................................................................................... 56
18.1. Block Diagram........................................................................................................................................ 56
18.2. Functional Description............................................................................................................................ 56
18.2.1. I2C Controller.................................................................................................................................. 56
18.3. UART Controller..................................................................................................................................... 57
18.4. SPI Controller......................................................................................................................................... 57
18.5. Dynamic Characteristics........................................................................................................................ 58
19. Timers............................................................................................................................................................ 62
19.1. Block Diagram........................................................................................................................................ 62
19.2. Functional Description............................................................................................................................ 63
19.2.1. Timer A........................................................................................................................................... 63
19.2.2. Timer B........................................................................................................................................... 63
19.2.3. Timer C.......................................................................................................................................... 63
19.2.4. Timer D.......................................................................................................................................... 64
- 3 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
19.2.5. Watchdog Timer............................................................................................................................. 64
19.2.6. SOC Bus Watchdog Timer............................................................................................................. 64
19.2.7. Wake-Up Timer.............................................................................................................................. 64
19.2.8. Real-Time Clock............................................................................................................................. 64
20. Thermal Characteristics................................................................................................................................. 65
21. Application Examples..................................................................................................................................... 66
22. Package Outline and Dimensions.................................................................................................................. 67
22.1. TQFN66-48 Package Outline and Dimensions......................................................................................67
23. Change List.................................................................................................................................................... 69
24. Legal Information........................................................................................................................................... 70
- 4 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
LIST OF TABLES
Table 1. Product Selection Summary..................................................................................................................... 9
Table 2. Ordering Information................................................................................................................................. 9
Table 3. Absolute Maximum Ratings....................................................................................................................10
Table 4. Multi-Mode Power Manager and System Pin Description.......................................................................14
Table 5. Configurable Analog Front End Pin Description......................................................................................15
Table 6. Application Specific Power Drivers Pin Description................................................................................16
Table 7. I/O Ports Pin Description........................................................................................................................ 16
Table 8. I/O Ports Pin Description (Continued).....................................................................................................17
Table 9. I/O Ports Pin Description (Continued).....................................................................................................18
Table 10. Multi-Mode Switching Supply Controller Electrical Characteristics.......................................................25
Table 11. Linear Regulators Electrical Characteristics.........................................................................................27
Table 12. Power System Electrical Characteristics..............................................................................................27
Table 13. Differential Programmable Gain Amplifier (DA) Electrical Characteristics............................................33
Table 14. Single-Ended Programmable Gain Amplifier (AMP) Electrical Characteristics.....................................33
Table 15. General Purpose Comparator (CMP) Electrical Characteristics...........................................................34
Table 16. Phase Comparator (PHC) Electrical Characteristics.............................................................................34
Table 17. Protection Comparator (PCMP) Electrical Characteristics....................................................................34
Table 18. Analog Output Buffer (BUF) Electrical Characteristics..........................................................................34
Table 19. Analog Front End I/O (AIO) Electrical Characteristics...........................................................................36
Table 20. Push Button (PBTN) Electrical Characteristics.....................................................................................36
Table 21. HP DAC and LP DAC Electrical Characteristics...................................................................................36
Table 22. Power Driver Resources by Part Numbers...........................................................................................39
Table 23. Microcontroller Port and PWM to Power Driver Mapping......................................................................41
Table 24. Power Driver Propagation Delay..........................................................................................................41
Table 25. Gate Drivers Electrical Characteristics.................................................................................................42
Table 26. ADC and Auto-Sampling Sequencer Electrical Characteristics.............................................................46
Table 27. Memory System Electrical Characteristics............................................................................................48
Table 28. Clock Control System Electrical Characteristics...................................................................................51
Table 29. Microcontroller and Clock Control System Electrical Characteristics....................................................53
Table 30. I/O Controller Electrical Characteristics................................................................................................55
Table 31. Serial Interface Dynamic Characteristics..............................................................................................58
Table 32. I2C Dynamic Characteristics................................................................................................................. 59
Table 33. SPI Dynamic Characteristics................................................................................................................ 61
Table 34. Thermal Characteristics........................................................................................................................ 65
Table 35. Data Sheet Change List........................................................................................................................ 69
- 5 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
LIST OF FIGURES
Figure 1-1. Power Application Controller................................................................................................................ 7
Figure 2-1. Simplified Application Diagram............................................................................................................8
Figure 6-1. Architectural Block Diagram............................................................................................................... 11
Figure 7-1. PAC5223QM Pin Configuration (TQFN66-48 Package)....................................................................12
Figure 9-1. Power Supply Bypass Capacitor Routing..........................................................................................19
Figure 10-1. Multi-Mode Power Manager............................................................................................................. 20
Figure 10-2. Buck Mode....................................................................................................................................... 21
Figure 10-3. SEPIC Mode.................................................................................................................................... 21
Figure 10-4. Flyback Mode................................................................................................................................... 22
Figure 10-5. Linear Regulators............................................................................................................................. 23
Figure 10-6. Power Up Sequence........................................................................................................................ 23
Figure 11-1. Configurable Analog Front End........................................................................................................29
Figure 12-1. Application Specific Power Drivers................................................................................................... 39
Figure 12-2. Typical Gate Driver Connections...................................................................................................... 40
Figure 12-3. High-Side Switching Transients and Optional Circuitry....................................................................41
Figure 13-1. ADC with Auto-Sampling Sequencer................................................................................................45
Figure 14-1. Memory System............................................................................................................................... 47
Figure 15-1. Clock Control System...................................................................................................................... 49
Figure 16-1. ARM Cortex-M0 Microcontroller Core..............................................................................................52
Figure 17-1. I/O controller.................................................................................................................................... 54
Figure 18-1. Serial Interface................................................................................................................................. 56
Figure 18-2. I2C Timing Diagram.......................................................................................................................... 60
Figure 18-3. SPI Timing Diagram......................................................................................................................... 61
Figure 19-1. Timers A, B, C, and D...................................................................................................................... 62
Figure 19-2. SOC Bus Watchdog and Wake-Up Timer........................................................................................63
Figure 19-3. Real-Time Clock and Watchdog Timer.............................................................................................63
Figure 21-1. 3-phase Motor Drive Using PAC5223 (Simplified Diagram).............................................................66
Figure 21-2. Solar LED Street Lighting Using PAC5223 (Simplified Diagram).....................................................66
- 6 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
1. GENERAL DESCRIPTION
The PAC5223 belongs to Active-Semi's broad portfolio of full-featured Power Application Controller® (PAC) products that
are highly optimized for controlling and powering next generation smart energy appliances, devices, and equipment. These
application controllers integrate a 50MHz ARM® Cortex®-M0 32-bit microcontroller core with Active-Semi's proprietary
and patent-pending Multi-Mode Power ManagerTM, Configurable Analog Front EndTM, and Application Specific Power
DriversTM to form the most compact microcontroller-based power and general purpose application systems ranging from
digital power supply to motor control. The PAC5223 microcontroller features up to 32kB of embedded FLASH and 8kB of
SRAM memory, a high-speed 10-bit 1µs analog-to-digital converter (ADC) with dual auto-sampling sequencers,
5V/3.3V I/Os, flexible clock sources, timers, a versatile 14-channel PWM engine, and several serial interfaces.
The Multi-Mode Power Manager (MMPM) provides “all-in-one” efficient power management solution for multiple types
of power sources. It features a configurable multi-mode switching supply controller capable of operating in buck, SEPIC or
AC/DC Flyback mode, and up to four linear regulated voltage supplies. The Application Specific Power Drivers (ASPD)
are high-voltage power drivers designed for each target set of control applications, including half bridge, H-bridge, 3-phase,
intelligent power module (IPM), and general purpose driving. The Configurable Analog Front End (CAFE) comprises
differential programmable gain amplifiers, single-ended programmable gain amplifiers, comparators, digital-to-analog
converters, and I/Os for programmable and inter-connectible signal sampling, feedback amplification, and sensor
monitoring of multiple analog input signals. Together, these modules and microcontroller enable a wide range of compact
applications with highly integrated power management, driving, feedback, and control for DC supply up to 70V and for line
AC supply.
The PAC5223 is available in a 48-pin, 6x6 mm TQFN package. The PAC family includes a range of part numbers
optimized to work with different targeted primary applications.
- 7 - Rev 1.17‒September 20, 2017
Figure 1-1. Power Application Controller
50MHz ARM CORTEX-M0
MICROCONTROLLER CORE & MEMORY
1-cycle 32-bit multiplier,
24-bit RTC, 24-bit WDT, 24-bit SysTick, NVIC,
FLASH & SRAM
50MHz ARM CORTEX-M0
MICROCONTROLLER CORE & MEMORY
1-cycle 32-bit multiplier,
24-bit RTC, 24-bit WDT, 24-bit SysTick, NVIC,
FLASH & SRAM
DATA ACQUISITION
& SEQUENCER
10-bit 1µs ADC,
dual auto-sampling
sequencer
DATA ACQUISITION
& SEQUENCER
10-bit 1µs ADC,
dual auto-sampling
sequencer
PWM ENGINE
4 16-bit timers,
14 channels,
HW dead-time control,
10ns resolution control
PWM ENGINE
4 16-bit timers,
14 channels,
HW dead-time control,
10ns resolution control
SERIAL
INTERFACE
SPI, I2C, UART
SERIAL
INTERFACE
SPI, I2C, UART
APPLICATION
SPECIFIC POWER
DRIVERS
High-side & low-side
gate drivers
APPLICATION
SPECIFIC POWER
DRIVERS
High-side & low-side
gate drivers
MULTI-MODE
POWER MANAGER
AC/DC, DC/DC,
linear regulators
MULTI-MODE
POWER MANAGER
AC/DC, DC/DC,
linear regulators
CONFIGURABLE ANALOG FRONT END
3 Differential PGAs,
4 Single-ended PGAs,
10 Comparators,
2 DACs (10-bit & 8-bit),
Temperature monitor
CONFIGURABLE ANALOG FRONT END
3 Differential PGAs,
4 Single-ended PGAs,
10 Comparators,
2 DACs (10-bit & 8-bit),
Temperature monitor
PAC5223
Power Application Controller
2. PAC FAMILY APPLICATIONS
General purpose high-voltage system controllers
Home appliances
Power tools
Motor controllers
LED lighting controllers
Uninterruptible power supply (UPS)
Solar micro-inverters
Wireless power controllers
Digital power controllers
Industrial applications
- 8 - Rev 1.17‒September 20, 2017
Figure 2-1. Simplified Application Diagram
50MHz ARM CORTEX-M0
MICROCONTROLLER CORE
& MEMORY
DATA
ACQUISITION
&
SEQUENCER
PWM
ENGINE
SERIAL
INTERFACE
APPLICATION
SPECIFIC
POWER
DRIVERS
MULTI-MODE
POWER
MANAGER
CONFIGURABLE
ANALOG FRONT END
M
BUCK/
BOOST/
FLYBACK
°C
SPI/I2C/UART
MONITORING
SIGNALS
PAC52xx
PAC5223
Power Application Controller
3. PRODUCT SELECTION SUMMARY
Table 1. Product Selection Summary
PART
NUMBER
PIN
PKG
POWER
MANAGER
CONFIGURABLE
ANALOG FRONT
END
APPLICATION SPECIFIC
POWER DRIVERS MICROCONTROLLER
PRIMARY
APPLICATIO
N
INPUT VOLTAGE
MULTI-MODESW
DIFF-PGA
PGA
COMPARATOR
DAC
ADC CHANNEL
POWER DRIVER
PWM CHANNEL
FAULTPROTECT
SPEED (MHz)
FLASH (kB)
SRAM (kB)
GPIO
INTERFACE
XTAL
PAC5223
48-pin
6x6
TQFN
5.2-
70V Y3 4 10 2 10 3 LS (1A/1A)
3 HS (1A/1A) 6 Int 50 32 8 25
SPI
I2C
UART
SWD
N3 half bridge,
3-phase control
Notes: DIFF-PGA = differential programmable gain amplifier, GD = gate driver, HS = high-side , LS = low-side, OD = open-drain driver,
PGA = programmable gain amplifier, UHV = ultra-high-voltage.
4. ORDERING INFORMATION
Table 2. Ordering Information
PART NUMBER(1) TEMPERATURE RANGE PACKAGE PINS PACKING
PAC5223QM -40°C to 105°C TQFN66-48 48 + Exposed Pad Tray
(1) See Product Selection Summary for product features for each part number.
- 9 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
5. ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings
(Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device
reliability.)
PARAMETER VALUE UNIT
VHM, DRM to VSSP -0.3 to 72 V
VP to VSS -0.3 to 20 V
CSM, REGO to VSS -0.3 to VP + 0.3 V
VSYS, AIO6/.. to VSS -0.3 to 6 V
VCC33 to VSS -0.3 to 4.1 V
VCC18 to VSS -0.3 to 2.5 V
AIOx/.. (except AIO6/..), VCCIO to VSS -0.3 to VSYS + 0.3 V
PDx/.., PEx/.. to VSS -0.3 to VCCIO + 0.3 V
PCx/.. to VSSA -0.3 to VCC33 + 0.3 V
DRLx to VSSP -0.3 to VP + 0.3 V
DRBx to VSSP -0.3 to 84 V
DRSx to VSSP -6 to 72 V
DRSx allowable offset slew rate (dVDRSx/dt) 5 V/ns
DRBx, DRHx to respective DRSx -0.3 to 20 V
VSSP, VSSA to VSS -0.3 to 0.3 V
VSS, VSYS, DRM, DRLx, DRHx, REGO RMS current(1) 0.2 ARMS
VSSP RMS current(1) 0.4 ARMS
VP RMS current(1) 0.6 ARMS
Operating temperature range -40 to 105 °C
Electrostatic discharge (ESD)
Human body model (JEDEC) 2 kV
Charge device model (JEDEC) 1 kV
Machine model (JEDEC) 200 V
(1) Peak current can be 10 times higher than RMS value for pulses shorter than 10µs.
- 10 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
6. ARCHITECTURAL BLOCK DIAGRAM
- 11 - Rev 1.17‒September 20, 2017
Figure 6-1. Architectural Block Diagram
8kB/4kB
SRAM
32kB/16kB
FLASH
GPIO (15)
SPI
WATCHDOG
RTC
SYSTEM
CONTROL
DEBUG
10-BIT
ADC
DAC (2)
CLOCK
CONTROL
AUTO
SAMPLING
MULTI-
MODE
SWITCHING
SUPPLY
LINEAR
REGU-
LATORS
(4)
DAxP/PCMPx
DAxN
AMPx/CMPx/PHCx
PGA/
CMP (4)
AIO
CONTROL
(10)
AIOx
HSGD (3)
DRLx
DRHx
DRSx
DRBx
LSGD (3)
APPLICATION SPECIFIC
POWER DRIVERS
CONFIGURABLE
ANALOG FRONT END
MULTI-MODE POWER
MANAGER
REGO
VCCIO
VCC18
DIFF-PGA/
PCMP (3)
VHM
DRM
CSM
VP
VCC33
VSYS
VSSP, VSS, VSSA
BUF6
PBTN
DATA ACQUISITION &
SEQUENCER
PCx, PDx, PEx
I2C
UART
SPICSx, SPIMISO,
SPIMOSI, SPICLK
I2CSDA, I2CSCL
UARTRX, UARTTX
nRESET1
PWMAx, PWMBx,
PWMCx, PWMDx PWM /
CC (14)
PWM ENGINE
DEAD TIME
(7)
TIMERS (4)
BRIDGE
SWDIO, SWDCL
PAC5223
Power Application Controller
ADx
ARM
CORTEX-M0
CORE
MUX
AHB/APB
PAC SOC BUS
PAC5223
Power Application Controller
7. PIN CONFIGURATION
7.1. PAC5223QM
- 12 - Rev 1.17‒September 20, 2017
Figure 7-1. PAC5223QM Pin Configuration (TQFN66-48 Package)
1PC4/AD4
2PC3/AD3
3
4
5
PC2/AD2
6
VCC33
7
8
AIO0/DA0N
9
AIO1/DA0P/PCMP0
10
AIO2/DA1N
11
AIO3/DA1P/PCMP1
12
AIO4/DA2N
AIO5/DA2P/PCMP2
AIO6/AMP6/CMP6/BUF6/PBTN
13AIO8/AMP8/CMP8/PHC8
14AIO9/AMP9/CMP9/PHC9
15VSYS
16REGO
17CSM
18VP
19
VHM
20DRM
21DRL0
22
23
DRL1
24
DRL2
DRS3
48
VSS47
46
45
VCCIO
44
PE5/SPICS2/I2CSDA
43
PE4/SPICS1/I2CSCL
42
PE3/SPICS0/nRESET1
41
PE2/SPIMISO/UARTRX
40
PE1/SPIMOSI/UARTTX
39
PE0/SPICLK
38
PD0/SWDIO
37
PD1/SWDCL/EXTCLK
PD2/PWMA3/PWMA4/PWMB0
36 PD3/PWMA5/PWMA7/PWMB1
35
34
PD5/PWMA5/PWMC1
33
PD7/PWMA6/PWMD0
32
31
30
DRB5
29
DRH5
28
DRS5
27
DRB4
26
DRH4
25
DRS4
DRB3
DRH3
PAC5223QM
TQFN66-48
EP (VSS)
VCC18
NC (1)
AIO7/AMP7/CMP7/PHC7
(1) Recommend to leave pin 33 unconnected.
PAC5223
Power Application Controller
8. FEATURES
Proprietary Multi-Mode Power Manager
Multi-mode switching supply controller configurable for high-voltage buck SEPIC or AC/DC Flyback
topologies
DC supply up to 70V or line AC input
4 linear regulators with power and hibernate management
Power and temperature monitor, warning, and fault detection
Proprietary Configurable Analog Front End
10 analog front end I/O pins
3 differential programmable gain amplifiers
4 single-ended programmable gain amplifiers
10 comparators
2 DACs (10-bit and 8-bit)
Proprietary Application Specific Power Drivers
3 low-side and 3 high-side gate drivers with 1A gate driving capability
Configurable delays and fast fault protection
50MHz ARM Cortex-M0 32-bit microcontroller core
Fast single cycle 32-bit x 32-bit multiplier
24-bit SysTick timer
Nested vectored interrupt controller (NVIC) with 20 external interrupts
Wake-up interrupt controller allowing power-saving sleep modes
Clock-gating allowing low power operation
32kB FLASH and 8kB SRAM memory
10-bit 1µs ADC with multi-input/multi-sample control engine
9 ADC inputs including input from configurable analog front end
3.3V I/Os
3 general purpose I/Os with tri-state and dedicated analog input to ADC
True 5V I/Os
12 general purpose I/Os with tri-state, pull-up and pull-down and dedicated I/O supply
Configurable as true 5V or 3.3V I/Os
Flexible clock and PLL from internal 2% oscillator, ring oscillator, external clock, or crystal
9 timing generators
Four 16-bit timers with up to 16 PWM/CC blocks and 7 independent dead-time controllers
24-bit watchdog timer
4s or 8s watchdog timer
24-bit real time clock
24-bit SysTick timer
Wake-up timer for sleep modes from 0.125s to 8s
SPI, I2C, and UART communication interfaces
SWD debug interface with interface disable function
- 13 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
9. PIN DESCRIPTION
Table 4. Multi-Mode Power Manager and System Pin Description
PIN
NAME PIN NUMBER TYPE DESCRIPTION
CSM 17 Analog Switching supply current sense input. Connect to the positive side of the current sense
resistor.
DRM 20 Analog Switching supply driver output. Connect to the base or gate of the external power NPN or
n-channel MOSFET. See PAC User Guide and application notes.
EP (VSS) EP Power Exposed pad. Must be connected to VSS in a star ground configuration. Connect to a large
PCB copper area for power dissipation heat sinking.
NC 33 No connection pin. Don't make any connection on this pin.
VSS 47 Power Ground.
REGO 16 Power System regulator output. Connect to VSYS directly or through an external power-dissipating
resistor.
VCC18 48 Power
Internally generated 1.8V core power supply. Connect a 2.2μF or higher value ceramic
capacitor from VCC18 to VSSA. See Figure 9-1. Power Supply Bypass Capacitor Routing
below.
VCC33 4 Power Internally generated 3.3V power supply. Connect a 2.2μF or higher value ceramic capacitor
from VCC33 to VSSA. See PCB layout note below.
VCCIO 46 Power
Internally generated digital I/O power supply. Connect a 4.7μF or higher value ceramic
capacitor from VCCIO to VSSA. See Figure 9-1. Power Supply Bypass Capacitor Routing
below.
VHM 19 Power
Switching supply controller supply input. Connect a 1μF or higher value ceramic capacitor,
or a 0.1μF ceramic capacitor in parallel with a 10μF or higher electrolytic capacitor from
VHM to VSSP. This pin requires good capacitive bypassing to VSSP
, so the ceramic capacitor
must be connected with a shorter than 10mm trace from the pin. See Figure 9-1. Power
Supply Bypass Capacitor Routing below.
VP 18 Power
Main power supply. Provides power to the power drivers as well as voltage feedback path
for the switching supply. Connect a properly sized supply bypass capacitor in parallel with
a 0.1μF ceramic capacitor from VP pin to VSS for voltage loop stabilization. This pin
requires good capacitive bypassing to VSS, so the ceramic capacitor must be connected with
a shorter than 10mm trace from the pin. See See Figure 9-1. Power Supply Bypass
Capacitor Routing below.
VSYS 15 Power 5V system power supply. Connect a 4.7μF or higher value ceramic capacitor from VSYS to
VSSP
. See Figure 9-1. Power Supply Bypass Capacitor Routing below.
- 14 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 5. Configurable Analog Front End Pin Description
PIN NAME PIN NUMBER FUNCTION TYPE DESCRIPTION
AIO0/DA0N 5
AIO0 I/O Analog front end I/O 0.
DA0N Analog Differential PGA 0 negative input.
AIO1/DA0P/PCMP0 6
AIO1 I/O Analog front end I/O 1.
DA0P Analog Differential PGA 0 positive input.
PCMP0 Analog Protection comparator input 0.
AIO2/DA1N 7
AIO2 I/O Analog front end I/O 2.
DA1N Analog Differential PGA 1 negative input.
AIO3/DA1P/PCMP1 8
AIO3 I/O Analog front end I/O 3.
DA1P Analog Differential PGA 1 positive input.
PCMP1 Analog Protection comparator input 1.
AIO4/DA2N 9
AIO4 I/O Analog front end I/O 4.
DA2N Analog Differential PGA 2 negative input.
AIO5/DA2P/PCMP2 10
AIO5 I/O Analog front end I/O 5.
DA2P Analog Differential PGA 2 positive input.
PCMP2 Analog Protection comparator input 2.
AIO6/AMP6/CMP6/BUF6/PBTN 11
AIO6 I/O Analog front end I/O 6.
AMP6 Analog PGA input 6.
CMP6 Analog Comparator input 6.
BUF6 Analog Buffer output 6.
PBTN Analog Push button input.
AIO7/AMP7/CMP7/PHC7 12
AIO7 I/O Analog front end I/O 7.
AMP7 Analog PGA input 7.
CMP7 Analog Comparator input 7.
PHC7 Analog Phase comparator input 7.
AIO8/AMP8/CMP8/PHC8 13
AIO8 I/O Analog front end I/O 8.
AMP8 Analog PGA input 8.
CMP8 Analog Comparator input 8.
PHC8 Analog Phase comparator input 8.
AIO9/AMP9/CMP9/PHC9 14
AIO9 I/O Analog front end I/O 9.
AMP9 Analog PGA input 9.
CMP9 Analog Comparator input 9.
PHC9 Analog Phase comparator input 9.
- 15 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 6. Application Specific Power Drivers Pin Description
PIN NAME PIN NUMBER TYPE DESCRIPTION
DRB3 26 Analog High-side gate driver bootstrap 3.
DRB4 29 Analog High-side gate driver bootstrap 4.
DRB5 32 Analog High-side gate driver bootstrap 5.
DRH3 25 Analog High-side gate driver 3.
DRH4 28 Analog High-side gate driver 4.
DRH5 31 Analog High-side gate driver 5.
DRL0 21 Analog Low-side gate driver 0.
DRL1 22 Analog Low-side gate driver 1.
DRL2 23 Analog Low-side gate driver 2.
DRS3 24 Analog High-side gate driver source 3.
DRS4 27 Analog High-side gate driver source 4.
DRS5 30 Analog High-side gate driver source 5.
Table 7. I/O Ports Pin Description
PIN NAME PIN NUMBER FUNCTION TYPE DESCRIPTION
PC2/AD2 3
PC2 I/O I/O port C2.
AD2 Analog ADC input 2.
PC3/AD3 2
PC3 I/O I/O port C3.
AD3 Analog ADC input 3.
PC4/AD4 1
PC4 I/O I/O port C4.
AD4 Analog ADC input 4.
- 16 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 8. I/O Ports Pin Description (Continued)
PIN NAME PIN NUMBER FUNCTION TYPE DESCRIPTION
PD0/SWDIO 39
PD0 I/O I/O port D0.
SWDIO I/O Serial wire debug I/O.
PD1/SWDCL/EXTCLK 38
PD1 I/O I/O port D1.
SWDCL I Serial wire debug clock.
EXTCLK I External clock.
PD2/PWMA3/PWMA4/PWMB0 37
PD2 I/O I/O port D2.
PWMA3 I/O Timer A PWM/capture 3.
PWMA4 I/O Timer A PWM/capture 4.
PWMB0 I/O Timer B PWM/capture 0.
PD3/PWMA5/PWMA7/PWMB1 36
PD3 I/O I/O port D3.
PWMA5 I/O Timer A PWM/capture 5.
PWMA7 I/O Timer A PWM/capture 7.
PWMB1 I/O Timer B PWM/capture 1.
PD5/PWMA5/PWMC1 35
PD5 I/O I/O port D5.
PWMA5 I/O Timer A PWM/capture 5.
PWMC1 I/O Timer C PWM/capture 1.
PD7/PWMA6/PWMD0 34
PD7 I/O I/O port D7.
PWMA6 I/O Timer A PWM/capture 6.
PWMD0 I/O Timer D PWM/capture 0.
PE0/SPICLK 40
PE0 I/O I/O port E0.
SPICLK I/O SPI clock.
PE1/SPIMOSI/UARTTX 41
PE1 I/O I/O port E1.
SPIMOSI I/O SPI master out slave in (MOSI).
UARTTX O UART transmit output.
PE2/SPIMISO/UARTRX 42
PE2 I/O I/O port E2.
SPIMISO I/O SPI master in slave out (MISO).
UARTRX I UART receive input.
- 17 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 9. I/O Ports Pin Description (Continued)
PIN NAME PIN NUMBER FUNCTION TYPE DESCRIPTION
PE3/SPICS0/nRESET1 43
PE3 I/O I/O port E3.
SPICS0 O SPI chip select 0.
nRESET1 I Reset input 1 (active low).
PE4/SPICS1/I2CSCL 44
PE4 I/O I/O port E4.
SPICS1 O SPI chip select 1.
I2CSCL I/O I2C clock.
PE5/SPICS2/I2CSDA 45
PE5 I/O I/O port E5.
SPICS2 O SPI chip select 2.
I2CSDA I/O I2C data.
- 18 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
- 19 - Rev 1.17‒September 20, 2017
Figure 9-1. Power Supply Bypass Capacitor Routing
PAC5223
Power Application Controller
10. MULTI-MODE POWER MANAGER (MMPM)
10.1. Features
Multi-mode switching supply controller configurable as high voltage buck, SEPIC or AC/DC Flyback
DC supply up to 70V or line AC input
4 linear regulators with power and hibernate management
Power and temperature monitor, warning, and fault detection
10.2. Block Diagram
10.3. Functional Description
The Multi-Mode Power Manager (Figure 10-1) is optimized to efficiently provide "all-in-one" power management required
by the PAC and associated application circuitry from a wide range of input power sources. It incorporates a dedicated multi-
mode switching supply (MMSS) controller operable as a buck, SEPIC or AC/DC flyback converter to efficiently convert
power from a DC input source to generate a main supply output VP. Four linear regulators provide VSYS, VCCIO, VCC33, and
VCC18 supplies for 5V system, 5V or 3.3V I/O, 3.3V mixed signal, and 1.8V microcontroller core circuitry. The power
manager also handles system functions including internal reference generation, timers, hibernate mode management, and
power and temperature monitoring.
10.3.1. Multi-Mode Switching Supply (MMSS) Controller
The MMSS controller drives an external power transistor for pulse-width modulation switching of an inductor or
transformer for power conversion. The DRM output drives the gate of the n-channel MOSFET or the base of the NPN
between the VHM on state and VSSP off state at proper duty cycle and switching frequency to ensure that the main supply
voltage VP is regulated. The VP regulation voltage is initially set to 15V during start up, and can be reconfigured to be 5V,
- 20 - Rev 1.17‒September 20, 2017
Figure 10-1. Multi-Mode Power Manager
IMOD
DAC
CSM
CURR
SENSE
DRM
DRIVER
MULTI-MODE POWER MANAGER
VHM
VSSP
PWM
LOGIC
ERROR
AMP
LINEAR
REG
VCCIO
LINEAR
REG
VCC33
LINEAR
REG
VCC18
SYSTEM
SUPPLY
REG
VOLTAGE
SETTING
VP
REGO
VSYS
COMP &
CURR LIMIT CLAMP
ERROR
COMP
MULTI-MODE SWITCHING
SUPPLY CONTROLLER
POWER
OK & OVP
MUX
MUX
START UP &
MODE CTRL
1.2V
HIBERNATE
2.5V VREF
TIMERS POWER
& TEMP
MON
VSSA
VSS
MUX
VMON
VTHREF VTEMP
PAC5223
Power Application Controller
9V, or 12V by the microcontroller after initialization. When VP is lower than the target regulation voltage, the internal
feedback control circuitry causes the inductor current to increase to raise VP. Conversely, when VP is higher than the
regulation voltage, the feedback loop control causes the inductor current to decrease to lower VP. The feedback loop is
internally stabilized. The output current capability of the switching supply is determined by the external current sense
resistor. In the high-side current sense buck or SEPIC mode, the inductor current signal is sensed differentially between the
CSM pin and VP, and has a peak current limit threshold of 0.26V. In the low-side current sense flyback mode, the inductor
current signal is sensed differentially between the CSM pin and VSSP, and has a peak current limit threshold of 1V.
The MMSS controller is flexible and configurable as a buck, SEPIC or an AC/DC converter. Input sources include battery
supply for buck mode (Figure 10-2) or SEPIC mode (Figure 10-3), and AC Line Supply for AC/DC Flyback (Figure 10-4).
The MMSS controller operational mode is determined by external configuration and register settings from the
microcontroller after power up. It can operate in either high-side or low-side current sense mode, and does not require
external feedback loop compensation circuitry. For optional extended application range, the MMSS also incorporates
additional digital control by the microcontroller to add accurate computations for outer feedback loop control such as power
factor correction and accurate current control.
- 21 - Rev 1.17‒September 20, 2017
Figure 10-2. Buck Mode
VHM
DRM
CSM
VP
PAC52xx
VP (15V default)
VIN VHM
DRM
CSM
VP
PAC5223
VIN
Figure 10-3. SEPIC Mode
PAC5223
VHM
DRM
CSM
VP
VP (9V/12V/15V)
VIN
PAC5223
Power Application Controller
The MMSS detects and selects between high-side and low-side mode during start up based on the placement of the current
sense resistor and the CSM pin voltage. It employs a safe start up mode with a 9.5kHz switching frequency until VP exceeds
4.3V under-voltage-lockout threshold, then transitions to the 45kHz default switching frequency for at least 6ms to bring VP
close to the target voltage, before enabling the linear regulators. Any extra load should only be applied after the supplies are
available and the microprocessor has initialized. The switching frequency can be reconfigured by the microprocessor to be
181kHz to 500kHz in the high switching frequency mode for battery-based applications, and to be 45kHz to 125kHz in the
low switching frequency mode for AC applications. Upon initialization, the microcontroller must reconfigure the MMSS to
the desired settings for VP regulation voltage, switching mode, switching frequency, and VHM clamp. Refer to the PAC
application notes and user guide for MMSS controller design and programming.
If a stable external 5V to 18V power source is available, it can power the VP main supply and all the linear regulators
directly without requiring the MMSS controller to operate. In such applications, VHM can be connected directly to VP and
the microcontroller should disable the MMSS upon initialization to reduce power loss.
10.3.2. Linear Regulators
The MMPM includes up to four linear regulators. The system supply regulator is a medium voltage regulator that takes the
VP supply and sources up to 200mA at REGO until VSYS, externally coupled to REGO, reaches 5V. This allows a properly
rated external resistor to be connected from REGO to VSYS to close the current loop and offload power dissipation between
VP and VSYS. Once VSYS is above 4V, the three additional 40mA linear regulators for VCCIO, VCC33, and VCC18 supplies
sequentially power up. Figure 10-5 shows typical circuit connections for the linear regulators. For 5V I/O systems, short the
VCCIO pin to VSYS to bypass the VCCIO regulator. For 3.3V I/O systems, the VCCIO regulator generates 3.3V. The VCC33 and
VCC18 regulators generate 3.3V and 1.8V, respectively. When VSYS, VCCIO, VCC33, and VCC18 are all above their respective
power good thresholds, and the configurable power on reset duration has expired, the microcontroller is initialized.
- 22 - Rev 1.17‒September 20, 2017
Figure 10-4. Flyback Mode
PAC5223
VHM
DRM
CSM
VP
VP (15V default)
VAC (120V/230V)
PAC5223
Power Application Controller
10.3.3. Power Up Sequence
The MMPM follows a typical power up sequence as in the Figure 10-6 below. A typical sequence begins with input power
supply being applied, followed by the safe start up and start up durations to bring the switching supply output VP to 15V,
before the linear regulators are enabled. When all the supplies are ready, the internal clocks become available, and the
microcontroller starts executing from the program memory. During initialization, the microcontroller can reconfigure the
switching supply to a different VP regulation voltage such as 15V and to an appropriate switching frequency and switching
mode. The total loading on the switching supply must be kept below 25% of the maximum output current until after the
reconfiguration of the switching supply is complete. For AC input supply applications, the start up sequence includes an
additional charging time for VHM depending on the start-up resistor and capacitor values.
10.3.4. Hibernate Mode
The IC can go into an ultra-low power hibernate mode via the microcontroller firmware or via the optional push button
(PBTN, see Push Button description in Configurable Analog Front End). In hibernate mode, only a minimal amount
(typically 18µA) of current is used by VHM, and the MMSS controller and all internal regulators are shut down to eliminate
power drain from the output supplies. The system exits hibernate mode after a wake-up timer duration (configurable from
- 23 - Rev 1.17‒September 20, 2017
Figure 10-5. Linear Regulators
VP
REGO
PAC5223
VSYS & VCCIO (5V)
VP (15V typical)
VSYS
VCCIO
VCC33
VCC18
VSS
VSSA (1)
4.7µF
1µF1µF
5V I/O connection shown.
Connect instead to a 4.7µF
capacitor for 3.3V I/O.
(1)
Figure 10-6. Power Up Sequence
VSYS and VCCIO (5V)
VP (5V/9V/12V/15V)
VCC33 (3.3V)
VCC18 (1.8V)
Safe start up
VIN or VHM
7.4V
4.3V
Start up
4V
87%
Microcontroller
initializing
Power-on-
reset delay
6ms SOC.PWRCFG.TRESET + 10.5 ms
(default: 32ms + 10.5ms = 42.5ms)
Microcontroller
reset
VSYS and VCCIO
VP
VCC33
VCC18
Internal clocks
VIN or VHM
Power on reset
Regulators
enabled
VP (start up default)
Reconfiguration by firmware System operation
Microcontroller
executing
PAC5223
Power Application Controller
125ms to 8s or infinite) has expired or, if push button enabled, after an additional push button event has been detected.
When exiting the hibernate mode, the power manager goes through the start up cycle and the microcontroller is
reinitialized. Only the persistent power manager status bits (resets and faults) are retained during hibernation.
10.3.5. Power and Temperature Monitor
Whenever any of the VSYS, VCCIO, VCC33, or VCC18 power supplies falls below their respective power good threshold voltage, a
fault event is detected and the microcontroller is reset. The microcontroller stays in the reset state until VSYS, VCCIO, VCC33,
and VCC18 supply rails are all good again and the reset time has expired. A microcontroller reset can also be initiated by a
maskable temperature fault event that occurs when the IC temperature reaches 170°C. The fault status bits are persistent
during reset, and can be read by the microcontroller upon re-initialization to determine the cause of previous reset.
A power monitoring signal VMON is provided onto the ADC pre-multiplexer for monitoring various internal power supplies.
VMON can be set to be VCC18, 0.4•VCC33, 0.4•VCCIO, 0.4•VSYS, 0.1•VREGO, 0.1•VP, 0.0333•VHM, or the internal compensation
voltage VCOMP for switching supply power monitoring.
For power and temperature warning, a VP low event at 77% of the regulation voltage and an IC temperature warning event
at 140°C are provided as maskable interrupts to the microcontroller. These warnings allow the microcontroller to safely
power down the system.
In addition to the temperature warning interrupt and fault reset, a temperature monitor signal VTEMP = 1.5 + 5.04e-3 • (T -
25°C) (V) is provided onto the ADC pre-multiplexer for IC temperature measurement.
10.3.6. Voltage Reference
The reference block includes a 2.5V high precision reference voltage that provides the 2.5V reference voltage for the ADC,
the DACs, and the 4-level programmable threshold voltage VTHREF (0.1V, 0.2V, 0.5V, and 1.25V).
- 24 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
10.4. Electrical Characteristics
Table 10. Multi-Mode Switching Supply Controller Electrical Characteristics
(VHM = 24V, VP = 12V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Input Supply (VHM)
IHIB;VHM VHM hibernate mode supply current VHM, hibernate mode 18 36 µA
ISU;VHM VHM start up supply current VHM < VUVLOR;VHM 75 120 µA
IOP;VHM VHM operating supply current DRM floating 0.3 0.5 mA
VOP:VHM VHM operating voltage range 5.0 70 V
VUVLOR;VHM VHM under-voltage lockout rising 6.1 7.4 8 V
VUVLOF;VHM VHM under-voltage lockout falling 5.1 6.6 7 V
VCLAMP;VHM VHM clamp voltage Clamp enabled, sink current = 100µA 14.5 16.9 19.5 V
ICLAMP;VHM VHM clamp sink current limit Clamp enabled 4 mA
Output Supply and Feedback (VP)
VREG;VP VP output regulation voltage Programmable to 5V, 9V, 12V, or 15V
Load = 0 to 500mA -7 -1 5 %
kPOK;VP VP power OK threshold VP rising, hysteresis = 10% 82 87 92 %
kOVP;VP VP over voltage protection threshold VP rising, hysteresis = 15%
MMPM Controller enabled 136 %
Switching Control
fSWMACC;DRM Switching frequency accuracy -10 10 %
fSWM;DRM Switching frequency programmable range
High frequency mode, 8 settings 181 500
Low frequency mode, 8 settings 45 125
kHz
fSSU;DRM Safe start up switching frequency 9.5 kHz
tONMIN;DRM Minimum on time 440 ns
tOFFMIN;DRM Minimum off time
Low duty-cycle & Low-frequency mode
Low duty-cycle & High frequency mode
High duty-cycle mode
25
440
820
%
nS
nS
- 25 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Current Sense (CSM Pin)
VDET;CSM CSM mode detection threshold Rising, hysteresis = 50mV 0.40 0.55 0.69 V
VHSLIM;CSM High-side current limit threshold 181kHz, duty = 25%, relative to VP 0.17 0.26 0.35 V
VLSLIM;CSM Low-side current limit threshold 45kHz, duty = 25% 0.7 1 1.48 V
tBLANK;CSM Current sense blanking time 200 ns
VPROT;CSM
Low-side abnormal current sense
protection threshold
VP < 4.3V 0.8
VP > 4.3V 1.9
V
Gate Driver Output (DRM Pin)
VOH;DRM High-level output voltage IDRM = -20mA VHM−1 V
VOL;DRM Low-level output voltage IDRM = 20mA 0.6 V
IOH;DRM High-level output source current VDRM = VHM - 5V -0.30 A
IOL;DRM Low-level output sink current VDRM = 5V 0.50 A
tPD;DRM Strong pull down pulse width High-side current sense mode 240 ns
- 26 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 11. Linear Regulators Electrical Characteristics
(VP = 12V and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
VOP;VP VP operating voltage range 4.7 18 V
VUVLO;VP VP under-voltage-lockout threshold VP rising, hysteresis = 0.2V 4 4.3 4.7 V
IQ;VP VP quiescent supply current Power manager only, including IQ;VSYS 400 750 µA
IQ;VSYS VSYS quiescent supply current VCCIO, VCC33, and VCC18 regulators only 350 600 µA
VSYS VSYS output voltage Load = 10µA to 200mA 4.8 5 5.18 V
VCCIO VCCIO output voltage Load = 10mA
VCCIO shorted to VSYS VSYS
V
VCCIO from regulator 3.152 3.3 3.398
VCC33 VCC33 output voltage Load = 10mA 3.185 3.3 3.415 V
VCC18 VCC18 output voltage Load = 10mA 1.834 1.9 1.979 V
ILIM;VSYS VSYS regulator current limit 220 330 mA
ILIM;VCCIO VCCIO regulator current limit 45 80 mA
ILIM;VCC33 VCC33 regulator current limit 45 80 mA
ILIM;VCC18 VCC18 regulator current limit 45 80 mA
kSCFB Short circuit current fold back 50 %
VDO;VSYS VSYS dropout voltage VP =5V, ISYS=100mA 350 680 mV
VUVLO;VSYS VSYS under-voltage-lockout threshold VSYS rising, hysteresis = 0.2V 3.5 4 4.4 V
kPOKIO VCCIO Power OK threshold VCCIO rising, hysteresis = 10% 75 82 89 %
kPOK33 VCC33 Power OK threshold VCC33 rising, hysteresis = 10% 71 78 85 %
kPOK18 VCC18 Power OK threshold VCC18 falling, hysteresis = 10% 58 66 74 %
Table 12. Power System Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
VREF Reference voltage
TA = 25°C 2.487 2.5 2.513
V
TA = -40°C to 105°C 2.463 2.5 2.537
kMON
Power monitoring voltage (VMON)
coefficient
VCC18 0.92 1 1.02
V/V
VSYS, VCCIO, VCC33 0.36 0.4 0.43
VP
, VREGO 0.09 0.1 0.11
VHM 0.03 0.0333 0.038
VTEMP Temperature monitor voltage at 25°C TA = 25°C, at ADC 1.475 1.5 1.540 V
kTEMP Temperature monitor coefficient At ADC 5.04 mV/K
TWARN Over-temperature warning threshold Hysteresis = 10°C 140 °C
TFAULT Over-temperature fault threshold Hysteresis = 10°C 170 °C
- 27 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
10.5. Typical Performance Characteristics
(VP = 12V and TA = 25°C unless otherwise specified.)
- 28 - Rev 1.17‒September 20, 2017
0 0.1 0.2 0.3 0.4 0.5
100
90
80
70
60
50
40
30
20
10
0
PACMMPM-001
Efficiency (%)
Buck Mode Efficiency
vs. Output Current
VIN = 48V
VIN = 24V
Output Current (A)
VP = 12V,
fSW;DRM = 181kHz
0 0.5 1 1.5 2 2.5
100
90
80
70
60
50
40
30
20
10
0
PACMMPM-003
Efficiency (%)
AC/DC Flyback Mode Efficiency
vs. Output Current
VAC = 230V
VAC = 120V
Output Current (A)
VP = 12V,
fSW;DRM = 45kHz
-40 0 40 80 120
80
70
60
50
40
30
20
10
0
PACMMPM-005
On Resistance (Ω)
DRM Driver Output
On Resistance vs. Temperature
Temperature (°C)
Pull up
Pull down
20 30 40 50 60
50
40
30
20
10
0
PACMMPM-002
Input Current (µA)
Buck Mode Hibernate Input Current
vs. Input Voltage
Input Voltage (V)
90 135 180 225 270
0.30
0.25
0.20
0.15
0.10
0.05
0
PACMMPM-004
Input Power (W)
AC/DC Flyback Mode Standby Power
vs. Input Voltage
Input Voltage (VAC)
VP = 12V,
all regulators on
RSTARTUP = 1MΩ
RSTARTUP = 2MΩ
PAC5223
Power Application Controller
11. CONFIGURABLE ANALOG FRONT END (CAFE)
11.1. Block Diagram
- 29 - Rev 1.17‒September 20, 2017
Figure 11-1. Configurable Analog Front End
AMPx
CONFIGURABLE ANALOG FRONT END
MUX
DAxP/PCMPx
DAxN
CMPx
MUX
MUX
S/H
MUX
PROTECT
LP DAC
HP DAC
OFFSET
CAL
AIOx
MUX
I/O
CONTROL
ADC MUX
ADC PRE-MUX
DINx
DINx
CONFIGURABLE DIGITAL SIGNAL MATRIX
CONFIGURABLE ANALOG SIGNAL MATRIX
PHCx
MUX
MUX
DINx
PHASE
REF
INT2/POS
PHASE
POS
PR1, PR2
PHASE COMPARATOR
COMPARATOR
AFE I/O
PGA
DIFF-PGA & PCOMP
PBTN
BUF6
PUSH
BUTTON
MUX
VSYS
INT1
VTEMP
, VMON, VREF/2
VSYS
(except AIO6)
3V
VTHREF
PAC5223
Power Application Controller
11.2. Functional Description
The device includes a Configurable Analog Front End (CAFE, Figure 11-1) accessible through up to 10 analog and I/O
pins. These pins can be configured to form flexible interconnected circuitry made up of up to 3 differential programmable
gain amplifiers, 4 single-ended programmable gain amplifiers, 4 general purpose comparators, 3 phase comparators, 10
protection comparators, and one buffer output. These pins can also be programmed as analog feed-through pins, or as
analog front end I/O pins that can function as digital inputs or digital open-drain outputs. The PAC proprietary configurable
analog signal matrix (CASM) and configurable digital signal matrix (CDSM) allow real time asynchronous analog and
digital signals to be routed in flexible circuit connections for different applications. A push button function is provided for
optional push button on, hibernate, and off power management function.
11.2.1. Differential Programmable Gain Amplifier (DA)
The DAxP and DAxN pin pair are positive and negative inputs, respectively, to a differential programmable gain amplifier.
The differential gain can be programmable to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x for zero ohm signal source impedance.
The differential programmable gain amplifier has -0.3V to 3.5V input common mode range, and its output can be
configured for routing directly to the ADC pre-multiplexer, or through a sample-and-hold circuit synchronized with the
ADC auto-sampling mechanism. Each differential amplifier is accompanied by offset calibration circuitry, and two
protection comparators for protection event monitoring. The programmable gain differential amplifier is optimized for use
with signal source impedance lower than 500Ω and with matched source impedance on both positive and negative
inputs for minimal offset. The effective gain is scaled by 13.5k / (13.5k + RSOURCE), where RSOURCE is the matched
source impedance of each input.
11.2.2. Single-Ended Programmable Gain Amplifier (AMP)
Each AMPx input goes to a single-ended programmable gain amplifier with signal relative to VSSA. The amplifier gain can
be programmed to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x, or as analog feed-through. The programmable gain amplifier output
is routed via a multiplexer to the configurable analog signal matrix CASM.
11.2.3. General Purpose Comparator (CMP)
The general purpose comparator takes the CMPx input and compares it to either the programmable threshold voltage
(VTHREF) or a signal from the configurable analog signal matrix CASM. The comparator has 0V to VSYS input common mode
range, and its polarity-selectable output is routed via a multiplexer to either a data input bit or the configurable digital signal
matrix CDSM. Each general purpose comparator has two mask bits to prevent or allow rising or falling edge of its output to
trigger second microcontroller interrupt INT2, where INT2 can be configured to active protection event PR1.
11.2.4. Phase Comparator (PHC)
The phase comparator takes the PHCx input and compares it to either the programmable threshold voltage (VTHREF) or a
signal from the configurable analog signal matrix CASM. The comparison signal can be set to a phase reference signal
generated by averaging the PHCx input voltages. In a three-phase motor control application, the phase reference signal acts
as a virtual center tap for BEMF detection. The PHCx inputs are optionally fed through to the CASM. The phase
comparator has 0V to VSYS input common mode range, and its polarity-selectable output is routed to a data input bit and to
the phase/position multiplexer synchronized with the auto-sampling sequencers.
11.2.5. Protection Comparator (PCMP)
Two protection comparators are provided in association with each differential programmable gain amplifier, with outputs
available to trigger protection events and accessible as read-back output bits. The high-speed protection (HP) comparator
compares the PCMPx pin to the 8-bit HP DAC output voltage, with full scale voltage of 2.5V. The limit protection (LP)
comparator compares the differential programmable gain amplifier output to the 10-bit LP DAC output voltage, with full
scale voltage of 2.5V.
Each protection comparator has a mask bit to prevent or allow it to trigger the main microcontroller interrupt INT1. Each
protection comparator also has one mask bit to prevent or allow it to activate protection event PR1, and another mask bit to
prevent or allow it to activate protection event PR2. These two protection events can be used directly by protection circuitry
in the Application Specific Power Drivers (ASPD) to protect devices being driven.
- 30 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
11.2.6. Analog Output Buffer (BUF)
A subset of the signals from the configurable analog signal matrix CASM can be multiplexed to the BUF6 pin for external
use. The buffer offset voltage can be minimized with the built-in swap function.
11.2.7. Analog Front End I/O (AIO)
Up to 10 AIOx pins are available in the device. In the analog front end I/O mode, the pin can be configured to be a digital
input or digital open-drain output. The AIOx input or output signal can be set to a data input or output register bit, or
multiplexed to one of the signals in the configurable digital signal matrix CDSM. The signal can be set to active high
(default) or active low, with VSYS supply rail. Where AIO6,7,8,9 supports microcontroller interrupt for external signals. Each
has two mask bits to prevent or allow rising or falling edge of its corresponding digital input to trigger second
microcontroller interrupt INT2.
11.2.8. Push Button (PBTN)
The push button PBTN, when enabled, can be used by the microcontroller to detect a user active-low push button event and
to put the system into an ultra-low-power hibernate mode. Once the system is in hibernate mode, PBTN can be used to
wake up the system. In addition, PBTN can also be used as a hardware reset for the microcontroller when it is held low for
longer than 8s during normal operation. The PBTN input is active low and has a 55kΩ pull-up resistor to 3V.
11.2.9. HP DAC and LP DAC
The 8-bit HP DAC can be used as the comparison voltage for the high-speed protection (HP) comparators, or routed for
general purpose use via the AB2 signal in the CASM. The HP DAC output full scale voltage is 2.5V.
The 10-bit LP DAC can be used as the comparison voltage for the limit protection (LP) comparators, or routed for general
purpose use via the AB3 signal in the CASM. The LP DAC output full scale voltage is 2.5V.
- 31 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
11.2.10. ADC Pre-Multiplexer
The ADC pre-multiplexer is a 16-to-1 multiplexer that selects between the 3 differential programmable gain amplifier
outputs, AB1 through AB9, temperature monitor signal (VTEMP), power monitor signal (VMON), and offset calibration
reference (VREF / 2). The ADC pre-multiplexer can be directly controlled or automatically scanned by the auto-sampling
sequencer.
When the ADC pre-multiplexer is automatically scanned, the unbuffered or sensitive signals should be masked by setting
appropriate register bits.
11.2.11. Configurable Analog Signal Matrix (CASM)
The CASM has 9 general purpose analog signals labeled AB1 through AB9 that can be used for:
Routing the single-ended programmable gain amplifier or analog feed-through output to AB1 through AB9
Routing an analog signal via AB1, AB2, or AB3 to the negative input of a general purpose comparator or
phase comparator
Routing the 8-bit HP DAC output to AB2
Routing the 10-bit LP DAC output to AB3
Routing analog signals via AB1 through AB12 to the ADC pre-multiplexer
Routing phase comparator feed-through signals to AB7, AB8, and AB9, and averaged voltage to AB1
11.2.12. Configurable Digital Signal Matrix (CDSM)
The CDSM has 7 general purpose bi-directional digital signals labeled DB1 through DB7 that can be used for:
Routing the AIOx input to or output signals from DB1 through DB7
Routing the general purpose comparator output signals to DB1 through DB7
- 32 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
11.3. Electrical Characteristics
Table 13. Differential Programmable Gain Amplifier (DA) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
PARAMETER CONDITIONS MIN TYP MAX UNI
T
ICC;DA Operating supply current Each enabled amplifier 150 300 µA
VICMR;DA Input common mode range -0.3 3.5 V
VOLR;DA Output linear range 0.1 3.5 V
VOS;DA Input offset voltage Gain = 48x, VDAxP= VDAxN = 0V, TA = 25°C -8 8 mV
A
VZI;DA
Differential amplifier gain
(zero ohm source impedance)
Gain = 1x
-2%
1
2%
Gain = 2x 2
Gain = 4x 4
Gain = 8x, VDAxP = 125mV, VDAxN = 0V,
TA = 25°C 8
Gain = 16x 16
Gain = 32x 32
Gain = 48x 48
kCMRR;DA Common mode rejection ratio Gain = 8x, VDAxP= VDAxN = 0V, TA = 25°C 55 dB
RINDIF;DA Differential input impedance 27 kΩ
Slew rate (1) Gain = 8x 7 10 V/µs
tST;DA Settling time (1) To 1% of final value 200 400 ns
(1) Guaranteed by design.
Table 14. Single-Ended Programmable Gain Amplifier (AMP) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
ICC;AMP Operating supply current Each enabled amplifier 80 140 µA
VOLR;AMP Output linear range 0.1 3.5 V
VOS;AMP Input offset voltage Gain = 1x, TA = 25°C, V
AMPX = 2.5V -10 10 mV
A
V;AMP Amplifier gain
Gain = 1x
-2%
1
2%
Gain = 2x 2
Gain = 4x 4
Gain = 8x, V
AMPx = 125mV, TA = 25°C 8
Gain = 16x 16
Gain = 32x 32
Gain = 48x 48
IIN;AMP Input current 0 1 µA
Slew rate (1) Gain = 8x 8 12 V/µs
tST;AMP Settling time (1) To 1% of final value 150 300 ns
(1) Guaranteed by design.
- 33 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 15. General Purpose Comparator (CMP) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
ICC;CMP Operating supply current Each enabled comparator 35 110 µA
VICMR;CMP Input common mode range 0 VSYS V
VOS;CMP Input offset voltage VCMPx = 2.5V, TA = 25°C -10 10 mV
VHYS;CMP Hysteresis 23 mV
IIN;CMP Input current 0 1 µA
tDEL;CMP Comparator delay (1) 0.1 µs
(1) Guaranteed by design.
Table 16. Phase Comparator (PHC) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
ICC;PHC Operating supply current Each enabled comparator 35 110 µA
VICMR;PHC Input common mode range 0 VSYS V
VOS;PHC Input offset voltage VPHCx = 2.5V, TA = 25°C -10 10 mV
VHYS;PHC Hysteresis 23 mV
IIN;PHC Input current 0 1 µA
tDEL;PHC Comparator delay (1) 0.1 µs
(1) Guaranteed by design.
Table 17. Protection Comparator (PCMP) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
ICC;PCMP Operating supply current Each enabled comparator 35 100 µA
VICMR;PCMP Input common mode range 0.3 VSYS -1 V
VOS;PCMP Input offset voltage VPCMPx = 2.5V, TA = 25°C -10 10 mV
VHYS;PCMP Hysteresis 20 mV
IIN;PCMP Input current 0 1 µA
tDEL;PCMP Comparator delay (1) 0.1 µs
(1) Guaranteed by design.
Table 18. Analog Output Buffer (BUF) Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
ICC;BUF Operating supply current No load 35 100 µA
VICMR;BUF Input common mode range 0.05 3.5 V
VOLR;AMP Output linear range 0.1 3.5 V
VOS;BUF Offset voltage VBUF = 2.5V, TA = 25°C -18 18 mV
IOMAX Maximum output current CL = 0.1nF 0.8 1.3 mA
- 34 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
- 35 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 19. Analog Front End I/O (AIO) Electrical Characteristics
(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
V
AIO Pin voltage range 0 5 V
VIH;AIO High-level input voltage 2.2 V
VIL;AIO Low-level input voltage 0.8 V
RPD;AIO Pull-down resistance Input mode 0.5 1 1.8 MΩ
VOL;AIO Low-level output voltage IAIOx = 7mA, open-drain output mode 0.4 V
IOL;AIO Low-level output sink current V
AIOx = 0.4V, open-drain output mode 6 14 mA
ILK;AIO High-level output leakage current V
AIOx = 5V, open-drain output mode 0 10 μA
Table 20. Push Button (PBTN) Electrical Characteristics
(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
VI;PBTN Input voltage range 0 5 V
VIH;PBTN High-level input voltage 2 V
VIL;PBTN Low-level input voltage 0.35 V
RPU;PBTN Pull-up resistance To 3V, push button input mode 40 55 95 kΩ
Table 21. HP DAC and LP DAC Electrical Characteristics
(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
VDACREF DAC reference voltage
TA = 25°C 2.480 2.5 2.520
V
TA = -40°C to 105°C 2.453 2.5 2.547
HP 8-bit DAC INL(1) -1 1 LSB
HP 8-bit DAC DNL(1) -0.5 0.5 LSB
LP 10-bit DAC INL(1) -2 2 LSB
LP 10-bit DAC DNL(1) -1 1 LSB
(1) Guaranteed by design and characterization.
- 36 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
11.4. Typical Performance Characteristics
(VSYS = 5V and TA = 25°C unless otherwise specified.)
- 37 - Rev 1.17‒September 20, 2017
0 500 1000 1500 2000 2500
5000
4000
3000
2000
1000
0
PACCAFE-001
Output Voltage (mV)
Differential PGA (DAx) Gain Characteristics
at 1x, 2x, 4x, and 8x Settings
Differential Input Voltage (mV)
1x
2x
4x
8x
0 50 100 150 200 250
PACCAFE-002
Output Voltage (mV)
Differential PGA (DAx) Gain Characteristics
at 16x, 32x, and 48x Settings
Differential Input Voltage (mV)
16x
5000
4000
3000
2000
1000
0
32x
48x
0 100h 200h 300h 3FFh
2500
2000
1500
1000
500
0
PACCAFE-005
Output Voltage (mV)
LP DAC Output Voltage vs. Input Code
Input Code
0 500 1000 1500 2000 2500
PACCAFE-003
Output Voltage (mV)
PGA (AMPx) Gain Characteristics
at 1x, 2x, 4x, and 8x Settings
Input Voltage (mV)
5000
4000
3000
2000
1000
0
1x
2x
4x
8x
0 40h 80h C0h FFh
2500
2000
1500
1000
500
0
PACCAFE-006
Output Voltage (mV)
HP DAC Output Voltage vs. Input Code
Input Code
PACCAFE-004
Output Voltage (mV)
PGA (AMPx) Gain Characteristics
at 16x, 32x, and 48x Settings
Input Voltage (mV)
0 50 100 150 200 250
16x
32x
48x
5000
4000
3000
2000
1000
0
PAC5223
Power Application Controller
- 38 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
12. APPLICATION SPECIFIC POWER DRIVERS (ASPD)
12.1. Features
3 low-side and 3 high-side gate drivers
1A gate driving capability
Open-drain drivers with input capability
Configurable delays and fast fault protection
12.2. Block Diagram
12.3. Functional Description
The Application Specific Power Drivers (ASPD, Figure 12-1) module handles power driving for power control
applications. The PAC5223 has three low-side gate drivers (DRLx), three high-side gate drivers (DRHx). Each gate driver
can drive an external MOSFET or IGBT switch in response to high-speed control signals from the microcontroller ports,
and a pair of high-side and low-side gate drivers can form a half-bridge driver.
Figure 12-2 below shows typical gate driver connections and Table 22 shows the ASPD available resources. The PAC5223
gate drivers support up to a 70V supply.
Table 22. Power Driver Resources by Part Numbers
- 39 - Rev 1.17‒September 20, 2017
Figure 12-1. Application Specific Power Drivers
DRHx
DRBx
DRSx
LEVEL
SHIFT
DELAY
HS
DRLx
LOW-SIDE GATE DRIVERS
DELAY
HIGH-SIDE GATE DRIVERS
VP
APPLICATION SPECIFIC POWER DRIVERS
ENDRV
FAULT
PROTECT
LS
PORT/PWM SIGNALS
PRE-
DRIVER
PRE-
DRIVER
PAC5223
Power Application Controller
PART
NUMBER
LOW-SIDE GATE DRIVER HIGH-SIDE GATE DRIVER
DRLx SOURCE /SINK CURRENT DRHx MAX SUPPLY SOURCE/ SINK CURRENT
PAC5223 3 1A/1A 3 70V 1A/1A
The ASPD includes built-in configurable fault protection for the internal gate drivers.
12.3.1. Low-Side Gate Driver
The DRLx low-side gate driver drives the gate of an external MOSFET or IGBT switch between the low-level VSSP power
ground rail and high-level VP supply rail. The DRLx output pin has sink and source output current capability of 1A. Each
low-side gate driver is controlled by a microcontroller port signal with 4 configurable levels of propagation delay.
12.3.2. High-Side Gate Driver
The DRHx high-side gate driver drives the gate of an external MOSFET or IGBT switch between its low-level DRSx driver
source rail and its high-level DRBx bootstrap rail. The DRSx pin can go up to 70V steady state. The DRHx output pin has
sink and source output current capability of 1A. The DRBx bootstrap pin can have a maximum operating voltage of 16V
relative to the DRSx pin, and up to 82V steady state. The DRSx pin is designed to tolerate momentary switching negative
spikes down to -5V without affecting the DRHx output state. Each high-side gate driver is controlled by a microcontroller
port signal with 4 configurable levels of propagation delay.
For bootstrapped high-side operation, connect an appropriate capacitor between DRBx and DRSx and a properly rated
bootstrap diode from VP to DRBx. To operate the DRHx output as a low-side gate driver, connect its DRBx pin to VP and its
DRSx pin to VSSP.
12.3.3. High-Side Switching Transients
Typical high-side switching transients are shown in Figure 12-3(a). To ensure functionality and reliability, the DRSx and
DRBx pins must not exceed the peak and undershoot limit values shown. This should be verified by probing the DRBx and
DRSx pins directly relative to VSS pin. A small resistor and diode clamp for the DRSx pin can be used to make sure that
the pin voltage stays within the negative limit value. In addition, the high-side slew rate dV/dt must be kept within ±5V/ns
for DRSx. This can be achieved by adding a resistor-diode pair in series, and an optional capacitor in parallel with the
power switch gate. The parallel capacitor also provides a low impedance and close gate shunt against coupling from the
switch drain. These optional protection and slew rate control are shown in Figure 12-3(b).
- 40 - Rev 1.17‒September 20, 2017
Figure 12-2. Typical Gate Driver Connections
DRHx
DRLx
DRSx
DRBx VPVIN
PAC5223
(To loads/inductors.)
PAC5223
Power Application Controller
12.3.4. Power Drivers Control
All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor must first set
the driver enable bit to '1'. The gate drivers are controlled by the microcontroller ports and/or PWM signals according to
Table 23, with configurable delays as shown in Table 24. The OHIx open-drain drivers are controlled by their
corresponding register bits. Refer to the PAC application notes and user guide for additional information on power drivers
control programming.
Table 23. Microcontroller Port and PWM to Power Driver Mapping
PART
NUMBER PWMA0 PWMA1 PWMA2
PWMA3/
PWMA4/
PWMB0
PWMA5/
PWMC0
PWMA6/
PWMD0
PAC5223 DRL0 DRL1 DRL2 DRH3 DRH4 DRH5
Table 24. Power Driver Propagation Delay
DRLx DRHx
RISING FALLING RISING FALLING
130ns 140ns 160ns 140ns
12.3.5. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using protection signal from the Configurable Analog
Front End (CAFE), designated as protection event 1 (PR1) signal. The DRL0/DRL1/DRL2 drivers are designated as low-
side group 1. The DRH3/DRH4/DRH5 gate drivers are designated as high-side group 1. The PR1 signal from the CAFE
can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit settings.
- 41 - Rev 1.17‒September 20, 2017
Figure 12-3. High-Side Switching Transients and Optional Circuitry
VDRSx
VDRSx ≥ -5V
VDRBx ≤ 83V
VDRBx
dV/dt
dV/dt
(a) High-Side Switching Transients (b) Optional Transient Protection and Slew Rate Control
DRHx
DRLx
DRSx
DRBx VP
VIN
PAC5223
PAC5223
Power Application Controller
12.4. Electrical Characteristics
Table 25. Gate Drivers Electrical Characteristics
(VP = 12V, VSYS = 5V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
Low-Side Gate Drivers (DRLx Pins)
VOH,DRL High-level output voltage IDRLx = -50mA VP−0.5 V
VOL,DRL Low-level output voltage IDRLx = 50mA 0.35 V
IOHPK,DRL High-level pulsed peak source current 10µs pulse -1 A
IOLPK,DRL Low-level pulsed peak sink current 10µs pulse 1 A
High-Side Gate Drivers (DRHx, DRBx and DRSx Pins)
VDRS Level-shift driver source voltage range
Repetitive, 10µs pulse -5 71
V
Steady state 0 70
VDRB Bootstrap pin voltage range
Repetitive, 10µs pulse 3 83
V
Steady state 5.2 82
VBS;DRB Bootstrap supply voltage range VDRBx, relative to respective VDRSx 5.2 16 V
VUVLO;DRB Bootstrap UVLO threshold VDRBx rising, relative to respective VDRSx
,hysteresis= 1V 3.5 4.5 V
IBS;DRB Bootstrap circuit supply current
Gate Driver Disabled 24 36
µA
Gate Driver Enabled 32 50
IOS;DRB Offset supply current
Gate Driver Disabled 0.5 10
µA
Gate Driver Enabled 0.5 10
VOH;DRH High-level output voltage IDRHx = -50mA VDRBx−0.6 V
VOL;DRH Low-level output voltage IDRHx = 50mA VDRSx +0.6 V
IOHPK;DRH High-level pulsed peak source current 10µs pulse -1 A
IOLPK;DRH Low-level pulsed peak sink current 10µs pulse 1 A
High-Side and Low-Side Gate Driver Propagation Delay
tPD Propagation Delay1
Delay setting 00 Delay + 0 ns
Delay setting 01 Delay +
50 ns
Delay setting 10 Delay +
100 ns
Delay setting 11 Delay +
200 ns
1 Delay from Power Driver Propagation Delay
- 42 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
12.5. Typical Performance Characteristics
(VP = 12V, VSYS = 5V and TA = 25°C unless otherwise specified.)
- 43 - Rev 1.17‒September 20, 2017
-40 0 40 80 120
500
400
300
200
100
0
PACASPD-007
Turn-On Delay (ns)
Low-Side Gate Driver (DRLx)
Turn-On Delay vs. Temperature
Temperature (°C)
00b setting (default)
11b setting
10b setting
CL = 1nF
01b setting
-40 0 40 80 120
500
400
300
200
100
0
PACASPD-008
Turn-Off Delay (ns)
Low-Side Gate Driver (DRLx)
Turn-Off Delay vs. Temperature
Temperature (°C)
00b setting (default)
11b setting
10b setting
01b setting
CL = 1nF
-40 0 40 80 120
3
2
1
0
PACASPD-001
Source/Sink Current (A)
Low-Side Gate Driver (DRLx)
Source/Sink Current vs. Temperature
Temperature (°C)
Sink current
Source current
-40 0 40 80 120
8
7
6
5
4
3
2
1
0
PACASPD-002
On Resistance (Ω)
Low-Side Gate Driver (DRLx)
On Resistance vs. Temperature
Temperature (°C)
Pull up Pull down
-40 0 40 80 120
PACASPD-003
Source/Sink Current (A)
High-Side Gate Driver (DRHx)
Source/Sink Current vs. Temperature
Temperature (°C)
3
2
1
0
Sink current
Source current
-40 0 40 80 120
PACASPD-004
On Resistance (Ω)
High-Side Gate Driver (DRHx)
On Resistance vs. Temperature
Temperature (°C)
Pull up Pull down
8
7
6
5
4
3
2
1
0
PAC5223
Power Application Controller
Typical Performance Characteristics (Continued)
(VP = 12V, VSYS = 5V and TA = 25°C unless otherwise specified.)
- 44 - Rev 1.17‒September 20, 2017
-40 0 40 80 120
500
400
300
200
100
0
PACASPD-009
Turn-On Delay (ns)
High-Side Gate Driver (DRHx)
Turn-On Delay vs. Temperature
Temperature (°C)
00b setting (default)
11b setting
10b setting
CL = 1nF
01b setting
-40 0 40 80 120
500
400
300
200
100
0
PACASPD-011
Turn-Off Delay (ns)
High-Side Gate Driver (DRHx)
Turn-Off Delay vs. Temperature
Temperature (°C)
CL = 1nF
00b setting (default)
11b setting
10b setting
01b setting
PAC5223
Power Application Controller
13. ADC WITH AUTO-SAMPLING SEQUENCER
13.1. Block Diagram
13.2. Functional Description
13.2.1. ADC
The analog-to-digital converter (ADC) is a 10-bit succesive approximation register (SAR) ADC with 1 μs conversion
time and up to 1MSPS capability. The ADC input clock has a user-configurable divider from /1 to /8 of the system clock.
The integrated analog multiplexer allows selection from up to 6 direct ADx inputs, and from up to 10 analog inputs signals
in the Configurable Analog Front End (CAFE), including up to 3 differential input pairs. The ADC can be configured for
repeating or non-repeating conversions and can interrupt the microcontroller when a conversion is finished.
13.2.2. Auto-Sampling Sequencer
Two independent and flexible auto-sampling sequencer state machines allow signal sampling using the ADC without
interaction from microcontroller core. Each auto-sampling sequencer state machine can be programmed to take and store up
to 8 samples each in the ADC result register from different analog inputs, able to control the ADC MUX and ADC Premux
as well as the precise timing of the S/H in the Configurable analog front end. The sampling start of the auto-sampling
sequencer can be precisely triggered using timers A, B, C, or D or any of their associated PWM edges (high-to-low or low-
to-high). It also supports manual start or a ping-pong-scheme, where one auto-sampling sequencer state machine triggers
the other when it finishes sampling.
The auto-sampling sequencer can interrupt the microcontroller when either conversion sequence is finished.
- 45 - Rev 1.17‒September 20, 2017
Figure 13-1. ADC with Auto-Sampling Sequencer
ADC
AHB/APB
ADC WITH AUTO-SAMPLING SEQUENCER
ADx
MUX
ADC PRE-MUX
VTEMP
, VMON, VREF/2
REGISTER
EMUX
S/H
10-BIT
ADC
DAxP
DAxN
DIFFERENTIAL PGA
DIFF-PGA
MUX
CONFIGURABLE ANALOG FRONT END
CASM
AUTO-SAMPLING
SEQUENCER
ADC RESULT REGISTERS
(16)
EMUX CONTROL
STATE MACHINE 1
STATE MACHINE 0
REGISTER
REGISTER
REGISTER
PAC5223
Power Application Controller
13.2.3. EMUX Control
A dedicated low latency interface controllable by the auto-sampling sequencer or register control allows changing the ADC
premultiplexer and asserting/deasserting the S/H circuit in the configurable analog front end, allowing back to back
conversions of multiple analog inputs without microcontroller interaction.
13.3. Electrical Characteristics
Table 26. ADC and Auto-Sampling Sequencer Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
ADC
fADCLK ADC conversion clock input 16 MHz
tADCONV ADC conversion time fADCLK = 16MHz 1 μs
ADC resolution 10 bits
ADC effective resolution 9.2 bits
ADC differential non-linearity (DNL) ±0.5 LSB
ADC integral non-linearity (INL) ±1 LSB
ADC offset error 0.6 %FS
ADC gain error 0.12 %FS
Reference Voltage
VREFADC ADC reference voltage input 2.5 V
Sample and Hold
tADCSH ADC sample and hold time fADCLK = 16MHz 188 ns
CADCIC ADC input capacitance 1.3 pF
Input Voltage Range
V
ADCIN ADC input voltage range ADC multiplexer input 0 VREFADC V
EMUX Clock Speed
fEMUXCLK EMUX engine clock input 50 MHz
PLL Clock Speed
fOUTPLL PLL output frequency TA = -40°C to 85°C 3.5 100 MHz
TA = 85°C to 105°C 3.5 80 MHz
- 46 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
14. MEMORY SYSTEM
14.1. Features
32kB embedded FLASH
100,000 program/erase cycles
10 years data retention
8kB SRAM
14.2. Block Diagram
14.3. Functional Description
The device has multiple banks of embedded FLASH memory, SRAM memory, as well as peripheral control registers that
are all program-accessible in a flat memory map.
14.3.1. Program and Data FLASH
32kB in 32 pages of 1kB each is available for program or data memory. Each of them can be individually erased or written
to while the microcontroller is executing a program from SRAM.
14.3.2. SRAM
Up to 8kB contiguous array of SRAM is available for non-persistent data storage. The SRAM memory supports word
(4-byte), half-word (2-byte) and byte address aligned access. The microcontroller may execute code out of SRAM for time-
critical applications, or when modifying the contents of FLASH memory.
- 47 - Rev 1.17‒September 20, 2017
Figure 14-1. Memory System
8kB
SRAM
AHB/APB
MEMORY SYSTEM
1kB FLASH
PAGES
FLASH
256B INFO
ROM
INFO ROM SRAM
PAC5223
Power Application Controller
14.4. Electrical Characteristics
Table 27. Memory System Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
Embedded FLASH
tREAD;FLASH FLASH read time 40 ns
tWRITE;FLASH FLASH write time 20 μs
tPERASE;FLASH FLASH page erase time 10 ms
NPERASE;FLASH FLASH program/erase cycles 100k cycles
tDR;FLASH FLASH data retention 10 years
SRAM
tSRAM SRAM access cycle time 20 ns
- 48 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
15. CLOCK CONTROL SYSTEM
15.1. Features
Ring oscillator with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings
High accuracy 1% trimmed 4MHz RC oscillator
Crystal oscillator driver supporting 2MHz to 10MHz crystals
External clock input up to 40MHz
PLL with 1MHz to 25 MHz input, and 3.5MHz to 100MHz output
/1 to /8 clock divider for HCLK
/1 to /128 clock divider for ACLK
15.2. Block Diagram
- 49 - Rev 1.17‒September 20, 2017
XIN
XOUT
EXTCLK
MUX
CRYSTAL
DRIVER
1% RC
OSCILLATOR
RING
OSCILLATOR
PLL
MUX
DIV
DIV
HCLK
CLOCK SOURCES PLL CLOCK TREE
DIV
RTCDIV
WDT
DIV WIC
DIV ADC
DIV
CORTEX M0
SYSTICK
SRAM
FLASH
DIV UART
DIV I2C
DIV SOC BUS
DIV SPI
DIV ADC EMUX
CLOCK
GATING
TIMERS A, B, C & D
CLOCK
GATING
CLOCK
GATING
ACLK
FCLK
FRCLK
CLOCK CONTROL SYSTEM
TIMERDIV
Figure 15-1. Clock Control System
XIN
XOUT
EXTCLK
MUX
CRYSTAL
DRIVER
1% RC
OSCILLATOR
RING
OSCILLATOR
PLL
MUX
DIV
DIV
HCLK
CLOCK SOURCES PLL CLOCK TREE
DIV
RTCDIV
WDT
DIV WIC
DIV ADC
DIV
CORTEX M0
SYSTICK
SRAM
FLASH
DIV UART
DIV I2C
DIV SOC BUS
DIV SPI
DIV ADC EMUX
CLOCK
GATING
TIMERS A, B, C & D
CLOCK
GATING
CLOCK
GATING
ACLK
FCLK
FRCLK
CLOCK CONTROL SYSTEM
TIMERDIV
FRCLK
PAC5223
Power Application Controller
15.3. Functional Description
The PAC clock control system covers a wide range of applications.
15.3.1. Free Running Clock (FRCLK)
The free running clock (FRCLK) is generated from one of the 4 clock sources: ring oscillator, trimmed RC oscillator,
crystal driver or external clock input. The FRCLK is used for the real-time clock (RTC), watchdog timer (WDT), input to
the PLL, or FCLK source to clock the system in low power and sleep mode.
15.3.2. Fast Clock (FCLK)
The fast clock (FCLK) is generated from the PLL or supplied by the FRCLK directly. The FCLK supplies the watchdog
timer (WDT), ADC, wake-up interrupt controller (WIC), SysTick timer, ARM Cortex-M0 peripheral high speed clock
(HCLK) and low speed clock (LSCLK).
15.3.3. High-Speed Clock (HCLK)
The high-speed clock (HCLK) is derived from the FCLK with a /1, /2, /4 or /8 divider. It supplies the peripheral AHB/APB
bus, Timers A to D, dead-time controllers, SPI interface, I2C interface, UART interface, EMUX interface, SOC bridge
interface and memory subsystem, and can go as high as 50MHz.
15.3.4. Auxiliary Clock (ACLK)
The auxiliary clock (ACLK) is derived from FCLK with a /1, /2, to /128 divider, and supplies the timer and dead -time
blocks. It can be clocked faster or slower than HCLK and can go as high as 100MHz.
15.3.5. Clock Gating
The clock tree supports clock gating in deep-sleep mode for the timer block, ADC, SPI interface, I 2C interface, UART
interface, memory subsystem and the ARM Cortex-M0 itself.
15.3.6. Ring Oscillator (ROSC)
The integrated ring oscillator provides 4 different clocks with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings. After
reset, the clock tree always defaults to this clock input with the lowest frequency setting.
15.3.7. Trimmed 4MHz RC Oscillator
The 1% trimmed 4MHz RC oscillator provides an accurate clock suitable for many applications. It is also used to derive the
clock for the Multi-Mode Power Manager.
15.3.8. Internal Slow RC Oscillator
An internal 32kHz RC oscillator is used during start up to provide an initial clock to analog circuitry. It is not used as a
clock input to the clock tree.
15.3.9. Crystal Oscillator Driver
The optional crystal oscillator driver can drive crystals from 2MHz to 10MHz to provide a highly accurate and stable clock
into the system.
15.3.10. External Clock Input
The clock tree can be supplied with an external clock up to 10MHz.
15.3.11. PLL
The integrated PLL input clock is supplied by the FRCLK with an input frequency range of 1MHz to 25MHz. The PLL
output frequency is adjustable from 3.5MHz to 100MHz.
- 50 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
15.4. Electrical Characteristics
Table 28. Clock Control System Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
Clock Tree (FRCLK, FCLK, HCLK, and ACLK)
fFRCLK Free running clock frequency 50 MHz
fFCLK Fast clock frequency 100 MHz
fHCLK High-speed clock frequency 50 MHz
fACLK Auxiliary clock frequency 100 MHz
Internal Oscillators
fROSC Ring oscillator frequency
Frequency setting = 11b 7.5
MHz
Frequency setting = 10b 9.6
Frequency setting = 01b 13.8
Frequency setting = 00b 25.7
fTRIM Trimmed RC oscillator frequency
TA = 25°C 3.96 4 4.04
MHz
TA = -40°C to 105°C 3.90 4 4.06
Trimmed RC oscillator clock jitter TA = -40°C to 85°C 0.5 %
Crystal Oscillator Driver
VIH;XIN XIN high-level input voltage 0.65•VCC18 V
VIL;XIN XIN low-level input voltage 0.35•VCC18 V
fXTAL Crystal oscillator frequency range 2 10 MHz
Recommended capacitive load
fXTAL = 2MHz to 3MHz 25
pFfXTAL = 3MHz to 6MHz 20
fXTAL = 6MHz to 10MHz 16
External circuit ESR
fXTAL = 2MHz to 3MHz 1000
ΩfXTAL = 3MHz to 6MHz 400
fXTAL = 6MHz to 10MHz 100
External Clock Input
fEXTCLK External clock input frequency range 40 MHz
tHIGH;EXTCLK External clock high time 10 ns
tLOW;EXTCLK External clock low time 10 ns
PLL
fINPLL PLL input frequency range 2 25 MHz
fOUTPLL PLL output frequency range 3.5 100 MHz
PLL settling time 0.5 ms
PLL period jitter
RMS 30
ps
Peak to peak ±150
- 51 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
16. ARM CORTEX-M0 MICROCONTROLLER CORE
16.1. Features
ARM Cortex-M0 core
Fast single-cycle 32-bit x 32-bit multiplier
24-bit SysTick timer
Up to 50MHz operation
Serial wire debug (SWD), with 4 break-point and 2 watch-point unit comparators
Nested vectored interrupt controller (NVIC) with 25 external interrupts
Wake-up interrupt controller (WIC) with GPIO, real-time clock (RTC) and watchdog timer (WDT) interrupts
enabled
Sleep and deep-sleep mode with clock gating
16.2. Block Diagram
16.3. Functional Description
The ARM Cortex-M0 microcontroller core is configured for little endian operation and includes the fast single-cycle 32-bit
multiplier and 24-bit SysTick timer and can operate at a frequency of up to 50MHz.
The microcontroller nested vectored interrupt controller (NVIC) supports 25 external interrupts for the device's peripherals
and sub-systems. For low-latency interrupt processing, the NVIC also supports interrupt tail-chaining. The wake-up
interrupt controller (WIC) is able to wake up the device from low-power modes using any GPIO interrupt, as well as from
the RTC or WDT. The ARM Cortex-M0 supports both sleep and deep-sleep low-power modes. The deep-sleep mode
supports clock gating to limit standby power even further.
Firmware debug support includes 4 break-point and 2 watch-point unit comparators using the serial wire debug (SWD)
protocol. The serial wire debug mechanism can be disabled to prevent device access to the firmware in the field.
- 52 - Rev 1.17‒September 20, 2017
Figure 16-1. ARM Cortex-M0 Microcontroller Core
SERIAL WIRE
DEBUG WITH
DISABLE
ARM
CORTEX-M0
AHB/APB
ARM CORTEX-M0 MICROCONTROLLER CORE
1-CYCLE
32X32
MULTIPLIER
WAKE-UP
INTERRUPT
CONTROLLER
24-BIT
SYSTICK
SWDDA
SWDCL NESTED
VECTORED
INTERRUPT
CONTROLLER
PAC5223
Power Application Controller
16.4. Electrical Characteristics
Table 29. Microcontroller and Clock Control System Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
fHCLK Microcontroller clock HCLK 50 MHz
IOP;VSYS VSYS operating supply current
fFRCLK = fHCLK = fACLK = ROSC 11b, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
2.5(1) 3.4 7
mA
fFRCLK = fHCLK = fACLK = ROSC 10, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
3.0(1) 4 7.8
fFRCLK = fHCLK = fACLK = ROSC 01, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
4.1(1) 5.3 9.5
fFRCLK = fHCLK = fACLK = ROSC 00, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
7.4(1) 9 15
fFRCLK = fHCLK = fACLK = CLKREF, PLL disabled,
CPU halt; other clock sources, ADC, timers,
and serial interface disabled
1.5(1) 2.3 4.4
fFRCLK = fHCLK = fACLK = 10MHz XTAL, PLL
disabled, CPU halt; other clock sources, ADC,
timers, and serial interface disabled
3.6(1) 4.5 6.7
fFRCLK = 4MHz CLKREF, fHCLK = 50MHz, fACLK
= fOUTPLL = 100MHz, CPU halt; other clock
sources, ADC, timers, and serial interface
disabled
20.9(1) 23.3 26.5
IQ;VCCIO VCCIO quiescent supply current 0.02 mA
(1) All minimum operating supply current values are for room temperature only
16.5. Typical Performance Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = 25°C unless otherwise specified.)
- 53 - Rev 1.17‒September 20, 2017
0 20 40 60 80 100
25
20
15
10
5
0
PACMCU-001
IVCC18 (mA)
IVCC18 vs. PLL Frequency
PLL Frequency (MHz)
fHCLK = fACLK = fOUTPLL
fHCLK = 0.5•fOUTPLL,
fACLK = fOUTPLL
PAC5223
Power Application Controller
17. I/O CONTROLLER
17.1. Features
5V-compliant I/O PAx, PDx, PEx
3.3V-compliant I/O PCx
Configurable drive strength on PAx, PDx, PEx
Configurable pull-up or pull-down on PAx, PDx, PEx
17.2. Block Diagram
17.3. Functional Description
The PAC can support up to 4 ports with 8 I/Os each from PAx, PCx, PDx, and PEx, in addition to the I/Os on the analog
front end. All PAx, PCx, PDx, and PEx ports have interrupt capability with configurable interrupt edge.
PAx, PDx, and PEx I/Os use VCCIO as the I/O supply voltage that is 5V on default parts (and 3.3V available from factory).
The drive current can be configured as 8mA or 16mA. They also support weak pull-up and pull-down to save external
components.
PCx uses VCC33 as its I/O supply voltage. The drive current is fixed to 8mA. PC0 to PC5 are also associated with analog
inputs AD0 to AD5 to the ADC.
- 54 - Rev 1.17‒September 20, 2017
Figure 17-1. I/O controller
PAx, PDx, PEx
DIGITAL I/O
GPIO INPUT
VCCIO (5V/3.3V)
GPIO OUTPUT
OUTPUT ENABLE
DRIVE STRENGTH
PULL UP
PULL DOWN
VCCIO (5V/3.3V)
PCx
GPIO INPUT
GPIO OUTPUT
OUTPUT ENABLE
VCC33 (3.3V)
INPUT ENABLE
ADC MUX
AHB/APB
PERIPHERAL
PERIPHERAL
GPIO (PCx)
GPIO (PAx, PDx, PEx)
PAC5223
Power Application Controller
17.4. Electrical Characteristics
Table 30. I/O Controller Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
PAx, PDx, PEx (5V Operation)
VIH High-level input voltage VCCIO = 5V 3 V
VIL Low-level input voltage VCCIO = 5V 0.8 V
IOL Low-level output sink current VCCIO = 5V,
VOL = 0.4V
Drive strength setting = 0b 7
mA
Drive strength setting = 1b 15
IOH High-level output source current VCCIO = 5V,
VOH = 2.4V
Drive strength setting = 0b -7
mA
Drive strength setting = 1b -15
RPU Weak pull-up resistance VCCIO = 5V 53 66 87 kΩ
RPD Weak pull-down resistance VCCIO = 5V 63 108 244 kΩ
IIL Input leakage current TA = 125°C -10 0 10 μA
PAx, PDx, PEx (3.3V Operation)
VIH High-level input voltage VCCIO = 3.3V 2 V
VIL Low-level input voltage VCCIO = 3.3V 0.8 V
IOL Low-level output sink current VCCIO = 3.3V,
VOL = 0.4V
Drive strength setting = 0b 4
mA
Drive strength setting = 1b 8
IOH High-level output source current VCCIO = 3.3V,
VOH = 2.4V
Drive strength setting = 0b -4
mA
Drive strength setting = 1b -8
RPU Weak pull-up resistance VCCIO = 3.3V 47 74 104 kΩ
RPD Weak pull-down resistance VCCIO = 3.3V 50 84 121 kΩ
IIL Input leakage current TA = 125°C -10 0 10 μA
PCx (3.3V Operation)
VIH High-level input voltage VCC33 = 3.3V 2 V
VIL Low-level input voltage VCC33 = 3.3V 0.8 V
IOL Low-level output sink current VCC33 = 3.3V, VOL = 0.4V 7 mA
IOH High-level output source current VCC33 = 3.3V, VOH = 2.4V -7 mA
IIL Input leakage current TA = 125°C -10 0 10 μA
- 55 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
18. SERIAL INTERFACE
18.1. Block Diagram
18.2. Functional Description
The device has up to three serial interfaces: I2C, UART, and SPI.
18.2.1. I2C Controller
The I2C controller is a configurable peripheral that can support various modes of operation:
I2C master operation
Normal mode (100kHz), fast mode (400kHz), or fast mode plus (1MHz)
Single and multi-master
Synchronization (multi-master)
Arbitration (multi-master)
7-bit or 10-bit slave addressing
I2C slave operation
Normal mode (100kHz), fast mode (400kHz), or fast mode plus (1MHz)
Clock stretching
7-bit or 10-bit slave addressing
The I2C peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and transmit
- 56 - Rev 1.17‒September 20, 2017
Figure 18-1. Serial Interface
SCL
SERIAL INTERFACE
SDA
I2C
MASTER
I2C
SLAVE
I2C
AHB/APB
SPICLK
SPIMISO
SPI
MASTER
SPI
SPIMOSI
SPICS0, 1, 2
TX
RX
16550-COMPATIBLE
UART
UART
SPI
SLAVE
PAC5223
Power Application Controller
data.
18.3. UART Controller
The UART peripheral is a configurable peripheral that can support various features and modes of operation:
Programmable clock selection
National Instruments PC16550D compatible
16-deep transmit and receive FIFO and fractional clock divisor
Up to 3.125Mbps communication speed (with HCLK = 50MHz)
The UART peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and
transmit data.
18.4. SPI Controller
The device contains an SPI controller that can each be used in either master or slave operation, with the following features:
SPI master operation
Control of up to three different SPI slaves
Operation up to 25MHz
Flexible multiple transmit mode for variable-size SPI data with user-defined chip-select behavior
Chip select “shaping” through programmable additional delay for chip-select setup, hold and wait time
for back-to-back transfers
SPI master or slave operation
Supports clock phase and polarity control
Data transmission/reception can be on 8-, 16-, 24- or 32-bit boundary
Selectable data bit ordering (LSB or MSB first)
Programmable chip select polarity
Selectable “auto-retransmit” mode
The SPI peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and transmit
data.
- 57 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
18.5. Dynamic Characteristics
Table 31. Serial Interface Dynamic Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNI
T
I2C
fI2CCLK I2C input clock frequency
Standard mode (100kHz) 2.8 MHz
Fast mode (400kHz) 2.8 MHz
Fast mode plus (1MHz) 6.14 MHz
UART
fUARTCLK UART input clock frequency fHCLK/16 MHz
UART baud rate fHCLK = 50MHz 3.125 Mbps
SPI
fSPICLK SPI input clock frequency
Master mode fHCLK/2 MHz
Slave mode fHCLK/2 MHz
- 58 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 32. I2C Dynamic Characteristics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
fSCL SCL clock frequency
Standard mode 0 100
Fast mode 0 400
Fast mode plus 0 1000
kHz
tLOW SCL clock low
Standard mode 4.7
Fast mode 1.3
Fast mode plus 0.5
μs
tHIGH SCL clock high
Standard mode 4.0
Fast mode 0.6
Fast mode plus 0.26
μs
tHD;STA Hold time for a repeated START condition
Standard mode 4.0
Fast mode 0.6
Fast mode plus 0.26
μs
tSU;STA
Set-up time for a repeated START
condition
Standard mode 4.7
Fast mode 0.6
Fast mode plus 0.26
μs
tHD;DAT Data hold time
Standard mode 0 3.45
Fast mode 0 0.9
Fast mode plus 0
μs
tSU;DAT Data set-up time
Standard mode 250
Fast mode 100
Fast mode plus 50
ns
tSU;STO Set-up time for STOP condition
Standard mode 4.0
Fast mode 0.6
Fast mode plus 0.26
μs
tBUF
Bus free time between a STOP and START
condition
Standard mode 4.7
Fast mode 1.3
Fast mode plus 0.5
μs
trRise time for SDA and SCL
Standard mode 1000
Fast mode 20 300
Fast mode plus 120
ns
tfFall time for SDA and SCL
Standard mode 300
Fast mode 300
Fast mode plus 120
ns
CbCapacitive load for each bus line
Standard mode, Fast mode 400 pF
Fast mode plus 550 pF
- 59 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
- 60 - Rev 1.17‒September 20, 2017
Figure 18-2. I2C Timing Diagram
S Sr P S
SDA
SCL
tHD;STA
tHIGH
tLOW
tSU;STA
tr
tf
tBUF
tSU;STO
tf
tr
tSU;DAT
tHD;DAT
PAC5223
Power Application Controller
Table 33. SPI Dynamic Characteristics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
tSCLK;HIGH SPICLK Input High Time
tSCLK;LOW SPICLK Input Low Time
tSS;SCLK SPICSn to SPICLK Time
tSS;MOSI SPICSn to SPIMISO High-impedance time
tr(SCLK) SPICLK Rise Time
tf(SCLK) SPICLK Fall Time
tr(MOSI) SPIMISO Rise Time
tf(SMOSI) SPIMISO Fall Time
tSU;MISO SPIMISO Setup Time
tH;MISO SPIMISO Hold Time
SPICLK = 25MHz
30 ns
30 ns
120 ns
10 50 ns
10 25 ns
10 25 ns
10 25 ns
10 25 ns
20 ns
20 ns
- 61 - Rev 1.17‒September 20, 2017
Figure 18-3. SPI Timing Diagram
SPICSn
SPICLK
[SPICFG.RCVCP = 0b]
SPIMOSI
SPIMISO
SPICLK
[SPICFG.RCVCP = 1b]
tSS;CLK tf(SCLK)
tr(SCLK)
tr(MOSI)
tf(MOSI)
tSS;MOSI
tSU;MISO
tH;MISO
tSCLK;HIGH
tSCLK;LOW
PAC5223
Power Application Controller
19. TIMERS
19.1. Block Diagram
- 62 - Rev 1.17‒September 20, 2017
Figure 19-1. Timers A, B, C, and D
PWMA0, PWMA1,
PWMA2, PWMA3
TIMERS A, B, C, AND D
AHB/APB
DEAD TIME
GENERATOR
PWMA4, PWMA5,
PWMA6, PWMA7
CAPTURE &
COMPARE
CAPTURE &
COMPARE
TIMER A
16-BIT
PWMB0 DEAD TIME
GENERATOR
PWMB1
CAPTURE &
COMPARE
CAPTURE &
COMPARE
PWMC0 DEAD TIME
GENERATOR
PWMC1
CAPTURE &
COMPARE
CAPTURE &
COMPARE
PWMD0 DEAD TIME
GENERATOR
PWMD1
CAPTURE &
COMPARE
CAPTURE &
COMPARE
TIMER B
16-BIT
TIMER C
16-BIT
TIMER D
16-BIT
TIMER A PWM
TIMER B PWM
TIMER C PWM
TIMER D PWM
SYNC
PAC5223
Power Application Controller
19.2. Functional Description
The device includes 9 timers: timer A, timer B, timer C, timer D, watchdog timer 1 (WDT), watchdog timer 2, wake-up
timer, real-time clock (RTC), and SysTick timer. The device supports up to 14 different PWM signals and has up to 7 dead-
time controllers. Timers A, B, C and D can be concatenated to synchronize to a single clock and start/stop signal for
applications that require a synchronized timer period between timers.
19.2.1. Timer A
Timer A is a general purpose 16-bit timer with 8 PWM/capture and compare units. It has 4 pairs of PWM signals going into
4 dead-time controllers. Timer A can be concatenated with timers B, C, and D to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
19.2.2. Timer B
Timer B is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going
into one dead-time controller, as well as 2 additional compare units that can be used for additional system time bases for
interrupts. Timer B can be concatenated with timers A, C, and D to synchronize the PWM/capture and compare units. It can
use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
19.2.3. Timer C
Timer C is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going
into one dead-time controller. Timer C can be concatenated with timers A, B, and D to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
- 63 - Rev 1.17‒September 20, 2017
Figure 19-2. SOC Bus Watchdog and Wake-Up Timer
SOC BUS
WATCHDOG
WAKE-UP
TIMER
SOC
SOC BUS
AHB/APB
SOC BUS WATCHDOG AND WAKE-UP TIMER
Figure 19-3. Real-Time Clock and Watchdog Timer
WDT
24-BIT
RTC
24-BIT
AHB/APB
REAL-TIME CLOCK AND WATCHDOG TIMER
PAC5223
Power Application Controller
19.2.4. Timer D
Timer D is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going
into one dead-time controller. Timer D can be concatenated with timers A, B, and C to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
19.2.5. Watchdog Timer
The 24-bit watchdog timer (WDT) can be used for long time period measurements or periodic wake up from sleep mode.
The watchdog timer can be used as a system watchdog, or as an interval timer, or both. The watchdog timer can use either
FRCLK or FCLK as clock input with an additional clock divider from /2 to /65536.
19.2.6. SOC Bus Watchdog Timer
The watchdog timer 2 is used to monitor internal SOC Bus communication. It will trigger device reset if there is no SOC
Bus communication to the AFE for 4s or 8s.
19.2.7. Wake-Up Timer
The wake-up timer can be used for very low power hibernate and sleep modes to wake up the micro controller periodically.
It can be configured to be 125ms, 250ms, 500ms, 1s, 2s, 4, or 8s.
19.2.8. Real-Time Clock
The 24-bit real-time clock (RTC) can be used for time measurements when an accurate clock source is used. This timer can
also be used for periodic wake up from sleep mode. The RTC uses FRCLK as clock input with an additional clock divider
from /2 to /65536.
- 64 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
20. THERMAL CHARACTERISTICS
Table 34. Thermal Characteristics
PARAMETER VALUE UNIT
Operating ambient temperature range -40 to 105 °C
Operating junction temperature range -40 to 125 °C
Storage temperature range -55 to 150 °C
Lead temperature (Soldering, 10 seconds) 300 °C
Junction-to-case thermal resistance (θJC)2.897 °C/W
Junction-to-ambient thermal resistance (θJA)23.36 °C/W
- 65 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
21. APPLICATION EXAMPLES
The following simplified diagrams show different examples of PAC applications. Refer to application notes for detailed
design description.
- 66 - Rev 1.17‒September 20, 2017
Figure 21-2. Solar LED Street Lighting Using PAC5223 (Simplified Diagram)
VP
PAC5223 DRM
CSM
VP
DRH3, DRH4
DRL0, DRL1
DRS3, DRS4
DRB3, DRB4
DAxP, DAxN, AMPx
DRL2
INTERFACE
MONITORING
SIGNALS
GPIO
Figure 21-1. 3-phase Motor Drive Using PAC5223 (Simplified Diagram)
VP
PAC5223 DRM
CSM
VP
DRHx
DRLx
DRSx
DRBx
DAxP, DAxN
INTERFACE
MONITORING
SIGNALS
GPIO
VAC
M
PAC5223
Power Application Controller
22. PACKAGE OUTLINE AND DIMENSIONS
22.1. TQFN66-48 Package Outline and Dimensions
- 67 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
Table 22-1. Dimensions
Millimeters Inches
Dimensions Min. Max. Min. Max.
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.203 0.008
b 0.150 0.250 0.006 0.010
D 5.924 6.076 0.233 0.239
D1 4.100 4.400 0.161 0.173
E 5.924 6.076 0.233 0.239
E1 4.100 4.400 0.161 0.173
e 0.400 0.016
L 0.324 0.476 0.013 0.019
K 0.200 0.008
- 68 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
23. CHANGE LIST
Table 35. Data Sheet Change List
DATE VERSION CHAPTER CHANGES
1.8 MMPM •Fixed MMPM Power-Up Sequence Timing Diagram
8-Aug-2016 1.11 Serial Interface •Added SPI dynamic timing parameters and diagram
15-Aug-2016 1.12
MMPM •Added Kmon min/max gain eleectrical characteristics
CAFE •Added Avzi;da min/max gain electrical characteristics
•Added AIO6 Vout over load dynamic characteristics
MCU •Added max supply current for different operational
conditions
29-Dec-2016 1.13 Package •Updated package dimensions.
6-Mar-2017 1.14 MMPM •Updated SEPIC diagram.
3-May-2017 1.15 Thermal •Updated junction temperature.
15-Jun-2017 1.16 Drivers •Update propagation delays.
- 69 - Rev 1.17‒September 20, 2017
PAC5223
Power Application Controller
24. LEGAL INFORMATION
Copyright © 2017 Active-Semi, Inc. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Active-Semi reserves the right to modify its products, circuitry or product specifications without notice. Active-Semi products are not intended, designed,
warranted or authorized for use as critical components in life-support, life-critical or safety-critical devices, systems, or equipment, nor in applications
where failure or malfunction of any Active-Semi product can reasonably be expected to result in personal injury, death or severe property or environmental
damage. Active-Semi accepts no liability for inclusion and/or use of its products in such equipment or applications. Active-Semi does not assume any
liability arising out of the use of any product, circuit, or any information described in this document. No license, express, implied or otherwise, is granted
under any patents, copyrights or other intellectual property rights of Active-Semi or others. Active-Semi assumes no liability for any infringement of the
intellectual property rights or other rights of third parties which would result from the use of information contained herein. Customers should evaluate
each product to make sure that it is suitable for their applications. Customers are responsible for the design, testing, and operation of their applications and
products using Active-Semi products. Customers should provide appropriate design and operating safeguards to minimize the risks associated with their
applications and products. All products are sold subject to Active-Semi's terms and conditions of sale supplied at the time of order acknowledgment.
Exportation of any Active-Semi product may be subject to export control laws.
Active-SemiTM, Active-Semi logo, Solutions for SustainabilityTM, Power Application Controller®, Micro Application ControllerTM, Multi-Mode Power
ManagerTM, Configurable Analog Front EndTM, and Application Specific Power DriversTM are trademarks of Active-Semi, Inc.
ARM® and Cortex® are registered trademarks of ARM Limited. All referenced brands and trademarks are the property of their respective owners.
For more information on this and other products, contact sales@active-semi.com or visit www.active-semi.com.
- 70 - Rev 1.17‒September 20, 2017
