CrossLink-NX Evaluation Board User Guide FPGA-EB-02028-1.3 November 2020 CrossLink-NX Evaluation Board User Guide Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice's product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Contents Acronyms in This Document ................................................................................................................................................. 5 1. Introduction .................................................................................................................................................................. 6 1.1. CrossLink-NX Evaluation Board ........................................................................................................................... 6 1.2. Features .............................................................................................................................................................. 6 1.3. CrossLink-NX Device .......................................................................................................................................... 11 1.4. Applying Power to the Board ............................................................................................................................ 11 2. Jumpers and Test Connection .................................................................................................................................... 12 3. Power Scheme ............................................................................................................................................................ 14 4. Programming and I2C .................................................................................................................................................. 15 4.1. JTAG Download Interface .................................................................................................................................. 15 4.2. Alternate JTAG Download Interface .................................................................................................................. 15 4.3. JTAG to MSPI Pass-through Interface ............................................................................................................... 16 4.4. SPI Flash Device Selection in Programmer ........................................................................................................ 16 4.5. Other JTAG Configuration Pins .......................................................................................................................... 17 5. CrossLink-NX Clock Sources ........................................................................................................................................ 18 6. Control Buses - I2C, UART, and SPI ............................................................................................................................. 19 6.1. I2C ...................................................................................................................................................................... 19 6.2. UART Topology .................................................................................................................................................. 19 6.3. SPI Topology ...................................................................................................................................................... 20 6.3.1. SPI Configuration .......................................................................................................................................... 20 7. LEDs and Switches ...................................................................................................................................................... 21 7.1. DIP Switch ......................................................................................................................................................... 21 7.2. General Purpose Push Buttons ......................................................................................................................... 21 7.3. General Purpose LEDs ....................................................................................................................................... 22 7.4. Indicator LEDs.................................................................................................................................................... 22 8. Headers/Connectors and LIFCL-40 Device Ball Mapping............................................................................................ 23 8.1. FMC LPC Connector ........................................................................................................................................... 23 8.2. Parallel FMC Configuration Header................................................................................................................... 25 8.3. Raspberry Pi Board GPIO Header ...................................................................................................................... 25 8.4. Camera Connector ............................................................................................................................................ 26 8.5. D-PHY1 Header .................................................................................................................................................. 27 8.6. PMOD Header ................................................................................................................................................... 28 8.7. JTAG Header ...................................................................................................................................................... 28 8.8. Parallel Configuration Header ........................................................................................................................... 29 8.9. ADC Test Header ............................................................................................................................................... 29 9. Software Requirements .............................................................................................................................................. 30 10. Storage and Handling ............................................................................................................................................. 30 11. Ordering Information.............................................................................................................................................. 30 Appendix A. CrossLink-NX Evaluation Board Schematics ................................................................................................... 31 Appendix B. CrossLink-NX Evaluation Board Bill of Materials ............................................................................................ 45 Appendix C. Fast Configuration Issues................................................................................................................................ 53 Appendix D. Schematics Updates for ADC Test .................................................................................................................. 54 References .......................................................................................................................................................................... 55 Lattice Semiconductor Documents................................................................................................................................. 55 Technical Support Assistance .............................................................................................................................................. 56 Revision History .................................................................................................................................................................. 57 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 3 CrossLink-NX Evaluation Board User Guide Figures Figure 1.1. Top View of CrossLink-NX Evaluation Board .......................................................................................................7 Figure 1.2. Bottom View of CrossLink-NX Evaluation Board .................................................................................................8 Figure 1.3. Silkscreen of CrossLink-NX Evaluation Board (Top .............................................................................................9 Figure 1.4. Silkscreen of CrossLink-NX Evaluation Board (Bottom) ....................................................................................10 Figure 2.1. Top View of CrossLink-NX Evaluation Board - Jumper Locations .....................................................................12 Figure 3.1. Board Power Scheme ........................................................................................................................................14 Figure 4.1. Configuration and I2C Architecture ...................................................................................................................15 Figure 4.2. SPI Flash Operation Dialog ................................................................................................................................16 Figure 6.1. I2C Architecture and UART Options ..................................................................................................................19 Figure A.1. Title Page ..........................................................................................................................................................31 Figure A.2. Block Diagram ...................................................................................................................................................32 Figure A.3. USB Interface ....................................................................................................................................................33 Figure A.4. Camera Interface (DPHYs) ................................................................................................................................34 Figure A.5. Raspberry Pi and User I/O Interface .................................................................................................................35 Figure A.6. SERDES SMAs/Switches/FMC Control ..............................................................................................................36 Figure A.7. I2C LEDs and Push Buttons ...............................................................................................................................37 Figure A.8. PMODs ..............................................................................................................................................................38 Figure A.9. Configuration and ADC .....................................................................................................................................39 Figure A.10. FMC-LPC..........................................................................................................................................................40 Figure A.11. Power CSI and Banks ......................................................................................................................................41 Figure A.12. Power Decoupling...........................................................................................................................................42 Figure A.13. Power Regulators ...........................................................................................................................................43 Figure A.14. Power Block Diagram......................................................................................................................................44 Tables Table 2.1. Jumper Table ......................................................................................................................................................13 Table 3.1. CrossLink-NX VCCIO Supply Options ..................................................................................................................14 Table 4.1. JTAG Connections...............................................................................................................................................15 Table 4.2. Other JTAG Signals .............................................................................................................................................17 Table 5.1. Clock Sources .....................................................................................................................................................18 Table 6.1. I2C Global Bus Connections ................................................................................................................................19 Table 6.2. CrossLink-NX SPI Connections ............................................................................................................................20 Table 7.1. Eight-Position DIP Switch Signals .......................................................................................................................21 Table 7.2. Push Button Switch Signals ................................................................................................................................21 Table 7.3. General Purpose LED Signals ..............................................................................................................................22 Table 7.4. Various LED Signals ............................................................................................................................................22 Table 8.1. FMC LPC Header Pin Connections ......................................................................................................................23 Table 8.2. Parallel FMC Configuration J27 Pin Connections ...............................................................................................25 Table 8.3. Raspberry Pi JP8 Header Pin Connections..........................................................................................................25 Table 8.4. Camera CN1 Connector Pin Connections ...........................................................................................................26 Table 8.5. D-PHY1 J6 Header Pin Connections ....................................................................................................................27 Table 8.6. J17, J18 and J19 Header Pin Connections ..........................................................................................................28 Table 8.7. J1 Header Pin Connections .................................................................................................................................28 Table 8.8. J27 Header Pin Connections ...............................................................................................................................29 Table 8.9. J26 Header Pin Connections ...............................................................................................................................29 Table 11.1. Ordering Information .......................................................................................................................................30 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Acronyms in This Document A list of acronyms used in this document. Acronym Definition caBGA Chip Array Ball Grid Array CMOS Complementary Metal-Oxide Semiconductor DIP Dual Inline Package DNI Do Not Install ESD Electro Static Discharge FMC LPC FPGA Mezzanine Low Pin Count Connector FPGA Field Programmable Logic Array FTDI Future Technology Devices International GPIO General Purpose Input/Output I2 C Inter-Integrated Circuit JTAG Joint Test Action Group LVDS Low-Voltage Differential Signaling PMOD Peripheral Module SPI Serial Peripheral Interface UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 5 CrossLink-NX Evaluation Board User Guide 1. Introduction The Lattice Semiconductor CrossLinkTM-NX Evaluation Board allows designers to investigate and experiment with the features of the CrossLink-NX Field Programmable Gate Array (FPGA). The features of the CrossLink-NX Evaluation Board can assist engineers with the rapid prototyping and testing of their specific designs. The CrossLink-NX Evaluation Board is part of the CrossLink-NX Evaluation Kit, which includes the following: CrossLink-NX Evaluation Board pre-loaded with the shipping demo design 12 V AC/DC power adapter and international plug adapters Lattice Radiant(R) Software license information USB-A to USB-B (Mini) Cable for programming FPGA through a PC Quick Start Guide The contents of this user guide include top-level functional descriptions of the various portions of the development board, descriptions of the on-board headers, diodes and switches and a complete set of schematics. 1.1. CrossLink-NX Evaluation Board The CrossLink-NX Evaluation Board features the CrossLink-NX FPGA in the 400-ball caBGA package (LIFCL-40-9BG400C) w the ability to expand the usability of the CrossLink-NX with Raspberry Pi, PMOD, FMC LPC connector, along with access to PCIe channel. 118 wide range I/O and 37 high speed differential pairs are available for user-defined applications. Figure 1.1 shows the top view of the CrossLink-NX Evaluation Board. Figure 1.2 shows the bottom view of the board. Figure 2.1 shows the jumper locations. 1.2. Features The CrossLink-NX Evaluation Board includes the following features: CrossLink-NX FPGA (LIFCL-40-9BG400C) General Purpose Input/Output (GPIO) breakout with Raspberry Pi, PMOD, and FMC connector MIPI CSI-2 Camera connector and D-PHY connector 118 wide range I/O and 37 high speed differential pair I/O with on board termination x1 Gen2 PCIe interface USB-B connection for device programming and Inter-Integrated Circuit (I2C) utility On-board Boot Flash - 128 Mbit Serial Peripheral Interface (SPI) Flash, with Quad read feature Eight input DIP switches, four push buttons, three status LEDs and 14 LEDs for demo purposes Lattice Radiant(R) Software programming support Multiple reference clock sources Potentiometer for ADC test Caution: The CrossLink-NX Evaluation Board contains ESD-sensitive components. ESD safe practices should be followed while handling and using the development board. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 12 V Power Input Camera Conn (CN1) xD-Phy 1 Header (J6) Serdes Test SMA Conn (J11, J15, J12, J16, J10 and J14) Power Status LEDs (D19-D27) Mini USB FTDI Interface Chip (U1) SPI Flash Memory (U6) Parallel Config Header (J20) Status LEDs JTAG Header(J1) LIFCL-40 Device (U3) User Switches (SW1) PMOD Conn (J17-J19) Raspberry PI Conn (JP5) ADC Test Header (J26) Prototype Area Potentiometer (U8) Output LEDs Push Buttons (D16-D3) (SW5-SW2) FPGA Mezzanine Carrier Card Conn (U9) FMC Parallel Config Header (J27) Figure 1.1. Top View of CrossLink-NX Evaluation Board (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 7 CrossLink-NX Evaluation Board User Guide 200 MHZ OSC for Serdes (U5) 125 MHZ OSC for Serdes (U4) Figure 1.2. Bottom View of CrossLink-NX Evaluation Board (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-EB-02028-1.3 PROTOTYPE AREA R68 H1 H40 FPGA MEZZANINE CARD C17 R9 JP2 BRD EDGE PMOD0 C16 JTAG FLASH/FPGA U7 PMOD1 R98 J19 J21 FMC CONFIG C40 J18 1 1 C1 J17 J22 R99 C100 GSRN PBO PROG CrossLink-NX Evaluation Board LIFCL-40-EVN REV B Copyright C 2019 MADE IN USA U9 1 PMOD2 J30 R110 R112 L12 C82 C98 TP8 R71 C62 PB1U10 C105 J29 R111 R109 MINI USB 1 J26 C89 C90 JP6 J1 J24 J25 R143 JP7 C99 C97 TP6 C136 U13 U6 R148 TP5 TP4 TP3 L13 R72 J23 TP_V1P8_LDO D7 R179 R175 D4 R174 D6 R178 D3 R177 C102 SW3 R176 D5JP8 D10 R182 SW2 D9 R181 R70 D8 R180 D11 R183 DEMO LEDS TP7 R69 R67 C63 C61 NX ADC TP_VCCIO2 TP_VCCIO1 L10 C48 R36 R35 R40 R77 C76 D12 R184 SW5 R186 D14 11 SW4 D13 R185 TP_VCCIO7 CROSSLINK FB7R149 C39 C134 TP_V1P0_LDO J38 TP13 J31 FB6 TP_VCCIO6 TP9 C103 C104 C101 R108 C56 L8 L4 L6 R39 R102 C88 U2 J20 RN1 C139 R37 C64 D2 1 64 J37 R38 J2 16 X1 J28 C133 C68 U3 17 J27 1 TP_VADJ POT BOARD EDGE GND TP_V1P8 J43 JP5 R163 R30 C122 J3 R80 C159 U16 C170 R170 R165 C167 L17 D34 R166 C160 R161 C163 R168 C157C156 D33 L16 C166 C165 C158 R169 FB8 C161 R164 R150 J36 J35 C164 J34 D16 R187 U14 TP_VCC_CORE_V1P0 R28R27 JP1 U1 R19 32 33 FB3 R20 R15 J9 R17 R21 FB1 R18 J7 FB2 48 49 J8 J44 1 R65 R66 R51 R47 R46 R49 R31 R41 TP_VCCIO0 R75 R73 R74 J32 D15 R145 C155 D36 3.3V R141 C137 TP_VCCIO5 TP_VCCIO4 TP_VCCIO3 C135 R140 1 D35 RASPBERRY PI AND USER I/O DEMO SW D-PHY 1 R76 1.8V/3.3V RPI/USER TP_V3P3 R162 1.8V 40 R153 J41 J33 J42 L15 SW1 C154 J5 TP_V1P8_VCCAUXSD TP_V1P8_VCCPLLSD R56 C49 C57 R52 R50 R62 R48 R54 R63 R60 C55 C54 R58 C53 C50 R55 TP_V1P0_VCCSD R24 1 D30 J4 TP2 TP1 R64R61R59 R57 R29 RXDP J11 RXDN TXDP SERDES C32 C26 C30 1 C147 2 JP4 TXDN L11 J13 J6 C143 C142 R160 R155 1.0V D31 C141 1.0VL D32 CLKP R156 R154 D29 1.8VL 1.2V CLKN J15 J12 J16 J10 J14 MIPI CSI-2 2 POWER 3 TP_V2P8 TP_V1P2 STATUS LEDS ACT R157 D1 TP10 C146 U15 D17 INITN R151 C149 D18 DONE R159 TP12 C144 JP3 ON 39 1 30 X2 J40 3.3V R121 TP_V5P0 2.8VL14 R152 C151 1.8V C152 D22 D24 R118 D26 R125 D23 R117 D25 R119 D27 R126 1 15 CN116 F1 5V C145 D19 D20 R114 D21 R115 POWER LEDS 12V J39 CrossLink-NX Evaluation Board User Guide U8 1 Figure 1.3. Silkscreen of CrossLink-NX Evaluation Board (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 9 CrossLink-NX Evaluation Board User Guide R23 U12 C138 Q5 Q2 C37 C38 C168 R134 C162 C169 C33 R78 C113 C107 C106 C131 C120 C96 C129 C95 C119 C127 C92 C93 R106 R107 Q3 Q6 C69 C45 C46 R45 C47 R43 C29 C25 C31C35 C27 C75 C118 C124 C128 C66 C125 C117 C114 C71 C70 C65 C126 C116 C130 C41 C115 C59 C85 R129 R130 R167 FB4 C140 R144 1 A R128 R133 C40 R138 R94 C44 C73 R122 C148 R81 R131 C86 C84 R93 C83 R123 R136 C81 C80 C87 C108 C60 C58 R84 R88 R89 R91 R85 C42 R100 305-PD-19-0943 NOV 2019 R171 R101 C79 R90 R87 R34 L5 R132 C153 C132 R97 R79 R32 R95 C72 R14 R33 L9 C9 C77 R147 C78 R86R92 R142 R146 C28 C109 R158 C123 C121 C36 R137 C150 L7 Q1 C34 A R104 R105 R103 R96 U11 R82 R83 C51 C52 C43 C74 R3 R2 R4 C111 R124 FB5 R1 R113 Q4 U4 R44 R127 R11 R10 C67 C110 R116 R22 C14 C5 D28 C94 R16 R12 C1 C112 C11 R42 C2 L1 R13 L3 C13 R53 C15 C12 C9 C7 C6 C10 L2 C8 C18 R26 R25 R120 C21 C20 C23 C22 U5 C4 R135 C3 R8 R173 R172 R5 R6 R7 C24 C19 Figure 1.4. Silkscreen of CrossLink-NX Evaluation Board (Bottom) (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 1.3. CrossLink-NX Device The CrossLink-NX Evaluation Board features the CrossLink-NX device in a 400-ball caBGA package, also referred to as LIFCL-40-9BG400C. For more information on the capabilities of CrossLink-NX, see CrossLink-NX Family Data Sheet (FPGA-DS-02049). 1.4. Applying Power to the Board Power LEDs light after applying 12 V power to CrossLink-NX Evaluation Board to indicate the board is functioning. An Early I/O demo design is programmed into on-board boot flash as the default pattern. With this pattern, LED0 (D3) (mapped an early I/O) immediately turns on as soon as 12 V power is supplied to the board. After about two seconds, as configuration is successfully completed, DONE LED (D18) lights, and LED2 (D5) and LED3 (D6) light alternately in a heartbeat pattern. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 11 CrossLink-NX Evaluation Board User Guide 2. Jumpers and Test Connection Current Measurement 2 Pin Header (J3-J5, J32, and J40) Serdes Test 125 MHz/200 MHz Ref CLK Selection (J13) Current Measurement 2 Pin Header (J7-J9) VCCIO0 Power Selection (J44) FTDI Reset (JP1) FTDI OSC Reset (JP2) VCCIO6 Power Selection (J33) Current Measurement 2 Pin Header (J28-J30, and J37) Raspberry Pi Conn Power (JP3 and JP4) ADC Test Selection (J21, J22, and J24-J26) Current Measurement 2 Pin Header (J34-J36, J41-J43, J23, J31, and J38) FMC VADJ 1.8 V, 2.5 V, and 3.3 V Selection (J6-J8) Figure 2.1. Top View of CrossLink-NX Evaluation Board - Jumper Locations (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Table 2.1. Jumper Table Part JP1 JP2 Description FTDI Reset Jumper FTDI Oscillator Jumper JP3 Raspberry Pi Connector Power JP4 Raspberry Pi Connector Power JP6, JP7, and JP8 VADJ Selection Jumper For FMC LPC Carrier Connector J13 125 MHz / 200 MHz OSC Selection Jumper ADC_REFP0 Selection Jumper ADC_REFP1 Selection Jumper ADC_DN0 Selection Jumper ADC_DP0 Selection Jumper J21 J22 J24 J25 J44 J33 J3,J4,J5,J7,J8,J9, J23,J28,J29,J30, J31,J32,J34,J35, J36,J37,J38,J40, J41,J42, and J43 VCCIO0 Supply Voltage Selection Jumper VCCIO6 Supply Voltage Selection Jumper Current Measurement 2 Pin Header Setting Default Open (active FTDI)/Short (reset FTDI) Default Short (12 MHz OSC connected)/Open (12 MHz OSC unconnected) Default Open (Raspberry Pi self-power)/Short (3.3v applies Paspberry Pi connector ) Default Open (Raspberry Pi self-power)/Short (5.0v applies Paspberry Pi connector ) NO Jumper -> 1.5 V (JP6, JP7, and JP8 open) Only JP8* Short -> 1.8 V Only JP7* Short -> 2.5 V Only JP6* Short -> 3.3 V Default 1-2 (125 MHz)/2-3 (200 MHz) Default 1-2 (V1P8_ADC_VREF)/2-3 (J26 connector Input Voltage) Default 1-2 (V1P8_ADC_VREF)/2-3 (J26 connector Input Voltage) Default 1-2 (Disable), 2-3 (J26 connector) To select POT, wire jumper: J24-1 to J25-2 and J24-2 to J25-1. Default 1-2 (3.3 V)/2-3 (1.8 V) Default 1-2 (3.3 V)/2-3 (1.8 V) -- *Note: Only one jumper at a time. Otherwise, damage could occur. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 13 CrossLink-NX Evaluation Board User Guide 3. Power Scheme The CrossLink-NX Evaluation Board has most of its power supplied by onboard regulators powered by an external 12 V power. Refer to Appendix A. CrossLink-NX Evaluation Board Schematics to see the details of these power supply options. Figure 3.1 shows the high-level power supply architecture of the board. Table shows the voltage options available for the various VCCIO supplies. +12.0 V F P GA Me z za ni ne Card (F MC ) Low P in Count (LP C) (U9) 12 V V3P3 S W - 3 A ( U 1 0) 1.5V/1.8V/2.5V/3.3V VCC_CORE_1P0 LDO (U14) VADJ V1P0_LDO +1.0 V LDO (U12) V3P3 +3.3 V V1P2 +1.2 V V2P8 +2.8 V Camera (CN1) LDO (U11) V1P8_LDO V1P8 +1.8 V V1P8_LDO VCC_CORE_V1P0 V1P8_DPHY V1P8_VCCAUX V1P0_LDO V1P0_DPHY V3P3 VCCIO7 V3P3/ V1P8 VCCIO6 V5P0 +5.0 V LDO (U13) SW (U1 5) SW (U1 6) +1.0 V 3.3 V VCC V1P8_LDO V1P8_VCCPLLSD0 V1P0_LDO V1P0_VCCSD0 VCCIO0 S erde s LIFCL-40 (U3) V3P3/V1P8 VCCIO1 V3P3 VCCIO2 V3P3 V1P8_VCCADC18 VCCIO5 VCCIO4 VCCIO3 V1P8 V1P8 V1P8 V1P8_LDO ADC V1P8_LDO +1.8 V FTDI (U1) Raspberry (JP5) Figure 3.1. Board Power Scheme Table 3.1. CrossLink-NX VCCIO Supply Options VCCIO Bank VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 Selection J44 Connector -- -- -- -- -- J42 Connector -- V3P3 Default Fixed Fixed N/A N/A N/A Default Fixed V1P8 Selectable N/A N/A Fixed Fixed Fixed Selectable N/A (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 4. Programming and I2C The JTAG/SPI programming architecture and I2C interface of the CrossLink-NX Evaluation Board is shown in Figure 4.1. DNI3 Raspberry Pi (JP5) FT2232H (U1) I2C Port 1 Mini USB (J2) UART (DNI ) rst# Port 0 SPI Flash (U6) LIFCL (U3) 2 SPI Header (J20) JTAG Notes: 1. Via DNI 0 2. Via DNI 0 3. Via DNI 0 JP1 JTAG Header (J1) DNI1 resistors R35, R36, R37 and R38 resistors R15 and R17 resistors R39 and R40 Raspberry Pi (JP5) Figure 4.1. Configuration and I2C Architecture 4.1. JTAG Download Interface The CrossLink-NX Evaluation Board has a built-in download controller for programming the CrossLink-NX device. It uses an FT2232H Future Technology Devices International (FTDI) part to convert USB to JTAG. To use the built-in download cable, connect the USB cable from a PC with Radiant Programmer tool installed to the mini USB connector on the board (J2). A mini USB to USB-A cable is included in the CrossLink-NX Evaluation Kit. The USB hub on the PC detects the cable of the USB function on Port 0, making the built-in cable available for use with the Radiant programming software. 4.2. Alternate JTAG Download Interface J1 is an 8-pin standalone JTAG header used with an external Lattice download cable that is available separately, when the FTDI part is disabled from the JTAG chain after setting the JP1 jumper. A USB download cable can be attached to the board using J1 to interface with the CrossLink-NX. For details on the connection between the USB download cable and J1, refer to Programming Cable User's Guide (FPGA-UG-02042). J1 can also be used as test point when USB to JTAG is working. Additionally, you can enable the JTAG access path through the Raspberry Pi header (JP5) for customer applications. This is done by connecting the JP5 header to the J1 header through some onboard resistors. The JTAG connections between J1 and JP5 are listed in Table . Table 4.1. JTAG Connections J1 Pin Number 1 2 3 4 5 6 7 8 JTAG Signal Name VCCIO1 TDO TDI -- -- TMS GND TCK CrossLink-NX Ball Location for JTAG -- F19 F17 -- -- F15 -- G18 Raspberry Pi Header (JP8) Pin Number -- 10 11 -- -- 12 -- 8 J1 to JP5 Isolation (Assembly) -- R36 (DNI) R38 (DNI) -- -- R37 (DNI) -- R35 (DNI) Raspberry Pi GPIO -- IO15 IO17 -- -- IO18 -- IO14 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 15 CrossLink-NX Evaluation Board User Guide 4.3. JTAG to MSPI Pass-through Interface The download controller can also access the JTAG to MSPI pass-through circuit that allows the slave SPI Flash to be erased, programmed, and read with Radiant Programmer. 4.4. SPI Flash Device Selection in Programmer The Flash device on this board is a Macronix MX25L12833F. Figure 4.2. SPI Flash Operation Dialog You may proceed with the Flash device programming by following the procedure in CrossLink-NX sysCONFIG Usage Guide (FPGA-TN-02099). (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 4.5. Other JTAG Configuration Pins The CrossLink-NX Evaluation Board provides test points for other JTAG configuration pins as shown in Table . Table 4.2. Other JTAG Signals Signal Name PROGRAMN INITN DONE CrossLink-NX Ball Location E11 D11 D12 Test Point -- TP10 TP12 Push Button SW5 -- -- For more information on CrossLink-NX JTAG and SPI programming, refer to CrossLink-NX sysCONFIG Usage Guide (FPGA-TN-02099). (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 17 CrossLink-NX Evaluation Board User Guide 5. CrossLink-NX Clock Sources The CrossLink-NX Evaluation Board has three options for the CrossLink-NX clock sources: Table 5.1. Clock Sources Clock Frequency 12 MHz 200 MHz 125 MHz Signal Name 12 MHz 200 MHz/200 MHz_n 125 MHz/125 MHz_n CrossLink-NX Ball Location L13 C12/ C11 C12/ C11 Clock Source U1 U5 U4 Comments JP2 installed. JP1 removed. Insert R65 & R66, remove R54 & R56 Insert R54 & R56, remove R65 & R66 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 6. Control Buses - I2C, UART, and SPI This section describes the topology of the various configuration and communication buses. 6.1. I2C The CrossLink-NX Evaluation Board uses the I2C bus to support CrossLink-NX configuration, and optionally to support Raspberry Pi communication. The global I2C bus has the signal names SDA and SCL and they are routed close to Raspberry Pi header as shown in Figure 4.1 and in more detail in Figure 6.1. Raspberry Pi connector is connected to a dedicated CrossLink-NX GPIO bank with a direct local I2C bus. Local I2C bus can optionally connect to the global I2C bus through resistors. The local I2C connections are summarized in Table . BDBUS1/2 SDA RASP_ID_SD FTDI 2232H (UI) BDBUS0 Bank6 (U3) SCL RASP_ID_SC Instantiated I 2C Resistors (R18, R19) SDA SCL Bank1 (U3) TXD_UART RXD_UART Figure 6.1. I2C Architecture and UART Options Table 6.1. I2C Global Bus Connections CrossLink-NX Bank 6 Component (Reference) Raspberry Pi header (JP5) Header Pin 27 28 CrossLink-NX 85 Ball M7 M4 Local Signal Name (Global I2C Signal) Resistor RASP_ID_SD (SDA) RASP_ID_SC (SCL) R40 (DNI) R39 (DNI) 6.2. UART Topology The board provides support for UART configuration by providing an uninstalled connection between the FTDI and CrossLink-NX. Two 0 resistors (R16 and R17) can be installed to connect Port 1 to two general purpose I/O (PR8A/F16 and PR10A/F18) in Bank 6 as shown in Figure 6.1. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 19 CrossLink-NX Evaluation Board User Guide 6.3. SPI Topology 6.3.1. SPI Configuration One of the major functions of SPI connections on the board is to support CrossLink-NX configuration from the SPI Flash or the Parallel Configuration Header. The CrossLink-NX Evaluation Board can support both Master SPI (MSPI) and Slave SPI (SSPI) modes for CrossLink-NX configuration. Table 6.2. CrossLink-NX SPI Connections Signal Name SPI_MCLK DQ0_MOSI DQ1_MISO CSSPIN DQ2 DQ3 MCSNO CrossLink-NX Ball E12 D13 D15 E13 D14 D16 E16 Parallel Configuration Header Pin 12 5 7 8 11 9 3 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 7. LEDs and Switches This section describes the CrossLink-NX Evaluation Board LEDs and switches that can be used in demo and customer designs. 7.1. DIP Switch Eight CrossLink-NX pins are connected to the SW1 DIP switch to allow for manually actuated inputs to the FPGA. One side of each switch is connected to GPIOs within the VCCIO2 bank and pulled up through 4.7 k resistors. The other side is grounded. The designated pins are connected as shown in Table . Table 7.1. Eight-Position DIP Switch Signals Signal Name SWITCH0 SWITCH1 SWITCH2 SWITCH3 CrossLink-NX Ball N14 M14 M16 M15 CrossLink-NX Bank 2 2 2 2 SWITCH4 SWITCH5 SWITCH6 SWITCH7 N15 N16 M17 M18 2 2 2 2 7.2. General Purpose Push Buttons The CrossLink-NX Evaluation Board provides three push button switches - SW2, SW3 and SW4 for demos and user applications. Two of the buttons control pre-defined functional pins, and the third is generic. Pressing these buttons drives a logic level "0" to the corresponding I/O pins. Table 7.2. Push Button Switch Signals Signal Name GSRN PROGRAMN PUSHBUTTON0 PUSHBUTTON1 CrossLink-NX Ball G19 E11 G14 G15 Push Button Reference SW4 SW5 SW2 SW3 Logic Level at Button Pressed 0 0 0 0 Information on PROGRAMN, refer to CrossLink-NX sysCONFIG Usage Guide (FPGA-TN-02099). SW2 is intended to be used as a global set/reset pin when active low, but can be substituted for another function if the user desires. SW2 and SW3 can be used as a generic input. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 21 CrossLink-NX Evaluation Board User Guide 7.3. General Purpose LEDs The CrossLink-NX Evaluation Board provides fourteen LEDs that are connected to I/O within Bank 1 & 0. The LEDs are lighted when the output is driven LOW. Table 7.3. General Purpose LED Signals Signal Name LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 CrossLink-NX Ball E17 F13 G13 F14 L16 L15 L20 L19 R17 R18 U20 T20 W20 V20 CrossLink-NX Bank / Color 1 (Green) 1 (Green) 1 (Green) 1 (Green) 1 (Green) 1 (Green) 1 (Green) 1 (Green) 2 (Green) 2 (Green) 2 (Green) 2 (Green) 2 (Yellow) 2 (Yellow) 7.4. Indicator LEDs Table lists various LEDs and describes their purpose. Table 7.4. Various LED Signals LEDs D1 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 Signal Name UART_ACT INITN DONE +12.0 V +5.0 V +3.3 V +2.8 V +1.2 V +1.8 V +1.0 V (VCC_CORE_V1P0) +1.8 V (V1P8_LDO) +1.0 V (V1P0_LDO) CrossLink-NX Ball F18 D11 D12 -- -- -- -- -- -- -- -- -- Color Green Red Green Green Green Green Green Green Green Green Green Green Purpose If installed, lights in UART mode Lights if configuration error Lights if successful configuration Lights if voltage present (external connection) Lights if voltage present Lights if voltage present Lights if voltage present Lights if voltage present Lights if voltage present Lights if voltage present Lights if voltage present Lights if voltage present (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 8. Headers/Connectors and LIFCL-40 Device Ball Mapping This section describes the CrossLink-NX Evaluation Board headers/connectors and ball mapping. 8.1. FMC LPC Connector Table 8.1. FMC LPC Header Pin Connections U9 Pin Name C1 C2 C3 C4 C5 C6 C7 Signal Name GND TXDP_FMC TXDN_FMC GND GND RXDP_FMC RXDN_FMC LIFCL-40 Ball -- -- -- -- -- -- -- U9 Pin Name D1 D2 D3 D4 D5 D6 D7 Signal Name PS_POR_B GND GND REFCLKP_FMC REFCLKN_FMC GND GND LIFCL-40 Ball -- -- -- -- -- -- -- C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 GND GND FMC_LA06_P FMC_LA06_N GND GND FMC_LA10_P FMC_LA10_N GND GND -- -- W9 Y9 -- -- W10 Y10 -- -- D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 FMC_LA01_CC_P FMC_LA01_CC_N GND FMC_LA05_P FMC_LA05_N GND FMC_LA09_P FMC_LA09_N GND FMC_LA13_P W13 V12 -- R5 R6 -- V6 U7 -- R9 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 FMC_LA14_P FMC_LA14_N GND GND FMC_LA18_CC_P FMC_LA18_CC_N GND GND FMC_LA27_P FMC_LA27_N GND GND FMC_SCL FMC_SDA GND GND GND 12V GND W11 Y11 -- -- R8 T8 -- -- Y13 Y14 -- -- -- -- -- -- -- -- -- D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 FMC_LA13_N GND FMC_LA17_P FMC_LA17_N GND FMC_LA23_P FMC_LA23_N GND FMC_LA26_P FMC_LA26_N GND FMC_TCK FMC_TDI FMC_TDO V3P3 FMC_TMS NO Connect GND V3P3 P9 -- U10 V10 -- P11 R11 -- T13 T14 -- -- -- -- -- -- -- -- -- C37 C38 12V GND -- -- D37 D38 GND V3P3 -- -- C39 C40 G1 V3P3 GND GND -- -- -- D39 D40 H1 GND V3P3 FMC_VREF -- -- T6 Y18 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 23 CrossLink-NX Evaluation Board User Guide U9 Pin Name G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 Signal Name FMC_CLK1_P FMC_CLK1_N GND GND FMC_LA00_CC_P FMC_LA00_CC_N GND FMC_LA03_P FMC_LA03_N GND FMC_LA08_P FMC_LA08_N GND FMC_LA12_P FMC_LA12_N GND FMC_LA16_P FMC_LA16_N GND FMC_LA20_P FMC_LA20_N GND FMC_LA22_P FMC_LA22_N LIFCL-40 Ball R7 T7 -- -- V11 U11 -- W6 Y6 -- Y7 Y8 -- U1 T1 -- P7 P8 -- T10 T11 -- V14 U14 U9 Pin Name H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 Signal Name FMC_PRSNT GND FMC_CLK0_P FMC_CLK0_N GND FMC_LA02_P FMC_LA02_N GND FMC_LA04_P FMC_LA04_N GND FMC_LA07_P FMC_LA07_N GND FMC_LA11_P FMC_LA11_N GND FMC_LA15_P FMC_LA15_N GND FMC_LA19_P FMC_LA19_N GND FMC_LA21_P LIFCL-40 Ball -- -- Y12 W12 -- Y2 Y3 -- V1 W1 -- W7 V7 -- P10 R10 -- W8 V9 -- U12 T12 -- P13 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 GND FMC_LA25_P FMC_LA25_N GND FMC_LA29_P FMC_LA29_N GND FMC_LA31_P FMC_LA31_N GND ADC_IN1P ADC_IN1N GND VADJ GND -- R12 P12 -- Y15 Y16 -- Y17 W17 -- -- -- -- -- -- H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 FMC_LA21_N GND FMC_LA24_P FMC_LA24_N GND FMC_LA28_P FMC_LA28_N GND FMC_LA30_P FMC_LA30_N GND VREF2_CON NO Connect GND VADJ R13 -- W14 W15 -- U15 V16 -- V17 U16 -- -- -- -- -- (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 8.2. Parallel FMC Configuration Header Table 8.2. Parallel FMC Configuration J27 Pin Connections J27 Pin Name Signal Name LIFCL-40 Ball 1 2 3 4 5 6 7 8 9 10 11 VCCIO2 VCCIO2 FMC_TCK PS_POR_B GND GND FMC_TDI FMC_PRSNT FMC_TDO FMC_SCL GND -- -- P19 N19 -- -- P20 N20 P17 M20 -- 12 13 14 GND FMC_TMS FMC_SDA -- P18 M19 8.3. Raspberry Pi Board GPIO Header The CrossLink-NX Evaluation Board provides a 40-pin receptacle which is compatible with the GPIO header of Raspberry Pi 2/3 serial models, or can be used for general purpose I/O. Table 8.3. Raspberry Pi JP8 Header Pin Connections JP5 Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal Name VSP3* RASP_5V* RASP_IO02 RASP_5V* RASP_IO03 GND RASP_IO04 RASP_IO14 GND RASP_IO15 RASP_IO17 RASP_IO18 RASP_IO27 GND RASP_IO22 RASP_IO23 VSP3* RASP_IO24 RASP_IO10 GND LIFCL-40 Ball -- -- L6 -- L5 -- M3 M2 -- L1 L2 R2 R1 -- P2 P1 -- K7 N4 -- 21 22 23 RASP_IO09 RASP_IO25 RASP_IO11 K6 K5 N7 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 25 CrossLink-NX Evaluation Board User Guide JP5 Pin Name 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Name RASP_IO08 GND RASP_IO07 RASP_ID_SD RASP_ID_SC RASP_IO05 GND RASP_IO06 RASP_IO12 RASP_IO13 GND RASP_IO19 RASP_IO16 RASP_IO26 RASP_IO20 GND RASP_IO21 LIFCL-40 Ball P6 -- N5 M7 M4 K8 -- L7 L8 M5 -- M6 N6 P5 R3 -- R4 *Note: 3.3 V and 5 V provide the power to the Raspberry Pi board when JP3 and JP4 are installed. When JP3 and JP4 are not installed, Raspberry Pi needs its own 3.3 V and 5 V power. When connecting directly to a Raspberry Pi board, depending on the individual setup, there may need to be an adapter to avoid mechanical interference between the two boards. A generic 40-pin (2x20), 100-mil spacing header extender serves this function. Alternately, the two boards can be connected by a length of ribbon cable with 2x20 connectors on either end. 8.4. Camera Connector Table 8.4. Camera CN1 Connector Pin Connections CN1 Pin Name 1 2 3 4 5 6 Signal Name NO Connect CAM0_CLKN CAM0_CLKP GND CAM0_3N CAM0_3P LIFCL-40 Ball -- B1 A2 -- B4 A4 7 8 9 10 11 12 13 14 15 16 17 GND CAM0_1N CAM0_1P GND CAM0_0N CAM0_0P GND CAM0_2N CAM0_2P GND GND -- B3 A3 -- C1 B2 -- D1 C2 -- -- 18 19 20 V2P8 NO Connect CAM0_MCLK -- -- -- (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide CN1 Pin Name 21 22 23 24 25 26 27 28 29 30 Signal Name NO Connect CAM_SDA CAM_SCL CAM_RESET V1P2 V1P8 GND GND V2P8 GND LIFCL-40 Ball -- W5 Y5 W18 -- -- -- -- -- -- J6 Pin Name 1 2 3 4 5 6 7 8 Signal Name GND GND DPHY1_CKP DPHY1_CKN GND GND DPHY1_DP0 DPHY1_DN0 LIFCL-40 Ball -- -- A8 B8 -- -- A7 B7 9 10 11 12 13 14 15 16 17 18 19 20 GND GND DPHY1_DP1 DPHY1_DN1 GND GND DPHY1_DP2 DPHY1_DN2 GND GND DPHY1_DP3 DPHY1_DN3 -- -- A9 B9 -- -- A6 B6 -- -- A10 B10 8.5. D-PHY1 Header Table 8.5. D-PHY1 J6 Header Pin Connections (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 27 CrossLink-NX Evaluation Board User Guide 8.6. PMOD Header The J17, J18 and J19 header can be used as GPIO or as a connector to a PMOD interface. Table 8.6. J17, J18 and J19 Header Pin Connections Pin Name J17 Pin Name 1 2 3 4 5 6 7 8 J18 Pin Name 1 2 3 4 5 6 7 8 J19 Pin Name 1 Signal Name LIFCL-40 Ball PMOD0_1 PMOD0_2 PMOD0_3 PMOD0_4 PMOD0_7 PMOD0_8 PMOD0_9 PMOD0_10 D10 D9 D7 D8 D6 D5 D4 D3 PMOD1_1 PMOD1_2 PMOD1_3 PMOD1_4 PMOD1_7 PMOD1_8 PMOD1_9 PMOD1_10 E10 E9 E7 E8 E4 E3 E2 F1 PMOD2_1 J2 2 3 4 5 6 7 8 PMOD2_2 PMOD2_3 PMOD2_4 PMOD2_7 PMOD2_8 PMOD2_9 PMOD2_10 J1 K2 K1 K3 K4 D17 E18 8.7. JTAG Header The J1 header is used to access the JTAG port of the CrossLink-NX or the Raspberry Pi interface. Table 8.7. J1 Header Pin Connections J1 Pin Name 1 2 3 4 5 6 7 Signal Name VCCIO1 TDO TDI No Connect No Connect TMS GND LIFCL-40 Ball -- F19 F17 -- -- F15 -- 8 TCK E19 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 8.8. Parallel Configuration Header The J27 header is used to access the SPI port of the CrossLink-NX. Table 8.8. J27 Header Pin Connections J27Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Signal Name VCCIO2 VCCIO2 FMC_TCK PS_POR_B GND GND FMC_TDI FMC_PRSNT FMC_TDO FMC_SCL GND GND FMC_TMS FMC_SDA LIFCL-40 Ball -- -- P19 N19 -- -- P20 N20 P17 M20 -- -- P18 M19 J26 Pin Name Signal Name LIFCL-40 Ball 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND GND J24 PIN3 GND J25 PIN3 GND GND GND ADC_IN1P GND ADC_IN1N GND GND GND VREF2_CON GND GND GND VREF1_CON GND -- -- -- -- -- -- -- -- T17 -- U17 -- -- -- -- -- -- -- -- -- 8.9. ADC Test Header Table 8.9. J26 Header Pin Connections (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 29 CrossLink-NX Evaluation Board User Guide 9. Software Requirements The following software versions are required to develop designs for the CrossLink-NX Evaluation Board: Lattice Radiant Software 2.0 or later Lattice Radiant Programmer 2.0 or later 10. Storage and Handling Static electricity can shorten the life span of electronic components. Observe these tips to prevent damage that can occur from electrostatic discharge: Use antistatic precautions such as operating on an antistatic mat and wearing an antistatic wristband. Store the development board in the provided packaging. Touch a metal USB housing to equalize voltage potential between you and the board. 11. Ordering Information Table 11.1. Ordering Information Description Ordering Part Number CrossLink-NX Evaluation Board LIFCL-40-EVN China RoHS Environment-Friendly Use Period (EFUP) (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Appendix A. CrossLink-NX Evaluation Board Schematics 5 4 3 2 1 D D CrossLink-NX Evaluation Board Rev - B-1 01 - Title page 02 - Block Diagram 03 - USB Interface C C 04 - Camera Interface (DPHYs) 05 - Raspberry Pi and User I/O Interface (Bank6) 06 - SERDES SMAs / Switches / FMC Control (Bank2) 07 - I2C LEDs and Push Buttons (Bank1) 08 - PMODs (Bank7) 09 - Configuration and ADC (Bank0) B B 10 - FMC-LPC (Bank3/4/5) 11 - Power CSI and Banks 12 - Power Decoupling 13 - Power Regulators 14 - Power Block Diagram A A Lattice Semiconductor Applications http://www.latticesemi.com/Support Notes: Resistors size 0402, tolerance 5%, unless otherwise specified. Ferrite Beads size 0402 unless otherwise specified. Capacitors >= 4.7uF size 0603 unless otherwise specified. Capacitors < 4.7uF size 0402 unless otherwise specified. 5 Title Title page Size B Date: 4 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev 1 of 14 B 1 Figure A.1. Title Page (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 31 CrossLink-NX Evaluation Board User Guide 5 4 3 2 1 Camera (Page 4) Header D SMAs (Page 6) QUAD SPI Flash (Page 9) D Power Regulators (Page 11,12,13) DPHY0 DPHY1 Serdes Bank 0 USB/FTDI JTAG I2C (Page 3) C PMOD X3 (Page 8) B Bank 1 Bank 7 Raspberry Pi and User I/O (Page 5) Bank 6 Bank 2 ADC Bank 5 Bank 4 LEDs/ Buttons (Page 7) LEDs CrossLink-NX 400 caBGA C Switches/ Long Trace Loopback (Page 6) B POT (Page 3) Bank 3 A A Lattice Semiconductor Applications http://www.latticesemi.com/Support FPGA Mezzanine Card (FMC) Low Pin Count (LPC) (Page 10) Title Size B Date: 5 4 3 Block Diagram Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev 2 of 14 B 1 Figure A.2. Block Diagram (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 5 4 3 2 1 V3P3 V3P3 D C2 C3 C4 0.1uF 0.1uF 0.1uF 0.1uF 10uF C5 D L1 2 1 600ohm 500mA FT_VPLL VBUS_5V VCCIO1 4.7uF C6 R1 J1 VCC1_8FT 1 2 3 4 5 6 7 8 V3P3 C10 2 0.1uF 50 SHLD 49 7 8 DM DP Part Number = 1734035-2 V3P3 10uF C14 V3P3 R10 R11 R9 FT_RSTb 2.2K R12 R13 C15 VCC NU ORG VSS CS CLK DI DO 10K 1 2 3 4 10K 10K FT_EECS FT_EECLK FT_EEDATA 12K R16 0.1uF JP1 Reset FTDI Default Open JP1 JUMPER 3 FT_OSCI 13 X1 1 VBUS_5V 2 DM 3 VBUS NC2 D+ NC3 D- 6 5 DP 4 DM ESDR0502N-UDFN6 A G1 G2 {7} 12MHz 2 JP2 20 31 42 56 4 9 DM DP ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 RESET# REF EECS EECLK EEDATA BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 OSCI OSCO TEST FTDI High-Speed USB 4 FT2232H C17 18pF 7M-12.000MAAJ VREGOUT AGND DP GND 3 ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 VREGIN 10 1 2 C16 18pF D2 1 FT_OSCO 3 63 62 61 2 1 93LC56C-I/SN B FT_REF 6 12K 2 8 7 6 5 U2 14 VCCIO VCCIO VCCIO VCCIO 4 5 6 7 8 9 Header 1x8 DNI BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 PWREN# SUSPEND# R4 2.2K C 16 17 18 19 21 22 23 24 ADBUS0 ADBUS1 ADBUS2 ADBUS3 33 0 0 0 R5 R6 R7 R8 DNI 1.0 K R173 TCK {5,7} TDI {5,7} TDO {5,7} TMS {5,7} PROGRAMN 26 27 28 29 30 32 33 34 {9} VCCIO1 2K CASE CASE CASE CASE 0.1uF U1 FT2232HL VCC1_8FT VPHY VPLL NC GND C13 0.1uF 38 39 40 41 43 44 45 46 0 0 DNI R15 DNI R17 TXD_UART RXD_UART {7} {7} D1 VCCIO1 UART_ACT R18 4.7K 48 52 53 54 55 57 58 59 R19 4.7K 0 0 0 TP1 1 TP2 1 R20 R21 R22 SCL {5,7} SDA {5,7} B 60 36 GND GND GND GND GND GND GND GND C 2 3 C12 10K 1 5 11 15 25 35 47 51 DD+ 0.1uF V3P3 Route USB pair 90 ohm impedance VCORE VCORE VCORE C11 VBUS 12 37 64 J2 4.7K 4.7K 4.7K 1 2 3 4 5 6 7 8 R14 LED_GREEN_0603 4.7uF 600ohm 500mA 1 R172 G 1 FT_VPHY C9 VCC R2 R3 0.1uF L3 2 1 600ohm 500mA L2 0.1uF USB_MINI_B VCCIO0 C7 V3P3 C8 C1 1 A JUMPER Lattice Semiconductor Applications http://www.latticesemi.com/Support Title USB Interface Size B Date: 5 4 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev of 14 3 B 1 Figure A.3. USB Interface (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 33 CrossLink-NX Evaluation Board User Guide 5 4 3 2 V1P8 R23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC1 CLK_N CLK_P DGND1 DATA3_N DATA3_P DGND2 DATA1_N DATA1_P DGND3 DATA0_N DATA0_P DGND4 DATA2_N DATA2_P DGND5 DGND6 AF_VDD2V8 NC2 MCLK SYNC SDA SCL XCLR DVDD1V2 DVDD1V8 DGND7 DGND8 AVDD2V8 DGND9 CN1 D C V2P8 CAM0_CLKN CAM0_CLKP 1 22 CAM0_3N CAM0_3P R24 3 STDBY# VDD OSCILLATOR OUT GND 4 C20 0.1uF 2 C21 C18 C22 C19 C23 C24 1uF 0.1uF 10uF 0.1uF 1uF 0.1uF D ASE3-27.000MHz-K-T CAM0_1N CAM0_1P VCCIO5 CAM0_0N CAM0_0P CAM0_2N CAM0_2P R25 R26 4.7k 4.7k V2P8 LVDS RX Termination Resistors CAM0_MCLK CAM_SDA {10} CAM_SDA CAM_SCL CAM_SCL {10} CAM_RESET V1P2 V1P8 {10} CAM0_CLKN CAM0_0N CAM0_1N CAM0_2N CAM0_3N R27 100 ohm DNI CAM0_CLKP R28 100 ohm DNI CAM0_0P R29 100 ohm DNI CAM0_1P R30 100 ohm DNI CAM0_2P R31 100 ohm DNI CAM0_3P NOTE: Place close to FPGA NOTE: 1. Match length within pair <= 0.1mm, match length between pairs <=1.0mm. 2. Differential impedance should be 100 ohms and 50 ohms as a single ended signal 3. All the power rails should be capable of carrying 1A current 1 1 2 2 R32 C27 C28 0.1uF 10uF VCCADPHY0 VCCPLLDPHY0 VCCDPHY0 J4 1 2 D2 B5 R33 C4 C33 C34 0.1uF 10uF 0.1 1% 0603 1 LIFCL-40-BG400 V1P0_LDO 1 J5 1 2 C35 C36 0.1uF 10uF 0.1 1% 0603 2 L7 220ohm 500mA 0.1uF A8 B8 A7 B7 A9 B9 A6 B6 A10 B10 DPHY1_CKP DPHY1_CKN DPHY1_DP0 DPHY1_DN0 DPHY1_DP1 DPHY1_DN1 DPHY1_DP2 DPHY1_DN2 DPHY1_DP3 DPHY1_DN3 VCCADPHY1 VCCPLLDPHY1 1 2 L6 220ohm 500mA 1 2 L8 220ohm 500mA C26 10uF VCCDPHY1 C7 C9 C29 C5 0.1uF C30 10uF B LIFCL-40-BG400 C31 C32 10uF 2 V1P0_LDO 1 2 L9 220ohm 500mA J6 DPHY1_CKP DPHY1_DP1 A DPHY1_DP2 DPHY1_DP3 1 3 5 7 9 11 13 15 17 19 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 DPHY1_CKN DPHY1_DN0 DPHY1_DN1 A Lattice Semiconductor Applications http://www.latticesemi.com/Support DPHY1_DN2 DPHY1_DN3 Title Header_2x10 Camera Interface (DPHYs) Size B Date: 4 2 L4 220ohm 500mA V1P0_LDO DPHY1_CKP DPHY1_CKN DPHY1_DP0 DPHY1_DN0 DPHY1_DP1 DPHY1_DN1 DPHY1_DP2 DPHY1_DN2 DPHY1_DP3 DPHY1_DN3 DPHY1_DP0 5 1 U3J 0.1uF Header_2x1 R34 C25 2 L5 220ohm 500mA 2 Header_2x1 U3I DPHY0_CKP DPHY0_CKN DPHY0_DP0 DPHY0_DN0 DPHY0_DP1 DPHY0_DN1 DPHY0_DP2 DPHY0_DN2 DPHY0_DP3 DPHY0_DN3 V1P8_LDO 1 0.1 1% 0603 1 C V1P8_LDO J3 Header_2x1 A2 B1 B2 C1 A3 B3 C2 D1 A4 B4 V1P8 X2 Keep LEDs away from Camera CAM0_CLKP CAM0_CLKN CAM0_0P CAM0_0N CAM0_1P CAM0_1N CAM0_2P CAM0_2N CAM0_3P CAM0_3N V1P2 100k camconn_imx258_1x30 B 1 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev of 14 4 B 1 Figure A.4. Camera Interface (DPHYs) (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 5 4 3 2 1 Raspberry PI and User I/O Connector VCCIO6 V3P3 VCCIO6 VCCIO6 D PL24A PL24B PL26A PL26B PL27A PL27B PL30A/PCLKT6_0 PL30B PL32A/PCLKT6_1 PL32B PL34A/PCLKT6_2 PL34B PL36A PL36B PL38A PL38B PL40A PL40B PL42A PL42B PL44A PL44B PL46A PL46B PL47A PL47B PL49A PL49B NC44 (Default) NC45 Option NC46 NC47 Bank6 C 3.3v 1.8v K5 K6 K7 K8 L1 L2 L5 L6 L7 L8 M2 M3 M4 M5 M6 M7 N4 N5 N6 N7 P1 P2 P5 P6 R1 R2 R3 R4 N3 N2 N1 M1 RASP_IO25 RASP_IO09 RASP_IO24 RASP_IO05 RASP_IO15 RASP_IO17 RASP_IO03 RASP_IO02 RASP_IO06 RASP_IO12 RASP_IO14 RASP_IO04 RASP_ID_SC RASP_IO13 RASP_IO19 RASP_ID_SD RASP_IO10 RASP_IO07 RASP_IO16 RASP_IO11 RASP_IO23 RASP_IO22 RASP_IO26 RASP_IO08 RASP_IO27 RASP_IO18 RASP_IO20 RASP_IO21 V5P0 1 L3 P3 R36 DNI R38 DNI 0 0 TDO {3,7} TDI {3,7} JP3 & JP4 Power For J5 Default Open JP3 JUMPER JP4 2 D 1 JUMPER 2 U3G C38 R35 DNI 0 0 DNI R39 0 DNI R40 TCK {3,7} SCL {3,7} SDA C37 0.1uF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 RASP_IO02 RASP_IO03 RASP_IO04 {3,7} RASP_IO17 RASP_IO27 RASP_IO22 RASP_IO10 RASP_IO09 RASP_IO11 R37 DNI 0 TMS {3,7} RASP_ID_SD RASP_IO05 RASP_IO06 RASP_IO13 RASP_IO19 RASP_IO26 JP5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 0.1uF RASP_5V RASP_IO14 RASP_IO15 RASP_IO18 RASP_IO23 RASP_IO24 RASP_IO25 RASP_IO08 RASP_IO07 RASP_ID_SC C RASP_IO12 RASP_IO16 RASP_IO20 RASP_IO21 LIFCL-40-BG400 Receptacle 20X2 DNI VCCIO6 C39 C40 C41 C42 10uF 10uF 0.1uF 0.1uF Layout: SS: Put box around Prototype Area SS: Row and Column Letters/Numbers Close to FMC-LPC and JP5 B B Through Hole Prototype Area V1P8 V3P3 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 A AF1 AE1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 A Lattice Semiconductor Applications http://www.latticesemi.com/Support Title Raspberry Pi and User I/O Interface Size B Date: 5 4 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev 5 of 14 B 1 Figure A.5. Raspberry Pi and User I/O Interface (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 35 CrossLink-NX Evaluation Board User Guide 5 4 V1P8_LDO J7 1 2 Header_2x1 C13 B11 1 MPZ1005S121CT000 D 0.1 1% PLL filter with DCR<=0.1 ohm DC must be <<5% drop across anti-resonance resistor under worst case 0603 2 TP_V1P8_VCCPLLSD R42 1 FB1 3 2 C43 10uF C44 0.1uF J8 1 FB2 Ref_return_pll 2 2 B15 B13 Header_2x1 V1P0_LDO TP_V1P0_VCCSD R44 MPZ1005S121CT000 R45 1.15K R_ext R_ext is chosen for 100 ohm Diff VCCPLLSD0 VCCAUXSD SD0_REXT SD0_RXDP SD0_RXDN SD0_REFRET SD0_TXDP SD0_TXDN SD0_REFCLKP SD0_REFCLKN VCCSD0_1 VCCSD0_2 R_ext RXDPF R41 DNI 100 ohm RXDNF Ref_return_pll TXDPF TXDNF REFCLKP R43 DNI 100 ohm REFCLKN C14 A16 A15 B14 A13 A12 C12 C11 Use little to no stub between selection resistors LIFCL-40-BG400 0.1 1% Place PLL series resistor, two caps and r_ext right underneath the chip on the reverse side of the board U3L 1 Serdes Bank 1 1 0603 C45 C46 10uF 0.1uF C47 0.1uF REFCLKP V3P3 R46 0 R47 DNI 0 R48 DNI 0 R49 0 R51 DNI 0 R52 DNI 0 R55 0 R57 DNI 0 R58 0 R59 DNI 0 D OSCP REFCLKP_SMA REFCLKP_FMC {10} L10 2 REFCLKN R53 1 FB3 TP_V1P8_VCCAUXSD MPZ1005S121CT000 0.1 1% C51 10uF 0603 C C52 0.1uF R50 10K U4 C48 1 C49 0.1uF 2 OE 6 2 OP ON NC C50 4 125MHz R54 0 5 125MHz_N R56 0 RXDPF RXDP 0.1uF C53 RXDNF RXDN 0.1uF 3 Ref_return_pll VCCIO2 U3C VCCIO2 VCCIO2 PR24A PR24B PR26A PR26B PR27A PR27B PR30A/PCLKT2_0 PR30B PR32A/PCLKT2_1 PR32B PR34A/PCLKT2_2 PR34B PR36A PR36B PR38A PR38B PR40A PR40B PR42A PR42B PR44A PR44B PR46A PR46B PR47A PR47B PR49A PR49B NC27 NC26 NC29 NC28 Bank2 3.3v A N14 M14 M16 M15 N15 N16 M17 M18 M19 M20 N19 N20 P19 P20 P17 P18 R17 R18 U20 T20 W20 V20 T18 U18 V18 V19 W19 Y19 R19 R20 P15 P16 SWITCH0 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 LED8 LED9 LED10 LED11 LED12 LED13 short_stub_trace RN1G 6 4_7K 11 EXB2HV472JV RN1F 3 4_7K 14 EXB2HV472JV RN1C 4 4_7K 13 EXB2HV472JV RN1D 1 C57 0.1uF OE 6 RN1B 7 4_7K 10 EXB2HV472JV C56 TXDNF AK5DAF1-200.0000T2 VCC 2 4_7K 15 EXB2HV472JV OP ON 2 NC DNI J13 4 200MHz R65 0 DNI 5 200MHz_N R66 0 DNI 2 3 4 5 REFCLKP_SMA R60 0 R61 DNI 0 R63 0 R64 DNI 0 J14 1 REFCLKN_SMA TP4 TP5 RXDP_FMC {10} C RXDN_FMC {10} TXDP_SMA TXDP_FMC {10} TXDN_SMA TXDN_FMC RXDP_SMA J12 2 3 4 5 1 {10} TXDP_SMA SMA DNI 2 3 4 5 J15 N14 M14 M16 M15 N15 N16 M17 M18 Signal SWITCH0 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 RXDN_SMA J16 2 3 4 5 SMA 1 TXDN_SMA SMA DNI Route SMA pairs as 100 ohm differential SWITCH 1 2 3 4 5 6 7 8 A Lattice Semiconductor Applications http://www.latticesemi.com/Support Title Serdes SMAs/Switches/FMC Control Size B Date: 3 1 DNI Switch Signal Map U3C Pin SMD SW DIP-8 Part Number = 219-8MST 1 {10} RXDN_SMA SMA DNI Two 50 ohm Lookbacks Traces: 6 inches and 10 inches Place TPs close to FPGA 4 J11 SMA SWITCH0 SWITCH1 SWITCH2 SWITCH3 SWITCH4 SWITCH5 SWITCH6 SWITCH7 10_inch_long_trace REFCLKN_FMC RXDP_SMA B 2 3 4 5 Minimize length as short as possible short_stub_trace. TP close to FPGA REFCLKN_SMA DNI LIFCL-40-BG400 5 2 3 4 5 SMA DIP SWITCH 6_inch_long_trace 1 TXDN 0.1uF DNI 1-2 = 125 Mhz (Default) 2-3 = 200 Mhz CON3 J10 SW1 FMC_SDA {10} FMC_SCL {10} PS_POR_B {10} FMC_PRSNT {10} FMC_TCK {10} FMC_TDI {10} FMC_TDO {10} FMC_TMS {10} LED8 {7} LED9 {7} LED10 {7} TP3 LED11 {7} LED12 {7} LED13 {7} TXDP 0.1uF C55 U5 1 U19 N17 RN1E 1 B 5 4_7K 12 EXB2HV472JV R62 10K GND C60 0.1uF RN1A 1 C59 0.1uF 10uF 1 4_7K 16 EXB2HV472JV 3 C58 RN1H C54 TXDPF OSCN 3 2 1 VCCIO2 8 4_7K 9 EXB2HV472JV OSCP V3P3 L11 2 1 600ohm 500mA 1UF-16V-0805SMT VCCIO2 OSCN AK5DAF1-125.0000T2 VCC 1 Header_2x1 GND J9 1UF-16V-0805SMT 1 V1P8_LDO 2 1 600ohm 500mA Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev of 14 6 B 1 Figure A.6. SERDES SMAs/Switches/FMC Control (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 5 4 3 2 1 VCCIO1 VCCIO1 D 2 4 1 3 LEDs Signal Map R70 100 PUSHBUTTON0 2 4 TP6 1 3 SW4 GSRN GSRN R71 100 PUSHBUTTON1 2 4 TP8 R69 10k R68 SW3 PB1 10k U3B pin Signal 10k R67 SW2 PB0 VCCIO1 1 3 R72 100 GSRN LED0 D3 F13 LED1 D4 G13 LED2 D5 F14 LED3 D6 L16 LED4 D7 L15 LED5 D8 L20 LED6 D9 L19 LED7 D10 D TP7 C63 10nF C61 10nF LED E17 C62 10nF VCCIO1 C LEDs VCCIO1 LED_GREEN_0603 J18 G17 U3B VCCIO1 VCCIO1 VCCIO1 C64 C65 C66 10uF 0.1uF 0.1uF B Bank1 3.3v A PR3B PR4A PR4B PR6A PR8A PR10A PR11A/SDA PR11B/SCL PR13B/PMU_WAKEUP PR15A PR15B PR17A/PCLKT1_2 PR17B PR19A/PCLKT1_1 PR19B PR20A/PCLKT1_0 PR20B NC5 NC4 NC3 NC2 NC1 NC25 NC6 NC13 NC18 NC7 NC8 NC17 NC16 NC9 NC10 NC11 NC12 NC14 NC15 NC19 NC20 NC21 NC22 NC23 NC24 JTAG_EN/JTAG PR13A/TCK/SCLK/PMU_EXT_CLK PR6B/TMS/SCSN PR8B/TDI/SSI PR10B/TDO/SSO E17 F13 G13 F14 F16 F18 E20 F20 G19 G14 G15 L13 L14 L16 L15 L20 L19 J15 H15 H14 H13 G20 H18 J16 H16 H17 J19 J20 H20 H19 K13 J13 K14 J14 K15 K16 K17 K18 K19 K20 L18 L17 E19 G18 F15 F17 F19 LED0 LED1 LED2 LED3 LED_GREEN_0603 G G G LED_GREEN_0603 TXD_UART RXD_UART SDA {3,5} SCL {3,5} R73 R74 GSRN PUSHBUTTON0 PUSHBUTTON1 12MHz TP9 LED_GREEN_0603 {3} LED4 LED5 LED6 LED7 LED_GREEN_0603 R175 2K R0402 R176 2K R0402 R177 2K R0402 U3C pin Signal G G G LED_GREEN_0603 R178 2K R0402 R179 2K R0402 D7 D8 R17 LED8 D11 R18 LED9 D12 U20 LED10 D13 T20 LED11 D14 W20 R180 2K R0402 R181 2K R0402 LED12 D15 V20 LED13 D16 D9 D10 VCCIO2 {6} LED8 {6} LED9 {6} LED10 {6} LED11 LED8 LED_GREEN_0603 LED9 LED_GREEN_0603 LED10 LED_GREEN_0603 LED11 LED_GREEN_0603 G G G G R182 2K R0402 R183 2K R0402 R184 2K R0402 R185 2K R0402 B D11 D12 D13 D14 VCCIO2 VCCIO1 {6} LED12 {6} LED13 LED12 LED_YELLOW_0603 LED13 LED_YELLOW_0603 G G R186 2K R0402 R187 2K R0402 D15 D16 Group LEDs 4,4,4,2 12bit ADC shown groups of 4 + 1 led for PWM brightness + 1 led for other use R75 1k TCK {3,5} TMS {3,5} TDI {3,5} TDO {3,5} A Lattice Semiconductor Applications http://www.latticesemi.com/Support Title I2C LEDs And Push Buttons LIFCL-40-BG400 Size B Date: 5 C LED D6 G LED_GREEN_0603 R0402 D5 LED_GREEN_0603 {3} {3} 2K D4 G 0 0 R174 D3 4 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev of 7 14 B 1 Figure A.7. I2C LEDs and Push Buttons (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 37 CrossLink-NX Evaluation Board User Guide 5 4 3 2 1 J17, J18 and J19 All Right-Angle PMOD connectors J17 D VCCIO7 PMOD0_1 D10 PMOD0_2 D9 PMOD0_3 D7 PMOD0_4 D8 PMOD0_7 D6 PMOD0_8 D5 PMOD0_9 D4 PMOD0_10 D3 PMOD1_1 E10 PMOD1_2 E9 PMOD1_3 E7 PMOD1_4 E8 PMOD1_7 E4 PMOD1_8 E3 PMOD1_9 E2 PMOD1_10 F1 PMOD2_1 J2 PMOD2_2 J1 PMOD2_3 K2 PMOD2_4 K1 PMOD2_7 K3 PMOD2_8 K4 F8 F7 F6 F5 F4 F3 F2 G2 G1 G8 H8 H7 H6 H5 G7 G6 H2 H1 G5 G4 J8 J7 G3 J6 J5 J4 J3 J18 PMOD0_1 1 7 PMOD0_7 PMOD1_1 1 7 PMOD1_7 PMOD0_2 2 8 PMOD0_8 PMOD1_2 2 8 PMOD1_8 PMOD0_3 3 9 PMOD0_9 PMOD1_3 3 9 PMOD1_9 PMOD0_4 4 10 PMOD0_10 PMOD1_4 4 10 PMOD1_10 5 11 6 12 PMOD 2x6 VCCIO7 5 11 6 12 PMOD 2x6 C67 0.1uF VCCIO7 C72 0.1uF C J19 PMOD2_1 1 7 PMOD2_7 PMOD2_2 2 8 PMOD2_8 PMOD2_3 3 9 PMOD2_4 4 10 5 11 6 12 PMOD 2x6 PMOD2_9 PMOD2_10 {9} {9} VCCIO7 C73 0.1uF B U3H PL3A/ULC_GPLL0T_IN PL3B/ULC_GPLL0C_IN PL4A PL4B PL6A PL6B PL8A PL8B PL10A PL10B PL11A PL11B PL13A PL13B PL15A PL15B PL17A/PCLKT7_2 PL17B PL19A/PCLKT7_1 PL19B PL20A/PCLKT7_0 PL20B NC61 NC48 NC49 NC50 NC51 NC64 NC65 NC52 NC53 NC54 NC55 NC56 NC57 NC58 NC59 NC60 NC62 NC63 NC66 NC67 NC68 NC69 NC70 NC71 NC72 NC73 NC74 VCCIO7 VCCIO7 E5 H3 D VCCIO7 C68 C69 C70 C71 10uF 10uF 0.1uF 0.1uF C Bank7 3.3v B LIFCL-40-BG400 PMOD2 unavailable when Bank0 / Flash set to 1.8V A A Lattice Semiconductor Applications http://www.latticesemi.com/Support Title PMODs Size B Date: 5 4 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev of 8 14 B 1 Figure A.8. PMODs (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 5 4 3 VCCIO0 C75 10uF 0.1uF U3A VCCIO0 D11 E11 D12 PT74A/INITN PT74B/PROGRAMN PT76B/DONE E12 E13 CSSPIN 33 DQ0_MOSI D13 DQ1_MISO D15 D14 DQ2 D16 DQ3 PT76A/MCLK/PCLKT0_0 PT78A/MCSN/PCLKT0_1 PT78B/MOSI/MD0 PT80A/MISO/MD1 PT80B/MD2 PT82A/MD3 D Bank0 E16 E18 D17 PT82B/MCSNO/MSDO PT84A PT84B 3.3v INITN PROGRAMN DONE R78 {3} Parallel / SPI Config Header INITN indicator will light R76 if an error occurs during 10k configuration programming SPI_MCLK R79 2.0k R77 100 PROGRAMN D17 R INITN MCSNO PMOD2_10 {8} PMOD2_9 {8} D18 1 3 R80 100 C76 10nF INITN 2 4 6 8 10 12 14 FLASH_CS DONE INITN CSSPIN 2 4 6 8 10 12 14 VCCIO0 SPI_MCLK D DNI Place close to Flash VCCIO0 R82 10k R83 1 Q1 2N2222/SOT23 J20 1 3 5 7 9 11 13 Header_2x7 DONE indicator will light when configuration is successfully completed 3 G LIFCL-40-BG400 1 PROGRAMN 3 MCSNO DQ0_MOSI 5 DQ1_MISO 7 9 DQ3 11 DQ2 13 SW5 PROGRAMN 2 4 TP10 LED_RED_0603 2.0k E15 C74 1 PROGRAMN R81 LED_GREEN_0603 VCCIO0 2 VCCIO0 VCCIO0 10k DONE VCCIO0 2 DONE 128 Mb SPI Flash TP12 R84 4.7k CSSPIN R88 0 DQ1_MISO R89 DQ2 R91 0 0 R86 1k R85 4.7k FLASH_CS C77 10nF VCCIO0 U6 C 1 2 3 4 C79 20pF DNI CS# S0/SIO1 W#/SIO2 GND VCC RESET#/SIO3 SCLK SI/SIO0 C78 0.1uF R87 4.7k DNI C 8 7 6 5 R90 R92 0 DQ3 SPI_MCLK DQ0_MOSI 0 MX25L12833FM2I-10G V1P8_ADC_VREF VREF1_CON 3 C82 1uF 1 C84 0.1uF 1 B V1P8_LDO FB4 J23 1 2 U7 IN EN FILTER GND 1 2 3 C83 2 R93 2.2k R94 R15 C86 0.1uF R14 U3K J22 J22: 1-2 V1P8_ADC_VREF (Default) 2-3 J26 connector input 1.8v ADC_REFP0 ADC_REFP1 ADC_DP0 ADC_DN0 VSSADC ADC_DP1 ADC_DN1 LIFCL-40-BG400 N13 P14 T16 R16 T17 U17 R95 1 2 3 100 V1P8_VCCADC18 10K POT J24 ADC_IN0 R96 A_IN0 B U8 PTD901-1015K-B103 2 1K CON3 C87 C88 1600pF 1600pF DNI 1 2 3 {10} {10} A C89 C90 1600pF 1600pF DNI R98 100 R99 100 ADC_IN1P ADC_IN1N {10} VREF2_CON VREF1_CON J24 1 = 10K POT J24 2 = ADC_DN0 J24 3 = J26-3 Connector J25 J25 1 = GROUND J25 2 = ADC_DP0 J25 3 = J26-5 Connector CON3 R97 100 1 3 5 7 9 11 13 15 17 19 J26 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 To select POT, wire jumper: J24-1 to J25-2 J24-2 to J25-1 2 4 6 8 10 12 14 16 18 20 A Lattice Semiconductor Applications http://www.latticesemi.com/Support Title Configuration and ADC Size B Header_2x10 Keep noisy signals away from ADC circuit Date: 5 4 C81 20pF DNI VREF2_CON 1 2 3 VCCADC18 C80 20pF DNI J21: 1-2 V1P8_ADC_VREF (Default) 2-3 J26 connector input CON3 V1P8_VCCADC18 C85 10uF J21 CON3 0.1uF MAX6070BAUT18+T MPZ1005S121CT000 0.1 1% OUTS 5 2 Header_2x1 0603 OUTF 6 3 1 4 1 L12 2 1 600ohm 500mA 2 V3P3 3 Project CrossLink-NX Evaluation Board Monday, Jul 20, 2020 2 Sheet Schematic Rev B-1 Board Rev 9 14 of B 1 Figure A.9. Configuration and ADC (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 39 CrossLink-NX Evaluation Board User Guide 5 4 VCCIO5 C FMC_LA27_P FMC_LA27_N FMC_SCL FMC_SDA FMC_SCL FMC_SDA +12.0V VCCIO4 V3P3 GND C94 10uF C95 C96 0.1uF FMC_LA16_P FMC_LA16_N FMC_LA20_P FMC_LA20_N FMC_LA22_P FMC_LA22_N FMC_LA25_P FMC_LA25_N FMC_LA29_P FMC_LA29_N FMC_LA31_P FMC_LA31_N {9} {9} ADC_IN1P ADC_IN1N GND R171 1.0k 0.1uF ASP-134603-01 ASP-134603-01 VADJ VCCIO3 10uF 0.1uF 0.1uF U3F VCCIO5 B 1.8v VCCIO4 VCCIO4 Bank4 1.8v A PB16A/VREF4_1 PB16B PB18A/PCLKT4_3 PB18B/PCLKC4_3 PB20A PB20B PB22A PB22B PB24A/PCLKT4_2 PB24B/PCLKC4_2 PB26A PB26B PB28A PB28B PB30A PB30B PB32A PB32B PB34A PB34B PB36A PB36B PB38A PB38B PB40A/PCLKT4_1 PB40B/PCLKC4_1 PB42A PB42B PB44A/PCLKT4_0 PB44B/PCLKC4_0 PB46A PB46B/VREF4_2 T6 U6 R7 T7 V6 U7 W6 Y6 W7 V7 P7 P8 R8 T8 Y7 Y8 R9 P9 P10 R10 W8 V9 W9 Y9 T10 T11 U10 V10 W10 Y10 P11 R11 FMC_VREF FMC_CLK1_P FMC_CLK1_N FMC_LA09_P FMC_LA09_N FMC_LA03_P FMC_LA03_N FMC_LA07_P FMC_LA07_N FMC_LA16_P FMC_LA16_N FMC_LA18_CC_P FMC_LA18_CC_N FMC_LA08_P FMC_LA08_N FMC_LA13_P FMC_LA13_N FMC_LA11_P FMC_LA11_N FMC_LA15_P FMC_LA15_N FMC_LA06_P FMC_LA06_N FMC_LA20_P FMC_LA20_N FMC_LA17_P FMC_LA17_N FMC_LA10_P FMC_LA10_N FMC_LA23_P FMC_LA23_N V15 U13 TP13 U3D VCCIO3 VCCIO3 VCCIO3 C108 10uF C106 C107 0.1uF 0.1uF VCCIO2 1 3 5 7 9 11 13 FMC_TCK FMC_TDI FMC_TDO FMC_TMS 1.8v J27 1 3 5 7 9 11 13 2 4 6 8 10 12 14 2 4 6 8 10 12 14 PS_POR_B FMC_PRSNT FMC_SCL FMC_SDA Header_2x7 DNI LIFCL-40-BG400 PB54A/PCLKT3_0/VREF3_1/ADC_CP5 PB54B/PCLKC3_0/ADC_CN5 PB56A/ADC_CP7 PB56B/ADC_CN7 PB58A/PCLKT3_1/ADC_CP6 PB58B/PCLKC3_1/ADC_CN6 PB60A/ADC_CP9 PB60B/ADC_CN9 PB62A/ADC_CP10 PB62B/ADC_CN10 PB64A/ADC_CP4 PB64B/ADC_CN4 PB66A/COMP1IP PB66B/COMP1IN PB68A/ADC_CP8 PB68B/ADC_CN8 PB70A/COMP2IP PB70B/COMP2IN PB72A/PCLKT3_2/ADC_CP13 PB72B/PCLKC3_2/ADC_CN13 PB74A/PCLKT3_3/ADC_CP14 PB74B/PCLKC3_3/ADC_CN14 PB76A/COMP3IP PB76B/COMP3IN PB78A/ADC_CP11 PB78B/ADC_CN11 PB80A/ADC_CP12 PB80B/ADC_CN12 PB82A/ADC_CP15 PB82B/ADC_CN15 PB84A/LRC_GPLL0T_IN PB84B/LRC_GPLL0C_IN/VREF3_2 Bank3 Parallel FMC CFG Header 4 FMC_LA12_P FMC_LA12_N FMC_LA04_P FMC_LA04_N FMC_LA02_P FMC_LA02_N FMC_LA05_P FMC_LA05_N U1 T1 V1 W1 Y2 Y3 R5 R6 Y5 W5 T5 U5 V5 T4 U4 V4 W4 Y4 T3 U3 T2 U2 V2 W2 CAM_SCL CAM_SDA {4} {4} C TP_VADJ LIFCL-40-BG400 {9} +12.0V 8 C97 C98 C99 1 0.1uF 5 3 C102 4 1uF W11 Y11 V11 U11 Y12 W12 W13 V12 U12 T12 R12 P12 Y13 Y14 V14 U14 P13 R13 W14 W15 T13 T14 Y15 Y16 U15 V16 V17 U16 Y17 W17 W18 Y18 U10 BD9D321EFJ VIN BOOT EN SW GND VREG SS FMC_LA14_P C105 FMC_LA14_N FMC_LA00_CC_P 3.3nF FMC_LA00_CC_N FMC_CLK0_P FMC_CLK0_N FMC_LA01_CC_P Use only below Jumpers: FMC_LA01_CC_N No Jumper 1.5V FMC_LA19_P FMC_LA19_N Only JP8 1.8V FMC_LA25_P Only JP7 2.5V FMC_LA25_N Only JP6 3.3V FMC_LA27_P FMC_LA27_N FMC_LA22_P FMC_LA22_N FMC_LA21_P FMC_LA21_N FMC_LA24_P FMC_LA24_N FMC_LA26_P FMC_LA26_N FMC_LA29_P FMC_LA29_N FMC_LA28_P FMC_LA28_N FMC_LA30_P FMC_LA30_N FMC_LA31_P FMC_LA31_N CAM_RESET Title CAM_RESET {4} FMC_VREF FB 7 C100 2.2uH SPM6530T-2R2M 6 0.1uF VADJ L13 R108 1.00k 1% 2 C101 0.1nF C103 C104 22uF 3 R109 1.02k 1% R110 2.55k 1% R111 750 1% R112 422 1% 22uF JP8 JP7 JP6 B A Lattice Semiconductor Applications http://www.latticesemi.com/Support FMC-LPC Size B LIFCL-40-BG400 Date: 5 D 9 U3E PB4A/CDR_RXP0/VREF5_1/ADC_CP0/COMP1P PB4B/CDR_RXN0/ADC_CN0/COMP1N PB6A/PCLKT5_0/CDR_RXP1/ADC_CP1/COMP2P PB6B/PCLKC5_0/CDR_RXN1/ADC_CN1/COMP2N PB8A/PCLKT5_1/LLC_GPLL0T_IN/ADC_CP3 PB8B/PCLKC5_1/LLC_GPLL0C_IN/ADC_CN3 PB10A/PCLKT5_2/ADC_CP2/COMP3P PB10B/PCLKC5_2/ADC_CN2/COMP3N PB12A/PCLKT5_3 PB12B/PCLKC5_3/VREF5_2 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 NC39 NC40 NC41 NC42 NC43 Bank5 VCCIO4 T9 V8 FMC_TDI 4.7K 4.7K 4.7K FMC_TDO FMC_TMS VCCIO5 V3 R105 2.2K 1 R107 4.7k FMC_LA12_P FMC_LA12_N C93 1 FMC_LA18_CC_P FMC_LA18_CC_N R106 4.7k FMC_LA08_P FMC_LA08_N C92 2 VCCIO2 FMC_LA03_P FMC_LA03_N VREF-A-M2C PRSNT-M2C_L GND CLK0-M2C_P CLK0-M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ2 R102R103R104 C91 JUMPER FMC_LA14_P FMC_LA14_N FMC_LA00_CC_P FMC_LA00_CC_N GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ1 GND R101 10k 1 FMC_LA10_P FMC_LA10_N FMC_CLK1_P FMC_CLK1_N {6} {6} FMC_VREF H1 FMC_PRSNT H2 H3 FMC_CLK0_P H4 FMC_CLK0_N H5 H6 FMC_LA02_P H7 FMC_LA02_N H8 H9 FMC_LA04_P H10 FMC_LA04_N H11 H12 FMC_LA07_P H13 FMC_LA07_N H14 H15 FMC_LA11_P H16 FMC_LA11_N H17 H18 FMC_LA15_P H19 FMC_LA15_N H20 H21 FMC_LA19_P H22 FMC_LA19_N H23 H24 FMC_LA21_P H25 FMC_LA21_N H26 H27 FMC_LA24_P H28 FMC_LA24_N H29 H30 FMC_LA28_P H31 FMC_LA28_N H32 H33 FMC_LA30_P H34 FMC_LA30_N H35 H36 H37 VREF2_CON H38 H39 GND H40 VADJ 2 FMC_LA06_P FMC_LA06_N PG_C2M GND GND GBTCLK0-M2C_P GBTCLK0-M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3V3AUX TMS TRST_L GA1 3V3 GND 3V3 GND 3V3 U9B JUMPER RXDP_FMC RXDN_FMC GND DP0-C2M_P DP0-C2M_N GND GND DP0-M2C_P DP0-M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12V0 GND 12V0 GND 3V3 GND G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 1 TXDP_FMC TXDN_FMC D1 PS_POR_B D2 D3 D4 REFCLKP_FMC D5 REFCLKN_FMC D6 D7 FMC_LA01_CC_P D8 FMC_LA01_CC_N D9 D10 FMC_LA05_P D11 FMC_LA05_N D12 D13 FMC_LA09_P D14 FMC_LA09_N D15 D16 FMC_LA13_P D17 FMC_LA13_N D18 D19 FMC_LA17_P D20 FMC_LA17_N D21 D22 FMC_LA23_P D23 FMC_LA23_N D24 D25 FMC_LA26_P D26 FMC_LA26_N D27 D28 FMC_TCK D29 FMC_TDI D30 FMC_TDO D31 D32 FMC_TMS D33 D34 D35 D36 D37 D38 D39 D40 2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 JUMPER {6} {6} VCCIO2 FMC_TCK R100 10k U9A EPAD D 1 10uF 25V 1206 {6} {6} 2 V3P3 PS_POR_B FMC_PRSNT {6} PS_POR_B {6} FMC_PRSNT {6} {6} 3 V3P3 FMC_TCK FMC_TDI FMC_TDO FMC_TMS FMC_TCK FMC_TDI FMC_TDO FMC_TMS 10uF 25V 1206 {6} {6} {6} {6} Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev 10 of 14 B 1 Figure A.10. FMC-LPC (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 40 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 5 4 3 2 1 +12.0V V1P8 V5P0 V1P2 V3P3 12VIN GOOD U11 3 C109 1.0uF OUT EN GND R114 2 5v C110 1.0uF R116 1.0k R113 R115 15k 3.3v 2.0k 4.7k Group LEDs together D LED_GREEN_0603 D19 5 G G EPAD D IN 1 LED_GREEN_0603 D20 G 4 LED_GREEN_0603 D21 NCP110AMX120TBG V3P3 V3P3 V3P3 R119 2.0k V2P8 V2P8 U12 G G LED_GREEN_0603 D23 R120 2.0k LED_GREEN_0603 D24 V1P8 R121 1.5k 3 V1P2 1 2.2k Q2 2N2222/SOT23 Q4 2N2222/SOT23 2 NCP110AMX280TBG R123 1 4.7k LED_GREEN_0603 D25 VCC_CORE_V1P0 3 C112 1.0uF 5 C 1.0v (CORE) LED_GREEN_0603 D22 1 2.2k Q3 2N2222/SOT23 R124 R122 C 2 2 G GND 3 EN 2.8v 1.8v 1.2v 1 EPAD OUT 2 3 C111 1.0uF IN G 4 R118 2.0k R117 2.0k V3P3 V1P8 CON3 1 2 2 VCCIO1 V3P3 1 Header_2x1 J30 1 2 2 VCCIO2 1 R127 R128 R129 0.1 1% 0603 0.1 1% 0603 0.1 1% 0603 V1P8 CON3 2 VCCIO3 2 V1P8 1 J35 1 2 2 VCCIO4 V1P8 Header_2x1 1 J36 2 2 VCCIO6 VCCIO7 J32 1 1 2 R125 2.0k 2 R130 R131 0.1 1% 0603 0.1 1% 0603 1 2 R126 2.0k 1.8v (LDO) Header_2x1 LED_GREEN_0603 V1P8_LDO D26 Q5 2N2222/SOT23 1.0v (LDO) LED_GREEN_0603 D27 1 4.7k R132 V1P0_LDO Q6 2N2222/SOT23 1 2.2k R133 B VCCIO5 2 Header_2x1 R134 R135 R136 0.1 1% 0603 0.1 1% 0603 0.1 1% 0603 1 TP_VCCIO0 VCCIO0 TP_VCCIO1 VCCIO1 VCCIO2 TP_VCCIO2 TP_VCCIO3 VCCIO3 1 1 Header_2x1 1 J34 1 Header_2x1 RPI / User I/O Voltage Select 1-2 3.3V (Default) 2-3 1.8V 1 1 V3P3 J31 1 2 3 Flash Voltage Select 1-2 3.3V (Default) 2-3 1.8V (Note PMOD2 unavailable) V1P8 V3P3 J33 Header_2x1 3 J29 2 1 G V3P3 3 VCCIO0 2 2 TP_VCCIO5 TP_VCCIO4 VCCIO4 VCCIO5 VCCIO6 TP_VCCIO6 TP_VCCIO7 VCCIO7 1 1 2 3 B 2 1 1 Header_2x1 1 J28 1 1 V3P3 J44 V3P3 G V3P3 A A Lattice Semiconductor Applications http://www.latticesemi.com/Support TP_V2P8 V2P8 Title Power CSI and Banks 1 V1P2 1 TP_V1P2 TP_V1P0_LDO V1P0_LDO 1 TP_V1P8_LDO V1P8_LDO 1 TP_VCC_CORE_V1P0 VCC_CORE_V1P0 1 1 TP_V1P8 V1P8 1 TP_V3P3 V3P3 1 TP_V5P0 V5P0 Size B Date: 5 4 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev 11 of 14 B 1 Figure A.11. Power CSI and Banks (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 41 CrossLink-NX Evaluation Board User Guide 5 4 VCC_CORE_V1P0 1 H9 K12 K9 1 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C123 10uF-16V-0603SMT 0.1uF C122 10uF-16V-0603SMT J37 10uF-16V-0603SMT C120 C121 0.1uF C119 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF U3O C118 2 Header_2x1 V1P8_LDO R137 H12 C124 0.1 1% 0603 C125 U3M NC75 NC76 NC77 NC78 NC79 NC80 NC81 B C129 C130 0.1uF C128 0.1uF 0.1uF 0.1uF V1P8_VCCAUX C126 C127 0.1uF C C131 1 J38 1 2 2 Header_2x1 V1P8_LDO R138 C132 C133 C134 10uF-16V-0603SMT LIFCL-40-BG400 FB5 MPZ1005S121CT000 10uF-16V-0603SMT N12 N10 N8 0.1uF VCCAUXH3 VCCAUXH4 VCCAUXH5 C117 10uF-16V-0603SMT VCCAUXA C116 0.1uF VCCAUX VCCAUX VCCAUX F12 J12 L12 N11 N9 F9 J9 L9 C115 0.1uF VCC VCC VCC VCC VCC VCC VCC VCC C114 0.1uF U3N 2 VCC_CORE = 1.0 V C113 D 3 0.1 1% 0603 FB6 MPZ1005S121CT000 VSSADPHY VSSADPHY VSSADPHY VSSADPHY VSSADPHY VSSADPHY VSSADPHY VSSSD3 VSSSD7 VSSSD2 VSSSD8 VSSSD12 VSSSD11 VSSSD10 VSSSD9 VSSSD1 VSSSD6 VSSSD4 VSSSD5 B20 C20 A19 A18 B18 C18 B17 LIFCL-40-BG400 NC82 NC83 1 N18 J17 Y20 T19 G16 E14 M13 W16 G12 M12 F11 G11 H11 J11 K11 L11 M11 F10 G10 H10 J10 K10 L10 M10 G9 M9 T15 M8 E6 V13 H4 L4 P4 W3 U9 U8 Y1 D C C10 C8 C6 A5 C3 E1 A1 A20 D20 B19 C19 D19 A17 C17 B16 C15 A14 B12 A11 B D18 C16 LIFCL-40-BG400 A A Lattice Semiconductor Applications http://www.latticesemi.com/Support Title Power Decoupling Size B Date: 5 4 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev 12 of 14 B 1 Figure A.12. Power Decoupling (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide 5 4 3 2 V1P8 1 V3P3 V1P0_LDO OUT EN GND +1.0 V 300 mA 1 2 C137 1uF 5 TP R141 1k C138 10uF 6 4 C136 1uF R142 10k 5 TLV73310PDQNT R147 0 DNI D R145 0 DNI VCC_CORE_V1P0 R149 Analog VCCA 1.0 V Power For DPHY And Serdes R156 1% 22uF,6.3V-0805SMT 200 -0603SMT 23 22 10 2 FB1 FB2 TRACK/SS2 VC1 VC2 PG1 PG2 D30 1N4448W 12 11 22uF,6.3V-0805SMT C168 22uF,6.3V-0805SMT 22uF,6.3V-0805SMT 10pF-0402SMT R169 768-0603SMT 1% 17 C145 20 R159 51K-0402SMT PG2 1 C159 19 20 DNI GND6 GND7 GND8 GND9 RT/SYNC 1000pF-0402SMT 2 17 R168 20K-0402SMT J43 1 2 2 Header_2x1 C R153 D32 DFLS220L 0.1 1% 0603 +3.3 V 1.35 A V3P3 R155 1.07K-0603SMT 1% R160 340-0603SMT 1% 1.2v/ms C153 C154 22uF,6.3V-0805SMT 22uF,6.3V-0805SMT B 1 2 2 Header_2x1 R163 4.7uH-SPD62R-472M D36 DFLS220L R1651% 1.15K-0603SMT 0.1 1% 0603 +1.8 V 1.1 A A V1P8 Lattice Semiconductor Applications http://www.latticesemi.com/Support C167 1.2v/ms 10pF-0402SMT R170 909-0603SMT 1% Freq = 625 KHz 4 1 C157 220NF-0402SMT 16V L17 18 1% Vout = 0.8*((R164/R169)+1) = 1.01 V J41 4.7uH-SPD62R-472M 1000pF-0402SMT 19 11 C163 330pF-0402SMT VC2 PG1 12 C162 10pF-0402SMT VC1 D34 1N4448W 1 VIN2 VIN1 FB2 TRACK/SS2 GND5 1.2v/ms 22 FB1 GND1 GND2 GND3 GND4 C164 23 1 V1P8 2 U16 LT3508EUF SW2 TRACK/SS1 MPZ1005S121CT000 0 Vout = 0.8*(R155/R160+1) = 3.32 V BOOST2 SW1 3 4 5 6 VCC_CORE_V1P0 A 24 DNI R167 63_4K-0402SMT R164 200-0603SMT 1% +1.0 V 1.35 A C161 10pF-0402SMT 2 D35 DFLS220L BOOST1 13 14 15 16 1 1000pF-0402SMT 2 C158 25 8 FB8 1.8 V 10 9 21 L16 4.7uH-SPD62R-472M SHDN 1 7 V1P8_LDO R150 DNI L15 18 RT/SYNC 2 2 C160 330pF-0402SMT 2 V1P8 Vout = 0.8*(R143/R148+1) = 1.81 V C143 220NF-0402SMT 16V 1 SW2 TRACK/SS1 +1.8 V 500 mA R144 1k C140 10uF D R148 909-0603SMT 1% VIN2 9 VIN1 SW1 Freq = 1.0 MHz R161 51K-0402SMT VCC_CORE_V1P0 C155 10uF,25V-1206SMT D33 C156 220NF-0402SMT 1N4448W 16V R166 30_1K-0402SMT 1 0.1 1% 0603 5 7 C139 1uF BD00IC0WHFV-GTR C148 10pF-0402SMT C152 1 J42 R162 C166 3 GND +12.0V Header_2x1 C165 R143 1.15K-0603SMT 1% V3P3 GND6 GND7 GND8 GND9 2 24 Vout = 0.8*(R154/R156+1) = 5.00 V 1 1000pF-0402SMT 2 BOOST2 GND5 C144 D31 DFLS220L R154 1.05K-0603SMT 1% 22uF,6.3V-0805SMT Core Power 1.0 V 2 EPAD U15 LT3508EUF 13 14 15 16 1 BOOST1 25 4.7uH-SPD62R-472M V5P0 C151 21 8 L14 1.2v/ms C150 22uF,6.3V-0805SMT 7 GND1 GND2 GND3 GND4 0.1 1% 0603 +5.0 V 1.1 A D29 1N4448W SHDN C142 16V 220NF-0402SMT R152 POWER INPUT 2 2 3 4 5 6 C B NC 1 3.3 V R151 51K-0402SMT 1% 2 R158 34K-0402SMT 1 Header_2x1 1 1 2 C146 330pF-0402SMT 1 J40 C141 10uF,25V-1206SMT RLP-134 R157 51K-0402SMT +11v to +16v V5P0 D28 SCHOTTKY/VISHAY-V12P10 K FB +12.0V 5.0 V F1251CT-ND 5A Fast-Blo SMT Socketed Fuse 2 Right angle mount, cable to board edge VO EN +12.0V F1 Male Power Jack 2.1mm 0 C147 10pF-0402SMT J39 PJ-002A 1 VCC DPHY, Serdes, ADC And VCCAUX Analog 1.8 V Power MPZ1005S121CT000 DNI 1 3 R146 0 DNI V1P0_LDO FB7 U13 2 3 IN 1 R140 10k U14 C149 330pF-0402SMT 4 C135 1uF V1P8_LDO C169 C170 22uF,6.3V-0805SMT 22uF,6.3V-0805SMT Vout = 0.8*((R165/R170)+1) = 1.81 V 3 Title Power Regulators Size B Date: Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev 13 of 14 B 1 Figure A.13. Power Regulators (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 43 CrossLink-NX Evaluation Board User Guide 5 4 3 2 1 +12.0 V V3P3 VADJ D V1P0_LDO +1.0 V V1P8_LDO V1P2 +1.2 V V2P8 +2.8 V Camera (CN1) LDO (U14) LDO (U11) LDO (U12) V3P3 +3.3 V V1P8_LDO VCC_CORE_V1P0 V1P8_DPHY V1P8_VCCAUX V1P0_LDO V1P0_DPHY V3P3 VCCIO7 V3P3/ V1P8 VCCIO6 V5P0 +5.0 V LDO (U13) S W (U 15 ) B S W (U 16 ) +1.0 V V1P8 +1.8 V 3.3 V S W- 3A ( U 1 0 ) 1 . 5 V/ 1 . 8 V / 2 . 5 V /3 . 3 V VCC_CORE_1P0 C FPGA Mezz ani ne Card (FMC) Low Pin Count (LP C) (U9) 12 V D VCC V1P8_LDO V1P8_VCCPLLSD0 V1P0_LDO V1P0_VCCSD0 VCCIO0 Serd es LIFCL-40 (U3) VCCIO1 V3P3 VCCIO2 V3P3 V1P8_VCCADC18 VCCIO5 VCCIO4 VCCIO3 V1P8 V1P8 V1P8 C V3P3/V1P8 V1P8_LDO ADC B V1P8_LDO +1.8 V FTDI (U1) A A Lattice Semiconductor Applications http://www.latticesemi.com/Support Title Power Block Diagram Raspberry (JP5) Size B Date: 5 4 3 Project CrossLink-NX Evaluation Board Friday, Nov 22, 2019 2 Sheet Schematic Rev B-1 Board Rev 14 of 14 B 1 Figure A.14. Power Block Diagram (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Appendix B. CrossLink-NX Evaluation Board Bill of Materials Item 1 2 3 4 Reference AG1,AF1,AE1,AD1,AC1, AB1,AA1,AG2,AF2,AE2, AD2,AC2,AB2,AA2,AG3, AF3,AE3,AD3,AC3,AB3, AA3,AG4,AF4,AE4,AD4, AC4,AB4,AA4,AG5,AF5, AE5,AD5,AC5,AB5,AA5, AG6,AF6,AE6,AD6,AC6, AB6,AA6,AG7,AF7,AE7, AD7,AC7,AB7,AA7,AG8, AF8,AE8,AD8,AC8,AB8, AA8,AG9,AF9,AE9,AD9, AC9,AB9,AA9,AG10,AF10, AE10,AD10,AC10,AB10, AA10,AG11,AF11,AE11, AD11,AC11,AB11,AA11 CN1 Qty 77 Part T POINT R PCB Footprint TP Comments DNL Part Number -- Manufacturer -- Description -- 1 camconn_imx258_1x30 camconn -- 24-5804-030-000-829+ Kyocera / Sunny Optical Sony IMX214 CSI Camera sensor C1,C2,C3,C4,C7,C8,C9, C11,C12,C13,C15,C18, C19,C20,C24,C25,C27, C29,C31,C33,C35,C37, C38,C41,C42,C44,C46, C47,C49,C50,C52,C53, C54,C55,C57,C59,C60, C65,C66,C67,C70,C71, C72,C73,C75,C78,C83, C84,C86,C92,C93,C95, C96,C99,C100,C106, C107,C113,C114,C115, C116,C117,C118,C119, C120,C124,C126,C127, C128,C129,C130,C131, C132 C5,C14,C22,C39,C40, C58,C64,C68,C69,C74, C91,C94,C108,C121, C122,C123,C125,C133, C134,C138,C140 73 0.1uF 0201 C0201 -- GRM033R61E104KE14J Murata CAP CER 0.1UF 25V 10% X5R 0201 21 10uF-0603SMT C0603 -- CL10A106MO8NQNC Samsung CAP CER 10UF 16V X5R 0603 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 45 CrossLink-NX Evaluation Board User Guide Item 5 Reference C6,C10 Qty 2 Part 4.7uF-0603SMT PCB Footprint C0603 Comments -- Part Number CL10A475KA8NQNC Manufacturer Samsung 6 C16,C17 2 18pF C0402 -- CL05C180JB5NNNC Samsung 7 12 1uF C0603 -- TMK107B7105KA-T Taiyo Yuden 10 10uF C0402 -- CL05A106MP8NUB8 Samsung 9 C21,C23,C82,C102, C109,C110,C111,C112, C135,C136,C137,C139 C26,C28,C30,C32,C34, C36,C43,C45,C51,C85 C48,C56 2 1UF-16V-0805SMT RLP-133 -- CL21B105KOFNNNG Samsung 10 C61,C62,C63,C76,C77 5 10nF RLP-130-A -- GRM155R61C103KA01D Murata 11 12 C79,C80,C81 C87,C89 3 2 20pF 1600pF RLP-132 C0805 DNL -- -- C0805C162J5GAC7800 -- Kemet 13 C88,C90 2 1600pF C0805 DNL C0805C162J5GAC7800 Kemet 14 C97,C98,C141,C155 4 10uF 25V 1206 C1206 -- TMK316BJ106KL-T Taiyo Yuden 15 C101 1 0.1nF C0603 -- CC0603JRNPO9BN101 Yageo 16 C103,C104 2 22uF C0603 -- GRM188R61A226ME15D Murata 17 C105 1 3.3nF C0201 -- GRM033R71E332KA12D Murata 18 C142,C143,C156,C157 4 220NF-0402SMT RLP-130-A -- CL05A224KO5NNNC Samsung 19 C144,C145,C158,C159 4 1000pF-0402SMT RLP-130-A -- CL05B102KB5NFNC Samsung 20 C146,C149,C160,C163 4 330pF-0402SMT RLP-130-A -- CL05B331KB5NNNC Samsung 21 C147,C148,C164,C167 4 10pF-0402SMT RLP-130-A -- CL05C100CB5NNNC Samsung 22 C150,C151,C152,C153,C 154,C165,C166,C168, C169,C170 C161,C162 10 22uF,6.3V-0805SMT RLP-133 -- CL21A226KPCLRNC Samsung 2 10pF-0402SMT RLP-130-A DNL -- -- 8 23 Description CAP CER 4.7UF 25V X5R 0603 CAP CER 18PF 50V C0G/NP0 0402 CAP CER 1UF 25V 10% X7R 0603 CAP CER 10UF 10V X5R 0402 CAP CER 1UF 16V X7R 0805 CAP CER 10000PF 16V X5R 0402 -- CAP CER 1600PF 50V NP0 0805 CAP CER 1600PF 50V NP0 0805 CAP CER 10UF 25V X5R 1206 CAP CER 100PF 50V C0G/NPO 0603 CAP CER 22UF 10V X5R 0603 CAP CER 3300PF 25V X7R 0201 CAP CER 0.22UF 16V X5R 0402 CAP CER 1000PF 50V X7R 0402 CAP CER 330PF 50V X7R 0402 CAP CER 10PF 50V C0G/NP0 0402 CAP CER 22UF 10V X5R 0805 -- (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Item 24 Reference Qty 23 Part LED_GREEN_0603 PCB Footprint APT1608 Comments -- Part Number 150060GS75000 Manufacturer Wurth Description 1 ESDR0502N-UDFN6 UDFN6_040 -- ESDR0502NMUTBG ON semi TVS DIODE 5.5VWM 6UDFN LED YELLOW CLEAR 0603 SMD LED RED CLEAR 0603 SMD DIODE SCHOTTKY 100V 12A TO277A DIODE GEN PURP 75V 150MA SOD323F DIODE SCHOTTKY 20V 2A POWERDI123 FERRITE BEAD 120 OHM 0402 1LN 25 D1,D3,D4,D5,D6,D7,D8, D9,D10,D11,D12,D13, D14,D18,D19,D20,D21, D22,D23,D24,D25,D26, D27 D2 26 D15,D16 2 LED_YELLOW_0603 APT1608 -- 150060YS75000 Wurth 27 D17 1 LED_RED_0603 APT1608 -- 150060RS75000 Wurth 28 D28 1 V12P10 -- V12P10-M3/86A Vishay 29 D29,D30,D33,D34 4 SCHOTTKY/VISHAYV12P10 1N4448W 1N4448W -- 1N4448WS On Semi 30 D31,D32,D35,D36 4 DFLS220L DFLS220L -- DFLS220L-7 31 FB1,FB2,FB3,FB4,FB5, FB6,FB7,FB8 F1 8 MPZ1005S121CT000 FB0402 -- MPZ1005S121CT000 Diodes Incorporated TDK Corporation 1 F1251CT-ND 154010 -- 0154010.DR Littelfuse Inc. 7 JUMPER Header_1x2 -- 61300211121 Wurth 34 JP1,JP2,JP3,JP4,JP6,JP7, JP8 JP5 1 Receptacle 20X2 HDR2542X20_socket DNL ESQ-120-23-T-D Samtec Inc. 35 J1 1 Header 1x8 DNL 22284081 Molex 36 J2 1 USB_MINI_B -- 1734035-2 37 21 Header_2x1 Regular 100 Mil Header -- TE Connectivity AMP Connectors -- CONN RCPT USB2.0 MINI B SMD R/A -- 38 J3,J4,J5,J7,J8,J9,J23,J28, J29,J30,J31,J32,J34,J35, J36,J37,J38,J40,J41,J42, J43 J6,J26 hdr_amp_872 20_8_1x8_10 0 USB_MINI_B1734035-2 Header_2x1 2 Header_2x10 Header_2x10 -- 61302021121 Wurth CONN HEADER VERT 20POS 2.54MM 39 J10,J11,J12,J14,J15,J16 6 SMA 901-10309 DNL 901-10309 Amphenol CONN SMA RCPT STR 50OHM EDGE MNT 32 33 LED GREEN CLEAR 0603 SMD FUSE BRD MNT 10A 125VAC/VDC SMD CONN HEADER VERT 2POS 2.54MM 40 Position Elevated Socket Connector Through Hole CONN HEADER 8POS .100 VERT TIN (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 47 CrossLink-NX Evaluation Board User Guide Item 40 Qty 7 Part CON3 PCB Footprint CON3 41 Reference J13,J21,J22,J24,J25,J33, J44 J17,J18,J19 Comments Default : Pin 1 and 2 -- Part Number 61300311121 Manufacturer Wurth 3 PMOD 2x6 42 43 J20,J27 J39 2 1 Header_2x7 PJ-002A PPPC062LJBN -RC Header_2x7 pj_002a_3p PPPC062LJBN-RC Sullins DNL -- -- 694106301002 -- Wurth 44 L1,L2,L3,L10,L11,L12 6 600ohm 500mA fb0603 -- BLM18AG601SN1D Murata 45 L4,L5,L6,L7,L8,L9 6 220ohm 500mA FB0402 -- CIM05U221NC Samsung 46 L13 1 2.2uH SPM6530T-2R2M -- SPM6530T-2R2M TDK Corporation L14,L15,L16,L17 4 4.7uH-SPD62R-472M SPM6530T2R2M SPD62R 47 -- SPD62R-472M API Delevan Inc. 48 Q1,Q2,Q3,Q4,Q5,Q6 6 2N2222/SOT23 -- MMBT2222ALT1G 49 RN1 1 EXB2HV472JV MMBT2222AL T-1 EXB-2HV -- EXB2HV472JV ON Semiconductor Panasonic 50 6 4.7K R0603 -- RC0603FR-074K7L yageo 51 R1,R2,R3,R102,R103, R104 R4,R9,R105 3 2.2K R0603 -- RC0603FR-072K2L yageo 52 R5,R78 2 33 R0402 -- ERJ-2RKF33R0X Panasonic 53 R6,R7,R8,R20,R21,R22 6 0 R0603 -- RC0603JR-070RL Yageo 54 R10,R11,R12,R172 4 10K R0603 -- RC0603FR-0710KL Yageo 55 R13,R16 2 12K R0603 -- RC0603FR-0712KL yageo 56 R14 1 2K-0603SMT RLP-101 -- RC0603FR-072KL Yageo 57 R15,R17,R35,R36,R37, R38,R39,R40,R145, R146,R147,R149,R150 R18,R19 13 0 R0603 DNL RC0603JR-070RL Yageo 2 4_7K-0603SMT RLP-101 -- CRCW06034K70FKEA Vishay 58 Description CONN HEADER VERT 3POS 2.54MM CONN HDR 12POS 0.1 GOLD PCB R/A Regular 100 Mil Header CONN PWR JACK 2.1X5.5MM SOLDER FERRITE CHIP 600 OHM 500MA 0603 FERRITE BEAD 220 OHM 0402 1LN FIXED IND 2.2UH 8.2A 19 MOHM SMD FIXED IND 4.7UH 2A 150 MOHM SMD TRANS NPN 40V 0.6A SOT23 RES ARRAY 8 RES 4.7K OHM 1506 RES SMD 4.7K OHM 1% 1/10W 0603 RES SMD 2.2K OHM 1% 1/10W 0603 RES SMD 33 OHM 1% 1/10W 0402 RES SMD 0 OHM JUMPER 1/10W 0603 RES SMD 10K OHM 1% 1/10W 0603 RES SMD 12K OHM 1/10W 1% 0603 RES SMD 2K OHM 1% 1/10W 0603 RES SMD 0 OHM JUMPER 1/10W 0603 RES SMD 4.7K OHM 1% 1/10W 0603 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Item 59 Reference R23 Qty 1 Part 100k PCB Footprint R0402 Comments -- Part Number ERJ-2RKF1003X Manufacturer Panasonic 60 R24 1 22 R0402 -- ERJ-2RKF22R0X Panasonic 61 R25,R26,R84,R85,R87, R106,R107,R114,R124, R132 R27,R28,R29,R30,R31, R41,R43 R32,R33,R34,R42,R44, R53,R94,R127,R128, R129,R130,R131,R134, R135,R136,R137,R138, R152,R153,R162,R163 R45 10 4.7k R0402 -- ERJ-2GEJ472X Panasonic 7 100 ohm 0201 R0201 DNL RC0201FR-07100RL Yageo 21 0.1 603 -- ERJ-3RSFR10V Panasonic 1 1.15K-0402SMT R0402 -- RC0402FR-071K15L Yageo 65 R46,R49,R54,R55,R56,R 58,R60,R63,R73,R74,R8 8,R89,R90,R91,R92 15 0 R0402 -- ERJ-2GE0R00X Panasonic 66 R47,R48,R51,R52,R57, R59,R61,R64,R65,R66 R50,R62,R67,R68,R69, R76,R82,R83,R100, R101,R140,R142 R70,R71,R72,R77,R80 10 0 R0402 DNL ERJ-2GE0R00X Panasonic 12 10K RLP-100 -- RC0402FR-0710KL Yageo 5 100 R0402 -- RC0402FR-07100RL Yageo 6 1.00k 1% R0402 -- ERJ-2RKF1001X Panasonic 9 2.0k R0402 -- ERJ-2RKF2001X Panasonic 71 R75,R108,R116,R141, R144,R171 R79,R81,R115,R117, R118,R119,R120,R125, R126 R86 1 1k R0402 DNL ERJ-2RKF1001X Panasonic 72 R93,R122,R123,R133 4 2.2k R0402 -- ERJ-2RKF2201X Panasonic 73 R95,R97,R98,R99 4 100 R0805 -- ERJ-6ENF1000V Panasonic 74 R96 1 1K R0805 -- ERJ-6ENF1001V Panasonic 62 63 64 67 68 69 70 Description RES SMD 100K OHM 1% 1/10W 0402 RES SMD 22 OHM 1% 1/10W 0402 RES SMD 4.7K OHM 5% 1/10W 0402 RES SMD 100 OHM 1% 1/20W 0201 RES 0.1 OHM 1% 1/10W 0603 RES SMD 1.15K OHM 1% 1/16W 0402 RES SMD 0.0OHM JUMPER 1/10W 0402 RES SMD 0.0OHM JUMPER 1/10W 0402 RES SMD 10K OHM 1% 1/16W 0402 RES SMD 100 OHM 1% 1/16W 0402 RES SMD 1K OHM 1% 1/10W 0402 RES SMD 2K OHM 1% 1/10W 0402 RES SMD 1K OHM 1% 1/10W 0402 RES SMD 2.2K OHM 1% 1/10W 0402 RES SMD 100 OHM 1% 1/8W 0805 RES SMD 1K OHM 1% 1/8W 0805 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 49 CrossLink-NX Evaluation Board User Guide Item 75 Reference R109 Qty 1 Part 1.02k 1% PCB Footprint R0402 Comments -- Part Number ERJ-2RKF1021X Manufacturer Panasonic 76 R110 1 2.55k 1% R0402 -- ERJ-2RKF2551X Panasonic 77 R111 1 750 1% R0402 -- ERJ-2RKF7500X Panasonic 78 R112 1 422 1% R0402 -- ERJ-2RKF4220X Panasonic 79 R113 1 15k RLP-103 -- ERJ-8GEYJ153V Panasonic 80 R121 1 1.5k R0402 -- ERJ-2GEJ152X Panasonic 81 R143,R165 2 1.15K-0603SMT RLP-101 -- RC0603FR-071K15L Yageo 82 R148,R170 2 909-0603SMT RLP-101 -- RC0603FR-07909RL Yageo 83 R151,R157,R159,R161 4 51K-0402SMT RLP-100 -- RC0402FR-0751KL yageo 84 R154 1 1.05K-0603SMT RLP-101 -- RC0603FR-071K05L Yageo 85 R155 1 1.07K-0603SMT RLP-101 -- RC0603FR-071K07L Yageo 86 R156,R164 2 200 -0603SMT RLP-101 -- RC0603FR-07200RL Yageo 87 R158 1 34K-0402SMT RLP-100 -- RC0402FR-0734KL Yageo 88 R160 1 340-0603SMT RLP-101 -- RC0603FR-07340RL Yageo 89 R166 1 30_1K-0402SMT RLP-100 -- ERJ-2RKF3012X Panasonic 90 R167 1 63_4K-0402SMT RLP-100 -- ERJ-2RKF6342X Panasonic 91 R168 1 20K-0402SMT RLP-100 -- ERJ-2RKF2002X Panasonic 92 R169 1 768-0603SMT RLP-101 -- RC0603FR-07768RL Yageo 93 R173 1 1.0 K R0603 DNL RC0603FR-071KL Yageo Description RES SMD 1.02K OHM 1% 1/10W 0402 RES SMD 2.55K OHM 1% 1/10W 0402 RES SMD 750 OHM 1% 1/10W 0402 RES SMD 422 OHM 1% 1/10W 0402 RES SMD 15K OHM 5% 1/4W 1206 RES SMD 1.5K OHM 5% 1/10W 0402 RES SMD 1.15K OHM 1% 1/10W 0603 RES SMD 909 OHM 1% 1/10W 0603 RES SMD 51K OHM 1% 1/16W 0402 RES SMD 1.05K OHM 1% 1/10W 0603 RES SMD 1.07K OHM 1% 1/10W 0603 RES SMD 200 OHM 1% 1/10W 0603 RES SMD 34K OHM 1% 1/16W 0402 RES SMD 340 OHM 1% 1/10W 0603 RES SMD 30.1K OHM 1% 1/10W 0402 RES SMD 63.4K OHM 1% 1/10W 0402 RES SMD 20K OHM 1% 1/10W 0402 RES SMD 768 OHM 1% 1/10W 0603 RES SMD 1K OHM 1% 1/10W 0603 (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 50 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Item 94 Reference Qty 14 Part 2K PCB Footprint R0402 Comments -- Part Number ERJ-2GEJ202X Manufacturer Panasonic Description 1 SMD SW DIP-8 219-8MST -- 219-8MST SWITCH SLIDE DIP SPST 100MA 20V 95 R174,R175,R176,R177, R178,R179,R180,R181, R182,R183,R184,R185, R186,R187 SW1 96 SW2,SW3,SW4,SW5 4 Push Button 4psmd_switch -- 434153017835 CTS Electrocomponen ts Wurth 97 TP_VCCIO1,TP_VCCIO2, TP_VCCIO3,TP_VCCIO4, TP_VCCIO5,TP_VCCIO6, TP_VCCIO7, TP_VCC_CORE_V1P0, TP_V1P0_VCCSD, TP_V1P0_LDO, TP_V1P2, TP_V1P8_VCCPLLSD, TP_V1P8_VCCAUXSD, TP_V1P8_LDO, TP_V1P8,TP_V2P8, TP_V3P3,TP_V5P0, TP_VCCIO0,TP_VADJ TP1,TP2,TP3,TP4,TP5 20 TP_S_40_63 tp_s_40_63 DNL -- -- SWITCH TACTILE SPSTNO 0.05A 12V -- 5 7 TP_S_40_63 TestPoint TP TP50 DNL DNL -- -- -- -- -- -- 1 FT2232HL tqfp64_0p5_1 2p2x12p2_h1 p6 so8_50_244 Customer Supplied FT2232HL FTDI IC USB HS DUAL UART/FIFO 64-LQFP -- 93LC56C-I/SN Microchip Customer Supplied -- -- -- IC EEPROM 2KBIT 3MHZ 8SOIC -- AK5DAF1-125.0000T2 Abracon LLC 98 99 100 TP6,TP7,TP8,TP9,TP10, TP12,TP13 U1 101 U2 1 93LC56C-I/SN 102 U3 1 LIFCL-40-BG400 103 U4 1 AK5DAF1-125.0000T2 LIFCL-40BG400 XTAL_AK5DAF1 104 U5 1 AK5DAF1-200.0000T2 XTAL_AK5DAF1 DNL AK5DAF1-200.0000T2 Abracon LLC 105 U6 1 MX25L12833FM2I-10G SO8_MX25L1 2833FM2I10G -- MX25L12833FM2I-10G Macronix RES SMD 2K OHM 5% 1/10W 0402 XTAL OSC XO 125MHZ 3.3V LVDS XTAL OSC XO 200MHZ 3.3V LVDS IC FLASH 128MBIT 133MHZ 8SOP (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 51 CrossLink-NX Evaluation Board User Guide Item 106 Reference U7 Qty 1 Part MAX6070BAUT18+T Comments -- Part Number MAX6070BAUT18+T Manufacturer Maxim Integrated -- PTD901-1015K-B103 Bourns Inc. -- ASP-134603-01 Samtec Inc. -- BD9D321EFJ-E2 -- NCP110AMX120TBG -- NCP110AMX280TBG -- BD00IC0WHFV-GTR TLV73310PDQNT PCB Footprint SOT236_MAX6070 PTD901_1015 K_B103 ASP_134603_ 01 HTSOP_8_BD 9D321 4XDFN_NCP1 10 4XDFN_NCP1 10 6HVSOF_BD0 0IC0WHFV 4X2SON 107 U8 1 PTD901-1015K-B103 108 U9 1 ASP-134603-01 109 U10 1 BD9D321EFJ 110 U11 1 NCP110AMX120TBG 111 U12 1 NCP110AMX280TBG 112 U13 1 BD00IC0WHFV-GTR 113 U14 1 114 U15,U16 115 -- TLV73310PDQNT 2 LT3508EUF LT3508EUF -- LT3508EUF#PBF Rohm Semiconductor ON Semiconductor ON Semiconductor Rohm Semiconductor Texas Instruments Linear Technology/Anal og Devices X1 1 7M-12.000MAAJ xtal_4p_7m -- 7M-12.000MAAJ-T TXC 116 X2 1 ASE3-27.000MHz-K-T 27MHZ -- ASE3-27.000MHz-K-T ABRACON 117 Shunt For Headers (BOM Line Item 40): J13,J21,J22,J24,J25,J33, J44 CN1 7 -- -- -- SPC02SYAN Sullins Connectors Solutions 1 -- DNL -- -- -- Camera Bracket #8-32 Screw 1 1 1 Camera Module with IMX258 -- -- -- -- -- -- DNL DNL -- -- -- 305-PD-19-0943 -- -- PACTRON -- -- -- 118 119 120 121 CrossLink NX Evaluation Board PCB RevB Description IC VREF SERIES 1.8V SOT23-6 POT 10K OHM 1/20W CARBON LINEAR CONN ARRAY RCPT 160POS SMD GOLD IC REG BUCK ADJ 3A 8HTSOP-J IC REG LINEAR 1.2V 200MA 4XDFN IC REG LINEAR 2.8V 200MA 4XDFN IC REG LINEAR POS ADJ 1A 6HVSOF IC REG LINEAR 1V 300MA 4X2SON IC REG BUCK ADJ 1.4A DL 24QFN CRYSTAL 12MHZ 18PF SMD Standard Clock Oscillators 27.000M 1.8V 30ppm CONN JUMPER SHORTING GOLD FLASH (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 52 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Appendix C. Fast Configuration Issues Early versions of the Evaluation Board were assembled with LIFCL-40-9BG400CES (ES suffix, Engineering Sample) devices. With -ES silicon, an Early I/O Release enabled bitstream is not compatible with the direct SRAM configuration Fast Configuration operation in Lattice Radiant Programmer. If attempted, the configuration operation will fail, since the board has Early I/O bitstream burned in onboard flash. Erasing flash and power cycling the board is suggested before executing Fast Configuration. Otherwise, you should select the SRAM Erase, Program, Verify operation in Lattice Radiant Programmer. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 53 CrossLink-NX Evaluation Board User Guide Appendix D. Schematics Updates for ADC Test Early versions of the schematic (Appendix A) contained errors, with pin swaps in Bank 0 and ADC symbol parts (reference designators U3A and U3K, respectively). These symbol errors have been corrected in the current schematic (Revision B-1 and later). As a result of the original error, the ADC channel 0 test access circuit is connected incorrectly: J24 is connected to the negative input and J25 is connected to the positive input (see Figure A.9). To effectively utilize the ADC test access circuit on the Crosslink-NX Evaluation Board Revision B, follow these guidelines: For single-ended use, voltages applied to J25-2 should be positive relative to voltages applied to J24-2. Do not use shunt position 1-2 for either J24 and J25. For single-ended testing utilizing the voltage generated by the 10 K potentiometer U8: Use a jumper wire to connect J24-1 and J25-2, connecting the POT to channel 0 POS input (ADC_DP0). Use a jumper wire to connect J24-2 and J25-1, connecting channel 0 NEG input (ADC_DN0) to ground. For differential testing, connect the signals directly to Pin 2 of J24 and J25, or use header J26. To route the ADC signals to header J26, use shunt positions 2-3 of both J24 and J25 to connect ADC_DN0 to connector J26-3 and ADC_DP0 to connector J26-5. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 54 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide References Lattice Semiconductor Documents Related documents available from your Lattice Semiconductor sales representative are listed on the table below. Document FPGA-UG-02042 FPGA-DS-02049 FPGA-TN-02099 Title Programming Cables CrossLink-NX Family Data Sheet CrossLink-NX sysCONFIG Usage Guide (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 55 CrossLink-NX Evaluation Board User Guide Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport. (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 56 FPGA-EB-02028-1.3 CrossLink-NX Evaluation Board User Guide Revision History Revision 1.3, November 2020 Section Change Summary Headers/Connectors and LIFCL-40 Device Ball Mapping Made the following revisions in Table 8.1. FMC LPC Header Pin Connections. Changed G32 pin to V16 Changed G34 pin to W17 Corrected table numbering in chapters 7 and 8. -- Revision 1.2, August 2020 Section Introduction Jumpers and Test Connection Appendix A. CrossLink Evaluation Board Schematics Appendix D. Schematics Updates for ADC Test Change Summary Added Figure 1.3. Silkscreen of CrossLink-NX Evaluation Board and Figure 1.4. Silkscreen of CrossLink-NX Evaluation Board (Bottom). Updated J24 and J25 usage for ADC testing in Table 2.1. Jumper Table. Updated schematics to version B-1. Added this section. Revision 1.1, March 2020 Section Introduction Appendix C. Fast Configuration Issues Change Summary Added Potentiometer for ADC test feature. Added call-outs to Figure 1.2. Bottom View of CrossLink-NX Evaluation Board. Updated the CrossLink-NX Device and the Applying Power to the Board sections. Added this section. Revision 1.0, December 2019 Section All Change Summary Initial release (c) 2019-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02028-1.3 57 www.latticesemi.com