General Description
The MAX5940A/MAX5940B provide complete interface
function for a powered device (PD) to comply with the
IEEE 802.3af standard in a power-over-ethernet system.
MAX5940A/MAX5940B provide the PD with a detection
signature, a classification signature, and an integrated
isolation switch with programmable inrush current con-
trol. These devices also feature power-mode undervolt-
age lockout (UVLO) with wide hysteresis, and
power-good outputs.
An integrated MOSFET provides PD isolation during
detection and classification. The MAX5940A/MAX5940B
guarantee a leakage current offset of less than 10µA dur-
ing the detection phase. A programmable current limit
prevents high inrush current during power-on. The device
features power-mode UVLO with wide hysteresis and
long deglitch time to compensate for twisted-pair cable
resistive drop and to assure glitch-free transition between
detection, classification, and power-on/-off phases.
The MAX5940A provides an active-high (PGOOD) open-
drain output and a fixed UVLO threshold. The MAX5940B
provides both active-high (PGOOD) and active-low
(PGOOD) outputs and has an adjustable UVLO threshold
with the default value compliant to the 802.3af standard.
The MAX5940A/MAX5940B are designed to work with or
without an external diode bridge.
The MAX5940A/MAX5940B are available in 8-pin SO
packages and are rated over the extended temperature
range of -40°C to +85°C.
Applications
IP Phones Security Cameras
Wireless Access Nodes IEEE 802.3af Power Devices
Computer Telephony
Features
♦Fully Integrated IEEE 802.3af-Compliant PD
Interface
♦PD Detection and Programmable Classification
Signatures
♦Less than 10µA Leakage Current Offset During
Detection
♦Integrated MOSFET For Isolation and Inrush
Current Limiting
♦Gate Output Allows External Control of the
Internal Isolation MOSFET
♦Programmable Inrush Current Control
♦Programmable Undervoltage Lockout
(MAX5940B Only)
♦Wide UVLO Hysteresis Accommodates Twisted-
Pair Cable Voltage Drop
♦PGOOD/PGOOD Outputs to Enable Downstream
DC-DC Converters
♦-40°C to +85°C Operating Temperature Range
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
60V 68nF
GND
VEE
GATE
RCLASS
PGOOD
DC-DC CONVERTER
GND
-48V
RCL
*OPTIONAL.
GND
V+
LOAD
VREG
D1*
OUT
2
3
45
6
8
COUT
CGATE
RDISC
25.5kΩ
SS_SHDN
MAX5014
MAX5940A
D2*
Typical Operating Circuits
19-2991; Rev 0; 10/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations appear at end of data sheet.
PART TEMP RANGE PIN-
PACKAGE UVLO
MAX5940AESA -40°C to +85°C 8 SO Fixed
MAX5940BESA -40°C to +85°C 8 SO Adjustable
Typical Operating Circuits continued at end of data sheet.
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, TA= -40°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages are referenced to VEE, unless otherwise noted.)
GND........................................................................-0.3V to +80V
OUT, PGOOD ...........................................-0.3V to (GND + 0.3V)
RCLASS, GATE ......................................................-0.3V to +12V
UVLO ........................................................................-0.3V to +8V
PGOOD to OUT.........................................-0.3V to (GND + 0.3V)
Maximum Input/Output Current (continuous)
OUT to VEE ...................................................................500mA
GND, RCLASS to VEE .....................................................70mA
UVLO, PGOOD, PGOOD to VEE .....................................20mA
GATE to VEE....................................................................80mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)..................470mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DETECTION MODE
Input Offset Current (Note 2) IOFFSET VIN = 1.4V to 10.1V 10 µA
Effective Differential Input
Resistance (Note 3) dR VIN = 1.4V up to 10.1V with 1V step,
OUT = PGOOD = GND 550 kΩ
CLASSIFICATION MODE
Classification Current Turn-Off
Threshold (Note 4) VTH
,
CLSS VIN rising 20.8 21.8 22.5 V
Class 0, RCL = 10kΩ02
Class 1, RCL = 732Ω9.17 11.83
Class 2, RCL = 392Ω17.29 19.71
Class 3, RCL = 255Ω26.45 29.55
Classification Current (Notes 5, 6) ICLASS
VIN = 12.6V to
20V, RDISC =
25.5kΩ
Class 4, RCL = 178Ω36.6 41.4
mA
POWER MODE
Operating Supply Voltage VIN VIN = (GND - VEE)67V
Operating Supply Current IIN Measure at GND, not including RDISC 0.4 1 mA
MAX5940A 34.3 35.4 36.6
Default Power Turn-On Voltage VUVLO
,
ON VIN increasing MAX5940B, UVLO = VEE 37.4 38.6 39.9 V
Default Power Turn-Off Voltage VUVLO
,
OFF VIN decreasing, UVLO = VEE for
MAX5940B 30 V
MAX5940A 4.2
Default Power Turn-On/Off
Hysteresis
VHYST,
UVLO MAX5940B, UVLO = VEE 7.4 V
External UVLO Programming
Range VIN,EX Set UVLO externally (MAX5940B only)
(Note 7) 12 67 V
UVLO External Reference Voltage VREF
,
UVLO 2.400 2.460 2.522 V
UVLO External Reference Voltage
Hysteresis HYST Ratio to VREF,UVLO 19.2 20 20.9 %
UVLO Bias Current IUVLO UVLO = 2.460V -1.5 +1.5 µA
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
_______________________________________________________________________________________ 3
Note 1: All min/max limits are production tested at +85°C. Limits at +25°C and -40°C are guaranteed by design.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between GND and VEE without any external
resistance. See Figure 1.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the PD Classification Mode section. RDISC and RCL must be ±1%, 100ppm or better. ICLASS includes the IC
bias current and the current drawn by RDISC.
Note 6: See the Thermal Dissipation section for details.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ(±1%), the turn-
on threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage (MAX5940B only).
Note 8: When the UVLO input voltage is below VTH,G,UVLO, the MAX5940B sets the UVLO threshold internally.
Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the
MAX5940A/MAX5940B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Note 10: Guaranteed by design.
Note 11: PGOOD references to OUT while PGOOD references to VEE.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
UVLO Input Ground-Sense
Threshold (Note 8) VTH
,
G
,
UVLO 50 440 mV
UVLO Input Ground-Sense Glitch
Rejection UVLO = VEE 7µs
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time (Note 9)
tOFF_DLY VIN, VUVLO falling 0.32 ms
TA = +25°C
(Note 10) 0.6 1.1
Isolation Switch N-Channel
MOSFET On-Resistance RON
Output current =
300mA, VGATE = 6V,
measured between
OUT and VEE TA = +85°C 0.8 1.5
Ω
Isolation Switch N-Channel
MOSFET Off-Threshold Voltage VGSTH OUT = GND, VGATE - VEE, output current
< 1µA 0.5 V
GATE Pulldown Switch Resistance RGPower-off mode, VIN = 12V,
UVLO = VEE for MAX5940B 38 80 Ω
GATE Charging Current IGVGATE = 2V 5 10 15 µA
GATE High Voltage VGATE IGATE = 1µA 5.59 5.76 5.93 V
VOUT - VEE, |VOUT - VEE| decreasing,
VGATE = 5.75V 1.16 1.23 1.31 V
PGOOD, PGOOD Assertion VOUT
Threshold VOUTEN
Hysteresis 70 mV
(GATE - VEE) increasing, OUT = VEE 4.62 4.76 4.91 V
PGOOD, PGOOD Assertion VGATE
Threshold VGSEN Hysteresis 80 mV
PGOOD, PGOOD Output Low
Voltage (Note 11) VOLDCDC ISINK = 2mA; for PGOOD, OUT ≤
(GND - 5V) 0.4 V
PGOOD Leakage Current (Note 11) GATE = high, GND - VOUT = 67V 1 µA
PGOOD Leakage Current (Note 11) GATE = VEE, PGOOD - VEE = 67V 1 µA
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, TA= -40°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
4 _______________________________________________________________________________________
IIN
IINi + 1
IINi
IOFFSET
dRi
1VVINi VINi + 1
IOFFSET ≅ IINi - VINi
dRi
dRi ≅ (VINi + 1 - VINi) = 1V
(IINi + 1 - IINi) (IINi + 1 - IINi)
VIN
Figure1 . Effective Differential Input Resistance/Offset Current
DETECTION CURRENT vs. INPUT VOLTAGE
MAX5940A/B toc01
INPUT VOLTAGE (V)
DETECTION CURRENT (mA)
8642
0.1
0.2
0.3
0.4
0.5
0
010
RDISC = 25.5kΩ
IIN + IRDISC
CLASSIFICATION CURRENT vs. INPUT VOLTAGE
MAX5940A/B toc02
INPUT VOLTAGE (V)
CLASSIFICATION CURRENT (mA)
252015105
10
20
30
40
50
0
030
CLASS 0
CLASS 1
CLASS 2
CLASS 3
CLASS 4
EFFECTIVE DIFFERENTIAL INPUT
RESISTANCE vs. INPUT VOLTAGE
MAX5940A/B toc03
INPUT VOLTAGE (V)
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (MΩ)
108642
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
012
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
MAX5940A/B toc04
INPUT VOLTAGE (V)
INPUT OFFSET CURRENT (µA)
9753
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
-3.5
111
NORMALIZED UVLO
vs. TEMPERATURE
MAX5940A/B toc05
TEMPERATURE (°C)
NORMALIZED UVLO
603510-15
0.992
0.994
0.996
0.998
1.000
1.002
1.004
1.006
1.008
1.010
0.990
-40 85
UVLO = VEE
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
MAX5940A/B toc06
ISINK (mA)
VPGOOD (mV)
15105
50
100
150
200
250
0
020
Typical Operating Characteristics
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE (MAX5940B), TA= -40°C to +85°C. Typical values
are at TA= +25°C. All voltages are referenced to VEE, unless otherwise noted.)
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
_______________________________________________________________________________________ 5
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
MAX5940A/B toc07
ISINK (mA)
VPGOOD (mV)
15105
80
160
240
320
400
0
020
OUT LEAKAGE CURRENT
vs. TEMPERATURE
MAX5940A/B toc08
TEMPERATURE (°C)
OUT LEAKAGE CURRENT (nA)
603510-15
4
8
12
16
20
0
-40 85
VOUT = 67V
INRUSH CURRENT CONTROL (VIN = 12V)
MAX5940A/B toc09
1ms/div
VGATE
5V/div
IINRUSH
100mA/div
VOUT TO VEE
10V/div
PGOOD
10V/div
INRUSH CURRENT CONTROL (VIN = 48V)
MAX5940A/B toc10
2ms/div
VGATE
5V/div
IINRUSH
100mA/div
VOUT TO VEE
50V/div
PGOOD
50V/div
INRUSH CURRENT CONTROL (VIN = 67V)
MAX5940A/B toc11
2ms/div
VGATE
5V/div
IINRUSH
100mA/div
VOUT TO VEE
50V/div
PGOOD
50V/div
Typical Operating Characteristics (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE (MAX5940B), TA= -40°C to +85°C. Typical values
are at TA= +25°C. All voltages are referenced to VEE, unless otherwise noted.)
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
6 _______________________________________________________________________________________
Pin Description
PIN
MAX5940A
MAX5940B
NAME
FUNCTION
1, 7 —N.C. No Connection. Not internally connected.
—1
UVLO
Undervoltage Lockout Programming Input for Power Mode. When UVLO is above its
threshold, the device enters power mode. Connect UVLO to VEE to use the default
undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a
threshold externally. The series resistance value of the external resistors must add to 25.5kΩ
(±1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull
UVLO to between VTH,G,UVLO and VREF,UVLO.
22
RCLASS
Classification Setting. Add a resistor from RCLASS to VEE to set a PD class (see Tables 1
and 2).
33
GATE
Gate of Internal N-Channel Power MOSFET. GATE sources 10µA when the device enters
power mode. Connect an external 100V ceramic capacitor (CGATE) from GATE to OUT to
program the inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection
and classification functions operate normally when GATE is pulled to VEE.
44V
EE Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect
VEE to -48V.
5 5 OUT Output Voltage. Drain of the integrated isolation N-channel power MOSFET.
66
PGOOD
Power-Good Indicator Output, Active-High, Open-Drain. PGOOD is referenced to OUT.
PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above
VEE. Otherwise, PGOOD is pulled to OUT (given that VOUT is at least 5V below GND).
Connect PGOOD to the ON pin of a downstream DC-DC converter.
—7
PGOOD
Power-Good Indicator Output, Active-Low, Open-Drain. PGOOD is referenced to VEE.
PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE.
Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream
DC-DC converter.
8 8 GND Ground. GND is the positive input terminal.
Detailed Description
Operating Modes
The PD front-end section of the MAX5940A/MAX5940B
operates in 3 different modes, PD detection signature,
PD classification, and PD power, depending on its input
voltage (VIN = GND - VEE). All voltage thresholds are
designed to operate with or without the optional diode
bridge while still complying with the IEEE 802.3af stan-
dard (see Figure 4).
Detection Mode (1.4V ≤VIN ≤10.1V)
In detection mode, the power source equipment (PSE)
applies two voltages on VIN in the range of 1.4V to
10.1V (1V step minimum), and then records the current
measurements at the two points. The PSE then com-
putes ∆V/∆I to ensure the presence of the 25.5kΩsig-
nature resistor. In this mode, most of the MAX5940A/
MAX5940B internal circuitry is off and the offset current
is less than 10µA.
If the voltage applied to the PD is reversed, install pro-
tection diodes on the input terminal to prevent internal
damage to the MAX5940A/MAX5940B (see the Typical
Application Circuits). Since the PSE uses a slope tech-
nique (∆V/∆I) to calculate the signature resistance, the
DC offset due to the protection diodes is subtracted
and does not affect the detection process.
Classification Mode (12.6V ≤VIN ≤20V)
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distrib-
ution. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor (RCL)
connected from RCLASS to VEE sets the classification
current.
The PSE determines the class of a PD by applying a volt-
age at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5940A/MAX5940B exhibit a cur-
rent characteristic with values indicated in Table 2. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification cur-
rent includes the current drawn by the 25.5kΩdetection
signature resistor and the supply current of the
MAX5940A/MAX5940B so the total current drawn by the
PD is within the IEEE 802.3af standard figures. The classi-
fication current is turned off whenever the device is in
power mode.
Power Mode
During power mode, when VIN rises above the undervolt-
age lockout threshold (VUVLO,ON), the MAX5940A/
MAX5940B gradually turn on the internal N-channel MOS-
FET Q1 (see Figure 2). The MAX5940A/MAX5940B
charge the gate of Q1 with a constant current source
(10µA, typ). The drain-to-gate capacitance of Q1 limits
the voltage rise rate at the drain of the MOSFET, thereby
limiting the inrush current. To reduce the inrush current,
add external drain-to-gate capacitance (see the Inrush
Current section). When the drain of Q1 is within 1.2V of
its source voltage and its gate-to-source voltage is
above 5V, the MAX5940A/MAX5940B asserts the
PGOOD/PGOOD outputs. The MAX5940A/MAX5940B
have a wide UVLO hysteresis and turn-off deglitch time
to compensate for the high impedance of the twisted-
pair cable.
Undervoltage Lockout
The MAX5940A/MAX5940B operate up to a 67V supply
voltage with a default UVLO turn-on (VUVLO,ON) set at
35V (MAX5940A) or 39V (MAX5940B) and a UVLO turn-
off (VUVLO,OFF) set at 30V. The MAX5940B has an
adjustable UVLO threshold using a resistor-divider con-
nected to UVLO (see Figure 3). When the input voltage
is above the UVLO threshold, the IC is in power mode
and the MOSFET is on. When the input voltage goes
below the UVLO threshold for more than tOFF_DLY, the
MOSFET turns off.
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
_______________________________________________________________________________________ 7
CLASS USAGE RCL (Ω) MAXIMUM POWER USED BY PD (W)
0 Default 10k 0.44 to 12.95
1 Optional 732 0.44 to 3.84
2 Optional 392 3.84 to 6.49
3 Optional 255 6.49 to 12.95
4 Not Allowed 178 Reserved*
*Class 4 reserved for future use.
Table 1. PD Power Classification/RCL Selection
CLASS CURRENT SEEN AT VIN (mA) IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
CLASS RCL (Ω)V
IN* (V)
MIN MAX MIIN MAX
0 10k 12.6 to 20 0 2 0 4
1 732 12.6 to 20 9.17 11.83 9 12
2 392 12.6 to 20 17.29 19.71 17 20
3 255 12.6 to 20 26.45 29.55 26 30
4 178 12.6 to 20 36.6 41.4 36 44
*VIN is measured across the MAX5940 input pins, which does not include the diode bridge voltage drop.
Table 2. Setting Classification Current
MAX5940A/MAX5940B
To adjust the UVLO threshold (MAX5940B only), con-
nect an external resistor-divider from GND to UVLO
and from UVLO to VEE. Use the following equations to
calculate R1 and R2 for a desired UVLO threshold:
R1 = 25.5kΩ- R2
where VIN,EX is the desired UVLO threshold. Since the
resistor-divider replaces the 25.5kΩPD detection resis-
tor, ensure that the sum of R1 and R2 equals 25.5kΩ
±1%. When using the external resistor-divider, the
MAX5940B has an external reference voltage hystere-
sis of 20% (typ). When UVLO is programmed external-
ly, the turn-off threshold is 80% (typ) of the new UVLO
threshold.
Rkx
V
V
REF UVLO
IN EX
2255=.,
,
Ω
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
8 _______________________________________________________________________________________
R1
GND
UVLO
GND
(UVLO)
( ) MAX5940B.
GATE
R2
R3
MAX5940B
CLASSIFICATION RCLASS
(PGOOD)
6.8V
EN
REF
2.46V
200mV
VEE
VGATE
1.2V, REF
5V, REF
Q4
PGOOD
OUT
Q3
Q1
Q2
EN
20%
Figure 2. Block Diagram
R1
UVLO
GND
VEE
R2
VIN = 12V TO 67V
MAX5940B
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
Inrush Current Limit
The MAX5940A/MAX5940B charge the gate of the
internal MOSFET with a constant current source (10µA,
typ). The drain-to-gate capacitance of the MOSFET lim-
its the voltage rise rate at the drain, thereby limiting the
inrush current. Add an external capacitor from GATE to
OUT to further reduce the inrush current. Use the fol-
lowing equation to calculate the inrush current:
PGOOD/
PGOOD
Outputs
(MAX5940A/MAX5940B)
PGOOD is an open-drain, active-high logic output.
PGOOD goes high impedance when VOUT is within 1.2V
of VEE and when GATE is 5V above VEE. Otherwise,
PGOOD is pulled to VOUT (given that VOUT is at least 5V
below GND). Connect PGOOD to the ON pin of a down-
stream DC-DC converter. Connect a 100kΩpullup resis-
tor from PGOOD to GND if needed.
(MAX5940B only)
PGOOD is an open-drain, active-low logic output.
PGOOD is pulled to VEE when VOUT is within 1.2V of VEE
and when GATE is 5V above VEE. Otherwise, PGOOD
goes high impedance. Connect PGOOD to the ON pin of
a downstream DC-DC converter. Connect a 100kΩ
pullup resistor from PGOOD to GND if needed.
Thermal Dissipation
During classification mode, if the PSE applies the maxi-
mum DC voltage, the maximum voltage drop from GND
to VRCLASS will be 13V. If the maximum classification
current of 42mA flows through the MAX5940A/
MAX5940B, then the maximum DC power dissipation will
be 546mW, which is slightly higher than the maximum
DC power dissipation of the IC at maximum operating
temperature. However, according to the IEEE 802.3af
standard, the duration of the classification mode is limit-
ed to 75ms (max). The MAX5940A/MAX5940B handle
the maximum classification power dissipation for the
maximum duration time without sustaining any internal
damage. If the PSE violates the IEEE 802.3af standard
by exceeding the 75ms maximum classification duration,
it may cause internal damage to the IC.
IIx
C
C
INRUSH G OUT
GATE
=
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
_______________________________________________________________________________________ 9
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
10 ______________________________________________________________________________________
R1*
60V 68nF
UVLO GND
VEE
GATE
RCLASS PGOOD
PGOOD
DC-DC CONVERTER
PHY
GND
-48V
TX
RX
RJ-45
POWER-OVER
SPAIR PAIRS
3
6
1
2
4
5
7
8
GND
-48V
R2* RCL
*R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR.
GND
V+
VREG
OUT
1
2
3
45
6
7
8COUT
CGATE
RDISC
25.5kΩ
SS_SHDN
MAX5014
MAX5940B
POWER-OVER
SIGNAL PAIRS
LOAD
+
-
+
-
VREG
Typical Application Circuits
Application Circuit 1
Figure 4. PD with Power-Over-Ethernet (Power is Provided by Either the Signal Pairs or the Spare Pairs)
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
______________________________________________________________________________________ 11
60V 68nF
UVLO GND
VEE
GATE
RCLASS PGOOD
PGOOD
DC-DC CONVERTER
GND
-48V
WALL
ADAPTER
SUPPLY
RCL
D1
GND
V+
VREG
OUT
1
2
3
45
6
7
8COUT
CGATE
RDISC
25.5kΩ
SS_SHDN
MAX5014
MAX5940B LOAD
R3
10kΩ
Typical Application Circuits (continued)
Figure 5. Adding Wall Adapter Input Supply (Wall Adapter Supply Takes Precedence Over Power-Over-Ethernet)
Application Circuit 2
Diode D1 prevents the power-over-ethernet to back
drive the wall adapter. Whenever the wall adapter
power is available, the GATE is pulled low to pinch off
the power-over-ethernet. R3 provides the GATE current
flow path. The wall adapter power pollutes the discov-
ery signature, preventing PSE from detecting this PD.
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
12 ______________________________________________________________________________________
60V 68nF
UVLO GND
VEE
GATE
RCLASS PGOOD
PGOOD
DC-DC CONVERTER
GND
-48V
WALL
ADAPTER
SUPPLY
RCL
D1
GND
V+
VREG
OUT
1
2
3
45
6
7
8COUT
CGATE
RDISC
25.5kΩ
SS_SHDN
MAX5014
MAX5940B LOAD
R4
4kΩ
2W
D2
Typical Application Circuits (continued)
Figure 6. Adding Wall Adapter Input Supply (Wall Adapter Supply And Power-Over-Ethernet Co-Exist, the One with Higher Voltage
Provides Power To The Load)
Application Circuit 3
D2 prevents the wall adapter power from polluting the
discovery and classification signatures. The optional
R4 provides the 10mA minimum power maintenance
signature to keep the power-over-ethernet from discon-
necting.
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
______________________________________________________________________________________ 13
60V 68nF
UVLO GND
VEE
GATE
RCLASS PGOOD
PGOOD
DC-DC CONVERTER
GND
-48V
WALL
ADAPTER
SUPPLY
RCL
D1
GND
V+
VREG
OUT
1
2
3
45
6
7
8COUT
CGATE
RDISC
25.5kΩ
SS_SHDN
MAX5014
MAX5940B LOAD
Typical Application Circuits (continued)
Application Circuit 4
If the wall adapter supply comes up first, it provides
power to the load and pollute the discovery and classi-
fication signatures. If the power-over-ethernet comes
up first, it powers the load until taken over by a wall
adapter with higher output voltage.
Figure 7. Adding Wall Adapter Input Supply (the One with Higher Voltage Provides Power to the Load)
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
14 ______________________________________________________________________________________
PGOOD
OUTVEE
1
2
8
7
GND
N.C.RCLASS
GATE
N.C.
SO
TOP VIEW
3
4
6
5
MAX5940A
PGOOD
OUTVEE
1
2
8
7
GND
PGOODRCLASS
GATE
UVLO
SO
3
4
6
5
MAX5940B
Pin Configurations
R1**
60V 68nF UVLO GND
VEE
GATE
RCLASS PGOOD
PGOOD
DC-DC CONVERTER
GND
-48V
R2** RCL
*OPTIONAL.
**R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR.
VREG
OUT
1
2
3
45
6
7
8COUT
CGATE
RDISC
25.5kΩ
MAX5940B
D1*
D2*
GND
V+
SS_SHDN
MAX5014
LOAD
Typical Operating Circuits (continued)
Chip Information
TRANSISTOR COUNT: 3,643
PROCESS: BiCMOS
MAX5940A/MAX5940B
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SOICN .EPS
PACKAGE OUTLINE, .150" SOIC
1
1
21-0041 B
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.010
0.069
0.019
0.157
0.010
INCHES
0.150
0.007
E
C
DIM
0.014
0.004
B
A1
MIN
0.053A
0.19
3.80 4.00
0.25
MILLIMETERS
0.10
0.35
1.35
MIN
0.49
0.25
MAX
1.75
0.050
0.016L0.40 1.27
0.3940.386D
D
MINDIM
D
INCHES
MAX
9.80 10.00
MILLIMETERS
MIN MAX
16 AC
0.337 0.344 AB8.758.55 14
0.189 0.197 AA5.004.80 8
N MS012
N
SIDE VIEW
H 0.2440.228 5.80 6.20
e 0.050 BSC 1.27 BSC
C
HE
eBA1
A
D
0-8
L
1
VARIATIONS:
