AUIRF7103Q
VDSS 50V
RDS(on) max. 130m
ID 3.0A
Description
Specifically designed for Automotive applications, this cellular
design of HEXFET® Power MOSFETs utilizes the latest
processing techniques to achieve low on-resistance per silicon
area. This benefit combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs are
well known for, provides the designer with an extremely efficient
and reliable device for use in Automotive and a wide variety of
other applications.
Features
Advanced Planar Technology
Dual N Channel MOSFET
Low On-Resistance
Logic Level Gate Drive
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
1 2015-9-30
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com
AUTOMOTIVE GRADE
Symbol Parameter Max. Units
ID @ TA = 25°C Continuous Drain Current, VGS @ 4.5V 3.0
A
ID @ TA = 70°C Continuous Drain Current, VGS @ 4.5V 2.5
IDM Pulsed Drain Current 25
PD @TA = 25°C Maximum Power Dissipation 2.4 W
Linear Derating Factor 16 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy (Thermally Limited) 22
mJ
IAR Avalanche Current See Fig.19,20, 16b, 16c A
EAR Repetitive Avalanche Energy mJ
dv/dt Peak Diode Recovery dv/dt 12 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Thermal Resistance
Symbol Parameter Typ. Max. Units
°C/W
RJL Junction-to-Drain Lead ––– 20
RJA Junction-to-Ambient  ––– 62.5
SO-8
AUIRF7103Q
Base part number Package Type Standard Pack Orderable Part Number
Form Quantity
AUIRF7103Q SO-8 Tape and Reel 4000 AUIRF7103QTR
G D S
Gate Drain Source
D1
D1
D
2
D2
G1
S2
G2
S1
Top View
8
1
2
3
45
6
7
AUIRF7103Q
2 2015-9-30
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width 400µs; duty cycle 2%.
Surface mounted on 1" in square Cu board.
Starting TJ = 25°C, L = 4.9mH, RG = 25, IAS = 3.0A. (See Fig. 12)
ISD 2.0A, di/dt 155A/µs, VDD V(BR)DSS, TJ 175°C.
Limited by TJmax , see Fig.16b, 16c, 19, 20 for typical repetitive avalanche performance.
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 50 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 130 mVGS = 10V, ID = 3.0A 
––– ––– 200 VGS = 4.5V, ID = 1.5A 
VGS(th) Gate Threshold Voltage 1.0 ––– 3.0 V VDS = VGS, ID = 250µA
gfs Forward Trans conductance 3.4 ––– ––– S VDS = 15V, ID = 3.0A
IDSS Drain-to-Source Leakage Current ––– ––– 2.0 µA VDS =40V, VGS = 0V
––– ––– 25 VDS = 40V,VGS = 0V,TJ =55°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Qg Total Gate Charge ––– 10 15
nC
ID = 2.0A
Qgs Gate-to-Source Charge ––– 1.2 ––– VDS = 40V
Qgd Gate-to-Drain Charge ––– 2.8 ––– VGS = 10V
td(on) Turn-On Delay Time ––– 5.1 –––
ns
VDD = 25V
tr Rise Time ––– 1.7 ––– ID = 1.0A
td(off) Turn-Off Delay Time ––– 15 ––– RG = 6.0
tf Fall Time ––– 2.3 ––– RD = 25
Ciss Input Capacitance ––– 255 –––
pF
VGS = 0V
Coss Output Capacitance ––– 69 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 29 ––– ƒ = 1.0MHz
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 3.0
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 12 integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.2 V TJ = 25°C,IS = 1.5A,VGS = 0V 
trr Reverse Recovery Time ––– 35 53 ns TJ = 25°C ,IF = 1.5A,
Qrr Reverse Recovery Charge ––– 45 67 nC di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
AUIRF7103Q
3 2015-9-30
Fig. 2 Typical Output Characteristics
Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance
vs. Temperature
Fig. 1 Typical Output Characteristics
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
ID, Drain-to-Source Current (A)
4.5V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (A)
4.5V
20µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
3.0 6.0 9.0 12.0 15.0
VGS, Gate-to-Source Voltage (V)
1.00
10.00
100.00
ID, Drain-to-Source Current )
TJ = 25°C
TJ = 175°C
VDS = 25V
20µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
3.0A
AUIRF7103Q
4 2015-9-30
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS
= 0V, f = 1 MHZ
Ciss = C
gs + C
gd , C
ds SHORTED
Crss
= C
gd
Coss
= C
ds + C
gd
0 3 6 9 12
0
3
6
9
12
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
I=
D2.0A
V = 10V
DS
V = 25V
DS
V = 40V
DS
0 1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.01
0.1
1
10
100
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
AUIRF7103Q
5 2015-9-30
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
25 50 75 100 125 150 175
0.0
0.6
1.2
1.8
2.4
3.0
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
1E-006 1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
100
Thermal Response ( Z thJA ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + TA
AUIRF7103Q
6 2015-9-30
Fig 12. Typical On-Resistance Vs.
Gate Voltage Fig 13. Typical On-Resistance Vs.
Drain Current
Fig 15. Typical Power Vs. Time
Fig. 14. Typical Threshold Voltage Vs. Junction
Temperature
4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0
-VGS,
Gate -to -Source Voltage (V)
0.09
0.10
0.11
0.12
0.13
0.14
0.15
RDS(on), Drain-to -Source On Resistance ()
ID = 3.0A
0 5 10 15 20 25 30 35 40
ID , Drain Current (A)
0.000
0.500
1.000
1.500
2.000
2.500
RDS (on) , Drain-to-Source On Resistance ()
VGS = 10V
VGS = 4.5V
-75 -50 -25 025 50 75 100 125 150
TJ , Temperature ( °C )
1.0
1.3
1.5
1.8
2.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1.00 10.00 100.00 1000.00
Time (sec)
0
10
20
30
40
50
60
70
Power (W)
AUIRF7103Q
7 2015-9-30
Fig 16a. Maximum Avalanche Energy
vs. Drain Current
Fig 17. Gate Charge Test Circuit Fig 18. Basic Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
Fig 16b. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 16c. Unclamped Inductive Waveforms
25 50 75 100 125 150 175
0
12
24
36
48
60
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
1.2A
2.5A
3.0A
AUIRF7103Q
8 2015-9-30
Fig 19. Typical Avalanche Current vs. Pulse width
Notes on Repetitive Avalanche Curves , Figures 19, 20:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16b, 16c.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 11, 16).
t
av = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
Z
thJC(D, tav) = Transient thermal resistance, see Figures 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 20. Maximum Avalanche Energy
vs. Temperature
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
tav (sec)
0.01
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Tj = 25°C due to
avalanche losses
0.01
0.10
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
5
10
15
20
25
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 3.0A
AUIRF7103Q
9 2015-9-30
SO-8 Part Marking Information
SO-8 Package Outline (Dimensions are shown in millimeters (inches)
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX
MILLIMETERSIN C H ES
MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
87
5
65
D B
E
A
e
6X
H
0.25 [.010] A
6
7
K x 45°
8X L 8X c
y
0.25 [.010] C AB
e1
A
A1
8X b
C
0.10 [.004]
4312
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050]
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
N O TES:
1. D IM EN SIO N IN G & TO LERAN C IN G PER ASM E Y14.5M -1994.
2. CONTROLLING DIMENSION: MILLIM ETER
3. DIMENSIONS ARE SHOW N IN MILLIMETERS [INCHES].
5 DIM EN SIO N D O ES N O T IN C LUD E M O LD PRO TRUSIO N S.
6 DIM EN SIO N D O ES N O T IN C LUD E M O LD PRO TRUSIO N S.
M O LD PRO TRU SIO N S N O T TO EXC EED 0.25 [.010].
7 D IM EN SIO N IS TH E LEN G TH O F LEAD FO R SO LD ERIN G TO
A S U B S T R A T E .
M O LD PRO TRU SIO N S N O T TO EXC EED 0.15 [.006].
8X 1.78 [.070]
AUIRF7103Q
10 2015-9-30
SO-8 Tape and Reel (Dimensions are shown in millimeters (inches)
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
AUIRF7103Q
11 2015-9-30
Qualification Information
Qualification Level
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification. Infineon’s
Industrial and Consumer qualification level is granted by extension of the higher
Automotive level.
Moisture Sensitivity Level SO-8 MSL1
ESD
Machine Model Class M1A (+/- 50V)†
AEC-Q101-002
Human Body Model Class H0 (+/- 250V)†
AEC-Q101-001
Charged Device Model Class C5 (+/- 1125V)†
AEC-Q101-005
RoHS Compliant Yes
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
Revision History
Date Comments
9/30/2015  Updated datasheet with corporate template
 Corrected ordering table on page 1.
4/3/2014  Added "Logic Level Gate Drive" bullet in the features section on page 1
 Updated data sheet with new IR corporate template
† Highest passing voltage.