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User's Manual V850ES/SG2, V850ES/SG2-H 32-bit Single-Chip Microcontrollers Hardware V850ES/SG2: PD703260 PD703260Y PD703261 PD703261Y PD703262 PD703262Y PD703263 PD703263Y PD70F3261 PD70F3261Y V850ES/SG2-H: PD703262HY PD703263HY PD70F3263 PD70F3263Y PD703270 PD703270Y PD703271 PD703271Y PD703272 PD703272Y PD703273 PD703273Y PD703283 PD703283Y PD70F3281 PD70F3281Y PD70F3283 PD70F3283Y PD70F3263HY PD703273HY PD703282HY PD703272HY PD70F3273HY PD703283HY PD70F3283HY Document No. U16541EJ5V1UD00 (5th edition) Date Published February 2008 N 2003, 2008 Printed in Japan PD70F3271 PD70F3271Y PD70F3273 PD70F3273Y PD703280 PD703280Y PD703281 PD703281Y PD703282 PD703282Y [MEMO] 2 User's Manual U16541EJ5V1UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U16541EJ5V1UD 3 IECUBE is a registered trademark of NEC Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America. EEPROM, IEBus, and Inter Equipment Bus are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. 4 User's Manual U16541EJ5V1UD These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of October, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 User's Manual U16541EJ5V1UD 5 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/SG2 and V850ES/SG2-H products and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/SG2 and V850ES/SG2-H shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User's Manual). Hardware How to Read This Manual Architecture * Pin functions * Data types * CPU function * Register set * On-chip peripheral functions * Instruction format and instruction set * Flash memory programming * Interrupts and exceptions * Electrical specifications * Pipeline operation It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the V850ES/SG2 and V850ES/SG2-H Read this manual according to the CONTENTS. To find the details of a register where the name is known Use APPENDIX C REGISTER INDEX. Register format The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. To understand the details of an instruction function Refer to the V850ES Architecture User's Manual available separately. To know the electrical specifications of the V850ES/SG2 and V850ES/SG2-H See CHAPTER 32 ELECTRICAL SPECIFICATIONS. The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note with caution that if "xxx.yyy" is described as is in a program, however, the compiler/assembler cannot recognize it correctly. The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. 6 User's Manual U16541EJ5V1UD Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 210 = 1,024 M (mega): 220 = 1,0242 G (giga): 230 = 1,0243 User's Manual U16541EJ5V1UD 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/SG2, V850ES/SG2-H Document Name Document No. V850ES Architecture User's Manual U15943E V850ES/SG2, V850ES/SG2-H Hardware User's Manual This manual Documents related to development tools Document Name Document No. IE-V850ES-G1 (In-Circuit Emulator) U16313E IE-703288-G1-EM1 (In-Circuit Emulator Option Board) U16697E IE-V850E1-CD-NW (PCMCIA Card Type On-Chip Debug Emulator) U16647E QB-V850ESSX2 (In-Circuit Emulator) U17091E QB-V850MINI (On-Chip Debug Emulator) U17638E QB-MINI2 (On-Chip Debug Emulator with Programming Function) U18371E CA850 Ver. 3.00 C Compiler Package Operation U17293E C Language U17291E Assembly Language U17292E Link Directive U17294E PM+ Ver. 6.30 Project Manager ID850 Ver. 3.00 Integrated Debugger Operation U17358E ID850QB Ver. 3.40 Integrated Debugger Operation U18604E TW850 Ver. 2.00 Performance Analysis Tuning Tool U17241E SM+ System Simulation Operation U18601E User Open Interface U18212E Basics U13430E Installation U17419E Technical U13431E Task Debugger U17420E Basics U18165E Installation U17421E RX850 Ver. 3.20 Real-Time OS RX850 Pro Ver. 3.21 Real-Time OS 8 U18416E Technical U13772E Task Debugger U17422E AZ850 Ver. 3.30 System Performance Analyzer U17423E PG-FP4 Flash Memory Programmer U15260E PG-FP5 Flash Memory Programmer U18865E User's Manual U16541EJ5V1UD CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................22 1.1 1.2 1.3 1.4 1.5 1.6 General .....................................................................................................................................22 Features....................................................................................................................................26 Application Fields ...................................................................................................................27 Ordering Information ..............................................................................................................28 Pin Configuration (Top View) .................................................................................................30 Function Block Configuration................................................................................................35 1.6.1 Internal block diagram ............................................................................................................... 35 1.6.2 Internal units .............................................................................................................................. 36 CHAPTER 2 PIN FUNCTIONS................................................................................................................39 2.1 2.2 2.3 2.4 List of Pin Functions...............................................................................................................39 Pin States .................................................................................................................................49 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins........50 Cautions ...................................................................................................................................54 CHAPTER 3 CPU FUNCTION.................................................................................................................55 3.1 3.2 3.3 Features....................................................................................................................................55 CPU Register Set.....................................................................................................................56 3.2.1 Program register set .................................................................................................................. 57 3.2.2 System register set.................................................................................................................... 58 Operation Modes .....................................................................................................................64 3.3.1 3.4 Specifying operation mode ........................................................................................................ 64 Address Space ........................................................................................................................65 3.4.1 CPU address space................................................................................................................... 65 3.4.2 Wraparound of CPU address space .......................................................................................... 66 3.4.3 Memory map.............................................................................................................................. 67 3.4.4 Areas ......................................................................................................................................... 69 3.4.5 Recommended use of address space ....................................................................................... 75 3.4.6 Peripheral I/O registers.............................................................................................................. 78 3.4.7 Programmable peripheral I/O registers...................................................................................... 89 3.4.8 Special registers ........................................................................................................................ 89 3.4.9 Cautions .................................................................................................................................... 93 CHAPTER 4 PORT FUNCTIONS............................................................................................................98 4.1 4.2 4.3 Features....................................................................................................................................98 Basic Port Configuration ........................................................................................................98 Port Configuration...................................................................................................................99 4.3.1 Port 0....................................................................................................................................... 104 4.3.2 Port 1....................................................................................................................................... 107 4.3.3 Port 3....................................................................................................................................... 108 4.3.4 Port 4....................................................................................................................................... 115 4.3.5 Port 5....................................................................................................................................... 118 User's Manual U16541EJ5V1UD 9 4.4 4.5 4.6 <R> 4.3.6 Port 7 .......................................................................................................................................122 4.3.7 Port 9 .......................................................................................................................................124 4.3.8 Port CM ...................................................................................................................................132 4.3.9 Port CT ....................................................................................................................................134 4.3.10 Port DH ....................................................................................................................................136 4.3.11 Port DL ....................................................................................................................................138 Block Diagrams..................................................................................................................... 141 Port Register Settings When Alternate Function Is Used ................................................ 171 Cautions ................................................................................................................................ 179 4.6.1 Cautions on setting port pins ...................................................................................................179 4.6.2 Cautions on bit manipulation instruction for port n register (Pn)...............................................182 4.6.3 Cautions on on-chip debug pins...............................................................................................183 4.6.4 Cautions on P05/INTP2/DRST pin...........................................................................................183 4.6.5 Cautions on P10, P11, and P53 pins when power is turned on ...............................................183 4.6.6 Hysteresis characteristics ........................................................................................................183 4.6.7 Cautions on separate bus mode ..............................................................................................183 CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 184 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 Features................................................................................................................................. 184 Bus Control Pins................................................................................................................... 185 5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............185 5.2.2 Pin status in each operation mode...........................................................................................185 Memory Block Function....................................................................................................... 186 External Bus Interface Mode Control Function ................................................................. 187 Bus Access ........................................................................................................................... 188 5.5.1 Number of clocks for access....................................................................................................188 5.5.2 Bus size setting function ..........................................................................................................189 5.5.3 Access by bus size ..................................................................................................................190 Wait Function ........................................................................................................................ 197 5.6.1 Programmable wait function ....................................................................................................197 5.6.2 External wait function...............................................................................................................198 5.6.3 Relationship between programmable wait and external wait ...................................................199 5.6.4 Programmable address wait function.......................................................................................200 Idle State Insertion Function ............................................................................................... 201 Bus Hold Function................................................................................................................ 202 5.8.1 Functional outline.....................................................................................................................202 5.8.2 Bus hold procedure..................................................................................................................203 5.8.3 Operation in power save mode ................................................................................................203 Bus Priority ........................................................................................................................... 204 Bus Timing ............................................................................................................................ 205 CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 211 6.1 6.2 6.3 6.4 Overview................................................................................................................................ 211 Configuration ........................................................................................................................ 212 Registers ............................................................................................................................... 214 Operation............................................................................................................................... 219 6.4.1 10 Operation of each clock ...........................................................................................................219 User's Manual U16541EJ5V1UD 6.4.2 6.5 Clock output function ............................................................................................................... 219 PLL Function..........................................................................................................................220 6.5.1 Overview ................................................................................................................................. 220 6.5.2 Registers ................................................................................................................................. 220 6.5.3 Usage ...................................................................................................................................... 223 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................224 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Overview.................................................................................................................................224 Functions ...............................................................................................................................224 Configuration .........................................................................................................................225 Registers ................................................................................................................................227 Timer Output Operations......................................................................................................240 Operation................................................................................................................................241 7.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)............................................................. 248 7.6.2 External event count mode (TPnMD2 to TPnMD0 bits = 001)................................................. 260 7.6.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010)..................................... 269 7.6.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) .............................................. 281 7.6.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100).............................................................. 288 7.6.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .................................................... 297 7.6.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) ........................................ 315 Selector Function ..................................................................................................................321 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................323 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Overview.................................................................................................................................323 Functions ...............................................................................................................................323 Configuration .........................................................................................................................324 Registers ................................................................................................................................327 Timer output operations .......................................................................................................343 Operation................................................................................................................................344 8.6.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) ............................................................ 351 8.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) ................................................ 362 8.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .................................... 372 8.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) ............................................. 385 8.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) ............................................................. 394 8.6.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) ................................................... 405 8.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110)........................................ 426 Selector Function ..................................................................................................................431 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM).............................................................................432 9.1 9.2 9.3 9.4 Overview.................................................................................................................................432 Configuration .........................................................................................................................433 Register ..................................................................................................................................434 Operation................................................................................................................................435 9.4.1 Interval timer mode.................................................................................................................. 435 9.4.2 Cautions .................................................................................................................................. 439 User's Manual U16541EJ5V1UD 11 CHAPTER 10 WATCH TIMER FUNCTIONS ...................................................................................... 440 10.1 10.2 10.3 10.4 Functions............................................................................................................................... 440 Configuration ........................................................................................................................ 441 Control Registers ................................................................................................................. 443 Operation............................................................................................................................... 447 10.4.1 Operation as watch timer .........................................................................................................447 10.4.2 Operation as interval timer.......................................................................................................448 10.4.3 Cautions...................................................................................................................................449 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 450 11.1 11.2 11.3 11.4 Functions............................................................................................................................... 450 Configuration ........................................................................................................................ 451 Registers ............................................................................................................................... 452 Operation............................................................................................................................... 454 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)................................................................... 455 12.1 12.2 12.3 12.4 12.5 12.6 Function................................................................................................................................. 455 Configuration ........................................................................................................................ 456 Registers ............................................................................................................................... 458 Operation............................................................................................................................... 460 Usage ..................................................................................................................................... 461 Cautions ................................................................................................................................ 461 CHAPTER 13 A/D CONVERTER ......................................................................................................... 462 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Overview................................................................................................................................ 462 Functions............................................................................................................................... 462 Configuration ........................................................................................................................ 463 Registers ............................................................................................................................... 466 Operation............................................................................................................................... 477 13.5.1 Basic operation ........................................................................................................................477 13.5.2 Conversion operation timing ....................................................................................................478 13.5.3 Trigger mode ...........................................................................................................................479 13.5.4 Operation mode .......................................................................................................................481 13.5.5 Power-fail compare mode ........................................................................................................485 Cautions ................................................................................................................................ 490 How to Read A/D Converter Characteristics Table........................................................... 495 CHAPTER 14 D/A CONVERTER ......................................................................................................... 499 14.1 14.2 14.3 14.4 12 Functions............................................................................................................................... 499 Configuration ........................................................................................................................ 499 Registers ............................................................................................................................... 500 Operation............................................................................................................................... 502 14.4.1 Operation in normal mode .......................................................................................................502 14.4.2 Operation in real-time output mode..........................................................................................502 14.4.3 Cautions...................................................................................................................................503 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..............................................504 15.1 15.2 15.3 15.4 15.5 15.6 Mode Switching of UARTA and Other Serial Interfaces....................................................504 15.1.1 CSIB4 and UARTA0 mode switching ...................................................................................... 504 15.1.2 UARTA2 and I2C00 mode switching ........................................................................................ 505 15.1.3 UARTA1 and I2C02 mode switching ........................................................................................ 506 Features..................................................................................................................................507 Configuration .........................................................................................................................508 Registers ................................................................................................................................510 Interrupt Request Signals.....................................................................................................517 Operation................................................................................................................................518 15.6.1 Data format.............................................................................................................................. 518 15.6.2 SBF transmission/reception format.......................................................................................... 520 15.6.3 SBF transmission .................................................................................................................... 522 15.6.4 SBF reception.......................................................................................................................... 523 15.6.5 UART transmission.................................................................................................................. 525 15.6.6 Continuous transmission procedure ........................................................................................ 526 15.6.7 UART reception ....................................................................................................................... 528 15.6.8 Reception errors ...................................................................................................................... 529 15.6.9 Parity types and operations ..................................................................................................... 531 15.6.10 Receive data noise filter .......................................................................................................... 532 15.7 15.8 Dedicated Baud Rate Generator ..........................................................................................533 Cautions .................................................................................................................................541 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................542 16.1 <R> 16.2 16.3 16.4 16.5 16.6 <R> Mode Switching of CSIB and Other Serial Interfaces........................................................542 16.1.1 CSIB4 and UARTA0 mode switching ...................................................................................... 542 16.1.2 CSIB0 and I2C01 mode switching ............................................................................................ 543 Features..................................................................................................................................544 Configuration .........................................................................................................................545 Registers ................................................................................................................................547 Interrupt Request Signals.....................................................................................................555 Operation................................................................................................................................556 16.6.1 Single transfer mode (master mode, transmission mode) ....................................................... 556 16.6.2 Single transfer mode (master mode, reception mode)............................................................. 558 16.6.3 Single transfer mode (master mode, transmission/reception mode)........................................ 560 <R> 16.6.4 Single transfer mode (slave mode, transmission mode) .......................................................... 562 <R> <R> 16.6.5 Single transfer mode (slave mode, reception mode) ............................................................... 564 16.6.6 Single transfer mode (slave mode, transmission/reception mode) .......................................... 566 <R> 16.6.7 Continuous transfer mode (master mode, transmission mode) ............................................... 568 16.6.8 Continuous transfer mode (master mode, reception mode)..................................................... 570 16.6.9 Continuous transfer mode (master mode, transmission/reception mode)................................ 573 16.6.10 Continuous transfer mode (slave mode, transmission mode).................................................. 577 <R> 16.6.11 Continuous transfer mode (slave mode, reception mode) ....................................................... 579 16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) .................................. 582 16.6.13 Reception error........................................................................................................................ 586 16.6.14 Clock timing ............................................................................................................................. 587 16.7 Output Pins ............................................................................................................................589 User's Manual U16541EJ5V1UD 13 16.8 Baud Rate Generator............................................................................................................ 590 16.8.1 16.9 Baud rate generation ...............................................................................................................591 Cautions ................................................................................................................................ 592 CHAPTER 17 I2C BUS .......................................................................................................................... 593 17.1 17.2 17.3 17.4 17.5 Mode Switching of I2C Bus and Other Serial Interfaces ................................................... 593 17.1.1 UARTA2 and I2C00 mode switching.........................................................................................593 17.1.2 CSIB0 and I2C01 mode switching ............................................................................................594 17.1.3 UARTA1 and I2C02 mode switching.........................................................................................595 Features................................................................................................................................. 596 Configuration ........................................................................................................................ 597 Registers ............................................................................................................................... 601 I2C Bus Mode Functions....................................................................................................... 617 17.5.1 17.6 17.7 17.8 17.9 17.10 17.11 17.12 17.13 17.14 Pin configuration ......................................................................................................................617 2 I C Bus Definitions and Control Methods .......................................................................... 618 17.6.1 Start condition..........................................................................................................................618 17.6.2 Addresses................................................................................................................................619 17.6.3 Transfer direction specification ................................................................................................620 17.6.4 ACK .........................................................................................................................................621 17.6.5 Stop condition ..........................................................................................................................622 17.6.6 Wait state.................................................................................................................................623 17.6.7 Wait state cancellation method ................................................................................................625 2 I C Interrupt Request Signals (INTIICn) .............................................................................. 626 17.7.1 Master device operation...........................................................................................................627 17.7.2 Slave device operation (when receiving slave address (address match))................................630 17.7.3 Slave device operation (when receiving extension code) ........................................................634 17.7.4 Operation without communication............................................................................................638 17.7.5 Arbitration loss operation (operation as slave after arbitration loss).........................................639 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ...................641 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 648 Address Match Detection Method ...................................................................................... 649 Error Detection...................................................................................................................... 649 Extension Code..................................................................................................................... 650 Arbitration ............................................................................................................................. 651 Wakeup Function.................................................................................................................. 652 Communication Reservation............................................................................................... 653 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................653 17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................657 17.15 Cautions ................................................................................................................................ 658 17.16 Communication Operations ................................................................................................ 659 17.16.1 Master operation in single master system................................................................................660 17.16.2 Master operation in multimaster system ..................................................................................661 17.16.3 Slave operation........................................................................................................................664 17.17 Timing of Data Communication .......................................................................................... 668 CHAPTER 18 IEBus CONTROLLER................................................................................................... 675 18.1 14 Functions............................................................................................................................... 675 User's Manual U16541EJ5V1UD 18.2 18.3 18.4 18.5 18.1.1 Communication protocol of IEBus ........................................................................................... 675 18.1.2 Determination of bus mastership (arbitration).......................................................................... 676 18.1.3 Communication mode.............................................................................................................. 676 18.1.4 Communication address .......................................................................................................... 676 18.1.5 Broadcast communication ....................................................................................................... 677 18.1.6 Transfer format of IEBus ......................................................................................................... 677 18.1.7 Transfer data ........................................................................................................................... 687 18.1.8 Bit format ................................................................................................................................. 689 Configuration .........................................................................................................................690 Registers ................................................................................................................................692 Interrupt Operations of IEBus Controller............................................................................722 18.4.1 Interrupt control block .............................................................................................................. 722 18.4.2 Example of identifying interrupt ............................................................................................... 725 18.4.3 Interrupt source list .................................................................................................................. 728 18.4.4 Communication error source processing list............................................................................ 729 Interrupt Request Signal Generation Timing and Main CPU Processing........................731 18.5.1 Master transmission ................................................................................................................ 731 18.5.2 Master reception...................................................................................................................... 733 18.5.3 Slave transmission .................................................................................................................. 735 18.5.4 Slave reception........................................................................................................................ 737 18.5.5 Interval of occurrence of interrupt request signal for IEBus control ......................................... 739 CHAPTER 19 CAN CONTROLLER ......................................................................................................743 19.1 19.2 19.3 19.4 19.5 19.6 19.7 Overview.................................................................................................................................743 19.1.1 Features .................................................................................................................................. 743 19.1.2 Overview of functions .............................................................................................................. 744 19.1.3 Configuration ........................................................................................................................... 745 CAN Protocol .........................................................................................................................746 19.2.1 Frame format ........................................................................................................................... 746 19.2.2 Frame types ............................................................................................................................ 747 19.2.3 Data frame and remote frame.................................................................................................. 747 19.2.4 Error frame .............................................................................................................................. 754 19.2.5 Overload frame........................................................................................................................ 755 Functions ...............................................................................................................................756 19.3.1 Determining bus priority........................................................................................................... 756 19.3.2 Bit stuffing................................................................................................................................ 756 19.3.3 Multi masters ........................................................................................................................... 756 19.3.4 Multi cast ................................................................................................................................. 756 19.3.5 CAN sleep mode/CAN stop mode function.............................................................................. 757 19.3.6 Error control function ............................................................................................................... 757 19.3.7 Baud rate control function........................................................................................................ 762 Connection with Target System ..........................................................................................766 Internal Registers of CAN Controller ..................................................................................767 19.5.1 CAN controller configuration.................................................................................................... 767 19.5.2 Register access type ............................................................................................................... 768 19.5.3 Register bit configuration ......................................................................................................... 785 Registers ................................................................................................................................789 Bit Set/Clear Function...........................................................................................................824 User's Manual U16541EJ5V1UD 15 19.8 19.9 <R> CAN Controller Initialization................................................................................................ 826 19.8.1 Initialization of CAN module.....................................................................................................826 19.8.2 Initialization of message buffer ................................................................................................826 19.8.3 Redefinition of message buffer ................................................................................................826 19.8.4 Transition from initialization mode to operation mode..............................................................828 19.8.5 Resetting error counter C0ERC of CAN module ......................................................................828 Message Reception .............................................................................................................. 829 19.9.1 Message reception ..................................................................................................................829 19.9.2 Reading reception data............................................................................................................830 19.9.3 Receive history list function .....................................................................................................831 19.9.4 Mask function...........................................................................................................................833 19.9.5 Multi buffer receive block function............................................................................................835 19.9.6 Remote frame reception ..........................................................................................................836 19.10 Message Transmission ........................................................................................................ 837 19.10.1 Message transmission .............................................................................................................837 19.10.2 Transmit history list function ....................................................................................................839 19.10.3 Automatic block transmission (ABT) ........................................................................................841 19.10.4 Transmission abort process.....................................................................................................842 19.10.5 Remote frame transmission .....................................................................................................843 19.11 Power Saving Modes............................................................................................................ 844 19.11.1 CAN sleep mode......................................................................................................................844 19.11.2 CAN stop mode .......................................................................................................................846 19.11.3 Example of using power saving modes....................................................................................847 19.12 Interrupt Function................................................................................................................. 848 19.13 Diagnosis Functions and Special Operational Modes ..................................................... 849 19.13.1 Receive-only mode ..................................................................................................................849 19.13.2 Single-shot mode.....................................................................................................................850 19.13.3 Self-test mode..........................................................................................................................851 19.13.4 Transmission/reception operation in each operation mode......................................................852 <R> 19.14 Time Stamp Function ........................................................................................................... 853 19.14.1 Time stamp function ................................................................................................................853 19.15 Baud Rate Settings............................................................................................................... 855 19.15.1 Bit rate setting conditions.........................................................................................................855 19.15.2 Representative examples of baud rate settings .......................................................................859 19.16 Operation of CAN Controller ............................................................................................... 863 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) ................................................................... 889 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 20.9 20.10 20.11 16 Features................................................................................................................................. 889 Configuration ........................................................................................................................ 890 Registers ............................................................................................................................... 891 Transfer Targets ................................................................................................................... 899 Transfer Modes ..................................................................................................................... 899 Transfer Types ...................................................................................................................... 900 DMA Channel Priorities........................................................................................................ 901 Time Related to DMA Transfer ............................................................................................ 901 DMA Transfer Start Factors................................................................................................. 902 DMA Abort Factors............................................................................................................... 903 End of DMA Transfer............................................................................................................ 903 User's Manual U16541EJ5V1UD 20.12 Operation Timing...................................................................................................................903 20.13 Cautions .................................................................................................................................908 CHAPTER 21 CRC FUNCTION ............................................................................................................912 21.1 21.2 21.3 21.4 21.5 Functions ...............................................................................................................................912 Configuration .........................................................................................................................912 Registers ................................................................................................................................913 Operation................................................................................................................................914 Usage......................................................................................................................................915 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................917 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 Features..................................................................................................................................917 Non-Maskable Interrupts ......................................................................................................921 22.2.1 Operation................................................................................................................................. 923 22.2.2 Restore.................................................................................................................................... 924 22.2.3 NP flag..................................................................................................................................... 925 Maskable Interrupts ..............................................................................................................926 22.3.1 Operation................................................................................................................................. 926 22.3.2 Restore.................................................................................................................................... 928 22.3.3 Priorities of maskable interrupts .............................................................................................. 929 22.3.4 Interrupt control register (xxICn) .............................................................................................. 933 22.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)........................................................................ 936 22.3.6 In-service priority register (ISPR)............................................................................................. 938 22.3.7 ID flag ...................................................................................................................................... 939 22.3.8 Watchdog timer mode register 2 (WDTM2) ............................................................................. 939 Software Exception ...............................................................................................................940 22.4.1 Operation................................................................................................................................. 940 22.4.2 Restore.................................................................................................................................... 941 22.4.3 EP flag..................................................................................................................................... 942 Exception Trap ......................................................................................................................943 22.5.1 Illegal opcode definition ........................................................................................................... 943 22.5.2 Debug trap............................................................................................................................... 945 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) ....................................947 22.6.1 Noise elimination ..................................................................................................................... 947 22.6.2 Edge detection......................................................................................................................... 947 Interrupt Acknowledge Time of CPU...................................................................................952 Periods in Which Interrupts Are Not Acknowledged by CPU...........................................955 Cautions .................................................................................................................................955 CHAPTER 23 KEY INTERRUPT FUNCTION ......................................................................................956 23.1 23.2 23.3 Function .................................................................................................................................956 Register ..................................................................................................................................957 Cautions .................................................................................................................................957 CHAPTER 24 STANDBY FUNCTION...................................................................................................958 24.1 Overview.................................................................................................................................958 User's Manual U16541EJ5V1UD 17 24.2 24.3 24.4 24.5 24.6 24.7 24.8 Registers ............................................................................................................................... 960 HALT Mode............................................................................................................................ 963 24.3.1 Setting and operation status ....................................................................................................963 24.3.2 Releasing HALT mode.............................................................................................................963 IDLE1 Mode ........................................................................................................................... 965 24.4.1 Setting and operation status ....................................................................................................965 24.4.2 Releasing IDLE1 mode ............................................................................................................966 IDLE2 Mode ........................................................................................................................... 968 24.5.1 Setting and operation status ....................................................................................................968 24.5.2 Releasing IDLE2 mode ............................................................................................................968 24.5.3 Securing setup time when releasing IDLE2 mode ...................................................................970 STOP Mode............................................................................................................................ 971 24.6.1 Setting and operation status ....................................................................................................971 24.6.2 Releasing STOP mode ............................................................................................................971 24.6.3 Securing oscillation stabilization time when releasing STOP mode .........................................974 Subclock Operation Mode ................................................................................................... 975 24.7.1 Setting and operation status ....................................................................................................975 24.7.2 Releasing subclock operation mode ........................................................................................975 Sub-IDLE Mode ..................................................................................................................... 977 24.8.1 Setting and operation status ....................................................................................................977 24.8.2 Releasing sub-IDLE mode .......................................................................................................978 CHAPTER 25 RESET FUNCTIONS ..................................................................................................... 980 25.1 25.2 25.3 <R> 25.4 Overview................................................................................................................................ 980 Registers to Check Reset Source....................................................................................... 982 Operation............................................................................................................................... 983 25.3.1 Reset operation via RESET pin ...............................................................................................983 25.3.2 Reset operation by watchdog timer 2 (WDT2RES)..................................................................985 25.3.3 Reset operation by low-voltage detector (LVIRES) (V850ES/SG2 only)..................................987 25.3.4 Reset operation by clock monitor (CLMRES) ..........................................................................988 25.3.5 Operation after reset release ...................................................................................................990 25.3.6 Reset function operation flow...................................................................................................992 Valid/Invalid of Internal RAM Data ...................................................................................... 993 CHAPTER 26 CLOCK MONITOR ........................................................................................................ 994 26.1 26.2 26.3 26.4 Functions............................................................................................................................... 994 Configuration ........................................................................................................................ 994 Register ................................................................................................................................. 995 Operation............................................................................................................................... 996 CHAPTER 27 LOW-VOLTAGE DETECTOR ....................................................................................... 999 27.1 27.2 27.3 27.4 Functions............................................................................................................................... 999 Configuration ........................................................................................................................ 999 Registers ............................................................................................................................. 1000 Operation............................................................................................................................. 1002 27.4.1 18 To use for internal reset signal (LVIRES) 19-21 ....................................................................1002 User's Manual U16541EJ5V1UD 27.4.2 27.5 27.6 To use for interrupt (INTLVI).................................................................................................. 1003 RAM Retention Voltage Detection Operation (Provided in Both V850ES/SG2 and V850ES/SG2-H).....................................................................................................................1004 Emulation Function (Provided in Both V850ES/SG2 and V850ES/SG2-H) ....................1005 CHAPTER 28 REGULATOR ................................................................................................................1006 28.1 28.2 Outline ..................................................................................................................................1006 Operation..............................................................................................................................1007 CHAPTER 29 ROM CORRECTION FUNCTION ...............................................................................1008 29.1 29.2 29.3 29.4 Overview...............................................................................................................................1008 Registers ..............................................................................................................................1009 ROM Correction Operation and Program Flow ................................................................1011 Cautions ...............................................................................................................................1013 CHAPTER 30 FLASH MEMORY.........................................................................................................1014 30.1 30.2 30.3 30.4 30.5 Features................................................................................................................................1014 Memory Configuration ........................................................................................................1015 Functional Outline...............................................................................................................1018 Rewriting by Dedicated Flash Memory Programmer.......................................................1021 30.4.1 Programming environment .................................................................................................... 1021 30.4.2 Communication mode............................................................................................................ 1022 30.4.3 Flash memory control ............................................................................................................ 1031 30.4.4 Selection of communication mode......................................................................................... 1032 30.4.5 Communication commands ................................................................................................... 1033 30.4.6 Pin connection ....................................................................................................................... 1034 Rewriting by Self Programming.........................................................................................1038 30.5.1 Overview ............................................................................................................................... 1038 30.5.2 Features ................................................................................................................................ 1039 30.5.3 Standard self programming flow ............................................................................................ 1040 30.5.4 Flash functions ...................................................................................................................... 1041 30.5.5 Pin processing ....................................................................................................................... 1041 30.5.6 Internal resources used ......................................................................................................... 1042 CHAPTER 31 ON-CHIP DEBUG FUNCTION....................................................................................1043 31.1 31.2 31.3 31.4 31.5 31.6 31.7 Features................................................................................................................................1043 Connection Circuit Example ..............................................................................................1044 Interface Signals..................................................................................................................1044 Register ................................................................................................................................1046 Operation..............................................................................................................................1048 ROM Security Function.......................................................................................................1049 31.6.1 Security ID............................................................................................................................. 1049 31.6.2 Setting ................................................................................................................................... 1050 Cautions ...............................................................................................................................1052 CHAPTER 32 ELECTRICAL SPECIFICATIONS ................................................................................1053 User's Manual U16541EJ5V1UD 19 32.1 32.2 32.3 32.4 32.5 32.6 32.7 32.8 Absolute Maximum Ratings .............................................................................................. 1053 Capacitance......................................................................................................................... 1055 Operating Conditions......................................................................................................... 1055 Oscillator Characteristics .................................................................................................. 1056 32.4.1 Main clock oscillator characteristics .......................................................................................1056 32.4.2 Subclock oscillator characteristics .........................................................................................1059 32.4.3 PLL characteristics ................................................................................................................1060 32.4.4 Internal oscillator characteristics............................................................................................1060 Regulator Characteristics.................................................................................................. 1061 DC Characteristics ............................................................................................................. 1062 32.6.1 I/O level .................................................................................................................................1062 32.6.2 Supply current........................................................................................................................1064 Data Retention Characteristics ......................................................................................... 1066 AC Characteristics ............................................................................................................. 1067 32.8.1 CLKOUT output timing........................................................................................................... 1068 32.8.2 Bus timing ..............................................................................................................................1068 32.9 Basic Operation .................................................................................................................. 1082 32.10 Flash Memory Programming Characteristics.................................................................. 1091 CHAPTER 33 PACKAGE DRAWINGS .............................................................................................. 1094 CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS......................................................... 1096 APPENDIX A DEVELOPMENT TOOLS............................................................................................. 1098 A.1 A.2 A.3 A.4 <R> <R> A.5 A.6 A.7 Software Package ............................................................................................................... 1103 Language Processing Software ........................................................................................ 1103 Control Software................................................................................................................. 1103 Debugging Tools (Hardware) ............................................................................................ 1104 A.4.1 When using in-circuit emulator IE-V850ES-G1 ......................................................................1104 A.4.2 When using IECUBE QB-V850ESSX2 ..................................................................................1106 A.4.3 When using on-chip debug emulator IE-V850E1-CD-NW......................................................1109 A.4.4 When using MINICUBE QB-V850MINI ..................................................................................1110 Debugging Tools (Software).............................................................................................. 1111 Embedded Software ........................................................................................................... 1112 Flash Memory Writing Tools ............................................................................................. 1112 <R> APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/SG2 AND V850ES/SG2-H ............. 1113 APPENDIX C REGISTER INDEX ....................................................................................................... 1115 APPENDIX D INSTRUCTION SET LIST ........................................................................................... 1127 D.1 D.2 20 Conventions ........................................................................................................................ 1127 Instruction Set (in Alphabetical Order) ............................................................................ 1130 User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY ....................................................................................................1137 E.1 E.2 Major Revisions in This Edition .........................................................................................1137 Revision History of Previous Editions ..............................................................................1147 User's Manual U16541EJ5V1UD 21 CHAPTER 1 INTRODUCTION The V850ES/SG2 and V850ES/SG2-H are products in the NEC Electronics V850 single-chip microcontrollers <R> designed for low-power operation for real-time control applications. <R> 1.1 General The V850ES/SG2 and V850ES/SG2-H are 32-bit single-chip microcontrollers that include the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter. Some models of the V850ES/SG2 and V850ES/SG2-H are provided with IEBusTM (Inter Equipment BusTM) or CAN (Controller Area Network) as an automotive LAN. In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/SG2 and V850ES/SG2-H feature multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. Moreover, as a realtime control system, the V850ES/SG2 and V850ES/SG2-H enable an extremely high cost-performance for applications that require a low power consumption, such as audio and car audio. Table 1-1 lists the products of the V850ES/SG2 and V850ES/SG2-H. Models of the V850ES/SG2 and V850ES/SG2-H with expanded I/O, timer/counter, and serial interface functions, V850ES/SJ2 and V850ES/SJ2-H, are also available. See Table 1-2 V850ES/SJ2, V850ES/SJ2-H Product List. 22 User's Manual U16541EJ5V1UD CHAPTER 1 INTRODUCTION Table 1-1. V850ES/SG2, V850ES/SG2-H Product List <R> Function ROM Type Size RAM Size Operating Frequency (MAX.) 256 KB 24 KB 20 MHz Part Number PD703260 Mask ROM PD703260Y PD703261 IEBus CAN None None None Maskable Interrupts Non-maskable Interrupts External Internal 8 47 2 On-chip 384 KB 32 KB None PD703261Y On-chip PD70F3261 PD70F3261Y PD703262 None Flash memory Mask ROM PD703262Y On-chip 512 KB None 40 KB On-chip PD703262HY 32 MHz PD703263 640 KB 48 KB 20 MHz PD703263Y 46 47 None On-chip PD703263HY PD70F3263 PD70F3263Y 32 MHz 20 MHz Flash memory PD703270 32 MHz Mask ROM PD703270Y 46 47 None On-chip PD70F3263HY PD703271 256 KB 24 KB 384 KB 32 KB 20 MHz 46 None 51 On-chip On-chip None PD703271Y On-chip PD70F3271 PD70F3271Y PD703272 Flash memory Mask ROM PD703272Y None On-chip 512 KB 40 KB None On-chip PD703272HY 32 MHz PD703273 640 KB 48 KB 20 MHz PD703273Y 50 51 None On-chip PD703273HY PD70F3273 PD70F3273Y 32 MHz 20 MHz Flash memory PD703280 32 MHz Mask ROM PD703280Y 50 51 None On-chip PD70F3273HY PD703281 256 KB 24 KB 20 MHz 50 None None On-chip 51 On-chip 384 KB 32 KB None PD703281Y On-chip PD70F3281 PD70F3281Y PD703282 None Flash memory Mask ROM PD703282Y On-chip 512 KB None 40 KB On-chip PD703282HY 32 MHz PD703283 640 KB 48 KB 20 MHz PD703283Y 50 None 51 On-chip PD703283HY PD70F3283 PD70F3283Y PD70F3283HY Remark 2 IC 32 MHz Flash memory 20 MHz 50 None 51 On-chip 32 MHz 50 The part numbers of the V850ES/SG2 and V850ES/SG2-H are shown as follows in this manual. User's Manual U16541EJ5V1UD 23 CHAPTER 1 INTRODUCTION * V850ES/SG2 <R> PD703260, 703260Y, 703261, 703261Y, 703262, 703262Y, 703263, 703263Y, 703270, 703270Y, 703271, 703271Y, 703272, 703272Y, 703273, 703273Y, 703280, 703280Y, 703281, 703281Y, 703282, 703282Y, 703283, 703283Y, 70F3261, 70F3261Y, 70F3263, 70F3263Y, 70F3271, 70F3271Y, 70F3273, 70F3273Y, 70F3281, 70F3281Y, 70F3283, 70F3283Y <R> * V850ES/SG2-H <R> * Mask ROM version PD703262HY, 703263HY, 703272HY, 703273HY, 703282HY, 703283HY, 70F3263HY, 70F3273HY, 70F3283HY PD703260, 703260Y, 703261, 703261Y, 703262, 703262Y, 703262HY, 703263, 703263Y, 703263HY, 703270, 703270Y, 703271, 703271Y, 703272, 703272Y, 703272HY, 703273, 703273Y, 703273HY, 703280, 703280Y, 703281, 703281Y, 703282, 703282Y, 703282HY, 703283, 703283Y, 703283HY * Flash memory version <R> PD70F3261, 70F3261Y, 70F3263, 70F3263Y, 70F3263HY, 70F3271, 70F3271Y, 70F3273, 70F3273Y, 70F3273HY, 70F3281, 70F3281Y, 70F3283, 70F3283Y, 70F3283HY * I2C bus version (Y version): All V850ES/SG2-H products have an on-chip I2C bus. <R> PD703260Y, 703261Y, 703262Y, 703262HY, 703263Y, 703263HY, 703270Y, 703271Y, 703272Y, 703272HY, 703273Y, 703273HY, 703280Y, 703281Y, 703282Y, 703282HY, 703283Y, 703283HY, 70F3261Y, 70F3263Y, 70F3263HY, 70F3271Y, 70F3273Y, 70F3273HY, 70F3281Y, 70F3283Y, 70F3283HY * General-purpose version <R> PD703260, 703260Y, 703261, 703261Y, 703262, 703262Y, 703262HY, 703263, 703263Y, 703263HY, 70F3261, 70F3261Y, 70F3263, 70F3263Y, 70F3263HY * IEBus controller version <R> PD703270, 703270Y, 703271, 703271Y, 703272, 703272Y, 703272HY, 703273, 703273Y, 703273HY, 70F3271, 70F3271Y, 70F3273, 70F3273Y, 70F3273HY * CAN controller version <R> PD703280, 703280Y, 703281, 703281Y, 703282, 703282Y, 703282HY, 703283, 703283Y, 703283HY, 70F3281, 70F3281Y, 70F3283, 70F3283Y, 70F3283HY 24 User's Manual U16541EJ5V1UD CHAPTER 1 INTRODUCTION Table 1-2. V850ES/SJ2, V850ES/SJ2-H Product List <R> Function Part Number PD703264 ROM Type Size Mask ROM 384 KB RAM Size Operating Frequency (MAX.) 32 KB 20 MHz PD703264Y PD70F3264 PD703265 Mask ROM 512 KB 640 KB 48 KB 20 MHz Mask ROM 384 KB 32 KB 20 MHz PD703275 Mask ROM 512 KB None 40 KB None On-chip PD703275HY 32 MHz PD703276 640 KB 48 KB 20 MHz PD703276Y 64 32 MHz Flash memory 20 MHz 63 None 64 On-chip PD70F3276HY 32 MHz Mask ROM 384 KB 32 KB 20 MHz PD703284Y 63 None None 1 ch 64 On-chip PD70F3284Y Flash memory PD703285 Mask ROM 512 KB None On-chip None 40 KB PD703285Y On-chip PD703285HY 32 MHz PD703286 640 KB 48 KB 20 MHz PD703286Y 63 64 None On-chip PD703286HY 32 MHz 20 MHz Flash memory 63 64 None On-chip PD70F3286HY 32 MHz Mask ROM 512 KB 40 KB 20 MHz PD703287Y 63 None 2 ch 68 On-chip PD703287HY 32 MHz PD703288 640 KB 48 KB 20 MHz PD703288Y 67 None 68 On-chip PD703288HY PD70F3286HY 63 None On-chip PD703276HY PD70F3288Y 64 On-chip On-chip PD703275Y PD70F3288 59 None On-chip Flash memory PD703287 59 60 None On-chip PD70F3274Y PD70F3286Y 60 None 32 MHz PD703274Y PD70F3286 2 59 32 MHz 20 MHz Flash memory PD70F3266HY PD70F3284 60 On-chip PD703266HY PD703284 9 None PD703266Y PD70F3276Y None 32 MHz PD703266 PD70F3276 None On-chip PD703265HY PD70F3274 None On-chip 40 KB PD703265Y PD703274 CAN Maskable Interrupts Non-Maskable Interrupts External Internal None PD70F3264Y PD70F3266Y IEBus On-chip Flash memory PD70F3266 2 IC 32 MHz Flash memory 20 MHz 67 None 68 On-chip 32 MHz User's Manual U16541EJ5V1UD 67 25 CHAPTER 1 INTRODUCTION 1.2 Features { Minimum instruction execution time: V850ES/SG2: 50 ns (operating with main clock (fXX) = 20 MHz) V850ES/SG2-H: 31.25 ns (operating with main clock (fXX) = 32 MHz) <R> { General-purpose registers: 32 bits x 32 registers { CPU features: Signed multiplication (16 x 16 32): 1 to 2 clocks Signed multiplication (32 x 32 64): 1 to 5 clocks Saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format { Memory space: <R> 64 MB of linear address space (for programs and data) External expansion: Up to 4 MB * Internal memory: RAM: 24/32/40/48 KB (see Table 1-1) Mask ROM: 256/384/512/640 KB (see Table 1-1) Flash memory: 384/640 KB (see Table 1-1) * External bus interface: Separate bus/multiplexed bus output selectable 8/16 bit data bus sizing function Wait function * Programmable wait function * External wait function Idle state function Bus hold function { Interrupts and exceptions: <R> Non-maskable interrupts: 2 sources Maskable interrupts: 54/55/58/59 sources (see Table 1-1) Software exceptions: 32 sources Exception trap: 2 sources { I/O lines: I/O ports: { Timer function: 16-bit interval timer M (TMM): 84 1 channel 16-bit timer/event counter P (TMP): 6 channels 16-bit timer/event counter Q (TMQ): 1 channel Watch timer: 1 channel Watchdog timer: 1 channel { Real-time output port: 6 bits x 1 channel { Serial interface: Asynchronous serial interface A (UARTA) 3-wire variable-length serial interface B (CSIB) I2C bus interface (I2C) (I2C bus versions (Y products) only) UARTA/CSIB: 1 channel UARTA/I2C: 2 26 2 channels CSIB/I C: 1 channel CSIB: 3 channels { IEBus controller: 1 channel (IEBus controller version only) { CAN controller: 1 channel (CAN controller version only) { A/D converter: 10-bit resolution: 12 channels { D/A converter: 8-bit resolution: 2 channels { DMA controller: 4 channels { CRC function: 16-bit error detection codes are generated for data in 8-bit units User's Manual U16541EJ5V1UD CHAPTER 1 INTRODUCTION { On-chip debug function: JTAG interface (flash memory version only) { ROM correction: 4 correction addresses specifiable { Clock generator: During main clock or subclock operation 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Clock-through mode/PLL mode selectable <R> { Internal oscillation clock: 200 kHz (TYP.) { Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode { Package: 100-pin plastic QFP (14 x 20) (V850ES/SG2 only (see 1.4 Ordering Information)) 100-pin plastic LQFP (fine pitch) (14 x 14) 1.3 Application Fields Audio, car audio, consumer devices User's Manual U16541EJ5V1UD 27 CHAPTER 1 INTRODUCTION <R> 1.4 Ordering Information (1) V850ES/SG2 Part Number PD703260GC-xxx-8EA-A PD703260GF-xxx-JBT-A PD703260YGC-xxx-8EA-A PD703260YGF-xxx-JBT-A PD703261GC-xxx-8EA-A PD703261GF-xxx-JBT-A PD703261YGC-xxx-8EA-A PD703261YGF-xxx-JBT-A PD703262GC-xxx-8EA-A PD703262YGC-xxx-8EA-A PD703263GC-xxx-8EA-A PD703263YGC-xxx-8EA-A PD703270GC-xxx-8EA-A PD703270GF-xxx-JBT-A PD703270YGC-xxx-8EA-A PD703270YGF-xxx-JBT-A PD703271GC-xxx-8EA-A PD703271GF-xxx-JBT-A PD703271YGC-xxx-8EA-A PD703271YGF-xxx-JBT-A PD703272GC-xxx-8EA-A PD703272YGC-xxx-8EA-A PD703273GC-xxx-8EA-A PD703273YGC-xxx-8EA-A PD703280GC-xxx-8EA-A PD703280YGC-xxx-8EA-A PD703281GC-xxx-8EA-A PD703281YGC-xxx-8EA-A PD703282GC-xxx-8EA-A PD703282YGC-xxx-8EA-A PD703283GC-xxx-8EA-A PD703283YGC-xxx-8EA-A Package 100-pin plastic LQFP (fine pitch) (14 x 14) 256 KB (mask ROM) 100-pin plastic QFP (14 x 20) 256 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 256 KB (mask ROM) 100-pin plastic QFP (14 x 20) 256 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (mask ROM) 100-pin plastic QFP (14 x 20) 384 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (mask ROM) 100-pin plastic QFP (14 x 20) 384 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 512 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 512 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 256 KB (mask ROM) 100-pin plastic QFP (14 x 20) 256 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 256 KB (mask ROM) 100-pin plastic QFP (14 x 20) 256 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (mask ROM) 100-pin plastic QFP (14 x 20) 384 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (mask ROM) 100-pin plastic QFP (14 x 20) 384 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 512 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 512 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 256 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 256 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 512 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 512 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (mask ROM) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (mask ROM) Remarks 1. xxx indicates ROM code suffix. 2. V850ES/SG2 microcontrollers are lead-free products. 28 Internal ROM User's Manual U16541EJ5V1UD CHAPTER 1 INTRODUCTION Part Number PD70F3261GC-8EA-A PD70F3261GF-JBT-A PD70F3261YGC-8EA-A PD70F3261YGF-JBT-A PD70F3263GC-8EA-A PD70F3263YGC-8EA-A PD70F3271GC-8EA-A PD70F3271GF-JBT-A PD70F3271YGC-8EA-A PD70F3271YGF-JBT-A PD70F3273GC-8EA-A PD70F3273YGC-8EA-A PD70F3281GC-8EA-A PD70F3281YGC-8EA-A PD70F3283GC-8EA-A PD70F3283YGC-8EA-A Remark Package Internal ROM 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (flash memory) 100-pin plastic QFP (14 x 20) 384 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (flash memory) 100-pin plastic QFP (14 x 20) 384 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (flash memory) 100-pin plastic QFP (14 x 20) 384 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (flash memory) 100-pin plastic QFP (14 x 20) 384 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 384 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (flash memory) 100-pin plastic LQFP (fine pitch) (14 x 14) 640 KB (flash memory) V850ES/SG2 microcontrollers are lead-free products. (2) V850ES/SG2-H Part Number PD703262HYGC-xxx-8EA-A PD703263HYGC-xxx-8EA-A PD703272HYGC-xxx-8EA-A PD703273HYGC-xxx-8EA-A PD703282HYGC-xxx-8EA-A PD703283HYGC-xxx-8EA-A PD70F3263HYGC-8EA-A PD70F3273HYGC-8EA-A PD70F3283HYGC-8EA-A Package Internal ROM 100-pin plastic QFP (14 x 20) 512 KB (mask ROM) 100-pin plastic QFP (14 x 20) 640 KB (mask ROM) 100-pin plastic QFP (14 x 20) 512 KB (mask ROM) 100-pin plastic QFP (14 x 20) 640 KB (mask ROM) 100-pin plastic QFP (14 x 20) 512 KB (mask ROM) 100-pin plastic QFP (14 x 20) 640 KB (mask ROM) 100-pin plastic QFP (14 x 20) 640 KB (flash memory) 100-pin plastic QFP (14 x 20) 640 KB (flash memory) 100-pin plastic QFP (14 x 20) 640 KB (flash memory) Remarks 1. xxx indicates ROM code suffix. 2. V850ES/SG2 microcontrollers are lead-free products. User's Manual U16541EJ5V1UD 29 CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) 100-pin plastic LQFP (fine pitch) (14 x 14) * V850ES/SG2 PD703260GC-xxx-8EA-A PD703260YGC-xxx-8EA-A PD703261GC-xxx-8EA-A PD703261YGC-xxx-8EA-A PD703262GC-xxx-8EA-A PD703262YGC-xxx-8EA-A PD703263GC-xxx-8EA-A PD703263YGC-xxx-8EA-A PD70F3261GC-8EA-A PD70F3261YGC-8EA-A PD70F3263GC-8EA-A PD70F3263YGC-8EA-A <R> <R> <R> <R> <R> <R> <R> <R> <R> <R> <R> <R> PD703270GC-xxx-8EA-A PD703270YGC-xxx-8EA-A PD703271GC-xxx-8EA-A PD703271YGC-xxx-8EA-A PD703272GC-xxx-8EA-A PD703272YGC-xxx-8EA-A PD703273GC-xxx-8EA-A PD703273YGC-xxx-8EA-A PD70F3271GC-8EA-A PD70F3271YGC-8EA-A PD70F3273GC-8EA-A PD70F3273YGC-8EA-A PD703280GC-xxx-8EA-A PD703280YGC-xxx-8EA-A PD703281GC-xxx-8EA-A PD703281YGC-xxx-8EA-A PD703282GC-xxx-8EA-A PD703282YGC-xxx-8EA-A PD703283GC-xxx-8EA-A PD703283YGC-xxx-8EA-A PD70F3281GC-8EA-A PD70F3281YGC-8EA-A PD70F3283GC-8EA-A PD70F3283YGC-8EA-A PD703272HYGC-xxx-8EA-A PD703273HYGC-xxx-8EA-A PD70F3273HYGC-8EA-A PD703282HYGC-xxx-8EA-A PD703283HYGC-xxx-8EA-A PD70F3283HYGC-8EA-A * V850ES/SG2-H PD703262HYGC-xxx-8EA-A PD703263HYGC-xxx-8EA-A PD70F3263HYGC-8EA-A <R> <R> <R> 30 User's Manual U16541EJ5V1UD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P70/ANI0Note 9 P71/ANI1Note 9 P72/ANI2Note 9 P73/ANI3Note 9 P74/ANI4Note 9 P75/ANI5Note 9 P76/ANI6Note 9 P77/ANI7Note 9 P78/ANI8Note 9 P79/ANI9Note 9 P710/ANI10Note 9 P711/ANI11Note 9 PDH1/A17 PDH0/A16 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1Note 1 CHAPTER 1 INTRODUCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PDH3/A19 PDH2/A18 P915/A15Note 8/INTP6/TIP50/TOP50 P914/A14Note 8/INTP5/TIP51/TOP51 P913/A13Note 8/INTP4 P912/A12Note 8/SCKB3 P911/A11Note 8/SOB3 P910/A10Note 8/SIB3 P99/A9Note 8/SCKB1 P98/A8Note 8/SOB1 P31/RXDA0/INTP7/SIB4 P32/ASCKA0/SCKB4/TIP00/TOP00 P33/TIP01/TOP01 P34/TIP10/TOP10 P35/TIP11/TOP11 P36/CTXD0Note 4/IETX0Note 5 P37/CRXD0Note 4/IERX0Note 5 EVSS EVDD P38/TXDA2/SDA00Note 3 P39/RXDA2/SCL00Note 3 P50/TIQ01/KR0/TOQ01/RTP00 P51/TIQ02/KR1/TOQ02/RTP01 P52/TIQ03/KR2/TOQ03/RTP02/DDINote 6 P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDONote 6 P54/SOB2/KR4/RTP04/DCKNote 6 P55/SCKB2/KR5/RTP05/DMSNote 6 P90/A0Note 8/KR6/TXDA1/SDA02Note 3 P91/A1Note 8/KR7/RXDA1/SCL02Note 3 P92/A2Note 8/TIP41/TOP41 P93/A3Note 8/TIP40/TOP40 P94/A4Note 8/TIP31/TOP31 P95/A5Note 8/TIP30/TOP30 P96/A6Note 8/TIP21/TOP21 P97/A7Note 8/SIB1/TIP20/TOP20 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AVREF0 AVSS P10/ANO0 P11/ANO1 AVREF1 PDH4/A20 PDH5/A21 ICNote 1/FLMD0Note 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P02/NMI P03/INTP0/ADTRG P04/INTP1 P05/INTP2/DRSTNotes 6, 7 P06/INTP3 P40/SIB0/SDA01Note 3 P41/SOB0/SCL01Note 3 P42/SCKB0 P30/TXDA0/SOB4 Notes 1. IC: Directly connect this pin to VSS (mask ROM version only). FLMD0: Connect these pins to VSS in the normal mode (flash memory version only). FLMD1: Flash memory version only 2. Connect the REGC pin to VSS via a 4.7 F capacitor. 3. SCL00 to SCL02 and SDA00 to SDA02 are valid only in the I2C bus version (Y product). 4. CTXD0 and CRXD0 are valid only in the CAN controller version. 5. IETX0 and IERX0 are valid only in the IEBus controller version. 6. DRST, DDI, DDO, DCK, and DMS are valid only in the flash memory version. <R> 7. Fix this pin to the low level from when the reset status has been released until the OCDM.OCDM0 bit is cleared (0) when the on-chip debug function is not used. For details, see 4.6.3 Cautions on on-chip debug pins. <R> 8. Port 9 cannot be used as port pins or other alternate-function pins when the A0 to A15 pins are used in <R> 9. To use port 7 (P70/ANI0 to P711/ANI11) as A/D converter function pins and port I/O pins in mix, be the separate bus mode. sure to observe usage cautions (refer to 13.6 (4) Alternate I/O). User's Manual U16541EJ5V1UD 31 CHAPTER 1 INTRODUCTION 100-pin plastic QFP (14 x 20) PD703260GF-xxx-JBT-A PD703260YGF-xxx-JBT-A PD703261GF-xxx-JBT-A PD703261YGF-xxx-JBT-A <R> <R> <R> <R> 32 PD703270GF-xxx-JBT-A PD703270YGF-xxx-JBT-A PD703271GF-xxx-JBT-A PD703271YGF-xxx-JBT-A User's Manual U16541EJ5V1UD PD70F3261GF-JBT-A PD70F3261YGF-JBT-A PD70F3271GF-JBT-A PD70F3271YGF-JBT-A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P72/ANI2Note 9 P73/ANI3Note 9 P74/ANI4Note 9 P75/ANI5Note 9 P76/ANI6Note 9 P77/ANI7Note 9 P78/ANI8Note 9 P79/ANI9Note 9 P710/ANI10Note 9 P711/ANI11Note 9 PDH1/A17 PDH0/A16 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 CHAPTER 1 INTRODUCTION 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1Note 1 PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PDH3/A19 PDH2/A18 P915/A15Note 8/INTP6/TIP50/TOP50 P914/A14Note 8/INTP5/TIP51/TOP51 P913/A13Note 8/INTP4 P912/A12Note 8/SCKB3 P911/A11Note 8/SOB3 P910/A10Note 8/SIB3 P99/A9Note 8/SCKB1 P98/A8Note 8/SOB1 P97/A7Note 8/SIB1/TIP20/TOP20 P96/A6Note 8/TIP21/TOP21 P34/TIP10/TOP10 P35/TIP11/TOP11 P36/CTXD0Note 4/IETX0Note 5 P37/CRXD0Note 4/IERX0Note 5 EVSS EVDD P38/TXDA2/SDA00Note 3 P39/RXDA2/SCL00Note 3 P50/TIQ01/KR0/TOQ01/RTP00 P51/TIQ02/KR1/TOQ02/RTP01 P52/TIQ03/KR2/TOQ03/RTP02/DDINote 6 P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDONote 6 P54/SOB2/KR4/RTP04/DCKNote 6 P55/SCKB2/KR5/RTP05/DMSNote 6 P90/A0Note 8/KR6/TXDA1/SDA02Note 3 P91/A1Note 8/KR7/RXDA1/SCL02Note 3 P92/A2Note 8/TIP41/TOP41 P93/A3Note 8/TIP40/TOP40 P94/A4Note 8/TIP31/TOP31 P95/A5Note 8/TIP30/TOP30 P71/ANI1Note 9 P70/ANI0Note 9 AVREF0 AVSS P10/ANO0 P11/ANO1 AVREF1 PDH4/A20 PDH5/A21 ICNote 1/FLMD0Note 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P02/NMI P03/INTP0/ADTRG P04/INTP1 P05/INTP2/DRSTNotes 6, 7 P06/INTP3 P40/SIB0/SDA01Note 3 P41/SOB0/SCL01Note 3 P42/SCKB0 P30/TXDA0/SOB4 P31/RXDA0/INTP7/SIB4 P32/ASCKA0/SCKB4/TIP00/TOP00 P33/TIP01/TOP01 Notes 1. IC: Directly connect this pin to VSS (mask ROM version only). FLMD0: Connect these pins to VSS in the normal mode (flash memory version only). FLMD1: Flash memory version only 2. Connect the REGC pin to VSS via a 4.7 F capacitor. 2 3. SCL00 to SCL02 and SDA00 to SDA02 are valid only in the I C bus version (Y product). 4. CTXD0 and CRXD0 are valid only in the CAN controller version. 5. IETX0 and IERX0 are valid only in the IEBus controller version. 6. DRST, DDI, DDO, DCK, and DMS are valid only in the flash memory version. <R> 7. Fix this pin to the low level from when the reset status has been released until the OCDM.OCDM0 bit is cleared (0) when the on-chip debug function is not used. For details, see 4.6.3 Cautions on on-chip debug pins. <R> 8. Port 9 cannot be used as port pins or other alternate-function pins when the A0 to A15 pins are used in the separate bus mode. <R> 9. To use port 7 (P70/ANI0 to P711/ANI11) as mixed A/D converter function pins and port I/O pins, be sure to observe usage cautions (refer to 13.6 (4) Alternate I/O). User's Manual U16541EJ5V1UD 33 CHAPTER 1 INTRODUCTION Pin names A0 to A21: Address bus PCM0 to PCM3: AD0 to AD15: Address/data bus PCT0, PCT1, ADTRG: A/D trigger input PCT4, PCT6: Port CT ANI0 to ANI11: Analog input PDH0 to PDH5: Port DH ANO0, ANO1: Analog output PDL0 to PDL15: Port DL ASCKA0: Asynchronous serial clock RD: Read strobe ASTB: Address strobe REGC: Regulator control AVREF0, AVREF1: Analog reference voltage RESET: Reset Port CM AVSS: Analog VSS RTP00 to RTP05: Real-time output port BVDD: Power supply for bus interface RXDA0 to RXDA2: Receive data BVSS: Ground for bus interface SCKB0 to SCKB4: Serial clock CLKOUT: Clock output SCL00 to SCL02: Serial clock CRXD0: CAN receive data SDA00 to SDA02: Serial data CTXD0: CAN transmit data SIB0 to SIB4: Serial input DCK: Debug clock SOB0 to SOB4: Serial output DDI: Debug data input TIP00, TIP01, DDO: Debug data output TIP10, TIP11, DMS: Debug mode select TIP20, TIP21, DRST: Debug reset TIP30, TIP31, EVDD: Power supply for port TIP40, TIP41, EVSS: Ground for port TIP50, TIP51, FLMD0, FLMD1: Flash programming mode TIQ00 to TIQ03: HLDAK: Hold acknowledge TOP00, TOP01, HLDRQ: Hold request TOP10, TOP11, IC: Internally connected TOP20, TOP21, IERX0: IEBus receive data TOP30, TOP31, IETX0: IEBus transmit data TOP40, TOP41, INTP0 to INTP7: External interrupt input TOP50, TOP51, KR0 to KR7: Key return TOQ00 to TOQ03: Timer output NMI: Non-maskable interrupt request TXDA0 to TXDA2: Transmit data P02 to P06: Port 0 VDD: Power supply P10, P11: Port 1 VSS: Ground P30 to P39: Port 3 WAIT: Wait P40 to P42: Port 4 WR0: Lower byte write strobe P50 to P55: Port 5 WR1: Upper byte write strobe P70 to P711: Port 7 X1, X2: Crystal for main clock P90 to P915: Port 9 XT1, XT2: Crystal for subclock 34 User's Manual U16541EJ5V1UD Timer input CHAPTER 1 INTRODUCTION 1.6.1 Function Block Configuration Internal block diagram NMI INTP0 to INTP7 TIQ00 to TIQ03 TOQ00 to TOQ03 TIP00 to TIP50, TIP01 to TIP51 TOP00 to TOP50, TOP01 to TOP51 16-bit timer/ counter Q: 1 ch 16-bit timer/ counter P: 6 ch Instruction queue Note 1 PC RAM 32-bit barrel shifter Note 2 System registers SOB2 SIB2 SCKB2 SOB3 SIB3 SCKB3 RTO CSIB0 I2C01Note 3 CSIB1 CSIB2 A/D converter CSIB3 UARTA0 CSIB4 TXDA1/SDA02Note 3 RXDA1/SCL02Note 3 UARTA1 I2C02Note 3 IETX0Note 6 IERX0Note 6 Internal oscillator CLKOUT CG CG PLL XT1 XT2 X1 X2 RESET LVINote 8 VDD Regulator VSS REGC ANI0 to ANI11 AVSS AVREF0 ADTRG ICNote 4/FLMD0Note 5 FLMD1Note 5 BVDD BVSS TXDA0/SOB4 RXDA0/SIB4 ASCKA0/SCKB4 TXDA2/SDA00Note 3 RXDA2/SCL00Note 3 A0 to A21 AD0 to AD15 PCM0 to PCM3 PCT0, PCT1, PCT4, PCT6 PDH0 to PDH5 PDL0 to PDL15 P90 to P915 P70 to P711 P50 to P55 P40 to P42 P30 to P39 P10, P11 P02 to P06 <R> SOB1 SIB1 SCKB1 BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 DMAC Ports SOB0/SCL01Note 3 SIB0/SDA01Note 3 SCKB0 Multiplier 16 x 16 32 General-purpose registers 32 bits x 32 ROM correction 16-bit interval timer M: 1 ch RTP00 to RTP05 CPU ROM INTC CLM 1.6 D/A converter AVREF1 ANO0, ANO1 Key return function KR0 to KR7 Note 3 UARTA2 I C00 CAN0Note 7 DRSTNote 5 DMSNote 5 DDINote 5 DCKNote 5 DDONote 5 Watch timer IEBusNote 6 EVSS On-chip debug functionNote 5 Watchdog timer 2 2 EVDD CTXD0Note 7 CRXD0Note 7 Notes 1. 256/384/512/640 KB (mask ROM) (see Table 1-1) 384/640 KB (flash memory) (see Table 1-1) 2. 24/32/40/48 KB (see Table 1-1) 3. I2C bus version (Y products) only 4. Mask ROM version only 5. Flash memory version only 6. IEBus controller version only 7. CAN controller version only <R> 8. V850ES/SG2 only User's Manual U16541EJ5V1UD 35 CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an instruction queue. (3) ROM This is a 640/512/384/256 KB mask ROM or flash memory mapped to addresses 0000000H to 009FFFFH/0000000H to 007FFFFH/0000000H to 005FFFFH/0000000H to 003FFFFH. It can be accessed from the CPU in one clock during instruction fetch. (4) RAM This is a 48/40/32/24 KB RAM mapped to addresses 3FF3000H to 3FFEFFFH/3FF5000H to 3FFEFFFH/3FF7000H to 3FFEFFFH/3FF9000H to 3FFEFFFH. It can be accessed from the CPU in one clock during data access. (5) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (6) Clock generator (CG) A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4 or 8. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (7) Internal oscillator An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP). The internal oscillator supplies the clock for watchdog timer 2 and timer M. (8) Timer/counter Six-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and onechannel 16-bit interval timer M (TMM), are provided on chip. (9) Watch timer This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz subclock or the 32.768 kHz clock fBRG from prescaler 3). The watch timer can also be used as an interval timer for the main clock. 36 User's Manual U16541EJ5V1UD CHAPTER 1 INTRODUCTION (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. Either the internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (11) Serial interface <R> The V850ES/SG2 and V850ES/SG2-H include three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire variable-length serial interface B (CSIB), and an I2C bus interface (I2C). In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins. In the case of CSIB, data is transferred via the SOB0 to SOB4 pins, SIB0 to SIB4 pins, and SCKB0 to SCKB4 pins. In the case of I2C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins. The I2C is provided only in I2C bus versions (Y Products) (see Table 1-1). (12) IEBus controller The IEBus controller is a small-scale digital data transmission system for transferring data between units. The IEBus controller is provided only in IEBus controller versions (see Table 1-1). (13) CAN controller The CAN controller is a small-scale digital data transmission system for transferring data between units. The CAN controller is provided only in CAN controller versions (see Table 1-1). (14) A/D converter This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive approximation method. (15) D/A converter A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip. (16) DMA controller A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O. (17) ROM correction A ROM correction function that replaces part of a program in the mask ROM with a program in the internal RAM is provided. Up to four correction addresses can be specified. (18) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8 channels). (19) Real-time output function The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare register match signal. User's Manual U16541EJ5V1UD 37 CHAPTER 1 INTRODUCTION (20) CRC function A CRC operation circuit that generates 16-bit CRC (Cyclic Redundancy Check) code upon setting of 8-bit data is provided on chip. (21) On-chip debug function An on-chip debug function via an on-chip debug emulator that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip debugging function is done with the control pin input level and the on-chip debug mode register (OCDM). The on-chip debug function is provided only in flash memory versions. (22) Ports The following general-purpose port functions and control pin functions are available. Port 38 I/O Alternate Function P0 5-bit I/O NMI, external interrupt, A/D converter trigger, debug reset P1 2-bit I/O D/A converter analog output P3 10-bit I/O External interrupt, serial interface, timer I/O, CAN data I/O, IEBus data I/O P4 3-bit I/O Serial interface P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface, debug I/O P7 12-bit I/O A/D converter analog input P9 16-bit I/O External address bus, serial interface, key interrupt input, timer I/O, external interrupt PCM 4-bit I/O External control signal PCT 4-bit I/O External control signal PDH 6-bit I/O External address bus PDL 16-bit I/O External address/data bus User's Manual U16541EJ5V1UD CHAPTER 2 PIN FUNCTIONS 2.1 <R> List of Pin Functions The names and functions of the pins in the V850ES/SG2 and V850ES/SG2-H are described below. There are four types of pin I/O buffer power supplies: AVREF0, AVREF1, BVDD, and EVDD. The relationship between these power supplies and the pins is described below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins AVREF0 Port 7 AVREF1 Port 1 BVDD Ports CM, CT, DH (bits 0 to 3), DL EVDD RESET, ports 0, 3 to 5, 9, DH (bits 4, 5) (1) Port pins (1/4) Pin Name P02 P03 Pin No. GF GC 19 17 20 P04 19 22 20 P06 23 21 P10 5 3 P05 I/O 18 21 Note 1 I/O Function Alternate Function Port 0 NMI 5-bit I/O port INTP0/ADTRG Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. INTP1 Note 2 INTP2/DRST 5 V tolerant. INTP3 I/O Port 1 ANO0 2-bit I/O port P11 <R> 6 4 Input/output can be specified in 1-bit units. ANO1 Notes 1. Fix this pin to low level from when the reset status has been released until the OCDM.OCDM0 bit is cleared (0) when the on-chip debug function is not used. For details, see 4.6.3 Cautions on on-chip debug pins. A pull-down resistor is incorporated. It can be disconnected by clearing the OCDM.OCDM0 bit to 0. 2. Flash memory versions only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) User's Manual U16541EJ5V1UD 39 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name P30 P31 Pin No. GF GC 27 25 28 I/O I/O 26 Function Alternate Function Port 3 TXDA0/SOB4 10-bit I/O port RXDA0/INTP7/SIB4 Input/output can be specified in 1-bit units. P32 29 27 P33 30 28 P34 31 29 TIP10/TOP10 P35 32 30 TIP11/TOP11 P36 33 31 CTXD0 P37 34 32 CRXD0 P38 37 35 TXDA2/SDA00 P39 38 36 RXDA2/SCL00 P40 24 22 P41 25 23 P42 26 24 P50 39 37 N-ch open-drain output can be specified in 1-bit units. TIP01/TOP01 5 V tolerant. I/O ASCKA0/SCKB4/TIP00/TOP00 Port 4 Note 1 /IETX0 Note 1 Note 2 /IERX0 SIB0/SDA01 Note 2 Note 3 Note 3 Note 3 3-bit I/O port P51 40 38 P52 41 39 P53 42 40 Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. 5 V tolerant. I/O SOB0/SCL01 Note 3 SCKB0 Port 5 TIQ01/KR0/TOQ01/RTP00 6-bit I/O port TIQ02/KR1/TOQ02/RTP01 Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. TIQ03/KR2/TOQ03/RTP02/DDI SIB2/KR3/TIQ00/TOQ00/RTP03/ 5 V tolerant. Note 4 DDO Note 4 P54 43 41 SOB2/KR4/RTP04/DCK P55 44 42 SCKB2/KR5/RTP05/DMS P70 2 100 P71 1 99 I/O Port 7 ANI0 12-bit I/O port ANI1 Input/output can be specified in 1-bit units. P72 100 98 P73 99 97 ANI3 P74 98 96 ANI4 P75 97 95 ANI5 P76 96 94 ANI6 P77 95 93 ANI7 P78 94 92 ANI8 P79 93 91 ANI9 P710 92 90 ANI10 P711 91 89 ANI11 Notes 1. CAN controller versions only 2. IEBus controller versions only 3. I2C bus versions (Y products) only 4. Flash memory versions only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 40 Note 4 User's Manual U16541EJ5V1UD ANI2 Note 4 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Pin No. GF GC P90 45 43 P91 46 44 I/O I/O Function Alternate Function Note Port 9 A0/KR6/TXDA1/SDA02 16-bit I/O port A1/KR7/RXDA1/SCL02 Input/output can be specified in 1-bit units. Note P92 47 45 P93 48 46 P94 49 47 A4/TIP31/TOP31 P95 50 48 A5/TIP30/TOP30 P96 51 49 A6/TIP21/TOP21 P97 52 50 A7/SIB1/TIP20/TOP20 P98 53 51 A8/SOB1 P99 54 52 A9/SCKB1 P910 55 53 A10/SIB3 P911 56 54 A11/SOB3 P912 57 55 A12/SCKB3 P913 58 56 A13/INTP4 P914 59 57 A14/INTP5/TIP51/TOP51 P915 60 58 A15/INTP6/TIP50/TOP50 PCM0 63 61 PCM1 64 65 63 PCM3 66 64 PCT0 67 65 PCT1 68 66 PCT4 69 67 PCT6 70 68 PDH0 89 87 90 I/O 88 A2/TIP41/TOP41 A3/TIP40/TOP40 5 V tolerant. 62 PCM2 PDH1 N-ch open-drain output can be specified in 1-bit units. Port CM WAIT 4-bit I/O port CLKOUT Input/output can be specified in 1-bit units. HLDAK HLDRQ I/O Port CT WR0 4-bit I/O port WR1 Input/output can be specified in 1-bit units. RD ASTB I/O Port DH A16 6-bit I/O port A17 Input/output can be specified in 1-bit units. PDH2 61 59 A18 PDH3 62 60 A19 PDH4 8 6 A20 PDH5 9 7 A21 Note I2C bus versions (Y products) only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) User's Manual U16541EJ5V1UD 41 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name PDL0 PDL1 Pin No. GF GC 73 71 74 72 I/O I/O Function Alternate Function Port DL AD0 16-bit I/O port AD1 Input/output can be specified in 1-bit units. PDL2 75 73 PDL3 76 74 PDL4 77 75 AD4 PDL5 78 76 AD5/FLMD1 PDL6 79 77 AD6 PDL7 80 78 AD7 PDL8 81 79 AD8 PDL9 82 80 AD9 PDL10 83 81 AD10 PDL11 84 82 AD11 PDL12 85 83 AD12 PDL13 86 84 AD13 PDL14 87 85 AD14 PDL15 88 86 AD15 AD3 Note Flash memory versions only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 42 AD2 User's Manual U16541EJ5V1UD Note CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/6) Pin Name Pin No. GF GC I/O Function Alternate Function Note 1 <R> A0 45 43 <R> A1 46 44 <R> A2 47 45 <R> A3 48 46 <R> A4 49 47 <R> A5 50 48 <R> A6 51 49 P96/TIP21/TOP21 <R> A7 52 50 P97/SIB1/TIP20/TOP20 <R> A8 53 51 P98/SOB1 <R> A9 54 52 P99/SCKB1 <R> A10 55 53 P910/SIB3 <R> A11 56 54 P911/SOB3 <R> A12 57 55 P912/SCKB3 <R> A13 58 56 P913/INTP4 <R> A14 59 57 P914/INTP5/TIP51/TOP51 <R> A15 60 58 P915/INTP6/TIP50/TOP50 A16 89 87 A17 90 88 PDH1 A18 61 59 PDH2 A19 62 60 PDH3 A20 8 6 PDH4 A21 9 7 PDH5 AD0 73 71 AD1 74 72 PDL1 AD2 75 73 PDL2 AD3 76 74 PDL3 AD4 77 75 PDL4 AD5 78 76 PDL5/FLMD1 AD6 79 77 PDL6 AD7 80 78 PDL7 AD8 81 79 PDL8 AD9 82 80 PDL9 AD10 83 81 PDL10 AD11 84 82 PDL11 AD12 85 83 PDL12 AD13 86 84 PDL13 AD14 87 85 PDL14 AD15 88 86 PDL15 Output Output I/O Address bus for external memory (when using separate bus) Port 9 cannot be used as port pins or other alternatefunction pins when the A0 to A15 pins are used in the separate bus mode. N-ch open-drain output selectable. 5 V tolerant. Address bus for external memory Address bus/data bus for external memory P90/KR6/TXDA1/SDA02 P91/KR7/RXDA1/SCL02 Note 1 P92/TIP41/TOP41 P93/TIP40/TOP40 P94/TIP31/TOP31 P95/TIP30/TOP30 PDH0 PDL0 Note 2 Notes 1. I2C bus versions (Y products) only 2. Flash memory versions only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) User's Manual U16541EJ5V1UD 43 CHAPTER 2 PIN FUNCTIONS (2/6) Pin Name Pin No. GF I/O Function Alternate Function GC ADTRG 20 18 ANI0 2 100 Input Input ANI1 1 99 P71 ANI2 100 98 P72 ANI3 99 97 P73 ANI4 98 96 P74 ANI5 97 95 P75 ANI6 96 94 P76 ANI7 95 93 P77 ANI8 94 92 P78 ANI9 93 91 P79 ANI10 92 90 P710 ANI11 91 89 ANO0 5 3 P711 P10 UARTA0 baud rate clock input. 5 V tolerant. P32/SCKB4/TIP00/TOP00 Address strobe signal output for external memory PCT6 6 4 29 27 Input ASTB 70 68 Output AVREF0 3 1 - AVREF1 7 5 AVSS 4 2 BVDD 72 BVSS CRXD0 CTXD0 DCK DDI Note 1 Note 3 Note 3 P70 Analog voltage output for D/A converter ASCKA0 Note 1 P03/INTP0 Output ANO1 CLKOUT A/D converter external trigger input. 5 V tolerant. Analog voltage input for A/D converter P11 Reference voltage input for A/D converter/positive power supply for port 7 - Reference voltage input for D/A converter/positive power supply for port 1 - - Ground potential for A/D and D/A converters (same potential as VSS) - 70 - Positive power supply pin for bus interface and alternatefunction ports - 71 69 - Ground potential for bus interface and alternate-function ports - 64 62 Output Internal system clock output PCM1 34 32 Input CAN receive data input. 5 V tolerant. P37/IERX0 Note 2 Note 2 33 31 Output CAN transmit data output. N-ch open-drain output selectable. 5 V tolerant. P36/IETX0 43 41 Input Debug clock input. 5 V tolerant. P54/SOB2/KR4/RTP04 41 39 Input Debug data input. 5 V tolerant. P52/TIQ03/KR2/TOQ03/RTP02 Note 3, 4 42 40 Output Debug data output. N-ch open-drain output selectable. 5 V tolerant. P53/SIB2/KR3/TIQ00/TOQ00/ RTP03 Note 3 44 42 Input Debug mode select input. 5 V tolerant. P55/SCKB2/KR5/RTP05 Debug reset input. 5 V tolerant. P05/INTP2 DDO DMS Note 3 DRST 22 20 Input EVDD 36 34 - Positive power supply for external (same potential as VDD) Ground potential for external (same potential as VSS) - Flash memory programming mode setting pin - 35 33 - FLMD0 Note 3 10 8 Input FLMD1 Note 3 78 76 EVSS Notes 1. 2. 3. 4. Remark 44 - PDL5/AD5 CAN controller versions only IEBus controller versions only Flash memory versions only In the on-chip debug mode, high-level output is forcibly set. GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) User's Manual U16541EJ5V1UD CHAPTER 2 PIN FUNCTIONS (3/6) Pin Name Pin No. I/O Function Alternate Function GF GC HLDAK 65 63 Output Bus hold acknowledge output PCM2 HLDRQ 66 64 Input Bus hold request input PCM3 Note 1 10 8 - IC 34 32 Input IEBus receive data input. 5 V tolerant. P37/CRXD0 Note 2 33 31 Output IEBus transmit data output. P36/CTXD0 IERX0 IETX0 - Internally connected Note 2 Note 3 Note 3 N-ch open-drain output selectable. 5 V tolerant. INTP0 20 18 Input 5 V tolerant. P03/ADTRG External interrupt request input (maskable, analog noise P04 INTP1 21 19 INTP2 22 20 INTP3 23 21 selectable for INTP3 pin. P06 INTP4 58 56 5 V tolerant. P913/A13 INTP5 59 57 P914/A14/TIP51/TOP51 INTP6 60 58 P915/A15/TIP50/TOP50 INTP7 28 26 P31/RXDA0/SIB4 39 37 KR0 Note 5 KR1 Note 5 40 38 KR2 Note 5 41 39 elimination). Note 4 Analog noise elimination or digital noise elimination Input P05/DRST Key interrupt input (on-chip analog noise eliminator). P50/TIQ01/TOQ01/RTP00 5 V tolerant. P51/TIQ02/TOQ02/RTP01 P52/TIQ03/TOQ03/ RTP02/DDI Note 4 KR3 Note 5 KR4 Note 5 43 41 P54/SOB2/RTP04/DCK KR5 Note 5 44 42 P55/SCKB2/RTP05/DMS KR6 Note 5 45 43 P90/A0/TXDA1/SDA02 KR7 Note 5 46 44 P91/A1/RXDA1/SCL02 Note 7 19 17 42 P53/SIB2/TIQ00/TOQ00/ 40 Note 4 RTP03/DDO NMI Note 4 Note 4 Note 6 Note 6 Input External interrupt input (non-maskable, analog noise P02 elimination). 5 V tolerant. RD 69 67 Output REGC 12 10 - Read strobe signal output for external memory Connection of regulator output stabilization capacitance PCT4 - (4.7 F) RESET 16 14 Input System reset input - Notes 1. Mask ROM versions only 2. IEBus controller versions only 3. CAN controller versions only 4. Flash memory versions only 5. Pull this pin up externally. 6. I2C bus versions (Y products) only 7. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is "No edge detected". Select the NMI pin valid edge using INTF0 and INTR0 registers. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) User's Manual U16541EJ5V1UD 45 CHAPTER 2 PIN FUNCTIONS (4/6) Pin Name RTP00 RTP01 Pin No. GF GC 39 37 40 I/O Output 38 RTP02 41 39 RTP03 42 40 Function Alternate Function Real-time output port. P50/TIQ01/KR0/TOQ01 N-ch open-drain output selectable. P51/TIQ02/KR1/TOQ02 5 V tolerant. P52/TIQ03/KR2/TOQ03/DDI P53/SIB2/KR3/TIQ00/TOQ00/ Note 1 DDO Note 1 RTP04 43 41 P54/SOB2/KR4/DCK RTP05 44 42 P55/SCKB2/KR5/DMS RXDA0 28 26 RXDA1 46 44 RXDA2 38 36 SCKB0 26 24 SCKB1 54 44 42 SCKB3 57 55 SCKB4 29 27 SCL00 Note 2 SCL01 Note 2 SCL02 Note 2 SDA00 Note 2 SDA01 Note 2 SDA02 Note 2 38 25 46 37 24 Input 36 I/O SIB0 24 22 SIB1 52 50 SIB2 42 40 Serial clock I/O (CSIB0 to CSIB4) P42 N-ch open-drain output selectable. P99/A9 Note 2 Note 2 P55/KR5/RTP05/DMS Note 1 P32/ASCKA0/TIP00/TOP00 I/O 2 2 Serial clock I/O (I C00 to I C02) P39/RXDA2 N-ch open-drain output selectable. P41/SOB0 5 V tolerant. I/O 22 43 P91/A1/KR7/SCL02 Note 1 P912/A12 44 45 P31/INTP7/SIB4 5 V tolerant. 5 V tolerant. 23 35 Serial receive data input (UARTA0 to UARTA2) P39/SCL00 52 SCKB2 P91/A1/KR7/RXDA1 2 2 Serial transmit/receive data I/O (I C00 to I C02) P38/TXDA2 N-ch open-drain output selectable. P40/SIB0 5 V tolerant. Input P90/A0/KR6/TXDA1 Note 2 Serial receive data input (CSIB0 to CSIB4) P40/SDA01 5 V tolerant. P97/A7/TIP20/TOP20 P53/KR3/TIQ00/TOQ00/ Note 1 RTP03/DDO SIB3 55 53 P910/A10 SIB4 28 26 P31/RXDA0/INTP7 SOB0 25 23 SOB1 53 51 Output Serial transmit data output (CSIB0 to CSIB4) P41/SCL01 N-ch open-drain output selectable. P98/A8 5 V tolerant. Note 2 SOB2 43 41 SOB3 56 54 P911/A11 SOB4 27 25 P30/TXDA0 P54/KR4/RTP04/DCK Notes 1. Flash memory versions only 2. I2C bus versions (Y products) only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 46 Note 1 User's Manual U16541EJ5V1UD Note 1 CHAPTER 2 PIN FUNCTIONS (5/6) Pin Name TIP00 Pin No. GF GC 29 27 I/O Input Function External event count input/capture trigger input/external Alternate Function P32/ASCKA0/SCKB4/TOP00 trigger input (TMP0). 5 V tolerant. TIP01 30 Capture trigger input (TMP0). 28 P33/TOP01 5 V tolerant. TIP10 31 External event count input/capture trigger input/external 29 P34/TOP10 trigger input (TMP1). 5 V tolerant. TIP11 32 Capture trigger input (TMP1). 30 P35/TOP11 5 V tolerant. TIP20 52 External event count input/capture trigger input/external 50 P97/A7/SIB1/TOP20 trigger input (TMP2). 5 V tolerant. TIP21 51 49 Capture trigger input (TMP2). 5 V tolerant. P96/A6/TOP21 TIP30 50 48 External event count input/capture trigger input/external P95/A5/TOP30 trigger input (TMP3). 5 V tolerant. TIP31 49 Capture trigger input (TMP3). 47 P94/A4/TOP31 5 V tolerant. TIP40 48 External event count input/capture trigger input/external 46 P93/A3/TOP40 trigger input (TMP4). 5 V tolerant. TIP41 47 Capture trigger input (TMP4). 45 P92/A2/TOP41 5 V tolerant. TIP50 60 External event count input/capture trigger input/external 58 P915/A15/INTP6/TOP50 trigger input (TMP5). 5 V tolerant. TIP51 59 Capture trigger input (TMP5). 57 P914/A14/INTP5/TOP51 5 V tolerant. TIQ00 42 40 Input External event count input/capture trigger input/external P53/SIB2/KR3/TOQ00/RTP03 trigger input (TMQ0). /DDO Note 5 V tolerant. TIQ01 39 37 Capture trigger input (TMQ0). P50/KR0/TOQ01/RTP00 5 V tolerant. P51/KR1/TOQ02/RTP01 TIQ02 40 38 TIQ03 41 39 Note P52/KR2/TOQ03/RTP02/DDI Note Flash memory versions only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) User's Manual U16541EJ5V1UD 47 CHAPTER 2 PIN FUNCTIONS (6/6) Pin Name TOP00 Pin No. GF GC 29 27 I/O Output Function Alternate Function Timer output (TMP0) P32/ASCKA0/SCKB4/TIP00 P33/TIP01 TOP01 30 28 N-ch open-drain output selectable. 5 V tolerant. TOP10 31 29 Timer output (TMP1) P34/TIP10 P35/TIP11 TOP11 32 30 N-ch open-drain output selectable. 5 V tolerant. TOP20 52 50 Timer output (TMP2) P97/A7/SIB1/TIP20 TOP21 51 49 N-ch open-drain output selectable. 5 V tolerant. P96/A6/TIP21 TOP30 50 48 Timer output (TMP3) P95/A5/TIP30 P94/A4/TIP31 TOP31 49 47 N-ch open-drain output selectable. 5 V tolerant. TOP40 48 46 Timer output (TMP4) P93/A3/TIP40 P92/A2/TIP41 TOP41 47 45 N-ch open-drain output selectable. 5 V tolerant. TOP50 60 58 Timer output (TMP5) P915/A15/INTP6/TIP50 N-ch open-drain output selectable. 5 V tolerant. P914/A14/INTP5/TIP51 Timer output (TMQ0) P53/SIB2/KR3/TIQ00/RTP03/ N-ch open-drain output selectable. 5 V tolerant. DDO TOP51 59 57 TOQ00 42 40 Output Note 1 TOQ01 39 37 P50/TIQ01/KR0/RTP00 TOQ02 40 38 P51/TIQ02/KR1/RTP01 TOQ03 41 39 P52/TIQ03/KR2/RTP02/DDI TXDA0 27 25 TXDA1 45 Output 43 TXDA2 37 35 VDD 11 9 VSS 13 WAIT 63 WR0 Serial transmit data output (UARTA0 to UARTA2) P30/SOB4 N-ch open-drain output selectable. P90/A0/KR6/SDA02 5 V tolerant. Note 2 P38/SDA00 - Positive power supply pin for internal 11 - Ground potential for internal 61 Input External wait input PCM0 67 65 Output Write strobe for external memory (lower 8 bits) PCT0 WR1 68 66 Write strove for external memory (higher 8 bits) PCT1 X1 14 12 Input X2 15 13 - XT1 17 15 Input XT2 18 16 - Connection of resonator for main clock Connection of resonator for subclock - - - 2. I2C bus versions (Y products) only GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 48 - - Notes 1. Flash memory versions only Remark - User's Manual U16541EJ5V1UD Note 2 Note 1 CHAPTER 2 PIN FUNCTIONS 2.2 Pin States The operation states of pins in the various modes are described below. <R> Table 2-2. Pin Operation States in Various Modes Pin Name During Reset During Reset (Immediately (Except After Power Immediately Is Turned On) After Power Is HALT Mode Note 2 IDLE1, IDLE2, Sub-IDLE Mode STOP Mode Note 2 Idle State Bus Hold Note 3 Note 2 Turned On) Note 4 P05/DRST Pulled down Note 5 Pulled down Note 1 P10/ANO0, Hi-Z Undefined Held Held Held Held Held Held Held Note 11 Held Held P11/ANO1 Note 4 P53/DDO Note 7 AD0 to AD15 Hi-Z Hi-Z Note 6 Held Held Held Held Held Hi-Z Note 7 Notes 8, 9 Hi-Z Hi-Z Held Hi-Z - - - - - Operating L L Operating Operating H H H Hi-Z A0 to A15 Undefined A16 to A21 Notes 8, 10 Undefined WAIT CLKOUT Note 8 Note 8 H WR0, WR1 RD ASTB Operating HLDAK Note 8 L - - - Operating Held Held Held Held HLDRQ Other port pins <R> Hi-Z Hi-Z Held Notes 1. These pins may momentarily output an undefined level upon power application. 2. Operates while an alternate function is operating. 3. In separate bus mode, the state of the pins in the idle state inserted after the T2 state is shown. In multiplexed bus mode, the state of the pins in the idle state inserted after the T3 state is shown. 4. Flash memory versions only 5. Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the state of this pin differs according to the OCDM.OCDM0 bit setting. 6. DDO output is specified in the on-chip debug mode. 7. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode). 8. Operates even in the HALT mode, during DMA operation. 9. In separate bus mode: Hi-Z In multiplexed bus mode: Undefined 10. In separate bus mode <R> 11. In port mode: Held When alternate function is used: Hi-Z Remark Hi-Z: High impedance Held: The state during the immediately preceding external bus cycle is held. L: Low-level output H: High-level output -: Input without sampling (not acknowledged) User's Manual U16541EJ5V1UD 49 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins (1/3) Pin Alternate Function I/O Circuit Pin No. GF GC Type 10-D P02 NMI 19 17 P03 INTP0/ADTRG 20 18 P04 INTP1 P05 INTP2/DRST Note 1 21 19 22 20 Recommended Connection Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. 10-N Input: Independently connect to EVSS via a resistor. Fixing to VDD level is prohibited. Output: Leave open. Internally pull-down after reset by RESET pin. P06 INTP3 23 21 10-D Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P10, P11 ANO0, ANO1 5, 6 3, 4 12-D Input: Independently connect to AVREF1 or AVSS via a resistor. Output:Leave open. <R> <R> P30 TXDA0/SOB4 27 25 10-G P31 RXDA0/INTP7/SIB4 28 26 10-D ASCKA0/SCKB4/TIP00 29 27 P33 TIP01/TOP01 30 28 P34 TIP10/TOP10 31 29 P35 TIP11/TOP11 32 30 33 31 10-G 10-D P36 CTXD0 P37 CRXD0 P38 /IETX0 Note 2 /IERX0 TXDA2/SDA00 P39 SIB0/SDA01 Note 3 34 32 Note 4 37 35 Note 4 38 36 24 22 25 23 26 24 RXDA2/SCL00 P40 Note 3 Note 4 P41 SOB0/SCL01 P42 SCKB0 Note 4 Notes 1. Flash memory versions only 2. CAN controller versions only 3. IEBus controller versions only 4. I2C bus versions (Y products) only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 50 Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P32 Note 2 Input: User's Manual U16541EJ5V1UD CHAPTER 2 PIN FUNCTIONS (2/3) Pin Alternate Function I/O Circuit Pin No. GF GC Type 10-D P50 TIQ01/KR0/TOQ01/RTP00 39 37 P51 TIQ02/KR1/TOQ02/RTP01 40 38 TIQ03/KR2/TOQ03/RTP02/ P52 DDI 39 42 40 43 41 44 42 2, 1, 100 to 89 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Note 1 SIB2/KR3/TIQ00/TOQ00/ P53 41 Recommended Connection Note 1 RTP03/DDO P54 SOB2/KR4/RTP04/DCK P55 SCKB2/KR5/RTP05/ DMS P70 to P711 Note 1 Note 1 ANI0 to ANI11 11-G Input: 100 to 91 Independently connect to AVREF0 or AVSS via a resistor. Output: Leave open. P90 P91 <R> <R> A0/KR6/TDXA1/SDA02 Note 2 45 43 A1/KR7/RXDA1/SCL02 Note 2 46 44 10-D Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P92 A2/TIP41/TOP41 47 45 P93 A3/TIP40/TOP40 48 46 P94 A4/TIP31/TOP31 49 47 P95 A5/TIP30/TOP30 50 48 P96 A6/TIP21/TOP21 51 49 P97 A7/SIB1/TIP20/TOP20 52 50 P98 A8/SOB1 53 51 10-G P99 A9/SCKB1 54 52 10-D P910 A10/SIB3 55 53 P911 A11/SOB3 56 54 10-G P912 A12/SCKB3 57 55 10-D P913 A13/INTP4 58 56 P914 A14/INTP5/TIP51/TOP51 59 57 P915 A15/INTP6/TIP50/TOP50 60 58 Notes 1. Flash memory versions only 2. I2C bus versions (Y products) only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) User's Manual U16541EJ5V1UD 51 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Alternate Function I/O Circuit Pin No. GF GC Type 5 PCM0 WAIT 63 61 PCM1 CLKOUT 64 62 PCM2 HLDAK 65 63 PCM3 HLDRQ 66 64 PCT0, PCT1 WR0, WR1 67, 68 65, 66 PCT4 RD 69 67 PCT6 ASTB 70 68 PDH0 to PDH3 A16 to A19 89, 90, 87, 88, 61, 62 59, 60 8, 9 6, 7 PDH4, PDH5 A20, A21 Recommended Connection Input: Independently connect to BVDD or BVSS via a resistor. Output: Leave open. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. PDL0 to PDL4 AD0 to AD4 PDL5 AD5/FLMD1 PDL6 to PDL15 AD6-AD15 Note 1 73 to 71 to 77 75 78 76 79 to 77 to 88 86 Input: Independently connect to BVDD or BVSS via a resistor. Output: Leave open. AVREF0 - 3 1 - Directly connect to VDD and always supply power. AVREF1 - 7 5 - Directly connect to VDD and always supply power. AVSS - 4 2 - Directly connect to VSS and always supply power. BVDD - 72 70 - Directly connect to VDD and always supply power. BVSS - 71 69 - Directly connect to VSS and always supply power. EVDD - 36 34 - - - 35 33 - - - 10 8 - EVSS FLMD0 Note 1 Directly connect to VSS in a mode other than the flash memory programming mode. IC - 10 8 - Directly connect to VSS. REGC - 12 10 - Connect regulator output stabilization capacitance RESET - 16 14 2 - VDD - 11 9 - - VSS - 13 11 - - X1 - 14 12 - - X2 - 15 13 - - XT1 - 17 15 16 Connect to VSS. XT2 - 18 16 16 Leave open. Note 2 (4.7 F). Notes 1. Flash memory versions only 2. Mask ROM versions only Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 52 User's Manual U16541EJ5V1UD CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 10-N Type 2 EVDD Data P-ch IN IN/OUT Schmitt-triggered input with hysteresis characteristics IN/OUT Open drain N-ch Output disable Note Input enable Type 5 EVDD/BVDD Data EVSS N-ch OCDM0 bit P-ch Type 11-G Output disable N-ch AVREF0 Data EVSS/BVSS Input enable P-ch IN/OUT Output disable N-ch Type 10-D AVSS EVDD P-ch Comparator Data + _ P-ch IN/OUT Open drain N-ch Output disable Note AVSS Input enable EVSS Type 12-D Input enable <R> AVREF0 (Threshold voltage) N-ch AVREF1 Type 10-G Data P-ch Output disable N-ch EVDD Data P-ch IN/OUT AVSS IN/OUT Open drain Output disable N-ch Input enable P-ch Analog output voltage EVSS Input enable N-ch Type 16 Feedback cut-off P-ch XT1 XT2 Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 53 CHAPTER 2 PIN FUNCTIONS 2.4 Cautions (1) Cautions on power application When the power is turned on, the following pins may momentarily output an undefined level. <R> * P10/ANO0 pin * P11/ANO1 pin * P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDONote pin Note The DDO pin is provided only in the flash memory versions. (2) Cautions on FLMD0 pin <R> To accurately start the user program operation, fix the FLMD0 pin to low level from when the reset status has been released until the oscillation stabilization time elapses and the firmware operation is completed. For details of firmware operation, see 25.3.5 (2) Firmware operation (flash memory version only). 54 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION <R> The CPU of the V850ES/SG2 and V850ES/SG2-H is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 Features Minimum instruction execution time: V850ES/SG2: <R> 50 ns (operating with main clock (fXX) = 20 MHz) V850ES/SG2-H: 31.25 ns (operating with main clock (fXX) = 32 MHz) Memory space Program (physical address) space: 64 MB linear Data (logical address) space: 4 GB linear General-purpose registers: 32 bits x 32 registers Internal 32-bit architecture 5-stage pipeline control Multiplication/division instruction Saturation operation instruction 32-bit shift instruction: 1 clock Load/store instruction with long/short format Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1 User's Manual U16541EJ5V1UD 55 CHAPTER 3 CPU FUNCTION 3.2 <R> CPU Register Set The registers of the V850ES/SG2 and V850ES/SG2-H can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User's Manual. (1) Program register set 31 r0 (2) System register set 0 31 0 (Zero register) EIPC (Interrupt status saving register) (Assembler-reserved register) EIPSW (Interrupt status saving register) r3 (Stack pointer (SP)) FEPC (NMI status saving register) r4 (Global pointer (GP)) FEPSW (NMI status saving register) r5 (Text pointer (TP)) r1 r2 r6 ECR (Interrupt source register) PSW (Program status word) CTPC (CALLT execution status saving register) r7 r8 r9 r10 r11 CTPSW (CALLT execution status saving register) r12 r13 DBPC r14 (Exception/debug trap status saving register) DBPSW (Exception/debug trap status saving register) r15 r16 CTBP r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (Element pointer (EP)) r31 (Link pointer (LP)) 31 PC 56 0 (Program counter) User's Manual U16541EJ5V1UD (CALLT base pointer) CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the SLD and SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. When using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time OS. If the real-time OS does not use r2, it can be used as a register for variables. Table 3-1. Program Registers Name Usage Operation r0 Zero register Always holds 0. r1 Assembler-reserved register Used as working register to create 32-bit immediate data r2 Register for address/data variable (if real-time OS does not use r2) r3 Stack pointer Used to create a stack frame when a function is called r4 Global pointer Used to access a global variable in the data area r5 Text pointer Used as register that indicates the beginning of a text area (area where program codes are located) r6 to r29 Register for address/data variable r30 Element pointer Used as base pointer to access memory r31 Link pointer Used when the compiler calls a function PC Program counter Holds the instruction address during program execution Remark For further details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer to the CA850 (C Compiler Package) Assembly Language User's Manual. (2) Program counter (PC) The program counter holds the instruction address during program execution. The lower 32 bits of this register are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs. Bit 0 is fixed to 0. This means that execution cannot branch to an odd address. 31 PC 26 25 Fixed to 0 1 0 Instruction address during program execution User's Manual U16541EJ5V1UD 0 Default value 00000000H 57 CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2. System Register Numbers System Register Name System Register Number Operand Specification LDSR Instruction STSR Instruction Note 1 0 Interrupt status saving register (EIPC) 1 Interrupt status saving register (EIPSW) Note 1 Note 1 2 NMI status saving register (FEPC) Note 1 3 NMI status saving register (FEPSW) 4 Interrupt source register (ECR) x 5 Program status word (PSW) Reserved for future function expansion (operation is not guaranteed if these registers are accessed) x x 16 CALLT execution status saving register (CTPC) 17 CALLT execution status saving register (CTPSW) 6 to 15 Exception/debug trap status saving register (DBPC) 19 Exception/debug trap status saving register (DBPSW) 20 CALLT base pointer (CTBP) Reserved for future function expansion (operation is not guaranteed if these registers are accessed) x x 18 21 to 31 Note 2 Note 2 Note 2 Note 2 Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by program if multiple interrupts are enabled. 2. These registers can be accessed only during the interval between the execution of the DBTRAP <R> instruction or illegal opcode execution and DBRET instruction. Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when execution is returned to the main routine by the RETI instruction after interrupt servicing (this is because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0). Remark : Can be accessed x: Access prohibited 58 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs). The address of the instruction next to the instruction under execution, except some instructions (see 22.8 Periods in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable interrupt occurs. The current contents of the PSW are saved to EIPSW. Because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are always fixed to 0). The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction. 31 EIPC 26 25 0 0 0 0 0 0 0 31 EIPSW Default value 0xxxxxxxH (x: Undefined) (Contents of saved PC) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 User's Manual U16541EJ5V1UD 0 (Contents of saved PSW) Default value 000000xxH (x: Undefined) 59 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW. The address of the instruction next to the one of the instruction under execution, except some instructions, is saved to FEPC when an NMI occurs. The current contents of the PSW are saved to FEPSW. Because only one set of NMI status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are always fixed to 0). The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction. 31 FEPC 26 25 0 0 0 0 0 0 0 31 FEPSW Default value 0xxxxxxxH (x: Undefined) (Contents of saved PC) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value 000000xxH (x: Undefined) (Contents of saved PSW) (3) Interrupt source register (ECR) The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt occurs. This register holds the exception code of each interrupt source. Because this register is a read-only register, data cannot be written to this register using the LDSR instruction. 31 16 15 ECR Bit position 60 0 FECC Bit name EICC Meaning 31 to 16 FECC Exception code of non-maskable interrupt (NMI) 15 to 0 EICC Exception code of exception or maskable interrupt User's Manual U16541EJ5V1UD Default value 00000000H CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution. However if the ID flag is set to 1, interrupt requests will not be acknowledged while the LDSR instruction is being executed. Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 8 7 6 5 4 3 2 1 0 PSW NP EP ID SAT CY OV S Z RFU Bit position Flag name Default value 00000020H Meaning 31 to 8 RFU Reserved field. Fixed to 0. 7 NP Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an NMI request is acknowledged, disabling multiple interrupts. 0: NMI is not being serviced. 1: NMI is being serviced. 6 EP Indicates that an exception is being processed. This bit is set to 1 when an exception occurs. Even if this bit is set, interrupt requests are acknowledged. 0: Exception is not being processed. 1: Exception is being processed. 5 ID Indicates whether a maskable interrupt can be acknowledged. 0: Interrupt enabled 1: Interrupt disabled 4 Note SAT Indicates that the result of a saturation operation has overflowed and is saturated. Because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: Not saturated 1: Saturated 3 CY Indicates whether a carry or a borrow occurs as a result of an operation. 0: Carry or borrow does not occur. 1: Carry or borrow occurs. 2 OV Note Indicates whether an overflow occurs during operation. 0: Overflow does not occur. 1: Overflow occurs. 1 S Note Indicates whether the result of an operation is negative. 0: The result is positive or 0. 1: The result is negative. 0 Z Indicates whether the result of an operation is 0. 0: The result is not 0. 1: The result is 0. Remark Also read Note on the next page. User's Manual U16541EJ5V1UD 61 CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed. Status of operation result Flag status SAT Result of operation of OV S saturation processing Maximum positive value is exceeded 1 1 0 7FFFFFFFH Maximum negative value is exceeded 1 1 1 80000000H 0 0 Operation result itself Positive (maximum value is not exceeded) Negative (maximum value is not exceeded) Holds value before operation 1 (5) CALLT execution status saving registers (CTPC and CTPSW) CTPC and CTPSW are CALLT execution status saving registers. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and those of the program status word (PSW) are saved to CTPSW. The contents saved to CTPC are the address of the instruction next to CALLT. The current contents of the PSW are saved to CTPSW. Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0). 31 CTPC 26 25 0 0 0 0 0 0 0 31 CTPSW 62 Default value 0xxxxxxxH (x: Undefined) (Saved PC contents) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 User's Manual U16541EJ5V1UD 0 (Saved PSW contents) Default value 000000xxH (x: Undefined) CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW. The contents to be saved to DBPC are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs. The current contents of the PSW are saved to DBPSW. <R> This register can be read or written only during the interval between the execution of the DBTRAP instruction or illegal opcode and DBRET instruction execution. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0). The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction. 31 DBPC 26 25 0 0 0 0 0 0 0 31 DBPSW Default value 0xxxxxxxH (x: Undefined) (Saved PC contents) 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default value 000000xxH (x: Undefined) (Saved PSW contents) (7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed to 0). Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 CTBP 26 25 0 0 0 0 0 0 0 (Base address) User's Manual U16541EJ5V1UD 0 Default value 0xxxxxxxH (x: Undefined) 63 CHAPTER 3 CPU FUNCTION 3.3 <R> Operation Modes The V850ES/SG2 and V850ES/SG2-H have the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released. Execution branches to the reset entry address of the internal ROM, and then instruction processing is started. (2) Flash memory programming mode In this mode, the internal flash memory can be programmed by using a flash memory programmer. <R> The following products are on-chip flash memory versions of the V850ES/SG2 and V850ES/SG2-H. <R> * PD70F3261, 70F3261Y, 70F3263, 70F3263Y, 70F3271, 70F3271Y, 70F3273, 70F3273Y, 70F3281, 70F3281Y, 70F3283, 70F3283Y, 70F3263HY, 70F3273HY, 70F3283HY (3) On-chip debug mode The V850ES/SG2 and V850ES/SG2-H are provided with an on-chip debug function that employs the JTAG (Joint Test Action Group) communication specifications and that is executed via an on-chip debug emulator. The on-chip debug function is provided only in the flash memory versions. For details, see CHAPTER 31 ON-CHIP DEBUG FUNCTION. 3.3.1 Specifying operation mode Specify the operation mode by using the FLMD0 and FLMD1 pins. <R> In the normal mode, input a low level to the FLMD0/IC pin after the reset status has been released and before the oscillation stabilization time expires and the firmware operation is completed. In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash memory programmer if a flash memory programmer is connected, but it must be input from an external circuit in the self-programming mode. Operation When Reset Is Released Operation Mode After Reset FLMD0 FLMD1 L x Normal operation mode H L Flash memory programming mode H H Setting prohibited Remark L: Low-level input H: High-level input x: Don't care 64 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION 3.4 Address Space 3.4.1 CPU address space For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space, however, is viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical address space is accessed regardless of the value of bits 31 to 26. Figure 3-1. Image on Address Space Image 63 4 GB Data space Peripheral I/O area Program space Image 1 Use-prohibited area Internal RAM area Internal RAM area Programmable peripheral I/O area or use-prohibited area 64 MB Use-prohibited area 64 MB Image 0 External memory area External memory area Internal ROM area (external memory area) 16 MB Internal ROM area (external memory area) Caution Only the programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB address space. User's Manual U16541EJ5V1UD 65 CHAPTER 3 CPU FUNCTION 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are contiguous addresses. That the highest address and the lowest address of the program space are contiguous in this way is called wraparound. Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O area, instructions cannot be fetched from this area. Therefore, do not execute an operation in which the result of a branch address calculation affects this area. 00000001H Program space 00000000H (+) direction (-) direction 03FFFFFFH 03FFFFFEH Program space (2) Data space The result of an operand address calculation operation that exceeds 32 bits is ignored. Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are contiguous, and wraparound occurs at the boundary of these addresses. 00000001H Data space 00000000H (+) direction FFFFFFFFH FFFFFFFEH Data space 66 User's Manual U16541EJ5V1UD (-) direction CHAPTER 3 CPU FUNCTION 3.4.3 <R> Memory map The areas shown below are reserved in the V850ES/SG2 and V850ES/SG2-H. Figure 3-2. Data Memory Map (Physical Addresses) 03FFFFFFH On-chip peripheral I/O area (4 KB) (80 KB) 03FEC000H 03FEBFFFH 03FFFFFFH 03FFF000H 03FFEFFFH Internal RAM area (60 KB) Use prohibited Use prohibitedNote 1 03FF0000H 03FEFFFFH 03FEF000H 03FEEFFFH Programmable peripheral I/O areaNote 2 or use prohibitedNote 3 01000000H 00FFFFFFH 03FEC000H External memory area (14 MB) 001FFFFFH External memory area (1 MB) 00200000H 001FFFFFH Internal ROM areaNote 4 (1 MB) (2 MB) 00000000H 00100000H 000FFFFFH 00000000H Notes 1. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the same area as the on-chip peripheral I/O area. 2. Only the programmable peripheral I/O area can be viewed in the 4 GB address space as the image in 256 MB unit. 3. Addresses 03FEC000H to 03FEC5FFH are allocated to addresses 03FEC000H to 03FEEFFFH of the CAN controller version as a programmable peripheral I/O area. Use of these addresses in a version without a CAN controller is prohibited. 4. Fetch access and read access to addresses 00000000H to 000FFFFFH is made to the internal ROM area. However, data write access to these addresses is made to the external memory area. User's Manual U16541EJ5V1UD 67 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map 03FFFFFFH 03FFF000H 03FFEFFFH Use prohibited (program fetch prohibited area) Internal RAM area (60 KB) 03FF0000H 03FEFFFFH Use prohibited (program fetch prohibited area) 01000000H 00FFFFFFH External memory area (14 MB) 00200000H 001FFFFFH 00100000H 000FFFFFH 00000000H 68 External memory area (1 MB) Internal ROM area (1 MB) User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION 3.4.4 Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (256 KB) 256 KB mask ROM is allocated to addresses 00000000H to 0003FFFFH in the following versions. Accessing addresses 00040000H to 000FFFFFH is prohibited. * PD703260, 703260Y, 703270, 703270Y, 703280, 703280Y Figure 3-4. Internal ROM Area (256 KB) 000FFFFFH Access-prohibited area 00040000H 0003FFFFH Internal ROM (256 KB) 00000000H (b) Internal ROM (384 KB) 384 KB mask ROM or flash memory is allocated to addresses 00000000H to 0005FFFFH in the following versions. Accessing addresses 00060000H to 000FFFFFH is prohibited. * PD703261, 703261Y, 703271, 703271Y, 703281, 703281Y, 70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y Figure 3-5. Internal ROM Area (384 KB) 000FFFFFH Access-prohibited area 00060000H 0005FFFFH Internal ROM (384 KB) 00000000H User's Manual U16541EJ5V1UD 69 CHAPTER 3 CPU FUNCTION (c) Internal ROM (512 KB) 512 KB mask ROM is allocated to addresses 00000000H to 0007FFFFH in the following versions. Accessing addresses 00080000H to 000FFFFFH is prohibited. * PD703262, 703262Y, 703272, 703272Y, 703282, 703282Y, 703262HY, 703272HY, 703282HY <R> Figure 3-6. Internal ROM Area (512 KB) 000FFFFFH 00080000H 0007FFFFH Access-prohibited area Internal ROM (512 KB) 00000000H (d) Internal ROM (640 KB) 640 KB mask ROM or flash memory is allocated to addresses 00000000H to 0009FFFFH in the following versions. Accessing addresses 000A0000H to 000FFFFFH is prohibited. * PD703263, 703263Y, 703273, 703273Y, 703283, 703283Y, 70F3263, 70F3263Y, 70F3273, 70F3273Y, <R> 70F3283, 70F3283Y, 703263HY, 703273HY, 703283HY, 70F3263HY, 70F3273HY, 70F3283HY Figure 3-7. Internal ROM Area (640 KB) 000FFFFFH 000A0000H 0009FFFFH Access-prohibited area Internal ROM (640 KB) 00000000H 70 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. (a) Internal RAM (24 KB) 24 KB RAM is allocated to addresses 03FF9000H to 03FFEFFFH of the following versions. Accessing addresses 03FF0000H to 03FF8FFFH is prohibited. * PD703260, 703260Y, 703270, 703270Y, 703280, 703280Y Figure 3-8. Internal RAM Area (24 KB) Logical address space Physical address space FFFFEFFFH 03FFEFFFH Internal RAM (24 KB) FFFF9000H FFFF8FFFH 03FF9000H 03FF8FFFH Access-prohibited area 03FF0000H FFFF0000H (b) Internal RAM (32 KB) 32 KB RAM is allocated to addresses 03FF7000H to 03FFEFFFH of the following versions. Accessing addresses 03FF0000H to 03FF6FFFH is prohibited. * PD703261, 703261Y, 703271, 703271Y, 703281, 703281Y, 70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y Figure 3-9. Internal RAM Area (32 KB) Logical address space Physical address space FFFFEFFFH 03FFEFFFH Internal RAM (32 KB) FFFF7000H FFFF6FFFH 03FF7000H 03FF6FFFH Access-prohibited area 03FF0000H FFFF0000H User's Manual U16541EJ5V1UD 71 CHAPTER 3 CPU FUNCTION (c) Internal RAM (40 KB) 40 KB RAM is allocated to addresses 03FF5000H to 03FFEFFFH of the following versions. Accessing addresses 03FF0000H to 03FF4FFFH is prohibited. * PD703262, 703262Y, 703272, 703272Y, 703282, 703282Y, 703262HY, 703272HY, 703282HY <R> Figure 3-10. Internal RAM Area (40 KB) Logical address space Physical address space FFFFEFFFH 03FFEFFFH Internal RAM (40 KB) FFFF5000H FFFF4FFFH 03FF5000H 03FF4FFFH Access-prohibited area 03FF0000H FFFF0000H (d) Internal RAM (48 KB) 48 KB RAM is allocated to addresses 03FF3000H to 03FFEFFFH of the following versions. Accessing addresses 03FF0000H to 03FF2FFFH is prohibited. * PD703263, 703263Y, 703273, 703273Y, 703283, 703283Y, 70F3263, 70F3263Y, 70F3273, <R> 70F3273Y, 70F3283, 70F3283Y, 703263HY, 703273HY, 703283HY, 70F3263HY, 70F3273HY, 70F3283HY Figure 3-11. Internal RAM Area (48 KB) Physical address space Logical address space FFFFEFFFH 03FFEFFFH Internal RAM (48 KB) 03FF3000H 03FF2FFFH 03FF0000H 72 Access-prohibited area User's Manual U16541EJ5V1UD FFFF3000H FFFF2FFFH FFFF0000H CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-12. On-Chip Peripheral I/O Area Physical address space Logical address space 03FFFFFFH FFFFFFFFH On-chip peripheral I/O area (4 KB) 03FFF000H FFFFF000H Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the onchip peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area. Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read, and data is written to the lower 8 bits. 3. Addresses not defined as registers are reserved for future expansion. The operation is undefined and not guaranteed when these addresses are accessed. <R> 4. The internal ROM/RAM area and on-chip peripheral I/O area are assigned to successive addresses. When accessing the internal ROM/RAM area by incrementing or decrementing addresses using pointer operations and such, therefore, be careful not to access the onchip peripheral I/O area by mistakenly extending over the internal ROM/RAM area boundary. User's Manual U16541EJ5V1UD 73 CHAPTER 3 CPU FUNCTION (4) Programmable peripheral I/O area Cautions 1. The programmable peripheral I/O area exists only in the CAN controller versions. This area cannot be used with products that are not equipped with the CAN controller. 2. Only the programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB address space. 12 KB of addresses 03FEC000H to 03FEEFFFH are reserved as the programmable peripheral I/O area. Figure 3-13. Programmable Peripheral I/O Area 03FEEFFFH Programmable peripheral I/O area (12 KB) 03FEC000H (5) External memory area 15 MB (00100000H to 00FFFFFFH) are allocated as the external memory area. For details, see CHAPTER 5 BUS CONTROL FUNCTION. <R> Caution The V850ES/SG2 and V850ES/SG2-H have 22 address pins (A0 to A21), so the external memory area appears as a repeated 4 MB image. When A20 and A21 pins are used, it is necessary to set that EVDD = BVDD = VDD. 74 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION 3.4.5 <R> Recommended use of address space The architecture of the V850ES/SG2 and V850ES/SG2-H requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer 32 KB can be directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H unconditionally corresponds to the memory map. To use the internal RAM area as the program space, access the following addresses. Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation (invalid fetch) straddling the on-chip peripheral I/O area does not occur. RAM Size Access Address 48 KB 03FF3000H to 03FFEFFFH 40 KB 03FF5000H to 03FFEFFFH 32 KB 03FF7000H to 03FFEFFFH 24 KB 03FF9000H to 03FFEFFFH (2) Data space <R> With the V850ES/SG2 and V850ES/SG2-H, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. User's Manual U16541EJ5V1UD 75 CHAPTER 3 CPU FUNCTION (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H 32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer. The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers dedicated to pointers. Example PD703261Y 00007FFFH Internal ROM area (R = ) 0 0 0 0 0 0 0 0 H F F F F F F F F H On-chip peripheral I/O area FFFFF000H FFFFEFFFH Internal RAM area FFFF8000H 76 User's Manual U16541EJ5V1UD 32 KB 4 KB 28 KB CHAPTER 3 CPU FUNCTION Figure 3-14. Recommended Memory Map Program space Data space FFFFFFFFH On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM FFFFFFFFH FFFF0000H FFFEFFFFH On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM FFFF3000H FFFF2FFFH FFFF0000H FFFEFFFFH 04000000H 03FFFFFFH Use prohibited 03FFF000H 03FFEFFFH Internal RAM Use prohibitedNote 03FF3000H 03FF2FFFH 03FF0000H 03FEFFFFH Use prohibited Program space 64 MB External memory 01000000H 00FFFFFFH 00100000H 000FFFFFH External memory 00100000H 000FFFFFH 000A0000H 0009FFFFH 00000000H Internal ROM Internal ROM 00000000H Internal ROM Note In the CAN controller version, the data space of addresses 03FEC000H to 03FEEFFFH is assigned as the programmable peripheral I/O area. Only the programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB address space. Remarks 1. indicates the recommended area. 2. This figure is the recommended memory map of the PD703263HY. User's Manual U16541EJ5V1UD 77 CHAPTER 3 CPU FUNCTION 3.4.6 Peripheral I/O registers (1/11) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFF004H Port DL register 8 R/W PDL 16 Note 1 0000H FFFFF004H Port DL register L PDLL 00H Note 1 FFFFF005H Port DL register H PDLH 00H Note 1 FFFFF006H Port DH register PDH 00H Note 1 FFFFF00AH Port CT register PCT 00H Note 1 FFFFF00CH Port CM register PCM 00H Note 1 FFFFF024H Port DL mode register PMDL Port DL mode register L PMDLL FFH FFFFF024H FFFFH Port DL mode register H PMDLH FFH FFFFF026H Port DH mode register PMDH FFH FFFFF02AH Port CT mode register PMCT FFH FFFFF02CH Port CM mode register PMCM FFH FFFFF044H FFFFF025H Port DL mode control register PMCDL FFFFF044H Port DL mode control register L PMCDLL 00H 0000H FFFFF045H Port DL mode control register H PMCDLH 00H FFFFF046H Port DH mode control register PMCDH 00H FFFFF04AH Port CT mode control register PMCCT 00H FFFFF04CH Port CM mode control register PMCCM 00H FFFFF064H Peripheral I/O area select control register BPC 0000H FFFFF066H Bus size configuration register BSC 5555H FFFFF06EH System wait control register VSWC FFFFF080H DMA source address register 0L DSA0L Undefined FFFFF082H DMA source address register 0H DSA0H Undefined FFFFF084H DMA destination address register 0L DDA0L Undefined FFFFF086H DMA destination address register 0H DDA0H Undefined FFFFF088H DMA source address register 1L DSA1L Undefined FFFFF08AH DMA source address register 1H DSA1H Undefined FFFFF08CH DMA destination address register 1L DDA1L Undefined FFFFF08EH DMA destination address register 1H DDA1H Undefined FFFFF090H DMA source address register 2L DSA2L Undefined FFFFF092H DMA source address register 2H DSA2H Undefined FFFFF094H DMA destination address register 2L DDA2L Undefined FFFFF096H DMA destination address register 2H DDA2H Undefined FFFFF098H DMA source address register 3L DSA3L Undefined FFFFF09AH DMA source address register 3H DSA3H Undefined Note 2 77H FFFFF09CH DMA destination address register 3L DDA3L Undefined FFFFF09EH DMA destination address register 3H DDA3H Undefined FFFFF0C0H DMA transfer count register 0 DBC0 Undefined FFFFF0C2H DMA transfer count register 1 DBC1 Undefined FFFFF0C4H DMA transfer count register 2 DBC2 Undefined Notes 1. The output latch is 00H or 0000H. When these registers are in the input mode, the pin statuses are read. 2. CAN controller versions only 78 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION (2/11) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 DMA transfer count register 3 DBC3 Undefined FFFFF0D0H DMA addressing control register 0 DADC0 0000H FFFFF0D2H DMA addressing control register 1 DADC1 0000H FFFFF0D4H DMA addressing control register 2 DADC2 0000H FFFFF0D6H DMA addressing control register 3 DADC3 0000H FFFFF0E0H DMA channel control register 0 DCHC0 00H FFFFF0E2H DMA channel control register 1 DCHC1 00H FFFFF0E4H DMA channel control register 2 DCHC2 00H FFFFF0E6H DMA channel control register 3 DCHC3 00H FFFFF100H R/W Interrupt mask register 0 IMR0 FFFFF100H Interrupt mask register 0L IMR0L FFH FFFFF101H Interrupt mask register 0H IMR0H FFH Interrupt mask register 1 IMR1 FFFFH FFFFH FFFFF102H Interrupt mask register 1L IMR1L FFH FFFFF103H Interrupt mask register 1H IMR1H FFH Interrupt mask register 2 IMR2 FFFFF104H FFFFH FFFFF104H Interrupt mask register 2L IMR2L FFH FFFFF105H Interrupt mask register 2H IMR2H FFH Interrupt mask register 3 IMR3 FFFFF106H <R> 16 FFFFF0C6H FFFFF102H <R> 8 FFFFH FFFFF106H Interrupt mask register 3L IMR3L FFH FFFFF107H Interrupt mask register 3H IMR3H FFH 47H Note FFFFF110H Interrupt control register LVIIC FFFFF112H Interrupt control register PIC0 47H FFFFF114H Interrupt control register PIC1 47H FFFFF116H Interrupt control register PIC2 47H FFFFF118H Interrupt control register PIC3 47H FFFFF11AH Interrupt control register PIC4 47H FFFFF11CH Interrupt control register PIC5 47H FFFFF11EH Interrupt control register PIC6 47H FFFFF120H Interrupt control register PIC7 47H FFFFF122H Interrupt control register TQ0OVIC 47H FFFFF124H Interrupt control register TQ0CCIC0 47H FFFFF126H Interrupt control register TQ0CCIC1 47H FFFFF128H Interrupt control register TQ0CCIC2 47H FFFFF12AH Interrupt control register TQ0CCIC3 47H FFFFF12CH Interrupt control register TP0OVIC 47H FFFFF12EH Interrupt control register TP0CCIC0 47H FFFFF130H Interrupt control register TP0CCIC1 47H FFFFF132H Interrupt control register TP1OVIC 47H FFFFF134H Interrupt control register TP1CCIC0 47H FFFFF136H Interrupt control register TP1CCIC1 47H FFFFF138H Interrupt control register TP2OVIC 47H Note V850ES/SG2 versions only User's Manual U16541EJ5V1UD 79 CHAPTER 3 CPU FUNCTION (3/11) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 16 FFFFF13AH Interrupt control register TP2CCIC0 47H FFFFF13CH Interrupt control register TP2CCIC1 47H FFFFF13EH Interrupt control register TP3OVIC 47H FFFFF140H Interrupt control register TP3CCIC0 47H FFFFF142H Interrupt control register TP3CCIC1 47H FFFFF144H Interrupt control register TP4OVIC 47H FFFFF146H Interrupt control register TP4CCIC0 47H FFFFF148H Interrupt control register TP4CCIC1 47H FFFFF14AH Interrupt control register TP5OVIC 47H FFFFF14CH Interrupt control register TP5CCIC0 47H FFFFF14EH Interrupt control register TP5CCIC1 47H FFFFF150H Interrupt control register TM0EQIC0 47H FFFFF152H Interrupt control register CB0RIC/IICIC1 47H FFFFF154H Interrupt control register CB0TIC 47H R/W Note 1 FFFFF156H Interrupt control register CB1RIC 47H FFFFF158H Interrupt control register CB1TIC 47H FFFFF15AH Interrupt control register CB2RIC 47H FFFFF15CH Interrupt control register CB2TIC 47H FFFFF15EH Interrupt control register CB3RIC 47H FFFFF160H Interrupt control register CB3TIC 47H FFFFF162H Interrupt control register UA0RIC/CB4RIC 47H FFFFF164H Interrupt control register UA0TIC/CB4TIC 47H FFFFF166H Interrupt control register UA1RIC/IICIC2 Note 1 47H FFFFF168H Interrupt control register UA1TIC 47H FFFFF16AH Interrupt control register UA2RIC/IICIC0 Note 1 47H FFFFF16CH Interrupt control register UA2TIC 47H FFFFF16EH Interrupt control register ADIC 47H FFFFF170H Interrupt control register DMAIC0 47H FFFFF172H Interrupt control register DMAIC1 47H FFFFF174H Interrupt control register DMAIC2 47H FFFFF176H Interrupt control register DMAIC3 47H FFFFF178H Interrupt control register KRIC 47H FFFFF17AH Interrupt control register WTIIC 47H FFFFF17CH Interrupt control register WTIC 47H FFFFF17EH Interrupt control register ERRIC0 / Note 3 ERRIC 47H FFFFF180H Interrupt control register WUPIC0 Note 3 STAIC Note 2 / 47H FFFFF182H Interrupt control register RECIC0 Note 3 IEIC1 / 47H Note 2 Note 2 Notes 1. I2C bus versions (Y products) only 2. CAN controller versions only 3. IEBus controller versions only 80 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION (4/11) Address Function Register Name Symbol Note 1 FFFFF184H Interrupt control register TRXIC0 Note 2 IEIC2 FFFFF1FAH In-service priority register ISPR / R/W Manipulatable Bits Default Value 1 8 16 R/W 47H R 00H Undefined 00H ADA0M0 00H ADA0M1 00H FFFFF1FCH Command register PRCMD FFFFF1FEH Power save control register PSC FFFFF200H A/D converter mode register 0 FFFFF201H A/D converter mode register 1 W R/W FFFFF202H A/D converter channel specification register ADA0S 00H FFFFF203H A/D converter mode register 2 ADA0M2 00H FFFFF204H Power-fail compare mode register ADA0PFM 00H FFFFF205H Power-fail compare threshold value register ADA0PFT FFFFF210H A/D conversion result register 0 ADA0CR0 A/D conversion result register 0H ADA0CR0H A/D conversion result register 1 ADA0CR1 A/D conversion result register 1H ADA0CR1H A/D conversion result register 2 ADA0CR2 A/D conversion result register 2H ADA0CR2H FFFFF211H FFFFF212H FFFFF213H FFFFF214H FFFFF215H FFFFF216H FFFFF217H FFFFF218H FFFFF219H FFFFF21AH FFFFF21BH FFFFF21CH FFFFF21DH FFFFF21EH FFFFF21FH FFFFF220H FFFFF221H FFFFF222H FFFFF223H FFFFF224H FFFFF225H FFFFF226H A/D conversion result register 3 ADA0CR3 A/D conversion result register 3H ADA0CR3H A/D conversion result register 4 ADA0CR4 A/D conversion result register 4H ADA0CR4H A/D conversion result register 5 ADA0CR5 A/D conversion result register 5H ADA0CR5H A/D conversion result register 6 ADA0CR6 A/D conversion result register 6H ADA0CR6H A/D conversion result register 7 ADA0CR7 A/D conversion result register 7H ADA0CR7H A/D conversion result register 8 ADA0CR8 A/D conversion result register 8H ADA0CR8H A/D conversion result register 9 ADA0CR9 A/D conversion result register 9H ADA0CR9H A/D conversion result register 10 ADA0CR10 A/D conversion result register 10H ADA0CR10H R Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined FFFFF282H D/A converter mode register DA0M FFFFF300H Key return mode register KRM Undefined Undefined DA0CS1 Undefined Undefined DA0CS0 Undefined Undefined D/A converter conversion value setting register 1 Undefined Undefined D/A converter conversion value setting register 0 SELCNT0 Undefined FFFFF281H CRCIN Undefined FFFFF280H Selector operation control register 0 Undefined ADA0CR11 CRC input register Undefined ADA0CR11H FFFFF310H A/D conversion result register 11 FFFFF308H Undefined A/D conversion result register 11H FFFFF227H 00H Undefined Undefined 00H 00H 00H 00H R/W 00H 00H Notes 1. CAN controller versions only 2. IEBus controller versions only User's Manual U16541EJ5V1UD 81 CHAPTER 3 CPU FUNCTION (5/11) Address Function Register Name Symbol R/W Manipulatable Bits 1 CRC data register CRCD FFFFF318H Noise elimination control register NFC FFFFF320H BRG1 prescaler mode register PRSM1 FFFFF321H BRG1 prescaler compare register PRSCM1 FFFFF324H BRG2 prescaler mode register PRSM2 FFFFF325H BRG2 prescaler compare register PRSCM2 FFFFF328H BRG3 prescaler mode register PRSM3 00H 00H OCKS1 OCKS2 Note 2 00H Note 2 00H 81H 00H 00H FFFFF360H IEBus control register BCR FFFFF361H IEBus power save register PSR Note 2 FFFFF363H IEBus unit status register USR FFFFF364H IEBus interrupt status register ISR R Note 2 Note 2 R/W Note 2 FFFFF365H IEBus error status register ESR FFFFF366H IEBus unit address register UAR FFFFF368H IEBus slave address register SAR Note 2 Note 2 Note 2 R Note 2 FFFFF36CH IEBus receive slave address register RSA FFFFF36EH IEBus control data register CDR DLR Note 2 R/W Note 2 Note 2 FFFFF370H IEBus data register DR FFFFF371H IEBus field status register FSR 00H Note 2 IIC division clock select register IEBus clock select register IEBus telegraph length register 00H FFFFF348H FFFFF36FH 00H 00H Note 1 FFFFF344H PAR 00H OCKS0 IEBus partner address register 00H 00H PRSCM3 IIC division clock select register FFFFF36AH BRG3 prescaler compare register FFFFF340H SSR 0000H 00H Note 1 FFFFF329H IEBus slave status register 16 R/W FFFFF312H FFFFF362H 8 D0000H efault Value Note 2 R 00H 0000H 0000H 0000H 0000H 00H 01H 00H 00H Note 2 01H Note 2 20H 00H Note 3 00H Note 3 FFFFF372H IEBus success count register SCR FFFFF373H IEBus communication count register CCR FFFFF400H Port 0 register P0 FFFFF402H Port 1 register P1 FFFFF406H Port 3 register P3 FFFFF406H Port 3 register L P3L 00H Note 3 FFFFF407H Port 3 register H P3H 00H Note 3 FFFFF408H Port 4 register P4 00H Note 3 FFFFF40AH Port 5 register P5 00H Note 3 FFFFF40EH Port 7 register L P7L 00H Note 3 FFFFF40FH Port 7 register H P7H 00H FFFFF412H Port 9 register P9 FFFFF412H Port 9 register L P9L 00H FFFFF413H Port 9 register H P9H 00H Port 0 mode register PM0 FFH FFFFF420H R/W Note 3 2 Notes 1. I C bus versions (Y products) only 2. IEBus controller versions only 3. The output latch is 00H or 0000H. When these registers are input, the pin statuses are read. 82 User's Manual U16541EJ5V1UD Note 3 0000H Note 3 0000H Note 3 Note 3 CHAPTER 3 CPU FUNCTION (6/11) Address Function Register Name Symbol R/W Manipulatable Bits Default Value R/W 1 8 16 FFFFF422H Port 1 mode register PM1 FFFFF426H Port 3 mode register PM3 FFH FFFFF426H Port 3 mode register L PM3L FFH FFFFF427H FFFFH Port 3 mode register H PM3H FFH FFFFF428H Port 4 mode register PM4 FFH FFFFF42AH Port 5 mode register PM5 FFH FFFFF42EH Port 7 mode register L PM7L FFH FFFFF42FH Port 7 mode register H PM7H FFH FFFFF432H Port 9 mode register PM9 FFFFF432H Port 9 mode register L PM9L FFFFH FFH FFFFF433H Port 9 mode register H PM9H FFH FFFFF440H Port 0 mode control register PMC0 FFFFF446H Port 3 mode control register PMC3 00H 0000H FFFFF446H Port 3 mode control register L PMC3L 00H FFFFF447H Port 3 mode control register H PMC3H 00H FFFFF448H Port 4 mode control register PMC4 00H FFFFF44AH Port 5 mode control register PMC5 FFFFF452H Port 9 mode control register PMC9 FFFFF452H Port 9 mode control register L PMC9L 00H FFFFF453H Port 9 mode control register H PMC9H 00H Port 0 function control register PFC0 00H FFFFF460H FFFFF466H 00H 0000H Port 3 function control register PFC3 FFFFF466H Port 3 function control register L PFC3L 0000H 00H FFFFF467H Port 3 function control register H PFC3H 00H FFFFF468H Port 4 function control register PFC4 00H FFFFF46AH Port 5 function control register PFC5 00H FFFFF472H Port 9 function control register PFC9 FFFFF472H Port 9 function control register L PFC9L 00H FFFFF473H Port 9 function control register H PFC9H 00H 0000H FFFFF484H Data wait control register 0 DWC0 7777H FFFFF488H Address wait control register AWC FFFFH FFFFF48AH Bus cycle control register BCC AAAAH FFFFF540H TMQ0 control register 0 TQ0CTL0 00H FFFFF541H TMQ0 control register 1 TQ0CTL1 00H FFFFF542H TMQ0 I/O control register 0 TQ0IOC0 00H FFFFF543H TMQ0 I/O control register 1 TQ0IOC1 00H FFFFF544H TMQ0 I/O control register 2 TQ0IOC2 00H FFFFF545H TMQ0 option register 0 TQ0OPT0 FFFFF546H TMQ0 capture/compare register 0 TQ0CCR0 0000H FFFFF548H TMQ0 capture/compare register 1 TQ0CCR1 0000H FFFFF54AH TMQ0 capture/compare register 2 TQ0CCR2 0000H FFFFF54CH TMQ0 capture/compare register 3 TQ0CCR3 0000H FFFFF54EH TMQ0 counter read buffer register TQ0CNT 0000H User's Manual U16541EJ5V1UD R 00H 83 CHAPTER 3 CPU FUNCTION (7/11) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 16 FFFFF590H TMP0 control register 0 TP0CTL0 00H FFFFF591H TMP0 control register 1 TP0CTL1 00H FFFFF592H TMP0I/O control register 0 TP0IOC0 00H FFFFF593H TMP0I/O control register 1 TP0IOC1 00H FFFFF594H TMP0I/O control register 2 TP0IOC2 00H FFFFF595H TMP0 option register 0 TP0OPT0 FFFFF596H TMP0 capture/compare register 0 TP0CCR0 0000H FFFFF598H TMP0 capture/compare register 1 TP0CCR1 0000H FFFFF59AH TMP0 counter read buffer register TP0CNT R FFFFF5A0H TMP1 control register 0 TP1CTL0 R/W FFFFF5A1H TMP1 control register 1 FFFFF5A2H TMP1I/O control register 0 FFFFF5A3H FFFFF5A4H R/W 00H 0000H 00H TP1CTL1 00H TP1IOC0 00H TMP1I/O control register 1 TP1IOC1 00H TMP1I/O control register 2 TP1IOC2 00H FFFFF5A5H TMP1 option register 0 TP1OPT0 00H FFFFF5A6H TMP1 capture/compare register 0 TP1CCR0 0000H FFFFF5A8H TMP1 capture/compare register 1 TP1CCR1 0000H FFFFF5AAH TMP1 counter read buffer register TP1CNT R FFFFF5B0H TMP2 control register 0 TP2CTL0 R/W FFFFF5B1H TMP2 control register 1 FFFFF5B2H TMP2I/O control register 0 FFFFF5B3H FFFFF5B4H 0000H 00H TP2CTL1 00H TP2IOC0 00H TMP2I/O control register 1 TP2IOC1 00H TMP2I/O control register 2 TP2IOC2 00H FFFFF5B5H TMP2 option register 0 TP2OPT0 00H FFFFF5B6H TMP2 capture/compare register 0 TP2CCR0 0000H FFFFF5B8H TMP2 capture/compare register 1 TP2CCR1 0000H FFFFF5BAH TMP2 counter read buffer register TP2CNT R FFFFF5C0H TMP3 control register 0 TP3CTL0 R/W FFFFF5C1H TMP3 control register 1 FFFFF5C2H TMP3I/O control register 0 FFFFF5C3H TMP3I/O control register 1 0000H 00H TP3CTL1 00H TP3IOC0 00H TP3IOC1 00H FFFFF5C4H TMP3I/O control register 2 TP3IOC2 00H FFFFF5C5H TMP3 option register 0 TP3OPT0 00H FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0 0000H FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1 0000H FFFFF5CAH TMP3 counter read buffer register TP3CNT R FFFFF5D0H TMP4 control register 0 TP4CTL0 R/W FFFFF5D1H TMP4 control register 1 FFFFF5D2H TMP4I/O control register 0 FFFFF5D3H TMP4I/O control register 1 0000H 00H TP4CTL1 00H TP4IOC0 00H TP4IOC1 00H FFFFF5D4H TMP4I/O control register 2 TP4IOC2 00H FFFFF5D5H TMP4 option register 0 TP4OPT0 00H FFFFF5D6H TMP4 capture/compare register 0 TP4CCR0 0000H FFFFF5D8H TMP4 capture/compare register 1 TP4CCR1 0000H 84 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION (8/11) Address Function Register Name Symbol R/W Manipulatable Bits 16 32 Default Value 1 8 00H FFFFF5DAH TMP4 counter read buffer register TP4CNT R FFFFF5E0H TMP5 control register 0 TP5CTL0 R/W 0000H FFFFF5E1H TMP5 control register 1 TP5CTL1 00H FFFFF5E2H TMP5I/O control register 0 TP5IOC0 00H FFFFF5E3H TMP5I/O control register 1 TP5IOC1 00H FFFFF5E4H TMP5I/O control register 2 TP5IOC2 00H FFFFF5E5H TMP5 option register 0 TP5OPT0 00H FFFFF5E6H TMP5 capture/compare register 0 TP5CCR0 FFFFF5E8H TMP5 capture/compare register 1 TP5CCR1 FFFFF5EAH TMP5 counter read buffer register TP5CNT FFFFF680H Watch timer operation mode register WTM FFFFF690H TMM0 control register 0 TM0CTL0 FFFFF694H TMM0 compare register 0 TM0CMP0 FFFFF6C0H Oscillation stabilization time select register OSTS 06H FFFFF6C1H PLL lockup time specification register PLLS 03H FFFFF6D0H Watchdog timer mode register 2 WDTM2 67H FFFFF6D1H Watchdog timer enable register WDTE 9AH FFFFF6E0H Real-time output buffer register 0L RTBL0 00H FFFFF6E2H Real-time output buffer register 0H RTBH0 00H FFFFF6E4H Real-time output port mode register 0 RTPM0 00H FFFFF6E5H Real-time output port control register 0 RTPC0 00H R R/W 0000H 0000H 0000H 00H 00H 0000H FFFFF706H Port 3 function control expansion register L PFCE3L 00H FFFFF70AH Port 5 function control expansion register PFCE5 00H FFFFF712H Port 9 function control expansion register PFCE9 FFFFF712H Port 9 function control expansion register L PFCE9L 00H FFFFF713H Port 9 function control expansion register H PFCE9H 00H 0000H FFFFF802H System status register SYS 00H FFFFF80CH Internal oscillation mode register RCM 00H FFFFF810H DMA trigger factor register 0 DTFR0 00H FFFFF812H DMA trigger factor register 1 DTFR1 00H FFFFF814H DMA trigger factor register 2 DTFR2 00H FFFFF816H DMA trigger factor register 3 DTFR3 00H FFFFF820H Power save mode register PSMR 00H FFFFF822H Clock control register CKC FFFFF824H Lock register LOCKR FFFFF828H Processor clock control register PCC FFFFF82CH PLL control register PLLCTL FFFFF82EH CPU operation clock status register CCLS FFFFF840H Correction address register 0 CORAD0 FFFFF840H Correction address register 0L FFFFF842H Correction address register 0H CORAD0L CORAD0H User's Manual U16541EJ5V1UD 0AH R 00H R/W 03H 01H R 00H R/W 00000000H 0000H 0000H 85 CHAPTER 3 CPU FUNCTION (9/11) Address Function Register Name Symbol R/W Manipulatable Bits 1 FFFFF844H R/W 32 00000000H Correction address register 1 CORAD1 Correction address register 1L CORAD1L 0000H FFFFF846H Correction address register 1H CORAD1H 0000H Correction address register 2 CORAD2 FFFFF848H Correction address register 2L CORAD2L FFFFF84AH Correction address register 2H CORAD2H Correction address register 3 CORAD3 FFFFF84CH Correction address register 3L CORAD3L FFFFF84EH FFFFF84CH <R> 16 FFFFF844H FFFFF848H <R> 8 Default Value 0000H 0000H 00000000H 00000000H 0000H Correction address register 3H CORAD3H FFFFF870H Clock monitor mode register CLM 00H FFFFF880H Correction control register CORCN 00H FFFFF888H Reset source flag register RESF 00H FFFFF890H Low voltage detection register LVIM 00H Note 1 0000H FFFFF891H Low voltage detection level select register LVIS 00H FFFFF892H Internal RAM data status register RAMS 01H FFFFF8B0H Prescaler mode register 0 PRSM0 00H FFFFF8B1H Prescaler compare register 0 PRSCM0 00H FFFFF9FCH On-chip debug mode register OCDM 01H FFFFF9FEH Peripheral emulation register 1 PEMU1 00H FFFFFA00H UARTA0 control register 0 UA0CTL0 10H FFFFFA01H UARTA0 control register 1 UA0CTL1 00H FFFFFA02H UARTA0 control register 2 UA0CTL2 FFH FFFFFA03H UARTA0 option control register 0 UA0OPT0 14H FFFFFA04H UARTA0 status register UA0STR 00H FFFFFA06H UARTA0 receive data register UA0RX R FFH FFFFFA07H UARTA0 transmit data register UA0TX R/W FFH FFFFFA10H UARTA1 control register 0 UA1CTL0 10H FFFFFA11H UARTA1 control register 1 UA1CTL1 00H FFFFFA12H UARTA1 control register 2 UA1CTL2 FFH FFFFFA13H UARTA1 option control register 0 UA1OPT0 14H FFFFFA14H UARTA1 status register UA1STR 00H FFFFFA16H UARTA1 receive data register UA1RX R FFH FFFFFA17H UARTA1 transmit data register UA1TX R/W FFH FFFFFA20H UARTA2 control register 0 UA2CTL0 10H FFFFFA21H UARTA2 control register 1 UA2CTL1 00H FFFFFA22H UARTA2 control register 2 UA2CTL2 FFFFFA23H UARTA2 option control register 0 UA2OPT0 FFFFFA24H UARTA2 status register UA2STR FFFFFA26H UARTA2 receive data register UA2RX R FFFFFA27H UARTA2 transmit data register UA2TX R/W FFFFFC00H External interrupt falling edge specification register 0 INTF0 Note 1 <R> Notes 1. V850ES/SG2 only 2. Only during emulation 86 User's Manual U16541EJ5V1UD Note 2 FFH 14H 00H FFH FFH 00H CHAPTER 3 CPU FUNCTION (10/11) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 8 16 FFFFFC06H External interrupt falling edge specification register 3 00H FFFFFC13H External interrupt falling edge specification register 9H INTF9H 00H FFFFFC20H External interrupt rising edge specification register 0 INTR0 00H FFFFFC26H External interrupt rising edge specification register 3 INTR3 00H INTF3 R/W FFFFFC33H External interrupt rising edge specification register 9H INTR9H 00H FFFFFC60H Port 0 function register PF0 00H FFFFFC66H Port 3 function register PF3 FFFFFC66H Port 3 function register L PF3L 00H FFFFFC67H Port 3 function register H PF3H 00H FFFFFC68H Port 4 function register PF4 00H FFFFFC6AH Port 5 function register PF5 FFFFFC72H Port 9 function register PF9 0000H 00H 0000H FFFFFC72H Port 9 function register L PF9L 00H FFFFFC73H Port function 9 control register H PF9H 00H FFFFFD00H CSIB0 control register 0 CB0CTL0 01H FFFFFD01H CSIB0 control register 1 CB0CTL1 00H FFFFFD02H CSIB0 control register 2 CB0CTL2 00H FFFFFD03H CSIB0 status register CB0STR FFFFFD04H CSIB0 receive data register CB0RX CSIB0 receive data register L CB0RXL FFFFFD04H FFFFFD06H CSIB0 transmit data register CB0TX CSIB0 transmit data register L CB0TXL FFFFFD10H CSIB1 control register 0 CB1CTL0 FFFFFD11H CSIB1 control register 1 CB1CTL1 FFFFFD06H FFFFFD12H CSIB1 control register 2 CB1CTL2 FFFFFD13H CSIB1 status register CB1STR FFFFFD14H CSIB1 receive data register CB1RX FFFFFD14H FFFFFD16H CSIB1 receive data register L CB1RXL CSIB1 transmit data register CB1TX 00H R 00H R/W 0000H 0000H 00H 01H 00H 00H 00H R 00H R/W 0000H 0000H CSIB1 transmit data register L CB1TXL 00H FFFFFD20H CSIB2 control register 0 CB2CTL0 01H FFFFFD21H CSIB2 control register 1 CB2CTL1 00H FFFFFD22H CSIB2 control register 2 CB2CTL2 00H FFFFFD23H CSIB2 status register CB2STR FFFFFD24H CSIB2 receive data register CB2RX CSIB2 receive data register L CB2RXL FFFFFD16H FFFFFD24H FFFFFD26H CSIB2 transmit data register CB2TX CSIB2 transmit data register L CB2TXL FFFFFD30H CSIB3 control register 0 CB3CTL0 FFFFFD31H CSIB3 control register 1 CB3CTL1 FFFFFD26H FFFFFD32H CSIB3 control register 2 CB3CTL2 FFFFFD33H CSIB3 status register CB3STR FFFFFD34H CSIB3 receive data register CB3RX CSIB3 receive data register L CB3RXL FFFFFD34H User's Manual U16541EJ5V1UD 00H R 00H R/W 0000H 0000H 00H 01H 00H 00H 00H R 0000H 00H 87 CHAPTER 3 CPU FUNCTION (11/11) Address Function Register Name Symbol R/W Manipulatable Bits Default Value 1 FFFFFD36H CSIB3 transmit data register CB3TX CSIB3 transmit data register L CB3TXL FFFFFD40H CSIB4 control register 0 CB4CTL0 FFFFFD41H CSIB4 control register 1 CB4CTL1 FFFFFD42H CSIB4 control register 2 CB4CTL2 FFFFFD43H CSIB4 status register CB4STR FFFFFD44H CSIB4 receive data register CB4RX CSIB4 receive data register L CB4RXL FFFFFD36H FFFFFD44H FFFFFD46H FFFFFD46H CSIB4 transmit data register CB4TX CSIB4 transmit data register L CB4TXL IIC shift register 0 IIC0 FFFFFD82H IIC control register 0 IICC0 Slave address register 0 SVA0 IIC clock select register 0 IICCL0 FFFFFD85H IIC function expansion register 0 IICX0 00H 00H 00H Note 00H R/W 0000H 0000H 00H 00H 00H 00H 00H 00H R 00H R/W 00H 00H 00H 00H 00H IICS0 IICF0 FFFFFD90H IIC shift register 1 IIC1 FFFFFD92H IIC control register 1 IICC1 Note Note Note FFFFFD93H Slave address register 1 SVA1 FFFFFD94H IIC clock select register 1 IICCL1 Note 00H Note R 00H Note R/W 00H 00H 00H 00H 00H Note FFFFFD95H IIC function expansion register 1 IICX1 FFFFFD96H IIC status register 1 IICS1 FFFFFD9AH IIC flag register 1 IICF1 Note FFFFFDA0H IIC shift register 2 IIC2 FFFFFDA2H IIC control register 2 IICC2 Note Note FFFFFDA3H Slave address register 2 SVA2 FFFFFDA4H IIC clock select register 2 IICCL2 Note 00H Note R 00H Note R/W 00H 00H Note FFFFFDA5H IIC function expansion register 2 IICX2 FFFFFDA6H IIC status register 2 IICS2 FFFFFDAAH IIC flag register 2 IICF2 FFFFFDBEH External bus interface mode control register EXIMC User's Manual U16541EJ5V1UD 01H Note IIC status register 0 IIC flag register 0 88 Note FFFFFD8AH Note I C bus versions (Y products) only Note FFFFFD86H 2 00H Note FFFFFD84H 0000H R Note FFFFFD83H 16 R/W Note FFFFFD80H 8 CHAPTER 3 CPU FUNCTION 3.4.7 Programmable peripheral I/O registers The BPC register is used for programmable peripheral I/O register area selection. (1) Peripheral I/O area select control register (BPC) The BPC register can be read or written in 16-bit units. Reset sets this register to 0000H. 15 BPC PA15 Bit position 15 14 0 13 12 11 10 9 8 6 5 4 3 2 1 0 Address PA13 PA12 PA11 PA10 PA09 PA08 PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00 FFFFF064H Bit name PA15 PA13 to PA00 Default value 0000H Function Enables/disables usage of programmable peripheral I/O area. PA15 13 to 0 7 Usage of programmable peripheral I/O area 0 Usage of programmable peripheral I/O area disabled 1 Usage of programmable peripheral I/O area enabled Specify an address in programmable peripheral I/O area (corresponding to A27 to A14, respectively). Caution When setting the PA15 bit to 1, be sure to set the BPC register to 8FFBH. When clearing the PA15 bit to 0, be sure to set the BPC register to 0000H. For a list of the programmable peripheral I/O register areas, see Table 19-16 Register Access Types. 3.4.8 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The <R> V850ES/SG2 and V850ES/SG2-H have eight and seven special registers, respectively. * Power save control register (PSC) * Clock control register (CKC) * Processor clock control register (PCC) * Clock monitor mode register (CLM) * Reset source flag register (RESF) <R> * Low voltage detection register (LVIM)Note * Internal RAM data status register (RAMS) * On-chip debug mode register (OCDM) <R> Note V850ES/SG2 only In addition, the PRCDM register is provided to protect against a write access to the special registers so that the application system does not inadvertently stop due to a program hang-up. A write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the SYS register. User's Manual U16541EJ5V1UD 89 CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the PRCMD register. <4> Write the setting data to the special register (by using the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) (<5> to <9> Insert NOP instructions (5 instructions).)Note <10> Enable DMA operation if necessary. [Example] With PSC register (setting standby mode) ST.B r11, PSMR[r0] <1>CLR1 0, DCHCn[r0] ; Set PSMR register (setting IDLE1, IDLE2, and STOP modes). ; Disable DMA operation. n = 0 to 3 <2>MOV0x02, r10 <3>ST.B r10, PRCMD[r0] ; Write PRCMD register. <4>ST.B r10, PSC[r0] ; Set PSC register. <5>NOPNote ; Dummy instruction <6>NOPNote ; Dummy instruction <7>NOPNote ; Dummy instruction Note <8>NOP ; Dummy instruction <9>NOPNote ; Dummy instruction <10>SET1 0, DCHCn[r0] ; Enable DMA operation. n = 0 to 3 (next instruction) There is no special sequence to read a special register. Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or STOP mode (by setting the PSC.STP bit to 1). Cautions 1. When a store instruction is executed to store data in the command register, interrupts are not acknowledged. This is because it is assumed that steps <3> and <4> above are performed by successive store instructions. If another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. Although dummy data is written to the PRCMD register, use the same general-purpose register used to set the special register (<4> in Example) to write data to the PRCMD register (<3> in Example). The same applies when a general-purpose register is used for addressing. 90 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register. In this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read). After reset: Undefined PRCMD W Address: FFFFF1FCH 7 6 5 4 3 2 1 0 REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0 User's Manual U16541EJ5V1UD 91 CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF802H < > SYS 0 0 0 PRERR 0 0 0 0 PRERR Detects protection error 0 Protection error did not occur 1 Protection error occurred The PRERR flag operates under the following conditions. (a) Set condition (PRERR flag = 1) (i) When data is written to a special register without writing anything to the PRCMD register (when <4> is executed without executing <3> in 3.4.8 (1) Setting data to special registers) (ii) When data is written to an on-chip peripheral I/O register other than a special register (including <R> execution of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.8 (1) Setting data to special registers is not the setting of a special register) Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) between an operation to write the PRCMD register and an operation to write a special register, the PRERR flag is not set, and the set data can be written to the special register. (b) Clear condition (PRERR flag = 0) (i) When 0 is written to the PRERR flag (ii) When the system is reset Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register, immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the write access takes precedence). 2. If data is written to the PRCMD register, which is not a special register, immediately after a write access to the PRCMD register, the PRERR bit is set to 1. 92 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION 3.4.9 Cautions (1) Registers to be set first <R> Be sure to set the following registers first when using the V850ES/SG2 and V850ES/SG2-H. * System wait control register (VSWC) * On-chip debug mode register (OCDM) * Watchdog timer mode register 2 (WDTM2) After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary. When using the external bus, set each pin to the alternate-function bus control pin mode by using the portrelated registers after setting the above registers. (a) System wait control register (VSWC) The VSWC register controls wait of bus access to the on-chip peripheral I/O registers. Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The <R> V850ES/SG2 and V850ES/SG2-H require wait cycles according to the operating frequency. Set the <R> following value to the VSWC register in accordance with the frequency used. However, if fCLK is greater than 20 MHz, only the V850ES/SG2-H can be used. The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H). Operating Frequency (fCLK) Set Value of VSWC Number of Waits 32 kHz fCLK < 16.6 MHz 00H 0 (no waits) <R> 16.6 MHz fCLK < 25 MHz 01H 1 <R> 25 MHz fCLK 32 MHz 11H 2 (b) On-chip debug mode register (OCDM) For details, see CHAPTER 31 ON-CHIP DEBUG FUNCTION. (c) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and the operation clock of the watchdog timer 2. The watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to activate this operation. For details, see CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2. User's Manual U16541EJ5V1UD 93 CHAPTER 3 CPU FUNCTION (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction but enters the wait status. If this wait status occurs, the number of clocks required to execute an instruction increases by the number of wait clocks shown below. This must be taken into consideration if real-time processing is required. When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the wait states set by the VSWC register. The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this time are shown below. (1/2) Peripheral Function 16-bit timer/event counter P (TMP) (n = 0 to 5) 16-bit timer/event counter Q (TMQ) Access k Read 1 or 2 TPnCCR0, TPnCCR1 Write * 1st access: No wait * Continuous write: 3 or 4 Read 1 or 2 TQ0CNT Read 1 or 2 TQ0CCR0 to TQ0CCR3 Write * 1st access: No wait * Continuous write: 3 or 4 Read 1 or 2 Watchdog timer 2 (WDT2) WDTM2 Write (when WDT2 operating) 3 Real-time output function (RTO) RTBL0 Write (RTPC0.RTPOE0 bit = 0) 1 RTBH0 Write (RTPC0.RTPOE0 bit = 0) 1 ADA0M0 Read 1 or 2 ADA0CR0 to ADA0CR11 Read 1 or 2 ADA0CR0H to ADA0CR11H Read 1 or 2 IICS0 to IICS2 Read 1 A/D converter <R> Register Name TPnCNT 2 2 I C00 to I C02 94 Note 1 User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION (2/2) Peripheral Function <R> Note 2 Register Name CAN controller C0GMABT, (m = 0 to 31, a = 1 to 4) C0GMABTD, Access Read/write k (fXX/fCANMOD + 1)/(2 + j) (MIN.) Note 3 (2 x fXX/fCANMOD + 1)/(2 + j) (MAX.) Note 3 C0MASKaL, C0MASKaH, C0LEC, C0INFO, C0ERC, C0IE, C0INTS, C0BRP, C0BTR, C0TS C0GMCTRL, <R> (fXX/fCAN + 1)/(2 + j) (MIN.) Note 3 (2xfXX/fCAN + 1)/(2 + j) (MAX.) Write (fXX/fCANMOD + 1)/(2 + j) (MIN.) Note 3 (2 x fXX/fCANMOD + 1)/(2 + j) (MAX.) Read (3 x fXX/fCANMODE + 1)/(2 + j) (MIN.) Note 3 (4 x fXX/fCANMODE + 1)/(2 + j) (MAX.) C0LIPT, C0LOPT Read (3 x fXX/fCANMODE + 1)/(2 + j) (MIN.) Note 3 (4 x fXX/fCANMODE + 1)/(2 + j) (MAX.) C0MCTRLm Write (4xfXX/fCAN + 1)/(2 + j) (MIN.) Note 3 (5xfXX/fCAN + 1)/(2 + j) (MAX.) Read (3xfXX/fCAN + 1)/(2 + j) (MIN.) ote 3 (4xfXX/fCAN + 1)/(2 + j) (MAX.) Write (8 bits) (4 x fXX/fCANMODE + 1)/(2 + j) (MIN.) Note 3 (5 x fXX/fCANMODE + 1)/(2 + j) (MAX.) Write (16 bits) (2 x fXX/fCANMODE + 1)/(2 + j) (MIN.) Note 3 (3 x fXX/fCANMODE + 1)/(2 + j) (MAX.) Read (8/16 bits) (3 x fXX/fCANMODE + 1)/(2 + j) (MIN.) Note 3 (4 x fXX/fCANMODE + 1)/(2 + j) (MAX.) Write 1 C0GMCS, C0CTRL C0RGPT, C0TGPT <R> Note 3 Read/write C0MDATA01m, C0MDATA0m, C0MDATA1m, C0MDATA23m, C0MDATA2m, C0MDATA3m, C0MDATA45m, C0MDATA4m, C0MDATA5m, C0MDATA67m, C0MDATA6m, C0MDATA7m, C0MDLCm, Note 3 Note 3 Note Note 3 Note 3 Note 3 Note 3 Note 3 C0MCONFm, C0MIDLm, C0MIDHm <R> CRC CRCD Number of clocks necessary for access = 3 + i + j + (2 + j) x k Notes 1. I2C bus versions (Y products) only 2. CAN controller versions only 3. Digits below the decimal point are rounded up. Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is generated, it can only be cleared by a reset. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock User's Manual U16541EJ5V1UD 95 CHAPTER 3 CPU FUNCTION Remark fXX: Main clock frequency = fXX fCANMOD: CAN module system clock fCAN: Supply clock to CAN i: Values (0 or 1) of higher 4 bits of VSWC register j: Values (0 or 1) of lower 4 bits of VSWC register (3) System reserved area <R> In the flash memory version of the V850ES/SG2 and V850ES/SG2-H, 0000007AH to 0000007FH is a system reserved area for function expansion, and therefore it is recommended that this area not be used. However, in the case of the special version of the following products, be sure to set 00H to 0000007AH. * PD70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y: Ver. 1.0 * PD70F3263, 70F3263Y, 70F3263HY, 70F3273, 70F3273Y, 70F3273HY, 70F3283, <R> 70F3283Y, 70F3283HY: No applicable versions Remarks 1. With products other than the above (including all the products listed in this manual), operations are not affected even if 00H is set to 0000007AH. 2. Check the product version by the number that follows DS, ES, or CS on the third line of the <R> package stamp. If the generic name is stamped (V850ES/SG2, V850ES/SG2-H, etc.), the above restriction does not apply. For enquiries, contact an NEC Electronics sales representative. 00000080H 0000007FH 0000007BH 0000007AH 00000079H System reserved area System reserved area (00H) Security IDNote (10 bytes) 00000070H 00000000H Note For the security ID, see 31.6.1 Security ID. Caution 96 When the data in the flash memory has been deleted, all the bits are set to 1. User's Manual U16541EJ5V1UD CHAPTER 3 CPU FUNCTION (4) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1> * ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu * sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu * Multiplication instruction: mul, mulh, mulhi, mulu Instruction <2> mov reg1, reg2 not reg1, reg2 satsubr reg1, reg2 satsub reg1, reg2 satadd reg1, reg2 satadd imm5, reg2 or reg1, reg2 xor reg1, reg2 and reg1, reg2 tst reg1, reg2 subr reg1, reg2 sub reg1, reg2 add reg1, reg2 add imm5, reg2 cmp reg1, reg2 cmp imm5, reg2 mulh reg1, reg2 shr imm5, reg2 sar imm5, reg2 shl imm5, reg2 <Example> <i> ld.w [r11], r10 * * * If the decode operation of the mov instruction <ii> immediately before the sld instruction <iii> and an interrupt request conflict before execution of the ld instruction <i> is complete, the execution result of instruction <i> may not be stored in a register. <ii> mov r10, r28 <iii> sld.w 0x28, r10 (b) Countermeasure <1> When compiler (CA850) is used Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> For assembler When executing the sld instruction immediately after instruction <ii>, avoid the above operation using either of the following methods. * Insert a nop instruction immediately before the sld instruction. * Do not use the same register as the sld instruction destination register in the above instruction <ii> executed immediately before the sld instruction. User's Manual U16541EJ5V1UD 97 CHAPTER 4 PORT FUNCTIONS 4.1 Features { I/O ports: 84 * 5 V tolerant/N-ch open-drain output selectable: 40 (ports 0, 3 to 5, 9) { Input/output specifiable in 1-bit units 4.2 Basic Port Configuration The V850ES/SG2 and V850ES/SG2-H feature a total of 84 I/O ports consisting of ports 0, 1, 3 to 5, 7, 9, CM, CT, <R> DH, and DL. The port configuration is shown below. Figure 4-1. Port Configuration Diagram P02 P90 P06 P915 P10 PCM0 Port 0 Port 9 Port 1 P11 P30 Port 3 P39 P40 Port 4 P42 Port CM PCM3 PCT0 PCT1 PCT4 PCT6 PDH0 Port DH P50 PDH5 Port 5 P55 P70 Port 7 PDL0 Port DL PDL15 P711 Caution Ports 0, 3 to 5, and 9 are 5 V tolerant. Table 4-1. I/O Buffer Power Supplies for Pins Power Supply 98 Port CT Corresponding Pins AVREF0 Port 7 AVREF1 Port 1 BVDD Ports CM, CT, DH (bits 0 to 3), DL EVDD RESET, ports 0, 3 to 5, 9, DH (bits 4, 5) User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS 4.3 Port Configuration Table 4-2. Port Configuration Item Configuration Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CM, CT, DH, DL) Control register Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DH, DL) Port n function control register (PFCn: n = 0, 3 to 5, 9) Port n function control expansion register (PFCEn: n = 3, 5, 9) Port n function register (PFn: n = 0, 3 to 5, 9) Ports I/O: 84 (1) Port n register (Pn) Data is input from or output to an external device by writing or reading the Pn register. The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins. Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units. After reset: 00H (output latch) Pn R/W 7 6 5 7 3 2 1 0 Pn7 Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 Pnm Control of output data (in output mode) 0 Output 0. 1 Output 1. Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register. Table 4-3. Writing/Reading Pn Register Setting of PMn Register Writing to Pn Register Note Output mode Data is written to the output latch (PMnm = 0) In the port mode (PMCn = 0), the contents of the output . Reading from Pn Register The value of the output latch is read. latch are output from the pins. Input mode Data is written to the output latch. (PMnm = 1) The pin status is not affected The pin status is read. Note . Note The value written to the output latch is retained until a new value is written to the output latch. User's Manual U16541EJ5V1UD 99 CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units. After reset: FFH PMn PMn7 R/W PMn6 PMn5 PMnm PMn4 PMn3 PMn2 PMn1 PMn0 Control of input/output mode 0 Output mode 1 Input mode (3) Port n mode control register (PMCn) The PMCn register specifies the port mode or alternate function. Each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. After reset: 00H PMCn PMCn7 R/W PMCn6 PMCnm 100 PMCn5 PMCn4 PMCn3 PMCn2 Specification of operation mode 0 Port mode 1 Alternate function mode User's Manual U16541EJ5V1UD PMCn1 PMCn0 CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. After reset: 00H PFCn PFCn7 R/W PFCn6 PFCn5 PFCnm PFCn4 PFCn3 PFCn2 PFCn1 PFCn0 Specification of alternate function 0 Alternate function 1 1 Alternate function 2 (5) Port n function control expansion register (PFCEn) The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. After reset: 00H PFCEn PFCn R/W PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0 PFCn7 PFCn6 PFCn5 PFCn3 PFCn1 PFCn0 PFCEnm PFCnm 0 0 Alternate function 1 0 1 Alternate function 2 1 0 Alternate function 3 1 1 Alternate function 4 PFCn4 PFCn2 Specification of alternate function User's Manual U16541EJ5V1UD 101 CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1-bit units. After reset: 00H PFn PFn7 PFnmNote PFn6 R/W PFn5 PFn4 PFn3 PFn2 PFn1 PFn0 Control of normal output/N-ch open-drain output 0 Normal output (CMOS output) 1 N-ch open-drain output Note The PFnm bit of the PFn register is valid only when the PMnm bit of the PMn register is 0 (when the output mode is specified) in port mode (PMCnm bit = 0). When the PMnm bit is 1 (when the input mode is specified), the set value of the PFn register is invalid. 102 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode "0" Input mode "1" PMn register Alternate function (when two alternate functions are available) "0" Alternate function 1 "0" PFCn register Alternate function 2 PMCn register "1" Alternate function (when three or more alternate functions are available) "1" Alternate function 1 (a) Alternate function 2 (b) PFCn register (c) PFCEn register Alternate function 3 (d) Alternate function 4 Remark (a) (b) (c) (d) PFCEnm PFCnm 0 0 1 1 0 1 0 1 Set the alternate functions in the following sequence. <1> Set the PFCn and PFCEn registers. <2> Set the PFCn register. <3> Set the INTRn or INTFn register (to specify an external interrupt pin). If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn registers are being set. User's Manual U16541EJ5V1UD 103 CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 5-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-4. Port 0 Alternate-Function Pins Pin Name Pin No. GF Alternate-Function Pin Name I/O Remark Block Type GC P02 19 17 NMI Input P03 20 18 INTP0/ADTRG Input N-1 P04 21 19 INTP1 Input L-1 Note Selectable as N-ch open-drain output L-1 P05 22 20 INTP2/DRST Input AA-1 P06 23 21 INTP3 Input L-1 Note The DRST pin is for on-chip debugging (flash memory version only). If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level between when the reset signal of the RESET pin is released and when the OCDM.OCDM0 bit is cleared (0). Although the mask ROM versions do not support the on-chip debug mode, an on-chip pull-down resistor is incorporated. Handle the P05/INTP2 pin the same as in flash memory versions. For details, see 4.6.3 Cautions on on-chip debug pins. Caution The P02 to P06 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) (1) Port 0 register (P0) After reset: 00H (output latch) P0 0 P06 P0n 104 R/W P05 Address: FFFFF400H P04 P03 P02 0 Output data control (in output mode) (n = 2 to 6) 0 Outputs 0 1 Outputs 1 User's Manual U16541EJ5V1UD 0 CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) After reset: FFH R/W PM0 PM06 1 Address: FFFFF420H PM05 PM0n PM04 PM03 PM02 1 1 0 0 I/O mode control (n = 2 to 6) 0 Output mode 1 Input mode (3) Port 0 mode control register (PMC0) After reset: 00H PMC0 0 R/W Address: FFFFF440H PMC06 PMC05 PMC06 PMC03 PMC02 Specification of P06 pin operation mode 0 I/O port 1 INTP3 input PMC05 Specification of P05 pin operation mode 0 I/O port 1 INTP2 input PMC04 Specification of P04 pin operation mode 0 I/O port 1 INTP1 input PMC03 Specification of P03 pin operation mode 0 I/O port 1 INTP0 input/ADTRG input PMC02 Caution PMC04 Specification of P02 pin operation mode 0 I/O port 1 NMI input The P05/INTP2/DRST pin becomes the DRST pin regardless of the value of the PMC05 bit when the OCDM.OCDM0 bit = 1. User's Manual U16541EJ5V1UD 105 CHAPTER 4 PORT FUNCTIONS (4) Port 0 function control register (PFC0) After reset: 00H PFC0 0 R/W Address: FFFFF460H 0 0 PFC03 0 PFC03 0 0 0 Specification of P03 pin alternate function 0 INTP0 input 1 ADTRG input (5) Port 0 function register (PF0) After reset: 00H PF0 0 PF0n Caution <R> R/W Address: FFFFFC60H PF06 PF05 PF04 PF03 0 0 Control of normal output or N-ch open-drain output (n = 2 to 6) 0 Normal output (CMOS output) 1 N-ch open drain output To pull up an output pin at a voltage of EVDD or higher, be sure to set the corresponding PF0n bit to 1. 106 PF02 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Table 4-5. Port 1 Alternate-Function Pins Pin Name <R> Pin No. Alternate-Function Pin Name I/O Remark Block Type GF GC P10 5 3 ANO0 Output - A-2 P11 6 4 ANO1 Output - A-2 Caution When the power is turned on, the P10 and P11 pins may momentarily output an undefined level. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) (1) Port 1 register (P1) After reset: 00H (output latch) P1 0 R/W 0 0 P1n <R> Caution Address: FFFFF402H 0 0 0 P11 P10 Output data control (in output mode) (n = 0, 1) 0 Outputs 0 1 Outputs 1 Do not read/write the P1 register during D/A conversion (see 14.4.3 Cautions). (2) Port 1 mode register (PM1) After reset: FFH PM1 1 R/W Address: FFFFF422H 1 1 PM1n 1 1 1 PM11 PM10 I/O mode control (n = 0, 1) 0 Output mode 1 Input mode Cautions 1. When using P1n as the alternate function (ANOn pin output), set the PM1n bit to 1. 2. When using one of the P10 and P11 pins as an I/O port and the other as a D/A output pin, do so in an application where the port I/O level does not change during D/A output. User's Manual U16541EJ5V1UD 107 CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 is a 10-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-6. Port 3 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF GC P30 27 25 TXDA0/SOB4 P31 28 26 RXDA0/INTP7/SIB4 P32 29 27 P33 30 P34 P35 P36 Output Remark Selectable as N-ch open-drain output Block Type G-3 Input N-3 ASCKA0/SCKB4/TIP00/TOP00 I/O U-1 28 TIP01/TOP01 I/O G-1 31 29 TIP10/TOP10 I/O G-1 32 30 TIP11/TOP11 I/O G-1 Output G-3 Input G-4 33 P37 I/O 34 31 32 CTXD0 Note 1 CRXD0 /IETX0 Note 1 Note 2 /IERX0 Note 2 Note 3 I/O G-12 Note 3 I/O G-6 P38 37 35 TXDA2/SDA00 P39 38 36 RXDA2/SCL00 Notes 1. CAN controller version only 2. IEBus controller version only 3. I2C bus version (Y products) only <R> Caution The P31 to P35 and P37 to P39 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 108 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 0000H (output latch) P3 (P3H) (P3L) R/W Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 P3n Output data control (in output mode) (n = 0 to 9) 0 Outputs 0 1 Outputs 1 Remarks 1. The P3 register can be read or written in 16-bit units. However, when using the higher 8 bits of the P3 register as the P3H register and the lower 8 bits as the P3L register, P3 can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the P3H register. (2) Port 3 mode register (PM3) After reset: FFFFH PM3 (PM3H) (PM3L) R/W Address: PM3 FFFFF426H, PM3L FFFFF426H, PM3H FFFFF427H 15 14 13 12 11 10 9 8 1 1 1 1 1 1 PM39 PM38 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n I/O mode control (n = 0 to 9) 0 Output mode 1 Input mode Remarks 1. The PM3 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PM3 register as the PM3H register and the lower 8 bits as the PM3L register, PM3 can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PM3H register. User's Manual U16541EJ5V1UD 109 CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) (1/2) After reset: 0000H PMC3 (PMC3H) (PMC3L) R/W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PMC39 PMC38 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 Specification of P39 pin operation mode 0 I/O port 1 RXDA2 input/SCL00 I/O PMC38 110 Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H Specification of P38 pin operation mode 0 I/O port 1 TXDA2 output/SDA00 I/O User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (2/2) PMC37 Specification of P37 pin operation mode 0 I/O port 1 CRXD0 input/IERX0 input PMC36 Specification of P36 pin operation mode 0 I/O port 1 CTXD0 output/IETX0 output PMC35 Specification of P35 pin operation mode 0 I/O port 1 TIP11 input/TOP11 output PMC34 Specification of P34 pin operation mode 0 I/O port 1 TIP10 input/TOP10 output PMC33 Specification of P33 pin operation mode 0 I/O port 1 TIP01 input/TOP01 output PMC32 Specification of P32 pin operation mode 0 I/O port 1 ASCKA0 input/SCKB4 I/O/TIP00 input/TOP00 output PMC31 Specification of P31 pin operation mode 0 I/O port 1 RXDA0 input/SIB4 input/INTP7 input PMC30 Specification of P30 pin operation mode 0 I/O port 1 TXDA0 output/SOB4 output Remarks 1. The PMC3 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMC3 register as the PMC3H register and the lower 8 bits as the PMC3L register, PMC3 can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMC3H register. User's Manual U16541EJ5V1UD 111 CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) After reset: 0000H Address: PFC3 FFFFF466H, PFC3L FFFFF466H, PFC3L FFFFF467H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PFC39 PFC38 PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 PFC3 (PFC3H) (PFC3L) R/W Remarks 1. For details of alternate function specification, see 4.3.3 (6) Port 3 alternate function specifications. 2. The PFC3 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFC3 register as the PFC3H register and the lower 8 bits as the PFC3L register, PFC3 can be read or written in 8-bit and 1-bit units. 3. To read/write bits 8 to 15 of the PFC3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFC3H register. (5) Port 3 function control expansion register L (PFCE3L) After reset: 00H PFCE3L Remark R/W 0 Address: FFFFF706H 0 0 0 0 PFCE32 For details of alternate function specification, see 4.3.3 (6) specifications. (6) Port 3 alternate function specifications PFC39 Specification of P39 pin alternate function 0 RXDA2 input 1 SCL00 input PFC38 112 Specification of P38 pin alternate function 0 TXDA2 output 1 SDA00 I/O User's Manual U16541EJ5V1UD 0 0 Port 3 alternate function CHAPTER 4 PORT FUNCTIONS PFC37 Specification of P37 pin alternate function 0 CRXD0 input 1 IERX0 input PFC36 Specification of P36 pin alternate function 0 CTXD0 output 1 IETX0 output PFC35 Specification of P35 pin alternate function 0 TIP11 input 1 TOP11 output PFC34 Specification of P34 pin alternate function 0 TIP10 input 1 TOP10 output PFC33 Specification of P33 pin alternate function 0 TIP01 input 1 TOP01 output PFCE32 PFC32 0 0 ASCKA0 input 0 1 SCKB4 I/O 1 0 TIP00 input 1 1 TOP00 output Specification of P32 pin alternate function PFC31 Specification of P31 pin alternate function Note 0 RXDA0 input/INTP7 1 SIB4 input PFC30 input Specification of P30 pin alternate function 0 TXDA0 output 1 SOB4 output Note The INTP7 pin and RXDA0 pin are alternate-function pins. When using the pin as the RXDA0 pin, disable edge detection for the INTP7 alternate-function pin. (Clear the INTF3.INTF31 bit and the INTR3.INTR31 bit to 0.) When using the pin as the INTP7 pin, stop UARTA0 reception. (Clear the UA0CTL0.UA0RXE bit to 0.) User's Manual U16541EJ5V1UD 113 CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) After reset: 0000H PF3 (PF3H) (PF3L) R/W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PF39 PF38 PF37 PF36 PF35 PF34 PF33 PF32 PF31 PF30 PF3n <R> Caution Address: PF3 FFFFFC66H, PF3L FFFFFC66H, PF3H FFFFFC67H Control of normal output or N-ch open-drain output (n = 0 to 9) 0 Normal output (CMOS output) 1 N-ch open-drain output To pull up an output pin at a voltage of EVDD or higher, be sure to set the corresponding PF3n bit to 1. Remarks 1. The PF3 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PF3 register as the PF3H register and the lower 8 bits as the PF3L register, PF3 can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PF3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PF3H register. 114 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-7. Port 4 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF GC P40 24 22 SIB0/SDA01 P41 25 23 SOB0/SCL01 26 24 SCKB0 P42 Note I/O I/O Note Remark Block Type Selectable as N-ch open-drain output G-6 I/O G-12 I/O E-3 2 Note I C bus versions (Y products) only Caution The P40 to P42 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) (1) Port 4 register (P4) After reset: 00H (output latch) P4 0 R/W 0 0 P4n Address: FFFFF408H 0 0 P42 P41 P40 Output data control (in output mode) (n = 0 to 2) 0 Outputs 0 1 Outputs 1 (2) Port 4 mode register (PM4) After reset: FFH PM4 1 R/W Address: FFFFF428H 1 1 PM4n 1 1 PM42 PM41 PM40 I/O mode control (n = 0 to 2) 0 Output mode 1 Input mode User's Manual U16541EJ5V1UD 115 CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H PMC4 0 R/W Address: FFFFF448H 0 0 PMC42 0 0 PMC42 PMC41 PMC40 Specification of P42 pin operation mode 0 I/O port 1 SCKB0 I/O PMC41 Specification of P41 pin operation mode 0 I/O port 1 SOB0 output/SCL01 I/O PMC40 Specification of P40 pin operation mode 0 I/O port 1 SIB0 input/SDA01 I/O (4) Port 4 function control register (PFC4) After reset: 00H PFC4 0 R/W Address: FFFFF468H 0 0 PFC41 0 0 PFC41 Specification of P41 pin alternate function 0 SOB0 output 1 SCL01 I/O PFC40 116 0 Specification of P40 pin alternate function 0 SIB0 input 1 SDA01 I/O User's Manual U16541EJ5V1UD PFC40 CHAPTER 4 PORT FUNCTIONS (5) Port 4 function register (PF4) After reset: 00H PF4 0 PF4n <R> Caution R/W 0 Address: FFFFFC68H 0 0 0 PF42 PF41 PF40 Control of normal output or N-ch open-drain output (n = 0 to 2) 0 Normal output (CMOS output) 1 N-ch open-drain output To pull up an output pin at a voltage of EVDD or higher, be sure to set the corresponding PF4n bit to 1. User's Manual U16541EJ5V1UD 117 CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 is a 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-8. Port 5 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF GC P50 39 37 TIQ01/KR0/TOQ01/RTP00 P51 40 38 TIQ02/KR1/TOQ02/RTP01 P52 41 P53 42 P54 43 P55 44 39 40 41 42 TIQ03/KR2/TOQ03/RTP02/DDI I/O I/O Note Note SIB2/KR3/TIQ00/TOQ00/RTP03/DDO SOB2/KR4/RTP04/DCK Note SCKB2/KR5/RTP05/DMS Note Remark Block Type Selectable as N-ch open-drain output U-5 I/O U-5 I/O U-6 I/O U-7 I/O U-8 I/O U-9 Note The DDI, DDO, DCK, and DMS pins are for on-chip debugging (flash memory version only). If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level between when the reset signal of the RESET pin is released and when the OCDM.OCDM0 bit is cleared (0). Although the mask ROM versions do not support the on-chip debug mode, an on-chip pull-down resistor is incorporated. Handle the P05/INTP2 pin the same as the flash memory versions. For details, see 4.6.3 Cautions on on-chip debug pins. <R> Cautions 1. When the power is turned on, the P53 pin may momentarily output an undefined level. 2. The P50 to P55 pins have hysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) (1) Port 5 register (P5) After reset: 00H (output latch) P5 0 0 P5n 118 R/W P55 Address: FFFFF40AH P54 P53 P52 P51 Output data control (in output mode) (n = 0 to 5) 0 Outputs 0 1 Outputs 1 User's Manual U16541EJ5V1UD P50 CHAPTER 4 PORT FUNCTIONS (2) Port 5 mode register (PM5) After reset: FFH PM5 1 R/W Address: FFFFF42AH 1 PM55 PM5n PM54 PM53 PM52 PM51 PM50 PMC51 PMC50 I/O mode control (n = 0 to 5) 0 Output mode 1 Input mode (3) Port 5 mode control register (PMC5) After reset: 00H PMC5 0 R/W 0 PMC55 Address: FFFFF44AH PMC55 PMC54 PMC53 PMC52 Specification of P55 pin operation mode 0 I/O port 1 SCKB2 I/O/KR5 input/RTP05 output PMC54 Specification of P54 pin operation mode 0 I/O port 1 SOB2 output/KR4 input/RTP04 output PMC53 Specification of P53 pin operation mode 0 I/O port 1 SIB2 input/KR3 input/TIQ00 input/TOQ00 output/RTP03 output PMC52 Specification of P52 pin operation mode 0 I/O port 1 TIQ03 input/KR2 input/TOQ03 output/RTP02 output PMC51 Specification of P51 pin operation mode 0 I/O port 1 TIQ02 input/KR1 input/TOQ02 output/RTP01 output PMC50 Specification of P50 pin operation mode 0 I/O port 1 TIQ01 input/KR0 input/TOQ01 output/RTP00 output User's Manual U16541EJ5V1UD 119 CHAPTER 4 PORT FUNCTIONS (4) Port 5 function control register (PFC5) After reset: 00H PFC5 Remark 0 R/W 0 Address: FFFFF46AH PFC55 PFC54 PFC53 PFC52 For details of alternate function specification, see 4.3.5 (6) PFC51 PFC50 Port 5 alternate function specifications. (5) Port 5 function control expansion register (PFCE5) After reset: 00H PFCE5 Remark 0 R/W 0 Address: FFFFF70AH PFCE55 PFCE54 PFCE53 PFCE52 For details of alternate function specification, see 4.3.5 (6) PFCE51 Port 5 alternate function specifications. (6) Port 5 alternate function specifications 120 PFCE55 PFC55 0 0 SCKB2 I/O 0 1 KR5 input 1 0 Setting prohibited 1 1 RTP05 output PFCE54 PFC54 0 0 SOB2 output 0 1 KR4 input 1 0 Setting prohibited 1 1 RTP04 output PFCE53 PFC53 0 0 SIB2 input 0 1 TIQ00 input/KR3 Specification of P55 pin alternate function 1 0 TOQ00 output 1 1 RTP03 output Specification of P54 pin alternate function Specification of P53 pin alternate function Note input User's Manual U16541EJ5V1UD PFCE50 CHAPTER 4 PORT FUNCTIONS PFCE52 PFC52 Specification of P52 pin alternate function 0 0 Setting prohibited 0 1 TIQ03 input/KR2 1 0 TOQ03 input 1 1 RTP02 output PFCE51 PFC51 0 0 Setting prohibited 0 1 TIQ02 input/KR1 1 0 TOQ02 output 1 1 RTP01 output PFCE50 PFC50 0 0 Setting prohibited 0 1 TIQ01 input/KR0 1 0 TOQ01 output 1 1 RTP00 output Note input Specification of P51 pin alternate function Note input Specification of P50 pin alternate function Note input Note The KRn pin and TIQ0m pin are alternate-function pins. When using the pin as the TIQ0m pin, disable KRn pin key return detection, which is the alternate function. (Clear the KRM.KRMn bit to 0.) Also, when using the pin as the KRn pin, disable TIQ0m pin edge detection, which is the alternate function (n = 0 to 3, m = 0 to 3). Pin Name Use as TIQ0m Pin Use as KRn Pin KR0/TIQ01 KRM.KRM0 bit = 0 TQ0IOC1. TQ0TIG2, TQ0IOC1. TQ0TIG3 bits = 0 KR1/TIQ02 KRM.KRM1 bit = 0 TQ0IOC1.TQ0TIG4, TQ0IOC1.TQ0TIG5 bits = 0 KR2/TIQ03 KRM.KRM2 bit = 0 TQ0IOC1.TQ0TIG6, TQ0IOC1.TQ0TIG7 bits = 0 KR3/TIQ00 KRM.KRM3 bit = 0 TQ0IOC1.TQ0TIG0, TQ0IOC1.TQ0TIG1 bits = 0 TQ0IOC2.TQ0EES0, TQ0IOC2.TQ0EES1 bits = 0 TQ0IOC2.TQ0ETS0, TQ0IOC2.TQ0ETS1 bits = 0 (7) Port 5 function register (PF5) After reset: 00H PF5 0 PF5n <R> Caution R/W 0 Address: FFFFFC6AH PF55 PF54 PF53 PF52 PF51 PF50 Control of normal output or N-ch open-drain output (n = 0 to 5) 0 Normal output (CMOS output) 1 N-ch open-drain output To pull up an output pin at a voltage of EVDD or higher, be sure to set the corresponding PF5n bit to 1. User's Manual U16541EJ5V1UD 121 CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 7 Port 7 is a 12-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-9. Port 7 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name I/O Remark - Block Type GF GC P70 2 100 ANI0 Input P71 1 99 ANI1 Input A-1 P72 100 98 ANI2 Input A-1 P73 99 97 ANI3 Input A-1 P74 98 96 ANI4 Input A-1 P77 97 95 ANI5 Input A-1 P76 96 94 ANI6 Input A-1 P77 95 93 ANI7 Input A-1 P78 94 92 ANI8 Input A-1 P79 93 91 ANI9 Input A-1 P710 92 90 ANI10 Input A-1 P711 91 89 ANI11 Input A-1 Remark A-1 GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) (1) Port 7 register H, port 7 register L (P7H, P7L) <R> After reset: 00H (output latch) Caution Address: P7L FFFFF40EH, P7H FFFFF40FH P7H 0 0 0 0 P711 P710 P79 P78 P7L P77 P76 P75 P74 P73 P72 P71 P70 P7n <R> R/W Output data control (in output mode) (n = 0 to 11) 0 Outputs 0 1 Outputs 1 Do not read/write the P7H and P7L registers during A/D conversion (see 13.6 (4) Alternate I/O). Remark These registers cannot be accessed in 16-bit units as the P7 register. They can be read or written in 8-bit or 1-bit units as the P7H and P7L registers. 122 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (2) Port 7 mode register H, port 7 mode register L (PM7H, PM7L) After reset: FFH R/W Address: PM7L FFFFF42EH, PM7H FFFFF42FH PM7H 1 1 1 1 PM711 PM710 PM79 PM78 PM7L PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 PM7n I/O mode control (n = 0 to 11) 0 Output mode 1 Input mode Caution When using the P7n pin as its alternate function (ANIn pin), set the PM7n bit to 1. Remark These registers cannot be accessed in 16-bit units as the PM7 register. They can be read or written in 8-bit or 1-bit units as the PM7H and PM7L registers. User's Manual U16541EJ5V1UD 123 CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-10. Port 9 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name GF GC P90 45 43 A0/KR6/TXDA1/SDA02 P91 46 44 A1/KR7/RXDA1/SCL02 P92 47 45 P93 48 P94 Note Note I/O I/O Remark Selectable as N-ch open-drain output Block Type U-10 I/O U-11 A2/TIP41/TOP41 I/O U-12 46 A3/TIP40/TOP40 I/O U-12 49 47 A4/TIP31/TOP31 I/O U-12 P95 50 48 A5/TIP30/TOP30 I/O U-12 P96 51 49 A6/TIP21/TOP21 I/O U-13 P97 52 50 A7/SIB1/TIP20/TOP20 I/O U-14 P98 53 51 A8/SOB1 Output G-3 P99 54 52 A9/SCKB1 I/O G-5 P910 55 53 A10/SIB3 I/O G-2 P911 56 54 A11/SOB3 Output G-3 P912 57 55 A12/SCKB3 I/O G-5 P913 58 56 A13/INTP4 I/O N-2 P914 59 57 A14/INTP5/TIP51/TOP51 I/O U-15 P915 60 58 A15/INTP6/TIP50/TOP50 I/O U-15 Note I2C bus versions (Y products) only <R> Caution The P90 to P97, P99, P910, and P912 to P915 pins have hysteresis characteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 124 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 0000H (output latch) R/W Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H 15 14 13 12 11 10 9 8 P9 (P9H) P915 P914 P913 P912 P911 P910 P99 P98 (P9L) P97 P96 P95 P94 P93 P92 P91 P90 P9n Output data control (in output mode) (n = 0 to 15) 0 Outputs 0 1 Outputs 1 Remarks 1. The P9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the P9 register as the P9H register and the lower 8 bits as the P9L register, P9 can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the P9H register. (2) Port 9 mode register (PM9) After reset: FFFFH PM9 (PM9H) (PM9L) R/W Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H 15 14 13 12 11 10 9 8 PM915 PM914 PM913 PM912 PM911 PM910 PM99 PM98 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PM9n I/O mode control (n = 0 to 15) 0 Output mode 1 Input mode Remarks 1. The PM9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PM9 register as the PM9H register and the lower 8 bits as the PM9L register, PM9 can be read or written in 8-bit and 1-bit units. 2. To read/write bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PM9H register. User's Manual U16541EJ5V1UD 125 CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) (1/2) After reset: 0000H 15 PMC9 (PMC9H) (PMC9L) R/W 14 Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H 9 8 PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 13 PMC99 PMC98 PMC97 PMC91 PMC90 PMC96 PMC915 12 PMC95 PMC94 11 PMC93 10 PMC92 Specification of P915 pin operation mode 0 I/O port 1 A15 output/INTP6 input/TIP50 input/TOP50 output PMC914 Specification of P914 pin operation mode 0 I/O port 1 A14 output/INTP5 input/TIP51 input/TOP51 output PMC913 Specification of P913 pin operation mode 0 I/O port 1 A13 output/INTP4 input PMC912 Specification of P912 pin operation mode 0 I/O port 1 A12 output/SCKB3 I/O PMC911 Specification of P911 pin operation mode 0 I/O port 1 A11 output/SOB3 output PMC910 Specification of P910 pin operation mode 0 I/O port 1 A10 output/SIB3 input PMC99 Specification of P99 pin operation mode 0 I/O port 1 A9 output/SCKB1 I/O Remarks 1. The PMC9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMC9 register as the PMC9H register and the lower 8 bits as the PMC9L register, PMC9 can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMC9H register. 126 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (2/2) PMC98 Specification of P98 pin operation mode 0 I/O port 1 A8 output/SOB1 output PMC97 Specification of P97 pin operation mode 0 I/O port 1 A7 output/SIB1 input/TIP20 input/TOP20 output PMC96 Specification of P96 pin operation mode 0 I/O port 1 A6 output/TIP21 input/TOP21 output PMC95 Specification of P95 pin operation mode 0 I/O port 1 A5 output/TIP30 input/TOP30 output PMC94 Specification of P94 pin operation mode 0 I/O port 1 A4 output/TIP31 input/TOP31 output PMC93 Specification of P93 pin operation mode 0 I/O port 1 A3 output/TIP40 input/TOP40 output PMC92 Specification of P92 pin operation mode 0 I/O port 1 A2 output/TIP41 input/TOP41 output PMC91 Specification of P91 pin operation mode 0 I/O port 1 A1 output/KR7 input/RXDA1 input/SCL02 I/O PMC90 <R> Caution Specification of P90 pin operation mode 0 I/O port 1 A0 output/KR6 input/TXDA1 output/SDA02 I/O Port 9 pins cannot be used as port pins or other alternate-function pins if even one of the A0 to A15 pins is used in the separate bus mode. After setting the PFC9 and PFCE9 registers to 0000H, therefore, set all 16 bits of the PMC9 register to FFFFH at once. If even one of the A0 to A15 pins is not used in the separate bus mode, port 9 pins can be used as port pins or other alternate-function pins. User's Manual U16541EJ5V1UD 127 CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) Caution <R> Port 9 pins cannot be used as port pins or other alternate-function pins if even one of the A0 to A15 pins is used in the separate bus mode. After setting the PFC9 and PFCE9 registers to 0000H, therefore, set all 16 bits of the PMC9 register to FFFFH at once. If even one of the A0 to A15 pins is not used in the separate bus mode, port 9 pins can be used as port pins or other alternate-function pins. After reset: 0000H PFC9 (PFC9H) (PFC9L) R/W Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H 15 14 9 8 PFC915 PFC914 PFC913 PFC912 13 12 PFC911 PFC910 PFC99 PFC98 PFC97 PFC96 PFC95 PFC93 PFC91 PFC90 PFC94 11 10 PFC92 Remarks 1. For details of alternate function specification, see 4.3.7 (6) Port 9 alternate function specifications. 2. The PFC9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFC9 register as the PFC9H register and the lower 8 bits as the PFC9L register, PFC9 can be read or written in 8-bit or 1-bit units. 3. To read/write bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFC9H register. (5) Port 9 function control expansion register (PFCE9) After reset: 0000H 15 PFCE9 (PFCE9H) (PFCE9L) R/W 14 PFCE915 PFCE914 PFCE97 PFCE96 Address: PFCE9 FFFFF712H, PFCE9L FFFFF712H, PFCE9H FFFFF713H 13 12 11 10 9 8 0 0 0 0 0 0 PFCE91 PFCE90 PFCE95 PFCE94 PFCE93 PFCE92 Remarks 1. For details of alternate function specification, see 4.3.7 (6) Port 9 alternate function specifications. 2. The PFCE9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PFCE9 register as the PFCE9H register and the lower 8 bits as the PFCE9L register, PFCE9 can be read or written in 8-bit or 1-bit units. 3. To read/write bits 8 to 15 of the PFCE9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PFCE9H register. 128 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (6) Port 9 alternate function specifications PFCE915 PFC915 0 0 A15 output 0 1 INTP6 input 1 0 TIP50 input 1 1 TOP50 output PFCE914 PFC914 0 0 A14 output 0 1 INTP5 input 1 0 TIP51 input 1 1 TOP51 output PFC913 Specification of P915 pin alternate function Specification of P914 pin alternate function Specification of P913 pin alternate function 0 A13 output 1 INTP4 input PFC912 Specification of P912 pin alternate function 0 A12 output 1 SCKB3 I/O PFC911 Specification of P911 pin alternate function 0 A11 output 1 SOB3 output PFC910 Specification of P910 pin alternate function 0 A10 output 1 SIB3 input PFC99 Specification of P99 pin alternate function 0 A9 output 1 SCKB1 I/O PFC98 Specification of P98 pin alternate function 0 A8 output 1 SOB1 output PFCE97 PFC97 0 0 Specification of P97 pin alternate function A7 output 0 1 SIB1 input 1 0 TIP20 input 1 1 TOP20 output User's Manual U16541EJ5V1UD 129 CHAPTER 4 PORT FUNCTIONS PFCE96 PFC96 0 0 Specification of P96 pin alternate function A6 output 0 1 Setting prohibited 1 0 TIP21 input 1 1 TOP21 output PFCE95 PFC95 0 0 A5 output 0 1 TIP30 input 1 0 TOP30 output 1 1 Setting prohibited PFCE94 PFC94 0 0 A4 output 0 1 TIP31 input 1 0 TOP31 output 1 1 Setting prohibited PFCE93 PFC93 0 0 A3 output 0 1 TIP40 input 1 0 TOP40 output 1 1 Setting prohibited PFCE92 PFC92 0 0 A2 output 0 1 TIP41 input 1 0 TOP41 output 1 1 Setting prohibited PFCE91 PFC91 0 0 A1 output 0 1 KR7 input 1 0 RXDA1 input/KR7 input 1 1 SCL02 I/O PFCE90 PFC90 0 0 A0 output 0 1 KR6 input 1 0 TXDA1 output 1 1 SDA02 I/O Specification of P95 pin alternate function Specification of P94 pin alternate function Specification of P93 pin alternate function Specification of P92 pin alternate function Specification of P91 pin alternate function Note Specification of P90 pin alternate function Note The RXDA1 and KR7 pins must not be used at the same time. When using the RXDA1 pin, do not use the KR7 pin. When using the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear the PFCE91 bit to 0). 130 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (7) Port 9 function register (PF9) After reset: 0000H PF9 (PF9H) (PF9L) Caution Address: PF3 FFFFFC72H, PF9L FFFFFC72H, PF9H FFFFFC73H 15 14 13 12 11 10 9 8 PF915 PF914 PF913 PF912 PF911 PF910 PF99 PF98 PF97 PF96 PF95 PF94 PF93 PF92 PF91 PF90 PF9n <R> R/W Control of normal output or N-ch open-drain output (n = 0 to 15) 0 Normal output (CMOS output) 1 N-ch open-drain output To pull up an output pin at a voltage of EVDD or higher, be sure to set the corresponding PF9n bit to 1. Remarks 1. The PF9 register can be read or written in 16-bit units. However, when using the higher 8 bits of the PF9 register as the PF9H register and the lower 8 bits as the PF9L register, PF9 can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PF9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PF9H register. User's Manual U16541EJ5V1UD 131 CHAPTER 4 PORT FUNCTIONS 4.3.8 Port CM Port CM is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-11. Port CM Alternate-Function Pins Pin Name Pin No. GF Alternate-Function Pin Name I/O Remark Input - Block Type GC PCM0 63 61 WAIT PCM1 64 62 CLKOUT Output D-2 PCM2 65 63 HLDAK Output D-2 PCM3 66 64 HLDRQ Input D-1 Remark D-1 GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) (1) Port CM register (PCM) After reset: 00H (output latch) R/W PCM 0 0 0 PCMn Address: FFFFF00CH 0 PCM3 PCM2 PCM1 PCM0 Output data control (in output mode) (n = 0 to 3) 0 Outputs 0 1 Outputs 1 (2) Port CM mode register (PMCM) After reset: FFH PMCM 1 R/W Address: FFFFF02CH 1 1 PMCMn 132 1 PMCM3 PMCM2 I/O mode control (n = 0 to 3) 0 Output mode 1 Input mode User's Manual U16541EJ5V1UD PMCM1 PMCM0 CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) After reset: 00H PMCCM 0 R/W Address: FFFFF04CH 0 0 PMCCM3 0 PMCCM3 PMCCM2 PMCCM1 PMCCM0 Specification of PCM3 pin operation mode 0 I/O port 1 HLDRQ input PMCCM2 Specification of PCM2 pin operation mode 0 I/O port 1 HLDAK output PMCCM1 Specification of PCM1 pin operation mode 0 I/O port 1 CLKOUT output PMCCM0 Specification of PCM0 pin operation mode 0 I/O port 1 WAIT input User's Manual U16541EJ5V1UD 133 CHAPTER 4 PORT FUNCTIONS 4.3.9 Port CT Port CT is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-12. Port CT Alternate-Function Pins Pin Name Pin No. GF Alternate-Function Pin Name I/O Remark - Block Type GC PCT0 67 65 WR0 Output PCT1 68 66 WR1 Output D-2 PCT4 69 67 RD Output D-2 PCT6 70 68 ASTB Output D-2 Remark D-2 GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) (1) Port CT register (PCT) After reset: 00H (output latch) PCT 0 PCT6 PCTn R/W Address: FFFFF00AH 0 PCT4 0 0 PCT1 PCT0 Output data control (in output mode) (n = 0, 1, 4, 6) 0 Outputs 0 1 Outputs 1 (2) Port CT mode register (PMCT) After reset: FFH PMCT 1 R/W Address: FFFFF02AH PMCT6 1 PMCTn 134 PMCT4 1 1 I/O mode control (n = 0, 1, 4, 6) 0 Output mode 1 Input mode User's Manual U16541EJ5V1UD PMCT1 PMCT0 CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) After reset: 00H PMCCT 0 R/W Address: FFFFF04AH PMCCT6 0 PMCCT6 PMCCT4 0 0 PMCCT1 PMCCT0 Specification of PCT6 pin operation mode 0 I/O port 1 ASTB output PMCCT4 Specification of PCT4 pin operation mode 0 I/O port 1 RD output PMCCT1 Specification of PCT1 pin operation mode 0 I/O port 1 WR1 output PMCCT0 Specification of PCT0 pin operation mode 0 I/O port 1 WR0 output User's Manual U16541EJ5V1UD 135 CHAPTER 4 PORT FUNCTIONS 4.3.10 Port DH Port DH is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-13. Port DH Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name I/O Remark - Block Type GF GC PDH0 89 87 A16 Output PDH1 90 88 A17 Output D-2 PDH2 61 59 A18 Output D-2 PDH3 62 60 A19 Output D-2 PDH4 8 6 A20 Output D-2 PDH5 9 7 A21 Output D-2 Remark D-2 GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) (1) Port DH register (PDH) After reset: 00H (output latch) PDH 0 R/W 0 PDH5 PDHn Address: FFFFF006H PDH4 PDH3 PDH2 PDH1 PDH0 Output data control (in output mode) (n = 0 to 5) 0 Outputs 0 1 Outputs 1 (2) Port DH mode register (PMDH) After reset: FFH PMDH 1 R/W Address: FFFFF026H 1 PMDH5 PMDHn 136 PMDH4 PMDH3 PMDH2 I/O mode control (n = 0 to 5) 0 Output mode 1 Input mode User's Manual U16541EJ5V1UD PMDH1 PMDH0 CHAPTER 4 PORT FUNCTIONS (3) Port DH mode control register (PMCDH) After reset: 00H PMCDH 0 R/W 0 PMCDHn Address: FFFFF046H PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 Specification of PDHn pin operation mode (n = 0 to 5) 0 I/O port 1 Am output (address bus output) (m = 16 to 21) User's Manual U16541EJ5V1UD 137 CHAPTER 4 PORT FUNCTIONS 4.3.11 Port DL Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-14. Port DL Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name I/O Remark - Block Type GF GC PDL0 73 71 AD0 I/O PDL1 74 72 AD1 I/O D-3 PDL2 75 73 AD2 I/O D-3 PDL3 76 74 AD3 I/O D-3 PDL4 77 75 AD4 I/O D-3 I/O D-3 Note D-3 PDL5 78 76 AD5/FLMD1 PDL6 79 77 AD6 I/O D-3 PDL7 80 78 AD7 I/O D-3 PDL8 81 79 AD8 I/O D-3 PDL9 82 80 AD9 I/O D-3 PDL10 83 81 AD10 I/O D-3 PDL11 84 82 AD11 I/O D-3 PDL12 85 83 AD12 I/O D-3 PDL13 86 84 AD13 I/O D-3 PDL14 87 85 AD14 I/O D-3 PDL15 88 86 AD15 I/O D-3 Note Since this pin is set in the flash memory programming mode, it does not need to be manipulated with the port control register. For details, see CHAPTER 30 FLASH MEMORY. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 138 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 0000H (output latch) R/W Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H 15 14 13 12 11 10 9 8 PDL (PDLH) PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn Output data control (in output mode) (n = 0 to 15) 0 Outputs 0 1 Outputs 1 Remarks 1. The PDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PDL register as the PDLH register and the lower 8 bits as the PDLL register, PDL can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PDLH register. (2) Port DL mode register (PMDL) After reset: FFFFH 15 PMDL (PMDLH) (PMDLL) R/W Address: PMDL FFFFF024H, PMDLL FFFFF024H, PMDLH FFFFF025H 9 8 PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10 14 13 PMDL9 PMDL8 PMDL7 PMDL1 PMDL0 PMDL6 PMDL5 PMDLn 12 PMDL4 11 PMDL3 10 PMDL2 I/O mode control (n = 0 to 15) 0 Output mode 1 Input mode Remarks 1. The PMDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register, PMDL can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMDLH register. User's Manual U16541EJ5V1UD 139 CHAPTER 4 PORT FUNCTIONS (3) Port DL mode control register (PMCDL) After reset: 0000H 15 R/W Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H 14 13 12 11 10 9 8 PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn Caution Specification of PDLn pin operation mode (n = 0 to 15) 0 I/O port 1 ADn I/O (address/data bus I/O) When the SMSEL bit of the EXIMC register = 1 (separate mode) and the BS30 to BS00 bits of the BSC register = 0 (8-bit bus width), do not specify the AD8 to AD15 pins. Remarks 1. The PMCDL register can be read or written in 16-bit units. However, when using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCDLL register, PMCDL can be read or written in 8-bit or 1-bit units. 2. To read/write bits 8 to 15 of the PMCDL register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the PMCDLH register. 140 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Block Diagrams Figure 4-3. Block Diagram of Type A-1 WRPM PMmn WRPORT Pmn Selector Pmn Selector Internal bus 4.4 Address P-ch RD A/D input signal N-ch User's Manual U16541EJ5V1UD 141 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type A-2 WRPM PMmn WRPORT Selector Pmn Selector Internal bus Pmn Address P-ch RD D/A output signal N-ch 142 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type D-1 WRPMC PMCmn WRPM WRPORT Pmn Selector Pmn Selector Internal bus PMmn Address RD Input signal when alternate function is used User's Manual U16541EJ5V1UD 143 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type D-2 WRPMC PMCmn WRPM PMmn Internal bus <R> Selector Output signal when alternate function is used WRPORT Selector Selector Pmn Address RD 144 User's Manual U16541EJ5V1UD Pmn CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D-3 WRPMC PMCmn Output enable signal of address/data bus Output buffer off signal Selector WRPM Internal bus PMmn Selector Output signal when alternate function is used WRPORT Pmn Selector Selector Pmn Address Input enable signal of address/data bus Input signal when alternate function is used RD User's Manual U16541EJ5V1UD 145 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type E-3 WRPF PFmn Output enable signal when alternate function is used WRPMC PMCmn PMmn EVDD Output signal when alternate function is used Selector Internal bus WRPM WRPORT P-ch Pmn Pmn N-ch Selector Selector EVSS Address <R> RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. 146 User's Manual U16541EJ5V1UD Note CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type G-1 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector WRPORT EVDD Output signal when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address <R> RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 147 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type G-2 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector WRPORT EVDD Output signal when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Address <R> RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. 148 User's Manual U16541EJ5V1UD Note CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type G-3 WRPF PFmn WRPFC PFCmn WRPMC WRPM PMmn WRPORT Selector Output signal 1 when alternate function is used Output signal 2 when alternate function is used EVDD Selector Internal bus PMCmn P-ch Pmn Pmn N-ch <R> Selector Selector EVSS <R> Address RD User's Manual U16541EJ5V1UD 149 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type G-4 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD WRPORT P-ch Pmn Pmn Selector N-ch Selector EVSS Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Selector RD Note Hysteresis characteristics are not available in port mode. 150 User's Manual U16541EJ5V1UD Note CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type G-5 WRPF PFmn Output enable signal when alternate function is used WRPFC PFCmn WRPMC WRPM PMmn Selector Output signal 1 when alternate function is used Output signal 2 when alternate function is used WRPORT EVDD Selector Internal bus PMCmn P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address <R> RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 151 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type G-6 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD Selector Output signal when alternate function is used WRPORT P-ch Pmn Pmn Selector N-ch Selector EVSS Address <R> Input signal 1 when alternate function is used Input signal 2 when alternate function is used Selector RD Note Hysteresis characteristics are not available in port mode. 152 User's Manual U16541EJ5V1UD Note CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type G-12 WRPF PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector Output signal 1 when alternate function is used EVDD Selector Output signal 2 when alternate function is used WRPORT P-ch Pmn Pmn Selector N-ch Selector Address EVSS Note <R> RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 153 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type L-1 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPMC Internal bus PMCmn WRPM PMmn EVDD WRPORT Pmn P-ch Pmn Selector N-ch Selector EVSS Note 2 Address RD Input signal 1 when alternate function is used Edge detection Noise elimination Notes 1. See 22.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2. Hysteresis characteristics are not available in port mode. 154 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type N-1 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC Internal bus PFCmn WRPMC PMCmn WRPM PMmn EVDD WRPORT Pmn P-ch Pmn Selector N-ch Selector EVSS Note 2 Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Edge detection Noise elimination Selector RD Notes 1. See 22.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2. Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 155 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type N-2 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC Internal bus PFCmn WRPMC PMCmn WRPM PMmn Output signal when alternate function is used EVDD Selector WRPORT Pmn P-ch Pmn Selector N-ch Selector EVSS Note 2 Address <R> RD Input signal when alternate function is used Edge detection Noise elimination Notes 1. See 22.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2. Hysteresis characteristics are not available in port mode. 156 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type N-3 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn EVDD WRPORT P-ch Pmn Pmn Selector N-ch Selector EVSS Note 2 Address Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used Edge detection Noise elimination Selector RD Input signal 2 when alternate function is used Notes 1. See 22.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2. Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 157 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type U-1 WRPF PFmn Output enable signal when alternate function is used WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Selector Output signal 1 when alternate function is used EVDD Selector Output signal 2 when alternate function is used WRPORT P-ch Pmn Pmn Selector N-ch Selector EVSS Address <R> Input signal 1 when alternate function is used Input signal 2 when alternate function is used Input signal 3 when alternate function is used Selector RD Note Hysteresis characteristics are not available in port mode. 158 User's Manual U16541EJ5V1UD Note CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of Type U-5 WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Output signal 2 when alternate function is used WRPORT EVDD Selector Selector Output signal 1 when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address <R> RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used Noise elimination Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 159 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of Type U-6 WRPF PFmn WROCDM0 OCDM0 WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Output signal 2 when alternate function is used WRPORT EVDD Selector Selector Output signal 1 when alternate function is used P-ch Pmn Pmn N-ch <R> Selector Selector EVSS Note Address RD Input signal 1-1 when alternate function is used Input signal 1-2 when alternate function is used Noise elimination Input signal when on-chip debugging Note Hysteresis characteristics are not available in port mode. 160 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of Type U-7 WRPF PFmn WROCDM0 OCDM0 WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM Selector Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal when on-chip debugging EVDD Selector WRPORT Selector PMmn P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address <R> RD Selector Input signal 1 when alternate function is used Input signal 2-1 when alternate function is used Input signal 2-2 when alternate function is used Noise elimination Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 161 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of Type U-8 WRPF PFmn WROCDM0 OCDM0 WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Output signal 2 when alternate function is used WRPORT EVDD Selector Selector Output signal 1 when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address <R> RD Input signal when alternate function is used Noise elimination Input signal when on-chip debugging Note Hysteresis characteristics are not available in port mode. 162 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of Type U-9 WRPF PFmn WROCDM0 OCDM0 Output enable signal when alternate function is used WRPFCE PFCEmn WRPFC Internal bus PFCmn WRPMC PMCmn WRPM PMmn Selector Output signal 1 when alternate function is used EVDD Selector Output signal 2 when alternate function is used WRPORT P-ch Pmn Pmn EVSS Selector Selector N-ch Note Address RD Input signal 1 when alternate function is used Input signal 2 when alternate function is used Noise elimination Selector <R> Input signal when on-chip debugging Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 163 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of Type U-10 WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector Output signal 1 when alternate function is used Output signal 2 when alternate function is used EVDD Selector Output signal 3 when alternate function is used WRPORT P-ch Pmn Pmn Selector N-ch Selector EVSS Address Note <R> Input signal 1 when alternate function is used Input signal 2 when alternate function is used Noise elimination Selector RD Note Hysteresis characteristics are not available in port mode. 164 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of Type U-11 WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn Selector Output signal 1 when alternate function is used EVDD Selector Output signal 2 when alternate function is used WRPORT P-ch Pmn Pmn Selector N-ch Selector EVSS Address Note <R> RD Input signal 2 when alternate function is used Noise elimination Selector Input signal 1 when alternate function is used Input signal 3 when alternate function is used Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 165 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of Type U-12 WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Output signal 2 when alternate function is used WRPORT EVDD Selector Selector Output signal 1 when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Address <R> RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. 166 User's Manual U16541EJ5V1UD Note CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of Type U-13 WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Output signal 2 when alternate function is used WRPORT EVDD Selector Selector Output signal 1 when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note Address <R> RD Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 167 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of Type U-14 WRPF PFmn WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Selector Output signal 1 when alternate function is used EVDD Selector Output signal 2 when alternate function is used WRPORT P-ch Pmn Pmn EVSS Selector Selector N-ch Note Address <R> Input signal 1 when alternate function is used Input signal 2 when alternate function is used Selector RD Note Hysteresis characteristics are not available in port mode. 168 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of Type U-15 WRPF PFmn WRINTR INTRmnNote 1 WRINTF INTFmnNote 1 WRPFCE PFCEmn WRPFC PFCmn Internal bus WRPMC PMCmn WRPM PMmn Output signal 2 when alternate function is used WRPORT EVDD Selector Selector Output signal 1 when alternate function is used P-ch Pmn Pmn N-ch Selector Selector EVSS Note 2 Address <R> Input signal 1 when alternate function is used Input signal 2 when alternate function is used Edge detection Noise elimination Selector RD Notes 1. See 22.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2. Hysteresis characteristics are not available in port mode. User's Manual U16541EJ5V1UD 169 CHAPTER 4 PORT FUNCTIONS Figure 4-32. Block Diagram of Type AA-1 WRPF PFmn WROCDM0 External reset signal OCDM0 WRINTR INTRmnNote 1 Internal bus WRINTF INTFmnNote 1 WRPMC PMCmn WRPM PMmn EVDD WRPORT Pmn P-ch Pmn Selector Selector N-ch EVSS Note 2 Address <R> RD N-ch Input signal when on-chip debugging Input signal when alternate function is used Edge detection Noise elimination EVSS Notes 1. See 22.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7). 2. Hysteresis characteristics are not available in port mode. 170 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS 4.5 Port Register Settings When Alternate Function Is Used Table 4-15 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin. User's Manual U16541EJ5V1UD 171 172 Table 4-15. Using Port Pin as Alternate-Function Pin (1/7) Pin Name Alternate Function Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register NMI Input P02 = Setting not required PM02 = Setting not required PMC02 = 1 - - INTP0 Input P03 = Setting not required PM03 = Setting not required PMC03 = 1 - PFC03 = 0 ADTRG Input P03 = Setting not required PM03 = Setting not required PMC03 = 1 - PFC03 = 1 P04 INTP1 Input P04 = Setting not required PM04 = Setting not required PMC04 = 1 - - P05 INTP2 Input P05 = Setting not required PM05 = Setting not required PMC05 = 1 - - DRSTNote 1 Input P05 = Setting not required PM05 = Setting not required PMC05 = Setting not required - - P02 P03 INTP3 Input P06 = Setting not required PM06 = Setting not required PMC06 = 1 - P10 ANO0 Output P10 = Setting not required PM10 = 1 - - - - User's Manual U16541EJ5V1UD P11 ANO1 Output P11 = Setting not required PM11 = 1 - - P30 TXDA0 Output P30 = Setting not required PM30 = Setting not required PMC30 = 1 - PFC30 = 0 SOB4 Output P30 = Setting not required PM30 = Setting not required PMC30 = 1 - PFC30 = 1 RXDA0 Input P31 = Setting not required PM31 = Setting not required PMC31 = 1 - Note 2, PFC31 = 0 INTP7 Input P31 = Setting not required PM31 = Setting not required PMC31 = 1 - Note 2, PFC31 = 0 SIB4 Input P31 = Setting not required PM31 = Setting not required PMC31 = 1 - PFC31 = 1 ASCKA0 Input P32 = Setting not required PM32 = Setting not required PMC32 = 1 PFCE32 = 0 PFC32 = 0 SCKB4 I/O P32 = Setting not required PM32 = Setting not required PMC32 = 1 PFCE32 = 0 PFC32 = 1 TIP00 Input P32 = Setting not required PM32 = Setting not required PMC32 = 1 PFCE32 = 1 PFC32 = 0 TOP00 Output P32 = Setting not required PM32 = Setting not required PMC32 = 1 PFCE32 = 1 PFC32 = 1 TIP01 Input P33 = Setting not required PM33 = Setting not required PMC33 = 1 - PFC33 = 0 TOP01 Output P33 = Setting not required PM33 = Setting not required PMC33 = 1 - PFC33 = 1 TIP10 Input P34 = Setting not required PM34 = Setting not required PMC34 = 1 - PFC34 = 0 TOP10 Output P34 = Setting not required PM34 = Setting not required PMC34 = 1 - PFC34 = 1 TIP11 Input P35 = Setting not required PM35 = Setting not required PMC35 = 1 - PFC35 = 0 TOP11 Output P35 = Setting not required PM35 = Setting not required PMC35 = 1 - PFC35 = 1 P31 P32 P33 P34 P35 OCDM0 (OCDM) = 1 Notes 1. Flash memory versions only 2. The INTP7 pin and RXDA0 pin are alternate-function pins. When using the pin as the RXDA0 pin, disable edge detection for the alternate-function INTP7 pin (clear the INTF3.INTF31 bit and INTR3.INTR31 bit to 0). When using the pin as the INTP7 pin, stop the UARTA0 reception operation (clear the UA0CTL0.UA0RXE bit to 0). Caution When using one of the P10 and P11 pins as an I/O port and the other as a D/A output pin (ANO0, ANO1), do so in an application where the port I/O level does not change during D/A output. CHAPTER 4 PORT FUNCTIONS P06 - Other Bits (Registers) Table 4-15. Using Port Pin as Alternate-Function Pin (2/7) Pin Name Alternate Function Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register Other Bits (Registers) PFCnx Bit of PFCn Register Output P36 = Setting not required PM36 = Setting not required PMC36 = 1 - PFC36 = 0 Output P36 = Setting not required PM36 = Setting not required PMC36 = 1 - PFC36 = 1 Input P37 = Setting not required PM37 = Setting not required PMC37 = 1 - PFC37 = 0 Input P37 = Setting not required PM37 = Setting not required PMC37 = 1 - PFC37 = 1 Output P38 = Setting not required PM38 = Setting not required PMC38 = 1 - PFC38 = 0 I/O P38 = Setting not required PM38 = Setting not required PMC38 = 1 - PFC38 = 1 RXDA2 Input P39 = Setting not required PM39 = Setting not required PMC39 = 1 - PFC39 = 0 SCL00Note 3 I/O P39 = Setting not required PM39 = Setting not required PMC39 = 1 - PFC39 = 1 SIB0 Input P40 = Setting not required PM40 = Setting not required PMC40 = 1 - PFC40 = 0 SDA01Note 3 I/O P40 = Setting not required PM40 = Setting not required PMC40 = 1 - PFC40 = 1 SOB0 Output P41 = Setting not required PM41 = Setting not required PMC41 = 1 - PFC41 = 0 SCL01Note 3 I/O P41 = Setting not required PM41 = Setting not required PMC41 = 1 - PFC41 = 1 P42 SCKB0 I/O P42 = Setting not required PM42 = Setting not required PMC42 = 1 P50 TIQ01 Input P50 = Setting not required PM50 = Setting not required PMC50 = 1 PFCE50 = 0 PFC50 = 1 KRM0 (KRM) = 0 KR0 Input P50 = Setting not required PM50 = Setting not required PMC50 = 1 PFCE50 = 0 PFC50 = 1 TQ0TIG2, TQ0TIG3 (TQ0IOC1) = 0 TOQ01 Output P50 = Setting not required PM50 = Setting not required PMC50 = 1 PFCE50 = 1 PFC50 = 0 RTP00 Output P50 = Setting not required PM50 = Setting not required PMC50 = 1 PFCE50 = 1 PFC50 = 1 TIQ02 Input P51 = Setting not required PM51 = Setting not required PMC51 = 1 PFCE51 = 0 PFC51 = 1 KRM1 (KRM) = 0 KR1 Input P51 = Setting not required PM51 = Setting not required PMC51 = 1 PFCE51 = 0 PFC51 = 1 TQ0TIG4, TQ0TIG5 (TQ0IOC1) = 0 TOQ02 Output P51 = Setting not required PM51 = Setting not required PMC51 = 1 PFCE51 = 1 PFC51 = 0 RTP01 Output P51 = Setting not required PM51 = Setting not required PMC51 = 1 PFCE51 = 1 PFC51 = 1 P36 CTXD0Note 1 IETX0 P37 Note 2 CRXD0Note 1 IERX0 P38 Note 2 TXDA2 SDA00 P39 User's Manual U16541EJ5V1UD P41 P51 Notes 1. CAN controller versions only 2. IEBus controller versions only 3. I2C bus versions (Y products) only - PF38 (PF3) = 1 PF39 (PF3) = 1 PF40 (PF4) = 1 PF41 (PF4) = 1 - CHAPTER 4 PORT FUNCTIONS P40 Note 3 173 174 Table 4-15. Using Port Pin as Alternate-Function Pin (3/7) Pin Name Alternate Function Name P52 PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register Other Bits (Registers) PFCnx Bit of PFCn Register TIQ03 Input P52 = Setting not required PM52 = Setting not required PMC52 = 1 PFCE52 = 0 PFC52 = 1 KRM2 (KRM) = 0 KR2 Input P52 = Setting not required PM52 = Setting not required PMC52 = 1 PFCE52 = 0 PFC52 = 1 TQ0TIG6, TQ0TIG7 (TQ0I0C1) = 0 TOQ03 Output P52 = Setting not required PM52 = Setting not required PMC52 = 1 PFCE52 = 1 PFC52 = 0 RTP02 Output P52 = Setting not required PM52 = Setting not required PMC52 = 1 PFCE52 = 1 PFC52 = 1 DDI Input P52 = Setting not required PM52 = Setting not required PMC52 = Setting not required PFCE52 = Setting not required PFC52 = Setting not required SIB2 Input P53 = Setting not required PM53 = Setting not required PMC53 = 1 PFCE53 = 0 PFC53 = 0 TIQ00 Input P53 = Setting not required PM53 = Setting not required PMC53 = 1 PFCE53 = 0 PFC53 = 1 KRM3 (KRM) = 0 KR3 Input P53 = Setting not required PM53 = Setting not required PMC53 = 1 PFCE53 = 0 PFC53 = 1 TQ0TIG0, TQ0TIG1 (TQ0IOC1) = 0, Note P53 Pnx Bit of Pn Register I/O OCDM0 (OCDM) = 1 User's Manual U16541EJ5V1UD TQ0ETS0, TQ0ETS1 (TQ0IOC2) = 0 TOQ00 Input P53 = Setting not required PM53 = Setting not required PMC53 = 1 PFCE53 = 1 PFC53 = 0 RTP03 Output P53 = Setting not required PM53 = Setting not required PMC53 = 1 PFCE53 = 1 PFC53 = 1 DDO Output P53 = Setting not required PM53 = Setting not required PMC53 = Setting not required PFCE53 = Setting not required PFC53 = Setting not required SOB2 Output P54 = Setting not required PM54 = Setting not required PMC54 = 1 PFCE54 = 0 PFC54 = 0 KR4 Input P54 = Setting not required PM54 = Setting not required PMC54 = 1 PFCE54 = 0 PFC54 = 1 RTP04 Output P54 = Setting not required PM54 = Setting not required PMC54 = 1 PFCE54 = 1 PFC54 = 1 DCK Input P54 = Setting not required PM54 = Setting not required PMC54 = Setting not required PFCE54 = Setting not required PFC54 = Setting not required SCKB2 I/O P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 0 KR5 Input P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 0 PFC55 = 1 RTP05 Output P55 = Setting not required PM55 = Setting not required PMC55 = 1 PFCE55 = 1 PFC55 = 1 DMSNote Input P55 = Setting not required PM55 = Setting not required PMC55 = Setting not required PFCE55 = Setting not required PFC55 = Setting not required Note P54 Note P55 Note Flash memory versions only OCDM0 (OCDM) = 1 OCDM0 (OCDM) = 1 OCDM0 (OCDM) = 1 CHAPTER 4 PORT FUNCTIONS TQ0EES0, TQ0EES1 (TQ0IOC2) = 0, Table 4-15. Using Port Pin as Alternate-Function Pin (4/7) Pin Name Alternate Function Name P70 ANI0 Input Pnx Bit of Pn Register P70 = Setting not required PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register PM70 = 1 - - - - - ANI1 Input P71 = Setting not required PM71 = 1 P72 ANI2 Input P72 = Setting not required PM72 = 1 - - - P73 ANI3 Input P73 = Setting not required PM73 = 1 - - - P74 ANI4 Input P74 = Setting not required PM74 = 1 - - - P75 ANI5 Input P75 = Setting not required PM75 = 1 - - - P76 ANI6 Input P76 = Setting not required PM76 = 1 - - - P77 ANI7 Input P77 = Setting not required PM77 = 1 - - - P78 ANI8 Input P78 = Setting not required PM78 = 1 - - - P79 ANI9 Input P79 = Setting not required PM79 = 1 - - - - - - - Other Bits (Registers) P710 ANI10 Input P710 = Setting not required PM710 = 1 - P711 ANI11 Input P711 = Setting not required PM711 = 1 - P90 A0 Output P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 0 PFC90 = 0 KR6 Input P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 0 PFC90 = 1 TXDA1 Output P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 1 PFC90 = 0 SDA02Note 2 I/O P90 = Setting not required PM90 = Setting not required PMC90 = 1 PFCE90 = 1 PFC90 = 1 PF90 (PF9) = 1 A1 Output P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 0 PFC91 = 0 Note 1 KR7 Input P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 0 PFC91 = 1 RXDA1/KR7Note 3 Input P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 1 PFC91 = 0 P91 = Setting not required PM91 = Setting not required PMC91 = 1 PFCE91 = 1 PFC91 = 1 P91 SCL02 I/O Note 1 PF91 (PF9) = 1 Notes 1. Port 9 pins cannot be used as port pins or other alternate-function pins if even one of the A0 to A15 pins is used in the separate bus mode. After setting the PFC9 and PFCE9 registers to 0000H, therefore, set all 16 bits of the PMC9 register to FFFFH at once. 2. I2C bus versions (Y products) only 3. The RXDA1 and KR7 pins must not be used at the same time. When using the RXDA1 pin, do not use the KR7 pin. When using the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear the PFCE91 bit to 0). CHAPTER 4 PORT FUNCTIONS User's Manual U16541EJ5V1UD P71 - Note 2 <R> I/O 175 176 Table 4-15. Using Port Pin as Alternate-Function Pin (5/7) Pin Name Alternate Function Name P92 P93 P94 User's Manual U16541EJ5V1UD P96 P97 P98 P99 Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register Other Bits (Registers) PFCnx Bit of PFCn Register A2 Output P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 0 PFC92 = 0 TIP41 Input P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 0 PFC92 = 1 TOP41 Output P92 = Setting not required PM92 = Setting not required PMC92 = 1 PFCE92 = 1 PFC92 = 0 A3 Output P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 0 TIP40 Input P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 0 PFC93 = 1 TOP40 Output P93 = Setting not required PM93 = Setting not required PMC93 = 1 PFCE93 = 1 PFC93 = 0 A4 Output P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 0 PFC94 = 0 TIP31 Input P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 0 PFC94 = 1 TOP31 Output P94 = Setting not required PM94 = Setting not required PMC94 = 1 PFCE94 = 1 PFC94 = 0 A5 Output P95 = Setting not required PM95 = Setting not required PMC95 = 1 PFCE95 = 0 PFC95 = 0 TIP30 Input P95 = Setting not required PM95 = Setting not required PMC95 = 1 PFCE95 = 0 PFC95 = 1 TOP30 Output P95 = Setting not required PM95 = Setting not required PMC95 = 1 PFCE95 = 1 PFC95 = 0 A6 Output P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 0 PFC96 = 0 TIP21 Input P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 1 PFC96 = 0 TOP21 Output P96 = Setting not required PM96 = Setting not required PMC96 = 1 PFCE96 = 1 PFC96 = 1 A7 Output P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 0 PFC97 = 0 SIB1 Input P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 0 PFC97 = 1 TIP20 Input P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 1 PFC97 = 0 TOP20 Output P97 = Setting not required PM97 = Setting not required PMC97 = 1 PFCE97 = 1 PFC97 = 1 A8 Output P98 = Setting not required PM98 = Setting not required PMC98 = 1 - PFC98 = 0 SOB1 Output P98 = Setting not required PM98 = Setting not required PMC98 = 1 - PFC98 = 1 A9 Output P99 = Setting not required PM99 = Setting not required PMC99 = 1 - PFC99 = 0 SCKB1 I/O P99 = Setting not required PM99 = Setting not required PMC99 = 1 - PFC99 = 1 Note Note Note Note Note Note Note Note <R> Note Port 9 pins cannot be used as port pins or other alternate-function pins if even one of the A0 to A15 pins is used in the separate bus mode. After setting the PFC9 and PFCE9 registers to 0000H, therefore, set all 16 bits of the PMC9 register to FFFFH at once. CHAPTER 4 PORT FUNCTIONS P95 I/O Table 4-15. Using Port Pin as Alternate-Function Pin (6/7) Pin Name Alternate Function Name P910 P911 P912 P913 Output Pnx Bit of Pn Register PMnx Bit of PMn Register P910 = Setting not required PM910 = Setting not required PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PMC910 = 1 - PFC910 = 0 PFC910 = 1 SIB3 Input P910 = Setting not required PM910 = Setting not required PMC910 = 1 - A11 Output P911 = Setting not required PM911 = Setting not required PMC911 = 1 - PFC911 = 0 PFC911 = 1 SOB3 Output P911 = Setting not required PM911 = Setting not required PMC911 = 1 - A12 Output P912 = Setting not required PM912 = Setting not required PMC912 = 1 - PFC912 = 0 PFC912 = 1 SCKB3 I/O P912 = Setting not required PM912 = Setting not required PMC912 = 1 - A13 Output P913 = Setting not required PM913 = Setting not required PMC913 = 1 - PFC913 = 0 - PFC913 = 1 P913 = Setting not required PM913 = Setting not required PMC913 = 1 Output P914 = Setting not required PM914 = Setting not required PMC914 = 1 PFCE914 = 0 PFC914 = 0 INTP5 Input P914 = Setting not required PM914 = Setting not required PMC914 = 1 PFCE914 = 0 PFC914 = 1 TIP51 Input P914 = Setting not required PM914 = Setting not required PMC914 = 1 PFCE914 = 1 PFC914 = 0 TOP51 Output P914 = Setting not required PM914 = Setting not required PMC914 = 1 PFCE914 = 1 PFC914 = 1 A15 Output P915 = Setting not required PM915 = Setting not required PMC915 = 1 PFCE915 = 0 PFC915 = 0 INTP6 Input P915 = Setting not required PM915 = Setting not required PMC915 = 1 PFCE915 = 0 PFC915 = 1 TIP50 Input P915 = Setting not required PM915 = Setting not required PMC915 = 1 PFCE915 = 1 PFC915 = 0 TOP50 Output P915 = Setting not required PM915 = Setting not required PMC915 = 1 PFCE915 = 1 PFC915 = 1 PCM0 WAIT Input PCM0 = Setting not required PMCM0 = Setting not required PMCCM0 = 1 - - PCM1 CLKOUT Output PCM1 = Setting not required PMCM1 = Setting not required PMCCM1 = 1 - - PCM2 HLDAK Output PCM2 = Setting not required PMCM2 = Setting not required PMCCM2 = 1 - - PCM3 HLDRQ Input PCM3 = Setting not required PMCM3 = Setting not required PMCCM3 = 1 - - - User's Manual U16541EJ5V1UD PCT0 WR0 Output PCT0 = Setting not required PMCT0 = Setting not required PMCCT0 = 1 - PCT1 WR1 Output PCT1 = Setting not required PMCT1 = Setting not required PMCCT1 = 1 - - - - PCT4 RD Output PCT4 = Setting not required PMCT4 = Setting not required PMCCT4 = 1 - PCT6 ASTB Output PCT6 = Setting not required PMCT6 = Setting not required PMCCT6 = 1 - Note Note Note Note Note Note Note Port 9 pins cannot be used as port pins or other alternate-function pins if even one of the A0 to A15 pins is used in the separate bus mode. After setting the PFC9 and PFCE9 registers to 0000H, therefore, set all 16 bits of the PMC9 register to FFFFH at once. CHAPTER 4 PORT FUNCTIONS Input A14 P915 Other Bits (Registers) PFCnx Bit of PFCn Register INTP4 P914 <R> A10 I/O 177 178 Table 4-15. Using Port Pin as Alternate-Function Pin (7/7) Pin Name Alternate Function Name I/O Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PMCn Register PFCEnx Bit of PFCEn Register PFCnx Bit of PFCn Register A16 Output PDH0 = Setting not required PMDH0 = Setting not required PMCDH0 = 1 - - PDH1 A17 Output PDH1 = Setting not required PMDH1 = Setting not required PMCDH1 = 1 - - PDH2 A18 Output PDH2 = Setting not required PMDH2 = Setting not required PMCDH2 = 1 - - PDH3 A19 Output PDH3 = Setting not required PMDH3 = Setting not required PMCDH3 = 1 - - PDH4 A20 Output PDH4 = Setting not required PMDH4 = Setting not required PMCDH4 = 1 - - PDH5 A21 Output PDH5 = Setting not required PMDH5 = Setting not required PMCDH5 = 1 - - PDL0 AD0 I/O PDL0 = Setting not required PMDL0 = Setting not required PMCDL0 = 1 - - PDL1 AD1 I/O PDL1 = Setting not required PMDL1 = Setting not required PMCDL1 = 1 - - PDL2 AD2 I/O PDL2 = Setting not required PMDL2 = Setting not required PMCDL2 = 1 - - PDL3 AD3 I/O PDL3 = Setting not required PMDL3 = Setting not required PMCDL3 = 1 - - PDL4 AD4 I/O PDL4 = Setting not required PMDL4 = Setting not required PMCDL4 = 1 - - PDL5 AD5 I/O PDL5 = Setting not required PMDL5 = Setting not required PMCDL5 = 1 - - - FLMD1 Input PDL5 = Setting not required PMDL5 = Setting not required PMCDL5 = Setting not required - AD6 I/O PDL6 = Setting not required PMDL6 = Setting not required PMCDL6 = 1 - - PDL7 AD7 I/O PDL7 = Setting not required PMDL7 = Setting not required PMCDL7 = 1 - - PDL8 AD8 I/O PDL8 = Setting not required PMDL8 = Setting not required PMCDL8 = 1 - - PDL9 AD9 I/O PDL9 = Setting not required PMCDL9 = 1 - - PDL10 AD10 I/O PDL10 = Setting not required PMDL10 = Setting not required PMCDL10 = 1 - - PDL11 AD11 I/O PDL11 = Setting not required PMDL11 = Setting not required PMCDL11 = 1 - - PDL12 AD12 I/O PDL12 = Setting not required PMDL12 = Setting not required PMCDL12 = 1 - - PDL13 AD13 I/O PDL13 = Setting not required PMDL13 = Setting not required PMCDL13 = 1 - - PDL14 AD14 I/O PDL14 = Setting not required PMDL14 = Setting not required PMCDL14 = 1 - - PDL15 AD15 I/O PDL15 = Setting not required PMDL15 = Setting not required PMCDL15 = 1 - - Note PDL6 PMDL9 = Setting not required Note Since this pin is set in the flash memory programming mode, it does not need to be manipulated using the port control register. For details, see CHAPTER 30 FLASH MEMORY. CHAPTER 4 PORT FUNCTIONS User's Manual U16541EJ5V1UD PDH0 Other Bits (Registers) CHAPTER 4 PORT FUNCTIONS 4.6 4.6.1 <R> Cautions Cautions on setting port pins (1) In the V850ES/SG2 and V850ES/SG2-H, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode), set by the PMCn register. In regards to this register setting sequence, note with caution the following. (a) Cautions on switching from port mode to alternate-function mode To switch from the port mode to alternate-function mode in the following order. <1> Set the PFn registerNote: N-ch open-drain setting <2> Set the PFCn and PFCEn registers: Alternate-function selection <3> Set the corresponding bit of the PMCn register to 1: Switch to alternate-function mode If the PMCn register is set first, note with caution that, at that moment or depending on the change of the pin states in accordance with the setting of the PFn, PFCn, and PFCEn registers, unexpected operations may occur. A concrete example is shown as Example below. Note N-ch open-drain output pin only Caution Regardless of the port mode/alternate-function mode, the Pn register is read and written as follows. * Pn register read: Read the port output latch value (when PMn.PMnm bit = 0), or read the pin states (PMn.PMnm bit = 1). * Pn register write: Write to the port output latch [Example] SCL01 pin setting example The SCL01 pin is used alternately with the P41/SOB0 pin. Select the valid pin functions with the PMC4, PFC4, and PF4 registers. PMC41 Bit PFC41 Bit PF41 Bit Valid Pin Functions 0 don't care 1 P41 (in output port mode, N-ch open-drain output) 1 0 1 SOB0 output (N-ch open-drain output) 1 1 SCL01 I/O (N-ch open-drain output) User's Manual U16541EJ5V1UD 179 CHAPTER 4 PORT FUNCTIONS The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below. Setting Order <1> Setting Contents Initial value Pin States Pin Level Port mode (input) Hi-Z SOB0 output Low level (high level depending on the (PMC41 bit = 0, PFC41 bit = 0, PF41 bit = 0) <2> PMC41 bit 1 CSIB0 setting) <3> PFC41 bit 1 SCL01 I/O High level (CMOS output) <4> PF41 bit 1 SCL01 I/O Hi-Z (N-ch open-drain output) In <2>, I2C communication may be affected since the alternate-function SOB0 output is output to the pin. In the CMOS output period of <2> or <3>, unnecessary current may be generated. (b) Cautions on alternate-function mode (input) The input signal to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the AND output of the PMCn register set value and the pin level. Thus, depending on the port setting and alternatefunction operation enable timing, unexpected operations may occur. Therefore, switch between the port mode and alternate-function mode in the following sequence. * To switch from port mode to alternate-function mode (input) Set the pins to the alternate-function mode using the PMCn register and then enable the alternatefunction operation. * To switch from alternate-function mode (input) to port mode Stop the alternate-function operation and then switch the pins to the port mode. The concrete examples are shown as Example 1 and Example 2. [Example 1] Switch from general-purpose port (P02) to external interrupt pin (NMI) When the P02/NMI pin is pulled up as shown in Figure 4-33 and the rising edge is specified in the NMI pin edge detection setting, even though high level is input continuously to the NMI pin during switching from the P02 pin to the an NMI pin (PMC02 bit = 0 1), this is detected as a rising edge as if the low level changed to high level, and an NMI interrupt occurs. To avoid it, set the NMI pin's valid edge after switching from the P02 pin to the NMI pin. 180 User's Manual U16541EJ5V1UD CHAPTER 4 PORT FUNCTIONS Figure 4-33. Example of Switching from P02 to NMI (Incorrect) 7 PMC0 6 5 4 3 2 01 0 1 0 0 0 3V PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Rising edge detector P02/NMI PMC02 bit = 0: Low level PMC02 bit = 1: High level Remark m = 2 to 6 [Example 2] Switch from external pin (NMI) to general-purpose port (P02) When the P02/NMI pin is pulled up as shown in Figure 4-34 and the falling edge is specified in the NMI pin edge detection setting, even though high level is input continuously to the NMI pin at switching from the NMI pin to the P02 pin (PMC02 bit = 1 0), this is detected as falling edge as if high level changed to low level, and NMI interrupt occurs. To avoid this, set the NMI pin edge detection as "No edge detected" before switching to the P02 pin. Figure 4-34. Example of Switching from NMI to P02 (Incorrect) 7 PMC0 6 5 4 3 0 2 10 1 0 0 0 3V PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Falling edge detector P02/NMI PMC02 bit = 1: High level PMC02 bit = 0: Low level Remark m = 2 to 6 (2) In port mode, the PFn.PFnm bit is valid only in the output mode (PMn.PMnm bit = 0). In the input mode (PMnm bit = 1), the value of the PFnm bit is not reflected in the buffer. User's Manual U16541EJ5V1UD 181 CHAPTER 4 PORT FUNCTIONS 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. <Example> When P90 pin is an output port, P91 to P97 pins are input ports (all pin statuses are high level), and the value of the port latch is 00H, if the output of P90 pin is changed from low level to high level via a bit manipulation instruction, the value of the port latch is FFH. Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in the following order in the V850ES/SG2 and <R> V850ES/SG2-H. <1> The Pn register is read in 8-bit units. <2> The targeted one bit is manipulated. <3> The Pn register is written in 8-bit units. In step <1>, the value of the output latch (0) of P90 pin, which is an output port, is read, while the pin statuses of P91 to P97 pins, which are input ports, are read. If the pin statuses of P91 to P97 pins are high level at this time, the read value is FEH. The value is changed to FFH by the manipulation in <2>. FFH is written to the output latch by the manipulation in <3>. Figure 4-35. Bit Manipulation Instruction (P90 Pin) Bit manipulation instruction (set1 0, P9L[r0]) is executed for P90 bit. P90 Low-level output P91 to P97 P90 High-level output P91 to P97 Pin status: High level Port 9L latch 0 0 Pin status: High level Port 9L latch 0 0 0 0 0 0 1 1 1 1 1 Bit manipulation instruction for P90 bit <1> P9L register is read in 8-bit units. * In the case of P90, an output port, the value of the port latch (0) is read. * In the case of P91 to P97, input ports, the pin status (1) is read. <2> Set (1) P90 bit. <3> Write the results of <2> to the output latch of P9L register in 8-bit units. 182 User's Manual U16541EJ5V1UD 1 1 1 CHAPTER 4 PORT FUNCTIONS 4.6.3 Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins (these pins are available only in the flashmemory versions). After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used. The following action must be taken if on-chip debugging is not used. * Clear the OCDM0 bit of the OCDM register (special register) (0) At this time, fix the P05/INTP2/DRST pin to low level from when reset by the RESET pin is released until the above action is taken. If a high level is input to the DRST pin before the above action is taken, it may cause a malfunction (CPU deadlock). Handle the P05 pin with the utmost care. Caution The P05/INTP2/DRST pin is not initialized to function as an on-chip debug pin (DRST) when a reset signal (WDT2RES) is generated due to a watchdog timer overflow, a reset signal (LVIRES) is generated by the low-voltage detector (LVI), or a reset signal (CLMRES) is generated by the clock monitor (CLM) (reset by the low-voltage detector (LVI) is available only in the V850ES/SG2). The <R> OCDM register holds the current value. 4.6.4 Cautions on P05/INTP2/DRST pin The P05/INTP2/DRST pin has an internal pull-down resistor (30 k TYP.). After a reset by the RESET pin, a pulldown resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0). 4.6.5 <R> Cautions on P10, P11, and P53 pins when power is turned on When the power is turned on, the following pins may momentarily output an undefined level. * P10/ANO0 pin * P11/ANO1 pin * P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDONote pin Note The DDO pin is provided only in the flash memory version. 4.6.6 Hysteresis characteristics In port mode, the following port pins do not have hysteresis characteristics. P02 to P06 P31 to P35, P37 to P39 <R> P40 to P42 P50 to P55 <R> <R> P90 to P97, P99, P910, P912 to P915 4.6.7 Cautions on separate bus mode Port 9 pins cannot be used as port pins or other alternate-function pins if even one of the A0 to A15 pins is used in the separate bus mode. After setting the PFC9 and PFCE9 registers to 0000H, therefore, set all 16 bits of the PMC9 register to FFFFH at once. If even one of the A0 to A15 pins is not used in the separate bus mode, port 9 pins can be used as port pins or other alternate-function pins. User's Manual U16541EJ5V1UD 183 CHAPTER 5 BUS CONTROL FUNCTION <R> The V850ES/SG2 and V850ES/SG2-H are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles. 8-bit/16-bit data bus selectable Wait function * Programmable wait function of up to 7 states * External wait function using WAIT pin Idle state function Bus hold function <R> Up to 4 MB of physical memory connectable The bus can be controlled at a voltage that is different from the operating voltage when BVDD EVDD = VDD. However, in separate bus mode or when the A20 and A21 pins are used, set BVDD = EVDD = VDD. 184 User's Manual U16541EJ5V1UD CHAPTER 5 BUS CONTROL FUNCTION 5.2 Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (Multiplexed Bus) Bus Control Pin Alternate-Function Pin I/O Function AD0 to AD15 PDL0 to PDL15 I/O A16 to A21 PDH0 to PDH5 Output WAIT PCM0 Input External wait control CLKOUT PCM1 Output Internal system clock WR0, WR1 PCT0, PCT1 Output Write strobe signal RD PCT4 Output Read strobe signal ASTB PCT6 Output Address strobe signal HLDRQ PCM3 Input HLDAK PCM2 Output Address/data bus Address bus Bus hold control Table 5-2. External Control Pins (Separate Bus) Bus Control Pin Alternate-Function Pin I/O AD0 to AD15 PDL0 to PDL15 I/O A0 to A15 P90 to P915 Output Address bus A16 to A21 PDH0 to PDH5 Output Address bus WAIT PCM0 Input External wait control CLKOUT PCM1 Output Internal system clock WR0, WR1 PCT0, PCT1 Output Write strobe signal RD PCT4 Output Read strobe signal HLDRQ PCM3 Input HLDAK PCM2 Output 5.2.1 Function Data bus Bus hold control Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows. Table 5-3. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed Separate Bus Mode Multiplexed Bus Mode Address bus (A21 to A0) Undefined Address bus (A21 to A16) Undefined Data bus (AD15 to AD0) Hi-Z Address/data bus (AD15 to AD0) Undefined Control signal (RD, WR0, WR1) High level Control signal (RD, WR0, WR1, ASTB) High level Caution When a write access is performed to the internal ROM area, address, data, and control signals are activated in the same way as access to the external memory area. 5.2.2 <R> Pin status in each operation mode For the pin status of the V850ES/SG2 and V850ES/SG2-H in each operation mode, see 2.2 Pin Status. User's Manual U16541EJ5V1UD 185 CHAPTER 5 BUS CONTROL FUNCTION 5.3 Memory Block Function The 16 MB external memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. Figure 5-1. Data Memory Map: Physical Address 03FFFFFFH On-chip peripheral I/O area (4 KB) (80 KB) 03FFFFFFH 03FFF000H 03FFEFFFH 03FEC000H 03FEBFFFH Internal RAM area (60 KB) Use prohibited Use prohibited Note 1 03FF0000H 03FEFFFFH 03FEF000H 03FEEFFFH Programmable peripheral I/O areaNote 2 or use prohibitedNote 3 01000000H 00FFFFFFH 03FEC000H Memory block 3 (8 MB) 00800000H 007FFFFFH Memory block 2 (4 MB) 00400000H 003FFFFFH 001FFFFFH Memory block 1 (2 MB) External memory area (1 MB) Memory block 0 (2 MB) Internal ROM areaNote 4 (1 MB) 00100000H 000FFFFFH 00200000H 001FFFFFH 00000000H 00000000H Notes 1. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the same area as the on-chip peripheral I/O area. 2. Only the programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB address space. 3. Addresses 03FEC000H to 03FEC5FFH are allocated to addresses 03FEC000H to 03FEEFFFH of the CAN controller version as a programmable peripheral I/O area. Use of these addresses in a version without a CAN controller is prohibited. 4. This area is an external memory area in the case of a data write access. 186 User's Manual U16541EJ5V1UD CHAPTER 5 BUS CONTROL FUNCTION 5.4 <R> External Bus Interface Mode Control Function The V850ES/SG2 and V850ES/SG2-H have the following two external bus interface modes. * Multiplexed bus mode * Separate bus mode These two modes can be selected by using the EXIMC register. (1) External bus interface mode control register (EXIMC) The EXIMC register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H EXIMC 0 R/W 0 Address: FFFFFFBEH 0 SMSEL Caution 0 0 0 0 SMSEL Mode selection 0 Multiplexed bus mode 1 Separate bus mode Set the EXIMC register from the internal ROM or internal RAM area before making an external access. After setting the EXIMC register, be sure to insert a NOP instruction. User's Manual U16541EJ5V1UD 187 CHAPTER 5 BUS CONTROL FUNCTION 5.5 5.5.1 Bus Access Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. (1) In V850ES/SG2 Area (Bus Width) Internal ROM (32 Bits) Internal RAM (32 Bits) External Memory (16 Bits) Bus Cycle Type Note 1 3+n Note 2 Note 1 3+n Note 2 Instruction fetch (normal access) 1 1 Instruction fetch (branch) 2 2 Operand data access 3 Note 2 1 3+n Notes 1. Increases by 1 if a conflict with a data access occurs. 2. 2 + n clocks (n: Number of wait states) when the separate bus mode is selected. Remark <R> Unit: Clocks/access (2) In V850ES/SG2-H Area (Bus Width) Internal ROM (32 Bits) Internal RAM (32 Bits) External Memory (16 Bits) Bus Cycle Type Note 1 3+n Note 2 Note 1 3+n Note 2 Instruction fetch (normal access) 1 1 Instruction fetch (branch) 3 2 Operand data access 4 1 Notes 1. Increases by 1 if a conflict with a data access occurs. 2. 2 + n clocks (n: Number of wait states) when the separate bus mode is selected. Remark 188 Unit: Clocks/access User's Manual U16541EJ5V1UD Note 2 3+n CHAPTER 5 BUS CONTROL FUNCTION 5.5.2 Bus size setting function Each external memory area selected by memory block n can be set by using the BSC register. However, the bus size can be set to 8 bits and 16 bits only. <R> The external memory areas of the V850ES/SG2 and V850ES/SG2-H are selected in memory blocks 0 to 3. (1) Bus size configuration register (BSC) The BSC register can be read or written in 16-bit units. Reset sets this register to 5555H. Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the BSC register are complete. After reset: 5555H BSC R/W 15 14 13 12 11 10 9 8 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 0 BS30 0 BS20 0 BS10 0 BS00 Memory block 3 BSn0 Caution Address: FFFFF066H Memory block 2 Memory block 1 Memory block 0 Data bus width of memory block n space (n = 0 to 3) 0 8 bits 1 16 bits Be sure to set bits 14, 12, 10, and 8 to "1", and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to "0". User's Manual U16541EJ5V1UD 189 CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 <R> Access by bus size The V850ES/SG2 and V850ES/SG2-H access the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. * The bus size of the on-chip peripheral I/O is fixed to 16 bits. * The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register). The operation when each of the above is accessed is described below. All data is accessed starting from the lower side. <R> The V850ES/SG2 and V850ES/SG2-H support only the little-endian format. Figure 5-2. Little-Endian Address in Word 31 24 23 16 15 8 7 0 000BH 000AH 0009H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H (1) Data space <R> The V850ES/SG2 and V850ES/SG2-H have an address misalign function. With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) Halfword-length data access A byte-length bus cycle is generated twice if the least significant bit of the address is 1. (b) Word-length data access (i) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10. 190 User's Manual U16541EJ5V1UD CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 15 15 7 8 7 8 7 0 0 2n + 1 7 2n Byte data 0 External data bus Byte data 0 External data bus (b) 8-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 7 7 0 0 7 7 0 0 2n + 1 2n Byte data Byte data External data bus User's Manual U16541EJ5V1UD External data bus 191 CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Address 15 15 2n + 1 8 7 8 7 15 15 8 7 8 7 0 0 Address 15 15 8 7 8 7 0 0 2n + 1 2n 0 Second access Address 2n + 2 2n 0 Halfword data External data bus Halfword data External data bus Halfword data External data bus (b) 8-bit data bus width <1> Access to even address (2n) First access 15 <2> Access to odd address (2n + 1) Second access 15 Address 8 7 7 0 0 15 Address 8 7 7 0 0 192 Halfword data External data bus Second access 15 Address 8 7 7 0 0 2n + 1 2n Halfword data External data bus First access Address 8 7 7 0 0 2n + 2 2n + 1 Halfword data External data Halfword data External data bus bus User's Manual U16541EJ5V1UD CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access 31 31 24 23 24 23 Address 16 15 15 8 7 8 7 0 0 Address 16 15 15 8 7 8 7 0 0 4n + 1 4n + 3 4n Word data External data bus 4n + 2 Word data External data bus <2> Access to address (4n + 1) First access Second access Third access 31 31 31 24 23 24 23 24 23 Address 16 15 15 8 7 0 Address 16 15 15 8 7 8 7 8 7 0 0 0 4n + 1 Address 16 15 15 8 7 8 7 0 0 4n + 3 4n + 2 Word data External data bus Word data External data bus User's Manual U16541EJ5V1UD 4n + 4 Word data External data bus 193 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access 31 31 24 23 24 23 Address 16 15 15 8 7 8 7 0 0 Address 16 15 15 8 7 8 7 0 0 4n + 3 4n + 5 4n + 2 Word data External data bus 4n + 4 Word data External data bus <4> Access to address (4n + 3) First access Second access Third access 31 31 31 24 23 24 23 24 23 Address 16 15 15 8 7 0 Address 16 15 15 8 7 8 7 8 7 0 0 0 4n + 3 Address 16 15 15 8 7 8 7 0 0 4n + 5 4n + 4 Word data External data bus 194 Word data External data bus User's Manual U16541EJ5V1UD 4n + 6 Word data External data bus CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 Address 8 7 7 0 0 Address 8 7 7 0 0 4n Word data External data bus Address 8 7 7 0 0 4n + 1 Word data External data bus Address 8 7 7 0 0 4n + 2 4n + 3 Word data External data bus Word data External data bus Third access Fourth access <2> Access to address (4n + 1) First access Second access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 7 0 0 Address 8 7 7 0 0 4n + 1 Word data External data bus Address 8 7 7 0 0 4n + 2 Word data External data bus Address 8 7 7 0 0 4n + 3 Word data External data bus User's Manual U16541EJ5V1UD Address 4n + 4 Word data External data bus 195 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 8 7 Address 7 4n + 2 0 0 Word data External data bus Address 8 7 7 4n + 3 0 0 Word data External data bus Address 8 7 7 4n + 4 0 0 Word data External data bus 8 7 Address 7 4n + 5 0 0 Word data External data bus <4> Access to address (4n + 3) First access Second access Third access Fourth access 31 31 31 31 24 23 24 23 24 23 24 23 16 15 16 15 16 15 16 15 Address 8 7 7 0 0 Address 8 7 7 0 0 4n + 3 Word data External data bus 196 Address 8 7 7 0 0 4n + 4 Word data External data bus Address 8 7 7 0 0 4n + 5 Word data External data bus User's Manual U16541EJ5V1UD 4n + 6 Word data External data bus CHAPTER 5 BUS CONTROL FUNCTION 5.6 5.6.1 Wait Function Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each memory block space. The number of wait states can be programmed by using the DWC0 register . Immediately after system reset, 7 data wait states are inserted for all the blocks. The DWC0 register can be read or written in 16-bit units. Reset sets this register to 7777H. Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are always accessed without a wait state. The on-chip peripheral I/O area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the DWC0 register are complete. 3. When the V850ES/SG2-H is used in separate bus mode and operated at fXX > 20 MHz, be <R> sure to insert one or more wait. After reset: 7777H DWC0 R/W Address: FFFFF484H 15 14 13 12 11 10 9 8 0 DW32 DW31 DW30 0 DW22 DW21 DW20 7 6 5 4 3 2 1 0 0 DW12 DW11 DW10 0 DW02 DW01 DW00 Memory block 2 Memory block 3 Memory block 0 Memory block 1 DWn2 DWn1 Number of wait states inserted in CSn space (n = 0 to 3) DWn0 <R> Multiplexed bus Separate bus fXX 20 MHz Caution 0 0 0 None 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 None fXX > 20 MHz Setting prohibited Be sure to clear bits 15, 11, 7, and 3 to "0". User's Manual U16541EJ5V1UD 197 CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is set to alternate function, the external wait function is enabled. Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function. The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2 and TW states of the bus cycle in the multiplexed bus mode. In the separate bus mode, it is sampled at the rising edge of the clock immediately after the T1 and TW states of the bus cycle. If the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. 198 User's Manual U16541EJ5V1UD CHAPTER 5 BUS CONTROL FUNCTION 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. Programmable wait Wait control Wait via WAIT pin For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait states will be inserted in the bus cycle. Figure 5-3. Inserting Wait Example (a) Multiplexed bus T2 T1 TW TW TW T3 CLKOUT WAIT pin Wait via WAIT pin Programmable wait Wait control (b) Separate bus TW T1 TW TW T2 CLKOUT WAIT pin Wait via WAIT pin Programmable wait Wait control Remark The circles indicate the sampling timing. User's Manual U16541EJ5V1UD 199 CHAPTER 5 BUS CONTROL FUNCTION 5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each memory block area (memory blocks 0 to 3). If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an address hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock. (1) Address wait control register (AWC) The AWC register can be read or written in 16-bit units. Reset sets this register to FFFFH. Cautions 1. Address setup wait and address hold wait cycles are not inserted when the internal ROM area, internal RAM area, and on-chip peripheral I/O areas are accessed. 2. Write to the AWC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the AWC register are complete. 3. When the V850ES/SG2-H is operated at fXX > 20 MHz, be sure to insert the address-hold <R> wait and the address-setup wait. After reset: FFFFH AWC R/W Address: FFFFF488H 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 AHW3 ASW3 AHW2 ASW2 AHW1 ASW1 AHW0 ASW0 Memory block 3 Memory block 2 Memory block 1 Specifies insertion of address hold wait (n = 0 to 3) AHWn <R> fXX 20 MHz fXX > 20 MHz 0 Not inserted Setting prohibited 1 Inserted Inserted Specifies insertion of address setup wait (n = 0 to 3) ASWn fXX 20 MHz <R> Caution 200 Memory block 0 fXX > 20 MHz 0 Not inserted Setting prohibited 1 Inserted Inserted Be sure to set bits 15 to 8 to "1". User's Manual U16541EJ5V1UD CHAPTER 5 BUS CONTROL FUNCTION 5.7 Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the memory block in the multiplex address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state. By inserting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). Whether the idle state is to be inserted can be programmed by using the BCC register. An idle state is inserted for all the areas immediately after system reset. (1) Bus cycle control register (BCC) The BCC register can be read or written in 16-bit units. Reset sets this register to AAAAH. Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle state insertion. 2. Write to the BCC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the BCC register are complete. After reset: AAAAH BCC R/W 15 14 13 12 11 10 9 8 1 0 1 0 1 0 1 0 7 6 5 4 3 2 1 0 BC31 0 BC21 0 BC11 0 BC01 0 Memory block 3 Memory block 2 Memory block 1 Memory block 0 Specifies insertion of idle state (n = 0 to 3) BCn1 Caution Address: FFFFF48AH 0 Not inserted 1 Inserted Be sure to set bits 15, 13, 11, and 9 to "1", and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to "0". User's Manual U16541EJ5V1UD 201 CHAPTER 5 BUS CONTROL FUNCTION 5.8 5.8.1 Bus Hold Function Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for the bus mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again. During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until an on-chip peripheral I/O register or the external memory is accessed. The bus hold status is indicated by assertion of the HLDAK pin (low level). The bus hold function enables the configuration of multi-processor type systems in which two or more bus masters exist. Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction. Status CPU bus lock Data Bus Width 16 bits Access Type Timing at Which Bus Hold Request Is Not Acknowledged Word access to even address Between first and second access Word access to odd address Between first and second access Between second and third access 8 bits Halfword access to odd address Between first and second access Word access Between first and second access Between second and third access Between third and fourth access Halfword access Read-modify-write access of bit - Between first and second access - manipulation instruction 202 Between read access and write access User's Manual U16541EJ5V1UD CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5> HLDAK = 0 Bus hold status <6> HLDRQ = 1 acknowledged <7> HLDAK = 1 <8> Bus cycle start request inhibition released Normal status <9> Bus cycle starts HLDRQ (input) HLDAK (output) <1> <2> <3><4> <5> 5.8.3 <6> <7><8><9> Operation in power save mode Because the internal system clock is stopped in the STOP, IDLE1, and IDLE2 modes, the bus hold status is not entered even if the HLDRQ pin is asserted. In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold status is cleared. User's Manual U16541EJ5V1UD 203 CHAPTER 5 BUS CONTROL FUNCTION 5.9 Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and instruction fetch (successive). An instruction fetch may be inserted between the read access and write access in a read-modify-write access. If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. Table 5-4. Bus Priority Priority High Low 204 External Bus Cycle Bus Master Bus hold External device DMA transfer DMAC Operand data access CPU Instruction fetch (branch) CPU Instruction fetch (successive) CPU User's Manual U16541EJ5V1UD CHAPTER 5 BUS CONTROL FUNCTION 5.10 Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 T1 T2 TW TW T3 TI T1 CLKOUT A21 to A16 A1 A2 A3 D2 A3 ASTB WAIT AD15 to AD0 A1 D1 A2 RD Idle state Programmable External wait wait 8-bit access Odd address AD15 to AD8 Active Hi-Z Hi-Z Active AD7 to AD0 Remark Even address The broken lines indicate high impedance. Figure 5-5. Multiplexed Bus Read Timing (Bus Size: 8 Bits) T1 T2 T3 T1 T2 TW TW T3 TI T1 CLKOUT A21 to A16, AD15 to AD8 A1 A2 A3 D2 A3 ASTB WAIT AD7 to AD0 A1 D1 A2 RD Programmable External wait wait Remark Idle state The broken lines indicate high impedance. User's Manual U16541EJ5V1UD 205 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 T1 T2 TW TW T3 T1 CLKOUT A21 to A16 A1 A2 A3 D2 A3 ASTB WAIT AD15 to AD0 WR1, WR0 A1 11 D1 00 A2 11 11 00 11 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Undefined AD7 to AD0 Undefined 01 WR1, WR0 Active 10 Figure 5-7. Multiplexed Bus Write Timing (Bus Size: 8 Bits) T1 T2 T3 T1 T2 TW TW T3 T1 CLKOUT A21 to A16, AD15 to AD8 A1 A2 A3 D2 A3 ASTB WAIT AD7 to AD0 WR1, WR0 A1 11 D1 10 A2 11 11 10 Programmable External wait wait 206 User's Manual U16541EJ5V1UD 11 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 TINote TH TH TH TH TINote T1 T2 T3 CLKOUT HLDRQ HLDAK A21 to A16 AD15 to AD0 A1 A1 Undefined Undefined D1 Undefined Undefined A2 A2 D2 ASTB RD Note This idle state (TI) does not depend on the BCC register settings. Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode. 2. The broken lines indicate high impedance. User's Manual U16541EJ5V1UD 207 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-9. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) T2 T1 T1 TW TW T2 TI T1 T2 CLKOUT WAIT A1 A21 to A0 A2 A3 RD AD15 to AD0 D1 D2 D3 Programmable External wait wait 8-bit access Odd address Even address AD15 to AD8 Active Hi-Z Hi-Z Active AD7 to AD0 Remark Idle state The broken lines indicate high impedance. Figure 5-10. Separate Bus Read Timing (Bus Size: 8 Bits) T2 T1 T1 TW TW T2 TI T1 T2 CLKOUT WAIT A21 to A0 A1 A2 A3 RD AD7 to AD0 D1 D2 Programmable External wait wait Remark 208 The broken lines indicate high impedance. User's Manual U16541EJ5V1UD D3 Idle state CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T2 T1 T1 TW TW T2 T1 T2 CLKOUT WAIT A1 A21 to A0 WR1, WR0 11 A2 00 AD15 to AD0 11 11 A3 00 D1 11 00 D2 11 D3 Programmable External wait wait 8-bit access Odd address Even address Active Undefined Undefined Active AD15 to AD8 AD7 to AD0 01 WR1, WR0 Remark 10 The broken lines indicate high impedance. Figure 5-12. Separate Bus Write Timing (Bus Size: 8 Bits) T2 T1 T1 TW TW T2 T1 T2 CLKOUT WAIT A1 A21 to A0 WR1, WR0 AD7 to AD0 11 A2 10 11 11 10 D1 D2 A3 11 10 11 D3 Programmable External wait wait Remark The broken lines indicate high impedance. User's Manual U16541EJ5V1UD 209 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, Write) T1 T2 T1 T2 TINote TH TH TH TH TINote T1 T2 CLKOUT HLDRQ HLDAK A21 to A0 A1 AD7 to AD0 WR1, WR0 D1 11 10 Undefined A2 Undefined A3 D2 11 10 D3 11 11 10 Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance. Figure 5-14. Address Wait Timing (Separate Bus Read, Bus Size: 16 Bits, 16-Bit Access) T1 T2 TASW CLKOUT CLKOUT ASTB ASTB WAIT WAIT A21 to A0 A1 TAHW A1 RD RD AD15 to AD0 A21 to A0 T1 D1 AD15 to AD0 D1 Remarks 1. TASW (address setup wait): Image of high-level width of T1 state expanded. 2. TAHW (address hold wait): Image of low-level width of T1 state expanded. 3. The broken lines indicate high impedance. 210 User's Manual U16541EJ5V1UD T2 11 CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. { Main clock oscillator * In clock-through mode V850ES/SG2: <R> fX = 2.5 to 10 MHz (fXX = 2.5 to 10 MHz) V850ES/SG2-H: fX = 2.5 to 8 MHz (fXX = 2.5 to 8 MHz) * In PLL mode V850ES/SG2: <R> fX = 2.5 to 5 MHz (fXX = 10 to 20 MHz) V850ES/SG2-H: fX = 2.5 to 5 MHz (x4: fXX = 10 to 20 MHz) fX = 2.5 to 4 MHz (x8: fXX = 20 to 32 MHz) { Subclock oscillator * fXT = 32.768 kHz { Multiply (x4/x8) function by PLL (Phase Locked Loop) * Clock-through mode/PLL mode selectable { Internal oscillator * fR = 200 kHz (TYP.) { Internal system clock generation * 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) { Peripheral clock generation { Clock output function Remark fX: Main clock oscillation frequency fXX: Main clock frequency fXT: Subclock frequency fR: Internal oscillation clock frequency User's Manual U16541EJ5V1UD 211 CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration Figure 6-1. Clock Generator FRC bit fBRG = fX/2 to fX/212 Prescaler 3 MCK MFRC bit bit X2 Main clock oscillator IDLE control PLLON bit fX PLL Main clock oscillator stop control Watch timer clock CLS, CK3 bits IDLE mode Selector X1 Timer M clock Watch timer clock, watchdog timer 2 clock fXT CK2 to CK0 bits IDLE fXX control Note Prescaler 2 fXX/32 fXX/16 fXX/8 fXX/4 fXX/2 STOP mode SELPLL bit HALT mode Selector XT2 fXT Selector Subclock oscillator Selector XT1 HALT fCPU control fCLK fXX Internal oscillator fR 1/8 divider fR/8 CPU clock Internal system clock Watchdog timer 2 clock, timer M clock RSTOP bit CLKOUT Port CM Prescaler 1 fXX to fXX/1,024 Peripheral clock, watchdog timer 2 clock fCAN CAN controller Note The internal oscillation clock is selected when the watchdog timer 2 overflows during the oscillation stabilization time. Remark fX: Main clock oscillation frequency fXX: Main clock frequency fCLK: Internal system clock frequency fXT: Subclock frequency fCPU: CPU clock frequency fBRG: Watch timer clock frequency fR: Internal oscillation clock frequency fCAN: CAN clock frequency 212 User's Manual U16541EJ5V1UD CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main resonator oscillates the following frequencies (fX). * In clock-through mode V850ES/SG2: <R> fX = 2.5 to 10 MHz V850ES/SG2-H: fX = 2.5 to 8 MHz * In PLL mode V850ES/SG2: <R> fX = 2.5 to 5 MHz V850ES/SG2-H: fX = 2.5 to 5 MHz (x4) fX = 2.5 to 4 MHz (x8) (2) Subclock oscillator The sub-resonator oscillates a frequency of 32.768 kHz (fXT). (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator. Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when the PCC.CLS bit = 1). (4) Internal oscillator Oscillates a frequency (fR) of 200 kHz (TYP.). (5) Prescaler 1 This prescaler generates the clock (fXX to fXX/1,024) to be supplied to the following on-chip peripheral functions: <R> TMP0 to TMP5, TMQ0, TMM0, CSIB0 to CSIB4, UARTA0 to UARTA2, I2C00 to I2C02Note 1, ADC, WDT2, CAN0Note 2 and IEBusNote 3 Notes 1. I2C bus versions (Y products) only 2. CAN controller versions only 3. IEBus versions only (6) Prescaler 2 This circuit divides the main clock (fXX). The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the CPU clock (fCPU) and internal system clock (fCLK). fCLK is the clock supplied to the INTC, ROM correction, ROM, and RAM blocks, and can be output from the CLKOUT pin. (7) Prescaler 3 This circuit divides the clock generated by the main clock oscillator (fX) to a specific frequency (32.768 kHz) and supplies that clock to the watch timer block. For details, see CHAPTER 10 WATCH TIMER FUNCTIONS. User's Manual U16541EJ5V1UD 213 CHAPTER 6 CLOCK GENERATION FUNCTION (8) PLL This circuit multiplies the clock generated by the main clock oscillator (fX) by x4 or x8. It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied clock is output. These modes can be selected by using the PLLCTL.SELPLL bit. Whether the clock is multiplied by x4 or x8 is selected by the CKC.CKDIV0 bit, and PLL is started or stopped by the PLLCTL.PLLON bit. 6.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset input sets this register to 03H. 214 User's Manual U16541EJ5V1UD CHAPTER 6 CLOCK GENERATION FUNCTION After reset: 03H R/W Address: FFFFF828H < > PCC FRC MCK MFRC FRC < > < > CLSNote CK3 CK2 CK1 CK0 Use of subclock on-chip feedback resistor 0 Used 1 Not used MCK Main clock oscillator control 0 Oscillation enabled 1 Oscillation stopped * Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop. It stops after the CPU clock has been changed to the subclock. * Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. * When the main clock is stopped and the device is operating with the subclock, clear (0) the MCK bit and secure the oscillation stabilization time by software before switching the CPU clock to the main clock or operating the on-chip peripheral functions. MFRC Use of main clock on-chip feedback resistor 0 Used 1 Not used CLSNote Status of CPU clock (fCPU) 0 Main clock operation 1 Subclock operation CK3 CK2 CK1 CK0 Clock selection (fCLK/fCPU) 0 0 0 0 fXX 0 0 0 1 fXX/2 0 0 1 0 fXX/4 0 0 1 1 fXX/8 0 1 0 0 fXX/16 0 1 0 1 fXX/32 0 1 1 x Setting prohibited 1 x x x fXT Note The CLS bit is a read-only bit. Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits. Remark x: don't care User's Manual U16541EJ5V1UD 215 CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation subclock operation <1> CK3 bit 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started. Max.: 1/fXT (1/subclock frequency) <3> MCK bit 1: Set the MCK bit to 1 only when stopping the main clock. Cautions 1. When stopping the main clock, stop the PLL. Also stop the operations of the on-chip peripheral functions operating with the main clock. 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied, then change to the subclock operation mode. Internal system clock (fCLK) > Subclock (fXT: 32.768 kHz) x 4 Remark Internal system clock (fCLK): Clock generated from the main clock (fXX) by setting bits CK2 to CK0 [Description example] _DMA_DISABLE: clrl 0, DCHCn[r0] -- DMA operation disabled. n = 0 to 3 <1> _SET_SUB_RUN : st.b r0, PRCMD[r0] set1 3, PCC[r0] -- CK3 bit 1 <2> _CHECK_CLS : tst1 4, PCC[r0] bz _CHECK_CLS -- Wait until subclock operation starts. <3> _STOP_MAIN_CLOCK : st.b r0, PRCMD[r0] set1 6, PCC[r0] -- MCK bit 1, main clock is stopped. _DMA_ENABLE: setl Remark 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3 The description above is simply an example. Note that in <2> above, the CLS bit is read in a closed loop. 216 User's Manual U16541EJ5V1UD CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation main clock operation <1> MCK bit 1: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3> CK3 bit 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <4> Main clock operation: It takes the following time after the CK3 bit is set until main clock operation is started. Max.: 1/fXT (1/subclock frequency) Therefore, insert one NOP instruction immediately after setting the CK3 bit to 0 or read the CLS bit to check if main clock operation has started. Caution Enable operation of the on-chip peripheral functions operating with the main clock only after the oscillation of the main clock stabilizes. If their operations are enabled before the lapse of the oscillation stabilization time, a malfunction may occur. [Description example] _DMA_DISABLE: clrl 0, DCHCn[r0] -- DMA operation disabled. n = 0 to 3 <1> _START_MAIN_OSC : st.b r0, PRCMD[r0] -- Release of protection of special registers clr1 6, PCC[r0] -- Main clock starts oscillating. 0x55, r0, r11 -- Wait for oscillation stabilization time. <2> movea _WAIT_OST : nop nop nop addi -1, r11, r11 cmp r0, r11 bne _WAIT_OST <3> st.b clr1 r0, PRCMD[r0] 3, PCC[r0] -- CK3 0 <4> _CHECK_CLS : tst1 4, PCC[r0] bnz _CHECK_CLS -- Wait until main clock operation starts. _DMA_ENABLE: setl Remark 0, DCHCn[r0] -- DMA operation enabled. n = 0 to 3 The description above is simply an example. Note that in <4> above, the CLS bit is read in a closed loop. User's Manual U16541EJ5V1UD 217 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF80CH < > RCM 0 0 0 RSTOP 0 0 0 0 RSTOP Oscillation/stop of internal oscillator 0 Internal oscillator oscillating 1 Internal oscillator stopped Cautions 1. The internal oscillator cannot be stopped while the CPU is operating on the internal oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1. 2. The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT overflow occurs during oscillation stabilization) even when the RSTOP bit is set to 1. At this time, the RSTOP bit remains being set to 1. (3) CPU operation clock status register (CCLS) The CCLS register indicates the status of the CPU operation clock. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00HNote CCLS 0 CCLSF R 0 Address: FFFFF82EH 0 0 0 0 0 CCLSF CPU operation clock status 0 Operating on main clock (fX) or subclock (fXT). 1 Operating on internal oscillation clock (fR). Note If WDT overflow occurs during oscillation stabilization after a reset is released, the CPU operates on <R> the internal oscillation clock (fR). At this time, the CCLSF bit is set to 1 and the reset value is 01H. 218 User's Manual U16541EJ5V1UD CHAPTER 6 CLOCK GENERATION FUNCTION 6.4 Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock Register Setting and PCC Register Operation Status CLK Bit = 0, MCK Bit = 0 During Reset During Oscillation HALT Mode IDLE1, IDLE2 Mode STOP Mode Stabilization Target Clock CLS Bit = 1, CLS Bit = 1, MCK Bit = 0 MCK Bit = 1 Subclock Sub-IDLE Subclock Sub-IDLE Mode Mode Mode Mode Time Count Main clock oscillator (fX) x x x x Subclock oscillator (fXT) CPU clock (fCPU) x x x x x x x Internal system clock (fCLK) x x x x x x Main clock (in PLL mode, fXX) x Note x x x x Peripheral clock (fXX to fXX/1,024) x x x x x x x WT clock (main) x x x x WT clock (sub) WDT2 clock (internal oscillation) x WDT2 clock (main) x x x x x x x WDT2 clock (sub) Note Lockup time Remark 6.4.2 : Operable x: Stopped Clock output function The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin. The internal system clock (fCLK) is selected by using the PCC.CK3 to PCC.CK0 bits. The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control register of port CM. The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the clock when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in the port mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin is Hi-Z. User's Manual U16541EJ5V1UD 219 CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 6.5.1 <R> PLL Function Overview In the V850ES/SG2 and V850ES/SG2-H, an operating clock that is 4 or 8 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions. * V850ES/SG2 <R> When PLL function is used: Input clock = 2.5 to 5 MHz (output: 10 to 20 MHz) Clock-through mode: Input clock = 2.5 to 10 MHz (output: 2.5 to 10 MHz) * V850ES/SG2-H 6.5.2 When PLL function is used (x4): Input clock = 2.5 to 5 MHz (output: 10 to 20 MHz) When PLL function is used (x8): Input clock = 2.5 to 4 MHz (output: 20 to 32 MHz) Clock-through mode: Input clock = 2.5 to 8 MHz (output: 2.5 to 8 MHz) Registers (1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the PLL function. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. After reset: 01H PLLCTL 0 R/W Address: FFFFF82CH 0 0 0 PLLON 0 0 < > < > SELPLL PLLON PLL operation stop register 0 PLL stopped 1 PLL operating (After PLL operation starts, a lockup time is required for frequency stabilization) SELPLL CPU operation clock selection register 0 Clock-through mode 1 PLL mode Cautions 1. To stop the PLL operation, first set the clock through mode (SELPLL bit = 0), wait for <R> at least 8 clocks, and then stop the PLL (PLLON bit = 0). When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clock-through mode), but be sure to stop the PLL in the above procedure. 2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not (unlocked), "0" is written to the SELPLL bit if data is written to it. 220 User's Manual U16541EJ5V1UD CHAPTER 6 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.8 Special registers). The CKC register controls the internal system clock in the PLL mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 0AH. After reset: 0AH CKC 0 R/W 0 0 0 1 0 1 CKDIV0 Internal system clock (fXX) in PLL mode CKDIV0 <R> Address: FFFFF822H 0 fXX = 4 x fX (fX = 2.5 to 5.0 MHz) 1 V850ES/SG2: fXX = 8 x fX (fX = 2.5 MHz) V850ES/SG2-H: fXX = 8 x fX (fX = 2.5 to 4.0 MHz) Cautions 1. The PLL mode cannot be used in case of the following oscillation frequency. * V850ES/SG2: <R> 5.0 MHz < fX 10.0 MHz * V850ES/SG2-H: 5.0 MHz < fX 8.0 MHz 2. Before changing the multiplication factor between 4 and 8 by using the CKC register, set the clock-through mode and stop the PLL. 3. Be sure to set bits 3 and 1 to "1" and clear bits 7 to 4 and 2 to "0". Remark Both the CPU clock and peripheral clock are divided by the CKC register, but only the CPU clock is divided by the PCC register. User's Manual U16541EJ5V1UD 221 CHAPTER 6 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status. The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R Address: FFFFF824H < > LOCKR 0 0 0 LOCK 0 0 0 0 LOCK PLL lock status check 0 Locked status 1 Unlocked status Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/clear conditions are as follows. [Set conditions] * Upon system resetNote * In IDLE2 or STOP mode * Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0) * Upon stopping main clock and using CPU with subclock (setting of PCC.CK3 bit to 1 and setting of PCC.MCK bit to 1) Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the oscillation stabilization time has elapsed. [Clear conditions] * Upon overflow of oscillation stabilization time following reset release (OSTS register default time (see 24.2 (3) Oscillation stabilization time select register (OSTS))) * Upon oscillation stabilization timer overflow (time set by OSTS register) following STOP mode release, when the STOP mode was set in the PLL operating status * Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed from 0 to 1 * After the setup time inserted upon release of the IDLE2 mode is released (time set by the OSTS register) when the IDLE2 mode is set during PLL operation. 222 User's Manual U16541EJ5V1UD CHAPTER 6 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units. Reset sets this register to 03H. After reset: 03H R/W 0 0 PLLS1 PLLS0 PLLS Address: FFFFF6C1H 0 0 0 0 PLLS1 PLLS0 Selection of PLL lockup time 10 0 0 2 /fX 0 1 211fX 1 0 212/fX 1 1 213/fX (default value) Cautions 1. Set so that the lockup time is 800 s or longer. 2. Do not change the PLLS register setting during the lockup period. 6.5.3 Usage (1) When PLL is used * After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1). * To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the LOCKR.LOCK bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then stop the PLL (PLLON bit = 0). * The PLL stops during transition to IDLE2 or STOP mode regardless of the setting and is restored from IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows. (a) To set the IDLE2/STOP mode in clock through mode * STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (MIN.) or more. * IDLE2 mode: Set the OSTS register so that the setup time is 350 s (MIN.) or more. <R> (b) To set IDLE2/STOP mode in PLL operation mode * STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (MIN.) or more. * IDLE2 mode: Set the OSTS register so that the setup time is 800 s (MIN.) or more. When shifting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary. (2) When PLL is not used * The clock-through mode (SELPLL bit = 0) is selected after the reset signal has been released, but the PLL is operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0). User's Manual U16541EJ5V1UD 223 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. <R> The V850ES/SG2 and V850ES/SG2-H have six timer/event counter channels, TMP0 to TMP5. 7.1 Overview An outline of TMPn is shown below. * Clock selection: 8 ways * Capture/trigger input pins: 2 * External event count input pins: 1 * External trigger input pins: 1 * Timer/counters: 1 * Capture/compare registers: 2 * Capture/compare match interrupt request signals: 2 * Overflow interrupt request signals: 1 * Timer output pins: 2 Remark 7.2 n = 0 to 5 Functions TMPn has the following functions. * Interval timer * External event counter * External trigger pulse output * One-shot pulse output * PWM output * Free-running timer * Pulse width measurement Remark 224 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.3 Configuration TMPn includes the following hardware. Table 7-1. Configuration of TMPn Item Configuration Timer register 16-bit counter x 1 each Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter read buffer register (TPnCNT) CCR0, CCR1 buffer registers Timer inputs 2 (TIPn0 Timer outputs Note 1 , TIPn1 pins) 2 (TOPn0, TOPn1 pins) Note 2 Control registers TMPn control registers 0, 1 (TPnCTL0, TPnCTL1) TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2) TMPn option register 0 (TPnOPT0) Notes 1. The TIPn0 pin functions alternately as a capture trigger input signal, external event count input signal, and external trigger input signal. 2. When using the functions of the TIPn0, TIPn1, TOPn0, and TOPn1 pins, see Table 4-15 Using Port Pin as Alternate-Function Pin. Remark n = 0 to 5 Figure 7-1. Block Diagram of TMPn Internal bus Selector TPnCNT Clear TIPn1 Edge detector CCR0 buffer register TIPn0 INTTPnOV 16-bit counter Output controller Selector fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64Note 1, fXX/256Note 2 fXX/128Note 1, fXX/512Note 2 CCR1 buffer register TOPn0 TOPn1 INTTPnCC0 INTTPnCC1 TPnCCR0 TPnCCR1 Internal bus Notes 1. TMP0, TMP2, TMP4 2. TMP1, TMP3, TMP5 Remark fXX: Main clock frequency User's Manual U16541EJ5V1UD 225 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPnCNT register. When the TPnCTL0.TPnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPnCNT register is read at this time, 0000H is read. Reset sets the TPnCE bit to 0. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR0 register is used as a compare register, the value written to the TPnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is cleared to 0000H after reset, as the TPnCCR0 register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR1 register is used as a compare register, the value written to the TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is cleared to 0000H after reset, as the TPnCCR1 register is cleared to 0000H. (4) Edge detector This circuit detects the valid edges input to the TIPn0 and TIPn1 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TPnIOC1 and TPnIOC2 registers. (5) Output controller This circuit controls the output of the TOPn0 and TOPn1 pins. The output controller is controlled by the TPnIOC0 register. (6) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. 226 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.4 Registers The registers that control TMPn are as follows. * TMPn control register 0 (TPnCTL0) * TMPn control register 1 (TPnCTL1) * TMPn I/O control register 0 (TPnIOC0) * TMPn I/O control register 1 (TPnIOC1) * TMPn I/O control register 2 (TPnIOC2) * TMPn option register 0 (TPnOPT0) * TMPn capture/compare register 0 (TPnCCR0) * TMPn capture/compare register 1 (TPnCCR1) * TMPn counter read buffer register (TPnCNT) Remarks 1. When using the functions of the TIPn0, TIPn1,TOPn0, and TOPn1 pins, see Table 4-15 Using Port Pin as Alternate-Function Pin. 2. n = 0 to 5 User's Manual U16541EJ5V1UD 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TPnCTL0 register by software. After reset: 00H R/W Address: TP0CTL0 FFFFF590H, TP1CTL0 FFFFF5A0H, TP2CTL0 FFFFF5B0H, TP3CTL0 FFFFF5C0H, TP4CTL0 FFFFF5D0H, TP5CTL0 FFFFF5E0H TPnCTL0 <7> 6 5 4 3 TPnCE 0 0 0 0 2 1 0 TPnCKS2 TPnCKS1 TPnCKS0 (n = 0 to 5) TPnCE TMPn operation control 0 TMPn operation disabled (TMPn reset asynchronouslyNote). 1 TMPn operation enabled. TMPn operation started. TPnCKS2 TPnCKS1 TPnCKS0 Internal count clock selection n = 0, 2, 4 <R> n = 1, 3, 5 0 0 0 fXX 0 0 1 fXX/2 0 1 0 fXX/4 0 1 1 fXX/8 1 0 0 fXX/16 1 0 1 fXX/32 1 1 0 fXX/64 fXX/256 1 1 1 fXX/128 fXX/512 Note The TPnOPT0.TPnOVF bit and 16-bit counter are reset at the same time. In addition, the timer output pins (TOPn0 and TOPn1 pins) are reset to the status set by the TPnIOC0 register when the 16-bit counter is reset. Cautions 1. Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0. When the value of the TPnCE bit is changed from 0 to 1, the TPnCKS2 to TPnCKS0 bits can be set simultaneously. 2. Be sure to clear bits 3 to 6 to "0". Remark fXX: Main clock frequency (2) TMPn control register 1 (TPnCTL1) The TPnCTL1 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. 228 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) After reset: 00H R/W Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H, TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H, TP4CTL1 FFFFF5D1H, TP5CTL1 FFFFF5E1H TPnCTL1 7 <6> <5> 4 3 0 TPnEST TPnEEE 0 0 2 1 0 TPnMD2 TPnMD1 TPnMD0 (n = 0 to 5) <R> TPnEST Software trigger control 0 - 1 Generate a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TPnEST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TPnEST bit as the trigger. The read value of the TPnEST bit is always 0. TPnEEE Count clock selection 0 Disable operation with external event count input (TIPn0 pin). (Perform counting with the count clock selected by the TPnCTL0.TPnCKS0 to TPnCKS2 bits.) 1 Enable operation with external event count input (TIPn0 pin). (Perform counting at the valid edge of the external event count input signal (TIPn0 pin).) The TPnEEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. TPnMD2 TPnMD1 TPnMD0 Timer mode selection 0 0 0 Interval timer mode 0 0 1 External event count mode 0 1 0 External trigger pulse output mode 0 1 1 One-shot pulse output mode 1 0 0 PWM output mode 1 0 1 Free-running timer mode 1 1 0 Pulse width measurement mode 1 1 1 Setting prohibited Cautions 1. The TPnEST bit is valid only in the external trigger pulse output mode or the one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. External event count input is selected in the external event count mode regardless of the value of the TPnEEE bit. 3. Set the TPnEEE and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) The operation is not guaranteed when rewriting is performed with the TPnCE bit = 1. If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits again. 4. Be sure to clear bits 3, 4, and 7 to "0". User's Manual U16541EJ5V1UD 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. 230 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) After reset: 00H R/W Address: TP0IOC0 FFFFF592H, TP1IOC0 FFFFF5A2H, TP2IOC0 FFFFF5B2H, TP3IOC0 FFFFF5C2H, TP4IOC0 FFFFF5D2H, TP5IOC0 FFFFF5E2H TPnIOC0 7 6 5 4 0 0 0 0 3 <2> TPnOL1 TPnOE1 1 <0> TPnOL0 TPnOE0 (n = 0 to 5) TOPn1 pin output level settingNote TPnOL1 <R> 0 TOPn1 pin high level start 1 TOPn1 pin low level start TPnOE1 TOPn1 pin output setting 0 Timer output disabled * When TPnOL1 bit = 0: Low level is output from the TOPn1 pin * When TPnOL1 bit = 1: High level is output from the TOPn1 pin 1 Timer output enabled (a pulse is output from the TOPn1 pin). TOPn0 pin output level settingNote TPnOL0 <R> 0 TOPn0 pin high level start 1 TOPn0 pin low level start TPnOE0 <R> TOPn0 pin output setting 0 Timer output disabled * When TPnOL0 bit = 0: Low level is output from the TOPn0 pin * When TPnOL0 bit = 1: High level is output from the TOPn0 pin 1 Timer output enabled (a pulse is output from the TOPn0 pin). Note The output level of the timer output pins (TOPn0, TOPn1) specified by the TPnOLm bit is shown below (m = 0, 1). * When TPnOLm bit = 0 * When TPnOLm bit = 1 16-bit counter <R> 16-bit counter TPnCE bit TPnCE bit TOPnm pin output TOPnm pin output Cautions 1. The pin output changes if the setting of the TPnIOC0 register is rewritten when the port is set to output TOPn0 and TOPn1. Therefore, note changes in the pin status by setting the port to the input mode and making the output status of the pins a high-impedance state. 2. Rewrite the TPnOL1, TPnOE1, TPnOL0, and TPnOE0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits again. 3. Even if the TPnOLm bit is manipulated when the TPnCE and TPnOEm bits are 0, the TOPnm pin output level varies (m = 0, 1). User's Manual U16541EJ5V1UD 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). <R> This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TP0IOC1 FFFFF593H, TP1IOC1 FFFFF5A3H, TP2IOC1 FFFFF5B3H, TP3IOC1 FFFFF5C3H, TP4IOC1 FFFFF5D3H, TP5IOC1 FFFFF5E3H TPnIOC1 7 6 5 4 3 2 1 0 0 0 0 0 TPnIS3 TPnIS2 TPnIS1 TPnIS0 TPnIS3 TPnIS2 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TPnIS1 TPnIS0 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges (n = 0 to 5) Capture trigger input signal (TIPn1 pin) valid edge setting Capture trigger input signal (TIPn0 pin) valid edge setting Cautions 1. Rewrite the TPnIS3 to TPnIS0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits again. 2. The TPnIS3 to TPnIS0 bits are valid only in the free-running timer mode (only when TPnOPT0.TPnCCS1, TPnCCS0 bits = 11) and the pulse width measurement mode. In all other modes, a capture operation is not possible. 232 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TP0IOC2 FFFFF594H, TP1IOC2 FFFFF5A4H, TP2IOC2 FFFFF5B4H, TP3IOC2 FFFFF5C4H, TP4IOC2 FFFFF5D4H, TP5IOC2 FFFFF5E4H TPnIOC2 7 6 5 4 0 0 0 0 3 2 1 0 TPnEES1 TPnEES0 TPnETS1 TPnETS0 (n = 0 to 5) TPnEES1 TPnEES0 External event count input signal (TIPn0 pin) valid edge setting 0 0 No edge detection (external event count invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TPnETS1 TPnETS0 External trigger input signal (TIPn0 pin) valid edge setting 0 0 No edge detection (external trigger invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges Cautions 1. Rewrite the TPnEES1, TPnEES0, TPnETS1, and TPnETS0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits again. 2. The TPnEES1 and TPnEES0 bits are valid only when the TPnCTL1.TPnEEE bit = 1 or when the external event count mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 001) has been set. 3. The TPnETS1 and TPnETS0 bits are valid only when the external trigger pulse output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 010) or the one-shot pulse output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 = 011) is set. User's Manual U16541EJ5V1UD 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: TP0OPT0 FFFFF595H, TP1OPT0 FFFFF5A5H, TP2OPT0 FFFFF5B5H, TP3OPT0 FFFFF5C5H, TP4OPT0 FFFFF5D5H, TP5OPT0 FFFFF5E5H TPnOPT0 7 6 0 0 5 4 TPnCCS1 TPnCCS0 3 2 1 <0> 0 0 0 TPnOVF (n = 0 to 5) TPnCCS1 <R> TPnCCR1 register capture/compare selection 0 Compare register selected 1 Capture register selected (cleared by setting TPnCTL0.TPnCE bit = 0) The TPnCCS1 bit setting is valid only in the free-running timer mode. TPnCCS0 <R> TPnCCR0 register capture/compare selection 0 Compare register selected 1 Capture register selected (cleared by setting TPnCTL0.TPnCE bit = 0) The TPnCCS0 bit setting is valid only in the free-running timer mode. TPnOVF TMPn overflow detection flag Set (1) Overflow occurred Reset (0) TPnOVF bit 0 written or TPnCTL0.TPnCE bit = 0 * The TPnOVF bit is set to 1 when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An overflow interrupt request signal (INTTPnOV) is generated at the same time that the TPnOVF bit is set to 1. The INTTPnOV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TPnOVF bit is not cleared to 0 even when the TPnOVF bit or the TPnOPT0 register are read when the TPnOVF bit = 1. * Before clearing the TPnOVF bit to 0 after the INTTPnOV signal has been generated, be sure to confirm (read) that the TPnOVF bit is set to 1. * The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be set to 1 by software. Writing 1 has no influence on the operation of TMPn. <R> Cautions 1. Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and then set the bits again. 2. Be sure to clear bits 1 to 3, 6, and 7 to "0". 234 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit. In the pulse width measurement mode, the TPnCCR0 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TPnCCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TPnCCR0 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R/W Address: TP0CCR0 FFFFF596H, TP1CCR0 FFFFF5A6H, TP2CCR0 FFFFF5B6H, TP3CCR0 FFFFF5C6H, TP4CCR0 FFFFF5D6H, TP5CCR0 FFFFF5E6H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPnCCR0 (n = 0 to 5) User's Manual U16541EJ5V1UD 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated. If TOPn0 pin output is enabled at this time, the output of the TOPn0 pin is inverted. When the TPnCCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. <R> The compare register is not cleared when the TPnCTL0.TPnCE bit = 0. (b) Function as capture register When the TPnCCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TPnCCR0 register if the valid edge of the capture trigger input pin (TIPn0 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TPnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIPn0) is detected. Even if the capture operation and reading the TPnCCR0 register conflict, the correct value of the TPnCCR0 register can be read. <R> The capture register is cleared when the TPnCTL0.TPnCE bit = 0. Remark n = 0 to 5 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode <R> <R> Capture/Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None <R> Note Triggered by writing to the TPnCCR1 register <R> Remark 236 How to Write Compare Register Note Note For details of anytime write and batch write, see 7.6 (2) Anytime write and batch write. User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit. In the pulse width measurement mode, the TPnCCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TPnCCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TPnCCR1 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R/W Address: TP0CCR1 FFFFF598H, TP1CCR1 FFFFF5A8H, TP2CCR1 FFFFF5B8H, TP3CCR1 FFFFF5C8H, TP4CCR1 FFFFF5D8H, TP5CCR1 FFFFF5E8H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPnCCR1 (n = 0 to 5) User's Manual U16541EJ5V1UD 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. If TOPn1 pin output is enabled at this time, the output of the TOPn1 pin is inverted. <R> The compare register is not cleared when the TPnCTL0.TPnCE bit = 0. (b) Function as capture register When the TPnCCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TPnCCR1 register if the valid edge of the capture trigger input pin (TIPn1 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TPnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIPn1) is detected. Even if the capture operation and reading the TPnCCR1 register conflict, the correct value of the TPnCCR1 register can be read. <R> The capture register is cleared when the TPnCTL0.TPnCE bit = 0. Remark n = 0 to 5 The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode <R> <R> Capture/Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Note Note Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None <R> Note Triggered by writing to the TPnCCR1 register <R> Remark 238 How to Write Compare Register For anytime write and batch write, see 7.6 (2) Anytime write and batch write. User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TPnCNT register is cleared to 0000H when the TPnCE bit = 0. If the TPnCNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TPnCNT register is cleared to 0000H after reset, as the TPnCE bit is cleared to 0. Caution Accessing the TPnCNT register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H R Address: TP0CNT FFFFF59AH, TP1CNT FFFFF5AAH, TP2CNT FFFFF5BAH, TP3CNT FFFFF5CAH, TP4CNT FFFFF5DAH, TP5CNT FFFFF5EAH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPnCNT (n = 0 to 5) User's Manual U16541EJ5V1UD 239 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5 Timer Output Operations The following table shows the operations and output levels of the TOPn0 and TOPn1 pins. Table 7-4. Timer Output Control in Each Mode Operation Mode TOPn1 Pin TOPn0 Pin Interval timer mode Square wave output External event count mode None External trigger pulse output mode External trigger pulse output One-shot pulse output mode One-shot pulse output PWM output mode PWM output Free-running timer mode Square wave output (only when compare function is used) Pulse width measurement mode None Remark Square wave output n = 0 to 5 Table 7-5. Truth Table of TOPn0 and TOPn1 Pins Under Control of Timer Output Control Bits TPnIOC0.TPnOLm Bit TPnIOC0.TPnOEm Bit TPnCTL0.TPnCE Bit Level of TOPnm Pin 0 0 x 1 0 Low-level output 1 Low level immediately before counting, high Low-level output level after counting is started 1 0 x High-level output 1 0 High-level output 1 High level immediately before counting, low level after counting is started Remark n = 0 to 5 m = 0, 1 240 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6 Operation TMPn can perform the following operations. TPnCTL1.TPnEST Bit Operation TIPn0 Pin (Software Trigger Bit) (External Trigger Input) Interval timer mode External event count mode Invalid Note 1 External trigger pulse output mode One-shot pulse output mode Note 2 Note 2 PWM output mode Free-running timer mode Pulse width measurement mode Note 2 Invalid Capture/Compare Compare Register Register Setting Write Compare only Anytime write Invalid Invalid Compare only Anytime write Valid Valid Compare only Batch write Valid Valid Compare only Anytime write Invalid Invalid Compare only Batch write Invalid Invalid Switching enabled Anytime write Invalid Invalid Capture only Not applicable Notes 1. To use the external event count mode, specify that the valid edge of the TIPn0 pin capture trigger input is not detected (by clearing the TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to "00"). 2. To use the external trigger pulse output mode, one-shot pulse output mode, or pulse width measurement mode, select the internal clock (by setting the TPnCTL1.TPnEEE bit to 0) as the count clock. Remark n = 0 to 5 User's Manual U16541EJ5V1UD 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) <R> (1) Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. Remark n = 0 to 5 (a) Counter start operation The 16-bit counter of TMPn starts counting from the default value FFFFH in all modes. It counts up from FFFFH to 0000H, 0001H, 0002H, 0003H, and so on. (b) Clear operation The 16-bit counter is cleared to 0000H when its value matches the value of the compare register and is cleared, and when its value is captured and cleared. The counting operation from FFFFH to 0000H that takes place immediately after the counter has started counting or when the counter overflows is not a clearing operation. Therefore, the INTTPnCC0 and INTTPnCC1 interrupt signals are not generated. (c) Overflow operation The 16-bit counter overflows when the counter counts up from FFFFH to 0000H in the free-running timer mode or pulse width measurement mode. If the counter overflows, the TPnOPT0.TPnOVF bit is set to 1 and an interrupt request signal (INTTPnOV) is generated. Note that the INTTPnOV signal is not generated under the following conditions. * Immediately after a counting operation has been started * If the counter value matches the compare value FFFFH and is cleared * When FFFFH is captured and cleared in the pulse width measurement mode and the counter counts up from FFFFH to 0000H Caution After the overflow interrupt request signal (INTTPnOV) has been generated, be sure to check that the overflow flag (TPnOVF bit) is set to 1. (d) Counter read operation during counting operation The value of the 16-bit counter of TMPn can be read by using the TPnCNT register during the count operation. When the TPnCTL0.TPnCE bit = 1, the value of the 16-bit counter can be read by reading the TPnCNT register. When the TPnCTL0.TPnCE bit = 0, the 16-bit counter is FFFFH and the TPnCNT register is 0000H. (e) Interrupt operation TMPn generates the following three types of interrupt request signals. * INTTPnCC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register and as a capture interrupt request signal to the TPnCCR0 register. * INTTPnCC1 interrupt: This signal functions as a match interrupt request signal of the CCR1 buffer register and as a capture interrupt request signal to the TPnCCR1 register. * INTTPnOV interrupt: This signal functions as an overflow interrupt request signal. 242 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) <R> (2) Anytime write and batch write The TPnCCR0 and TPnCCR1 registers in TMPn can be rewritten during timer operation (TPnCTL0.TPnCE bit = 1), but the write method (anytime write, batch write) of the CCR0 and CCR1 buffer registers differs depending on the mode. (a) Anytime write In this mode, data is transferred at any time from the TPnCCR0 and TPnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. (n = 0 to 5). Figure 7-2. Flowchart of Basic Operation for Anytime Write START Initial settings * Set values to TPnCCRm register * Timer operation enable (TPnCE bit = 1) Transfer values of TPnCCRm register to CCRm buffer register TPnCCRm register rewrite Transfer to CCRm buffer register Timer operation * Match between 16-bit counter and CCR1 buffer registerNote * Match between 16-bit counter and CCR0 buffer register * 16-bit counter clear & start INTTPnCC1 signal output INTTPnCC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Remarks 1. The above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0 to 5 m = 0, 1 User's Manual U16541EJ5V1UD 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-3. Timing of Anytime Write TPnCE bit = 1 D01 FFFFH D01 D02 16-bit counter D11 D11 D12 D12 0000H D01 TPnCCR0 register CCR0 buffer register 0000H D01 D11 TPnCCR1 register CCR1 buffer register D02 0000H D02 D12 D11 D12 INTTPnCC0 signal INTTPnCC1 signal Remarks 1. D01, D02: Setting values of TPnCCR0 register D11, D12: Setting values of TPnCCR1 register 2. The above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0 to 5 244 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Batch write In this mode, data is transferred all at once from the TPnCCR0 and TPnCCR1 registers to the CCR0 and CCR1 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TPnCCR1 register. Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TPnCCR1 register. In order for the setting value when the TPnCCR0 and TPnCCR1 registers are rewritten to become the 16bit counter comparison value (in other words, in order for this value to be transferred to the CCR0 and CCR1 buffer registers), it is necessary to rewrite the TPnCCR0 register and then write to the TPnCCR1 register before the 16-bit counter value and the CCR0 buffer register value match. Therefore, the values of the TPnCCR0 and TPnCCR1 registers are transferred to the CCR0 and CCR1 buffer registers upon a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Thus even when wishing only to rewrite the value of the TPnCCR0 register, also write the same value (same as preset value of the TPnCCR1 register) to the TPnCCR1 register. User's Manual U16541EJ5V1UD 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-4. Flowchart of Basic Operation for Batch Write START Initial settings * Set values to TPnCCRm register * Timer operation enable (TPnCE bit = 1) Transfer values of TPnCCRm register to CCRm buffer register TPnCCR0 register rewrite TPnCCR1 register rewrite Timer operation * Match between 16-bit counter and CCR1 buffer registerNote * Match between 16-bit counter and CCR0 buffer register * 16-bit counter clear & start * Transfer of values of TPnCCRm register to CCRm buffer register Batch write enable INTTPnCC1 signal output INTTPnCC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCR1 buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Caution Writing to the TPnCCR1 register includes enabling of batch write. Thus, rewrite the TPnCCR1 register after rewriting the TPnCCR0 register. Remarks 1. The above flowchart illustrates an example of the operation in the PWM output mode. 2. n = 0 to 5 m = 0, 1 246 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-5. Timing of Batch Write TPnCE bit = 1 D01 FFFFH D02 D11 D12 16-bit counter D03 D02 D12 D12 D12 0000H TPnCCR0 register D01 CCR0 buffer register 0000H TPnCCR1 register CCR1 buffer register 0000H D02 D01 D11 D03 D02 Note 1 Note 2 D12 D11 Note 1 Same value write D12 Note 3 D12 Note 1 D03 D12 Note 1 INTTPnCC0 signal INTTPnCC1 signal TOPn0 pin output TOPn1 pin output Notes 1. Because the TPnCCR1 register was not rewritten, D03 is not transferred. 2. Because the TPnCCR1 register has been written (D12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TPnCCR0 register (D01). 3. Because the TPnCCR1 register has been written (D12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit counter and the value of the TPnCCR0 register (D02). Remarks 1. D01, D02, D03: Setting values of TPnCCR0 register D11, D12: Setting values of TPnCCR1 register 2. The above timing chart illustrates the operation in the PWM output mode as an example. 3. n = 0 to 5 User's Manual U16541EJ5V1UD 247 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) <R> 7.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the interval set by the TPnCCR0 register if the TPnCTL0.TPnCE bit is set to 1. A square wave with a duty factor of 50% whose half cycle is equal to the interval can be output from the TOPn0 pin. The TPnCCR1 register is not used in the interval timer mode. However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register, and when the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. In addition, a square wave with a duty factor of 50%, which is inverted when the INTTPnCC1 signal is generated, can be output from the TOPn1 pin. The value of the TPnCCR0 and TPnCCR1 registers can be rewritten even while the timer is operating. Figure 7-6. Configuration of Interval Timer Clear Count clock selection Output controller 16-bit counter Match signal TPnCE bit TOPn0 pin INTTPnCC0 signal CCR0 buffer register TPnCCR0 register Remark n = 0 to 5 Figure 7-7. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter D0 D0 D0 D0 0000H TPnCE bit TPnCCR0 register D0 TOPn0 pin output INTTPnCC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Remark 248 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOPn0 pin is inverted, and a compare match interrupt request signal (INTTPnCC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TPnCCR0 register + 1) x Count clock cycle Remark n = 0 to 5 Figure 7-8. Register Setting for Interval Timer Mode Operation (1/3) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 TPnCKS2 TPnCKS1 TPnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnCTL1 0 0 0/1Note TPnMD2 TPnMD1 TPnMD0 0 0 0 0 0 0, 0, 0: Interval timer mode 0: Operate on count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count with external event count input signal <R> Note The TPnEEE bit can be set to 1 only when the timer output (TOPn1) is used. However, set the TPnCCR0 and TPnCCR1 registers to the same value. User's Manual U16541EJ5V1UD 249 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-8. Register Setting for Interval Timer Mode Operation (2/3) (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting to output level of TOPn0 pin before count operation 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Setting to output level of TOPn1 pin before count operation 0: Low level 1: High level <R> (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1Note 0/1Note 0 0 Select valid edge of external event count input (TIPn0 pin). Note The TPnEES1 and TPnEES0 bits can be set only when the timer output (TOPn1) is used. However, set the TPnCCR0 and TPnCCR1 registers to the same value. (e) TMPn counter read buffer register (TPnCNT) By reading the TPnCNT register, the count value of the 16-bit counter can be read. (f) TMPn capture/compare register 0 (TPnCCR0) If the TPnCCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle Remark 250 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-8. Register Setting for Interval Timer Mode Operation (3/3) <R> (g) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is not used in the interval timer mode. However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, the TOPn1 pin output is inverted and a compare match interrupt request signal (INTTPnCC1) is generated. By setting this register to the same value as the value set in the TPnCCR0 register, a square wave with a duty factor of 50% can be output from the TOPn1 pin. When the TPnCCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the register by the interrupt mask flag (TPnCCIC1.TPnCCMK1). Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the interval timer mode. 2. n = 0 to 5 User's Manual U16541EJ5V1UD 251 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 7-9. Software Processing Flow in Interval Timer Mode FFFFH D0 16-bit counter D0 D0 0000H TPnCE bit TPnCCR0 register D0 TOPn0 pin output INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 registerNote, TPnCCR0 register <R> TPnCE bit = 1 Initial setting of these registers is performed before setting the TPnCE bit to 1. The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started (TPnCE bit = 1). Note The TPnEES1 and TPnEES0 bits can be set only when timer output (TOPn1) is used. However, set the TPnCCR0 and TPnCCR1 registers to the same value. <R> <2> Count operation stop flow TPnCE bit = 0 The counter is initialized and counting is stopped by clearing the TPnCE bit to 0. The output level of the TOPn0 pin is as specified by the TPnIOC0 register. STOP Remark 252 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing <R> (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock, and the output of the TOPn0 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH 0000H 0000H 0000H 0000H TPnCE bit TPnCCR0 register 0000H TOPn0 pin output INTTPnCC0 signal Interval time Interval time Interval time Count clock cycle Count clock cycle Count clock cycle Remark n = 0 to 5 User's Manual U16541EJ5V1UD 253 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted. At this time, an overflow interrupt request signal (INTTPnOV) is not generated, nor is the overflow flag (TPnOPT0.TPnOVF bit) set to 1. FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register FFFFH TOPn0 pin output INTTPnCC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle Remark 254 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register When the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH D1 D1 16-bit counter D2 D2 D2 0000H TPnCE bit D1 TPnCCR0 register TPnOL0 bit D2 L TOPn0 pin output INTTPnCC0 signal Interval time (1) Interval time (NG) Interval time (2) Remarks 1. Interval time (1): (D1 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle Interval time (2): (D2 + 1) x Count clock cycle 2. n = 0 to 5 If the value of the TPnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TPnCCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted. Therefore, the INTTPnCC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock period". User's Manual U16541EJ5V1UD 255 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register Figure 7-10. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Output controller Match signal TOPn1 pin INTTPnCC1 signal Clear Count clock selection 16-bit counter Match signal TPnCE bit CCR0 buffer register TPnCCR0 register Remark 256 n = 0 to 5 User's Manual U16541EJ5V1UD Output controller TOPn0 pin INTTPnCC0 signal CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) <R> When the TPnCCR1 register is set to the same value as the TPnCCR0 register, the INTTPnCC1 signal is generated at the same timing as the INTTPnCC0 signal and the TOPn1 pin output is inverted. In other words, a square wave with a duty factor of 50% can be output from the TOPn1 pin. The following shows the operation when the TPnCCR1 register is set to other than the value set in the TPnCCR0 register. If the set value of the TPnCCR1 register is less than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle. At the same time, the output of the TOPn1 pin is inverted. The TOPn1 pin outputs a square wave with a duty factor of 50% after outputting a short-width pulse. Figure 7-11. Timing Chart When D01 D11 FFFFH D01 16-bit counter D11 D01 D11 D01 D11 D01 D11 0000H TPnCE bit TPnCCR0 register D01 TOPn0 pin output INTTPnCC0 signal TPnCCR1 register D11 TOPn1 pin output INTTPnCC1 signal Remark n = 0 to 5 User's Manual U16541EJ5V1UD 257 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed. When the TPnCCR1 register is not used, it is recommended to set its value to FFFFH. <R> Figure 7-12. Timing Chart When D01 < D11 FFFFH D01 D01 D01 16-bit counter 0000H TPnCE bit TPnCCR0 register D01 TOPn0 pin output INTTPnCC0 signal D11 TPnCCR1 register TOPn1 pin output INTTPnCC1 signal Remark 258 L n = 0 to 5 User's Manual U16541EJ5V1UD D01 Consequently, the CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) <R> (3) Operation by external event count input (TIPn0) (a) Operation To count the 16-bit counter at the valid edge of external event count input (TIPn0) in the interval timer mode, the valid edge of the external event count input is necessary once because the 16-bit counter is cleared from FFFFH to 0000H immediately after the TPnCE bit is set from 0 to 1. When 0001H is set to both the TPnCCR0 and TPnCCR1 registers, the TOPn1 pin output is inverted each time the 16-bit counter counts twice. The TPnCTL1.TPnEEE bit can be set to 1 in the interval timer mode only when the timer output (TOPn1) is used with the external event count input. FFFFH 0001H 0001H 16-bit counter 0001H 0000H TPnCE bit External event count input (TIPn0 pin input) TPnCCR0 register 0001H 0001H 0001H TPnCCR1 register 0001H 0001H 0001H TOPn1 pin output 2-count width Number of external events: 3 Remark 2-count width 2-count width Number of external events: 2 Number of external events: 2 n = 0 to 5 User's Manual U16541EJ5V1UD 259 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input (TIPn0) is counted when the <R> TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the number of edges set by the TPnCCR0 register have been counted. The TOPn0 and TOPn1 pins cannot be used. When using the TOPn1 pin for external event count input, set the TPnCTL1.TPnEEE bit to 1 in the interval timer mode (see 7.6.1 (3) Operation by external event count input (TIPn0)). The TPnCCR1 register is not used in the external event count mode. <R> Caution In the external event count mode, the TPnCCR0 and TPnCCR1 registers must not be cleared to 0000H. Figure 7-13. Configuration in External Event Count Mode Clear TIPn0 pin (external event count input) Edge detector 16-bit counter Match signal TPnCE bit CCR0 buffer register TPnCCR0 register Remark 260 n = 0 to 5 User's Manual U16541EJ5V1UD INTTPnCC0 signal CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-14. Basic Timing in External Event Count Mode FFFFH 16-bit counter D0 D0 D0 0000H 16-bit counter TPnCE bit External event count input (TIPn0 pin input) TPnCCR0 register TPnCCR0 register D0 <R> D0 0000 0001 D0 INTTPnCC0 signal INTTPnCC0 signal <R> D0 - 1 Number of external event count (D0)Note times Number of external event count (D0 + 1) times Number of external event count (D0 + 1) times Note In the external event count mode, when the TPnCTL0.TPnCE bit is set to 1 (operation starts), the 16-bit counter is cleared from FFFFH to 0000H at the same time. The first count operation starts from 0001H each time the valid edge of the external event count input is detected. Therefore, the count of the first count operation is one number smaller than the count of the second or subsequent count operation. Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. 2. n = 0 to 5 User's Manual U16541EJ5V1UD 261 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTPnCC0) is generated. <R> The INTTPnCC0 signal is generated for the first time when the valid edge of the external event count input has been detected "value set to TPnCCR0 register" times. After that, the INTTPnCC0 signal is generated each time the valid edge of the external event count input has been detected "value set to TPnCCR0 register + 1" times. Figure 7-15. Register Setting for Operation in External Event Count Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 TPnCKS2 TPnCKS1 TPnCKS0 0 0 0 0 0 0 0 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnCTL1 0 0 0 TPnMD2 TPnMD1 TPnMD0 0 0 0 0 1 0, 0, 1: External event count mode (c) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (TIPn0 pin) 262 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-15. Register Setting for Operation in External Event Count Mode (2/2) (d) TMPn counter read buffer register (TPnCNT) The count value of the 16-bit counter can be read by reading the TPnCNT register. <R> (e) TMPn capture/compare register 0 (TPnCCR0) If the TPnCCR0 register is set to D0, the count is cleared when the number of external events has reached (D0) and the first compare match interrupt request signal (INTTPnCC0) is generated. The second compare match interrupt request signal (INTTPnCC0) is generated when the number of external events has reached (D0 + 1). <R> (f) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register is not used in the external event count mode. However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. When the TPnCCR1 registers are not used, it is recommended to set their value to FFFFH. Also mask the register by the interrupt mask flag (TPnCCIC1.TPnCCMK1). Cautions 1. Set 00H to the TPnIOC0 register. <R> 2. When the external clock is used as the count clock, the external clock can be input only from the TIPn0 pin. At this time, clear the TPnIOC1.TPnIS1 and TPnIS0 bits to 00 (capture trigger input (TIPn0 pin): No edge detected). Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the external event count mode. 2. n = 0 to 5 User's Manual U16541EJ5V1UD 263 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 7-16. Flow of Software Processing in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H TPnCE bit TPnCCR0 register D0 INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting TPnCTL1 register, TPnIOC2 register, TPnCCR0, TPnCCR1 registers Initial setting of these registers is performed before the TPnCE bit is set to 1. TPnCE bit = 1 <2> Count operation stop flow TPnCE bit = 0 The counter is initialized and counting is stopped by clearing the TPnCE bit to 0. STOP Remark 264 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TPnCCR0 and TPnCCR1 registers to 0000H. 2. In the external event count mode, use of the timer output (TOPn0, TOPn1) is disabled. If performing timer output (TOPn1) using external event count input (TIPn0), set the interval timer mode, and set the operation enabled (TPnCTL1.TPnEEE bit = 1) by the external event count input for the count clock (refer to 7.6.1 (3) Operation by external event count input (TIPn0)). (a) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTPnCC0 signal is generated. At this time, the TPnOPT0.TPnOVF bit is not set. FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register FFFFH INTTPnCC0 signal Number of external event count FFFFH times <R> Remark Number of external event count 10000H times Number of external event count 10000H times n = 0 to 5 User's Manual U16541EJ5V1UD 265 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TPnCCR0 register When the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH D1 16-bit counter D1 D2 D2 D2 0000H TPnCE bit TPnCCR0 register D1 D2 INTTPnCC0 signal Number of external event count (1) (D1) times <R> Remark Number of external event count (NG) (10000H + D2 + 1) times Number of external event count (2) (D2 + 1) times n = 0 to 5 If the value of the TPnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TPnCCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTPnCC0 signal is generated. Therefore, the INTTPnCC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times". 266 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPnCCR1 register Figure 7-17. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Match signal INTTPnCC1 signal Clear TIPn0 pin (external event count input) Edge detector 16-bit counter Match signal TPnCE bit INTTPnCC0 signal CCR0 buffer register TPnCCR0 register Remark n = 0 to 5 If the set value of the TPnCCR1 register is smaller than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle. Figure 7-18. Timing Chart When D01 D11 FFFFH D01 16-bit counter D11 D01 D11 D01 D11 D01 D11 0000H TPnCE bit TPnCCR0 register D01 INTTPnCC0 signal TPnCCR1 register D11 INTTPnCC1 signal Remark n = 0 to 5 User's Manual U16541EJ5V1UD 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match. <R> It is recommended to set FFFFH to the TPnCCR1 register when the TPnCCR1 register is not used. Figure 7-19. Timing Chart When D01 < D11 FFFFH D01 D01 D01 16-bit counter 0000H TPnCE bit TPnCCR0 register D01 INTTPnCC0 signal D11 TPnCCR1 register INTTPnCC1 signal Remark 268 L n = 0 to 5 User's Manual U16541EJ5V1UD D01 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input (TIPn0) is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave with a duty factor of 50% that has the set value of the TPnCCR0 register + 1 as half its cycle can also be output from the TOPn0 pin. Figure 7-20. Configuration in External Trigger Pulse Output Mode TIPn0 pinNote (external trigger input) Edge detector TPnCCR1 register Transfer Software trigger generation S Output controller R (RS-FF) CCR1 buffer register Match signal TOPn1 pin INTTPnCC1 signal Clear Count clock selection Count start control 16-bit counter Output controller Match signal TPnCE bit TOPn0 pinNote INTTPnCC0 signal CCR0 buffer register Transfer TPnCCR0 register <R> Note Because the external trigger input pin (TIPn0) and timer output pin (TOPn0) share the same alternatefunction pin, two functions cannot be used at the same time. <R> Caution In external trigger pulse output mode, select the internal clock (set TPnCTL1.TPnEEE bit = 0) as the count clock. Remark n = 0 to 5 User's Manual U16541EJ5V1UD 269 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-21. Basic Timing in External Trigger Pulse Output Mode FFFFH D0 D1 16-bit counter D0 D0 D1 D1 D0 D1 0000H TPnCE bit External trigger input (TIPn0 pin input) D0 TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) D1 TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Wait Active level for width (D1) trigger Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) 16-bit timer/event counter P waits for a trigger when the TPnCE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM wave\form from the TOPn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOPn0 pin is inverted. The TOPn1 pin outputs a high-level regardless of the status (high/low) when a trigger occurs.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TPnCCR1 register) x Count clock cycle Cycle = (Set value of TPnCCR0 register + 1) x Count clock cycle Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1) The compare match request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input (TIPn0) signal, or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as the trigger. Remark 270 n = 0 to 5, m = 0, 1 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clock <R> 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE <R> TPnCTL1 0 0/1 TPnMD2 TPnMD1 TPnMD0 0 0 0 0 1 0 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TPnCKS0 to TPnCKS2 bits Generate software trigger when 1 is written (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1Note 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting level of TOPn1 pin in status of waiting for external trigger 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Setting level of TOPn1 pin in status of waiting for external trigger 0: Low level 1: High level * When TPnOL1 bit = 0 * When TPnOL1 bit = 1 16-bit counter 16-bit counter TOPn1 pin output TOPn1 pin output Note Clear this bit to 0 when the TOPn0 pin is not used in the external trigger pulse output mode. User's Manual U16541EJ5V1UD 271 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 <R> TPnIOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (TIPn0 pin) (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) If D0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the external trigger pulse output mode. 2. n = 0 to 5 272 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 7-23. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH D01 16-bit counter D00 D10 D00 D10 D01 D01 D11 D10 D11 D00 D10 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) D10 TPnCCR1 register D10 D11 D10 CCR1 buffer register D10 D10 D11 D10 INTTPnCC1 signal TOPn1 pin output <1> Remark <2> <3> <4> <5> n = 0 to 5 User's Manual U16541EJ5V1UD 273 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-23. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> PnCCR0, TPnCCR1 register setting change flow START Setting of TPnCCR1 register Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnCCR0 register, TPnCCR1 register TPnCE bit = 1 Initial setting of these registers is performed before setting the TPnCE bit to 1. Only writing of the TPnCCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. <4> PnCCR0, TPnCCR1 register setting change flow The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting is enabled (TPnCE bit = 1). Trigger wait status Setting of TPnCCR0 register When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. Setting of TPnCCR1 register <2> TPnCCR0 and TPnCCR1 register setting change flow Setting of TPnCCR0 register Setting of TPnCCR1 register Remark <5> Count operation stop flow Writing the same value (same as the TPnCCR1 register already set) to the TPnCCR1 register is necessary only when the set cycle is changed. TPnCE bit = 0 STOP When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. n = 0 to 5 m = 0, 1 274 User's Manual U16541EJ5V1UD Counting is stopped. CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected. FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D11 D01 D11 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register D00 D01 D00 D01 INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register CCR1 buffer register D10 D10 D11 D11 INTTPnCC1 signal TOPn1 pin output Remark n = 0 to 5 User's Manual U16541EJ5V1UD 275 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level width to the TPnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TPnCCR0 register, and then write the same value (same as the TPnCCR1 register already set) to the TPnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TPnCCR1 register has to be set. After data is written to the TPnCCR1 register, the value written to the TPnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TPnCCR0 or TPnCCR1 register again after writing the TPnCCR1 register once, do so after the INTTPnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TPnCCRm register to the CCRm buffer register conflicts with writing the TPnCCRm register. Remark n = 0 to 5 m = 0, 1 276 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform <R> To output a 0% waveform, set the TPnCCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTPnCO0 and INTTPnCC1 signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TPnCE bit <R> External trigger input (TIPn0 pin input) TPnCCR0 register D0 D0 D0 TPnCCR1 register 0000H 0000H 0000H INTTPnCC0 signal INTTPnCC1 signal TOPn1 pin output Remark L n = 0 to 5 To output a 100% waveform, set a value of (set value of TPnCCR0 register + 1) to the TPnCCR1 register. If the set value of the TPnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TPnCE bit <R> External trigger input (TIPn0 pin input) TPnCCR0 register D0 D0 D0 TPnCCR1 register D0 + 1 D0 + 1 D0 + 1 INTTPnCC0 signal INTTPnCC1 signal TOPn1 pin output Remark n = 0 to 5 User's Manual U16541EJ5V1UD 277 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with CCR1 buffer register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF D1 - 1 0000 0000 External trigger input (TIPn0 pin input) D1 CCR1 buffer register INTTPnCC1 signal TOPn1 pin output Shortened Remark n = 0 to 5 If the trigger is detected immediately before the INTTPnCC1 signal is generated, the INTTPnCC1 signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOPn1 pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter FFFF 0000 D1 - 2 0000 External trigger input (TIPn0 pin input) CCR1 buffer register D1 INTTPnCC1 signal TOPn1 pin output Extended Remark 278 n = 0 to 5 User's Manual U16541EJ5V1UD 0001 D1 - 1 D1 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0000 External trigger input (TIPn0 pin input) D0 CCR0 buffer register INTTPnCC0 signal TOPn1 pin output Extended Remark n = 0 to 5 If the trigger is detected immediately before the INTTPnCC0 signal is generated, the INTTPnCC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOPn1 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 External trigger input (TIPn0 pin input) CCR0 buffer register D0 INTTPnCC0 signal TOPn1 pin output Shortened Remark n = 0 to 5 User's Manual U16541EJ5V1UD 279 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other mode INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register. Count clock 16-bit counter TPnCCR1 register D1 - 1 D1 - 1 D1 D1 + 1 D1 + 2 D1 TOPn1 pin output INTTPnCC1 signal Remark n = 0 to 5 Usually, the INTTPnCC1 signal is generated in synchronization with the next count up, after the count value of the 16-bit counter matches the value of the TPnCCR1 register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOPn1 pin. 280 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input (TIPn0) is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin. Instead of the external trigger input (TIPn0), a software trigger can also be generated to output the pulse. When the software trigger is used, the TOPn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 7-24. Configuration in One-Shot Pulse Output Mode TIPn0 pinNote (external trigger input) Edge detector TPnCCR1 register Transfer Software trigger generation S Output controller R (RS-FF) CCR1 buffer register Match signal Count clock selection INTTPnCC1 signal Clear Count start control S Output controller R (RS-FF) 16-bit counter Match signal TPnCE bit TOPn1 pin TOPn0 pinNote INTTPnCC0 signal CCR0 buffer register Transfer TPnCCR0 register <R> Note Because the external trigger input pin (TIPn0) and timer output pin (TOPn0) share the same alternate-function pin, two functions cannot be used at the same time. <R> Caution In one-shot pulse output mode, select the internal clock (set TPnCTL1.TPnEEE bit = 0) as the count clock. Remark n = 0 to 5 User's Manual U16541EJ5V1UD 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25. Basic Timing in One-Shot Pulse Output Mode FFFFH D0 16-bit counter D1 D0 D1 D0 D1 0000H TPnCE bit External trigger input (TIPn0 pin input) D0 TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) D1 TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Delay (D1) Active level width (D0 - D1 + 1) Delay (D1) Delay Active level width (D1) (D0 - D1 + 1) Active level width (D0 - D1 + 1) When the TPnCE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOPn1 pin. <R> After the one-shot pulse is output, the 16-bit counter is set to 0000H, stops counting, and waits for a trigger. When the trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TPnCCR1 register) x Count clock cycle Active level width = (Set value of TPnCCR0 register - Set value of TPnCCR1 register + 1) x Count clock cycle The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The valid edge of an external trigger input (TIPn0 pin) or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as the trigger. Remark n = 0 to 5 m = 0, 1 282 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clock <R> 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE <R> TPnCTL1 0 0/1 0 TPnMD2 TPnMD1 TPnMD0 0 0 0 1 1 0, 1, 1: One-shot pulse output mode 0: Operate on count clock selected by TPnCKS0 to TPnCKS2 bits Generate software trigger when 1 is written (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1Note 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of TOPn0 pin output level in status of waiting for external trigger 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Setting of TOPn1 pin output level in status of waiting for external trigger 0: Low level 1: High level * When TPnOL1 bit = 0 * When TPnOL1 bit = 1 16-bit counter 16-bit counter TOPn1 pin output TOPn1 pin output Note Clear this bit to 0 when the TOPn0 pin is not used in the one-shot pulse output mode. User's Manual U16541EJ5V1UD 283 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 <R> TPnIOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (TIPn0 pin) (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) If D0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D0 - D1 + 1) x Count clock cycle Output delay period = D1 x Count clock cycle <R> Caution The one-shot pulse is not output if the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register in the one-shot pulse output mode. Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the one-shot pulse output mode. 2. n = 0 to 5 284 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 7-27. Software Processing Flow in One-Shot Pulse Output Mode FFFFH D00 D01 16-bit counter D10 D11 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register D00 D01 D10 D11 INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output <2> <1> <1> Count operation start flow <3> <2> TPnCCR0, TPnCCR1 register setting change flow START Setting of TPnCCR0, TPnCCR1 registers Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnCCR0 register, TPnCCR1 register TPnCE bit = 1 Initial setting of these registers is performed before setting the TPnCE bit to 1. As rewriting the TPnCCRm register immediately forwards to the CCRm buffer register, rewriting immediately after the generation of the INTTPnCC0 signal is recommended. <3> Count operation stop flow The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting has been started (TPnCE bit = 1). Trigger wait status TPnCE bit = 0 Count operation is stopped STOP Remark n = 0 to 5 m = 0, 1 User's Manual U16541EJ5V1UD 285 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRm register When the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH D00 16-bit counter D00 D10 D10 D00 D10 D01 D11 0000H TPnCE bit External trigger input (TIPn0 pin input) D00 TPnCCR0 register D01 INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) D10 TPnCCR1 register D11 INTTPnCC1 signal TOPn1 pin output Delay (D10) Delay (D10) Active level width (D00 - D10 + 1) Active level width (D00 - D10 + 1) Delay (10000H + D11) Active level width (D01 - D11 + 1) When the TPnCCR0 register is rewritten from D00 to D01 and the TPnCCR1 register from D10 to D11 where D00 > D01 and D10 > D11, if the TPnCCR1 register is rewritten when the count value of the 16-bit counter is greater than D11 and less than D10 and if the TPnCCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches D11, the counter generates the INTTPnCC1 signal and asserts the TOPn1 pin. When the count value matches D01, the counter generates the INTTPnCC0 signal, deasserts the TOPn1 pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the one-shot pulse that is originally expected. Remark n = 0 to 5 m = 0, 1 286 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other mode INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register. Count clock 16-bit counter D1 - 2 D1 - 1 TPnCCR1 register D1 D1 + 1 D1 + 2 D1 TOPn1 pin output INTTPnCC1 signal Remark n = 0 to 5 Usually, the INTTPnCC1 signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TPnCCR1 register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the TOPn1 pin. Remark n = 0 to 5 User's Manual U16541EJ5V1UD 287 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1. In addition, a square wave with a duty factor of 50% with the set value of the TPnCCR0 register + 1 as half its cycle is output from the TOPn0 pin. <R> Figure 7-28. Configuration in PWM Output Mode TPnCCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal Internal count clock TIPn0 pinNote (external event count input) Edge detector Count clock selection INTTPnCC1 signal Clear Count start control 16-bit counter Output controller Match signal TPnCE bit TOPn1 pin TOPn0 pinNote INTTPnCC0 signal CCR0 buffer register Transfer TPnCCR0 register Note Because the external event count input pin (TIPn0) and timer output pin (TOPn0) share the same alternate-function pin, two or more functions cannot be used at the same time. Remark 288 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-29. Basic Timing in PWM Output Mode FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D11 D01 D11 0000H TPnCE bit TPnCCR0 register CCR0 buffer register D00 D01 D00 D01 INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register D10 D11 D10 D11 INTTPnCC1 signal TOPn1 pin output Active period Cycle (D10) (D00 + 1) Inactive period (D00 - D10 + 1) When the TPnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOPn1 pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TPnCCR1 register ) x Count clock cycle Cycle = (Set value of TPnCCR0 register + 1) x Count clock cycle Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1) The PWM waveform can be changed by rewriting the TPnCCRm register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H. Remark n = 0 to 5, m = 0, 1 User's Manual U16541EJ5V1UD 289 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-30. Setting of Registers in PWM Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 TPnCKS2 TPnCKS1 TPnCKS0 0/1 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnCTL1 0 0 0/1 TPnMD2 TPnMD1 TPnMD0 0 0 1 0 0 1, 0, 0: PWM output mode 0: Operate on count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count external event input signal (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1Note 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of TOPn0 pin output level before count operation 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Setting of TOPn1 pin output level before count operation 0: Low level 1: High level * When TPnOL1 bit = 0 * When TPnOL1 bit = 1 16-bit counter 16-bit counter TOPn1 pin output TOPn1 pin output Note Clear this bit to 0 when the TOPn0 pin is not used in the PWM output mode. 290 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-30. Register Setting in PWM Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (TIPn0 pin). (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) If D0 is set to the TPnCCR0 register and D1 to the TPnCCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used in the PWM output mode. 2. n = 0 to 5 User's Manual U16541EJ5V1UD 291 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 7-31. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 16-bit counter D00 D01 D00 D10 D10 D01 D11 D11 D10 D00 D10 0000H TPnCE bit TPnCCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTPnCC0 signal TOPn0 pin output D10 TPnCCR1 register D10 D10 CCR1 buffer register D11 D10 D10 D11 D10 INTTPnCC1 signal TOPn1 pin output <1> Remark 292 <2> <3> n = 0 to 5 User's Manual U16541EJ5V1UD <4> <5> CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow (duty only) START Setting of TPnCCR1 register Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnCCR0 register, TPnCCR1 register TPnCE bit = 1 Initial setting of these registers is performed before setting the TPnCE bit to 1. Only writing of the TPnCCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of compare register m is transferred to the CCRm buffer register. <4> TPnCCR0, TPnCCR1 register setting change flow (frequency and duty) The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting is enabled (TPnCE bit = 1). Setting of TPnCCR0 register When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. Setting of TPnCCR1 register <2> TPnCCR0, TPnCCR1 register setting change flow (frequency only) Setting of TPnCCR0 register Setting of TPnCCR1 register Remark <5> Count operation stop flow Writing the same value (same as preset value of the TPnCCR1 register) to the TPnCCR1 register is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TPnCCRm register is transferred to the CCRm buffer register. TPnCE bit = 0 Counting is stopped. STOP n = 0 to 5 m = 0, 1 User's Manual U16541EJ5V1UD 293 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRa register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected. FFFFH D01 16-bit counter D00 D10 D00 D10 D00 D10 D01 D11 D11 0000H TPnCE bit TPnCCR0 register D00 CCR0 buffer register D01 D00 TPnCCR1 register D10 CCR1 buffer register D01 D11 D10 D11 TOPn1 pin output INTTPnCC0 signal To transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level to the TPnCCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TPnCCR0 register, and then write the same value (same as preset value of the TPnCCR1 register) to the TPnCCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TPnCCR1 register has to be set. After data is written to the TPnCCR1 register, the value written to the TPnCCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TPnCCR0 or TPnCCR1 register again after writing the TPnCCR1 register once, do so after the INTTPnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TPnCCRm register to the CCRm buffer register conflicts with writing the TPnCCRm register. Remark 294 n = 0 to 5, m = 0, 1 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform <R> To output a 0% waveform, set the TPnCCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the INTTPnCC0 and INTTPnCC1 signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Count clock 16-bit counter FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 TPnCE bit TPnCCR0 register D00 D00 D00 TPnCCR1 register 0000H 0000H 0000H INTTPnCC0 signal INTTPnCC1 signal TOPn1 pin output Remark L n = 0 to 5 To output a 100% waveform, set a value of (set value of TPnCCR0 register + 1) to the TPnCCR1 register. If the set value of the TPnCCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 TPnCE bit TPnCCR0 register D00 D00 D00 TPnCCR1 register D00 + 1 D00 + 1 D00 + 1 INTTPnCC0 signal INTTPnCC1 signal L TOPn1 pin output Remark n = 0 to 5 User's Manual U16541EJ5V1UD 295 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other mode INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register. Count clock 16-bit counter TPnCCR1 register D1 - 2 D1 - 1 D1 D1 + 1 D1 + 2 D1 TOPn1 pin output INTTPnCC1 signal Remark n = 0 to 5 Usually, the INTTPnCC1 signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TPnCCR1 register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the output signal of the TOPn1 pin. 296 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRm register can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits. Figure 7-32. Configuration in Free-Running Timer Mode TPnCCR1 register (compare) TPnCCR0 register (capture) Output controller TOPn1 pinNote 2 Output controller TOPn0 pinNote 1 TPnCCS0, TPnCCS1 bits (capture/compare selection) Internal count clock Edge detector TIPn0 pinNote 1 (external event count input/ capture trigger input) Count clock selection 0 TPnCE bit INTTPnCC1 signal 1 Edge detector 0 TPnCCR0 register (capture) INTTPnCC0 signal 1 Edge detector TIPn1 pinNote 2 (capture trigger input) <R> INTTPnOV signal 16-bit counter TPnCCR1 register (compare) Notes 1. Because the external event count input pin (TIPn0), capture trigger input pin (TIPn0), and timer output pin (TOPn0) share the same alternate-function pin, two or more functions cannot be used at the same time. <R> 2. Because the capture trigger input pin (TIPn1) and timer output pin (TOPn1) are the same alternate-function pin, two or more functions cannot be used at the same time. Remark n = 0 to 5 m = 0, 1 User's Manual U16541EJ5V1UD 297 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) * Compare operation When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signals of the TOPnm pins are inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Confirm that the overflow flag is set to 1 and then clear it to 0 by executing the CLR instruction via software. The TPnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at that time by anytime write, and compared with the count value. Figure 7-33. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH D00 D00 D01 16-bit counter D10 D10 D11 D01 D11 D11 0000H TPnCE bit TPnCCR0 register D00 D01 INTTPnCC0 signal TOPn0 pin output TPnCCR1 register D10 D11 INTTPnCC1 signal TOPn1 pin output INTTPnOV signal TPnOVF bit Cleared to 0 by CLR instruction Remark Cleared to 0 by CLR instruction n = 0 to 5 m = 0, 1 298 User's Manual U16541EJ5V1UD Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) * Capture operation When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal (INTTPnCCm) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Confirm that the overflow flag is set to 1 and then clear it to 0 by executing the CLR instruction via software. Figure 7-34. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH D10 D00 16-bit counter D11 D12 D13 D01 D02 D03 0000H TPnCE bit TIPn0 pin input TPnCCR0 register D00 D01 D02 D03 INTTPnCC0 signal TIPn1 pin input TPnCCR1 register D10 D11 D12 D13 INTTPnCC1 signal INTTPnOV signal TPnOVF bit Cleared to 0 by CLR instruction Remark Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction n = 0 to 5 User's Manual U16541EJ5V1UD 299 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Register Setting in Free-Running Timer Mode (1/3) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 TPnCKS2 TPnCKS1 TPnCKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1 (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnCTL1 0 0 0/1 TPnMD2 TPnMD1 TPnMD0 0 0 1 0 1 1, 0, 1: Free-running timer mode 0: Operate with count clock selected by TPnCKS0 to TPnCKS2 bits 1: Count on external event count input signal (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnIOC0 0 0 0 0 0/1 TPnOE1 TPnOL0 0/1 0/1 TPnOE0 0/1 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting output level of TOPn0 pin before count operation 0: Low level 1: High level 0: Disable TOPn1 pin output 1: Enable TOPn1 pin output Setting output level of TOPn1 pin before count operation 0: Low level 1: High level 300 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Register Setting in Free-Running Timer Mode (2/3) (d) TMPn I/O control register 1 (TPnIOC1) TPnIOC1 0 0 0 TPnIS3 TPnIS2 TPnIS1 TPnIS0 0/1 0/1 0/1 0/1 0 Select valid edge of TIPn0 pin inputNote <R> Select valid edge of TIPn1 pin input <R> Note Set the valid edge selection of the unused alternate external input signals to "No edge detection". (e) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (TIPn0 pin)Note <R> <R> Note Set the valid edge selection of the unused alternate external input signals to "No edge detection". (f) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOPT0 0 0 0/1 0/1 TPnOVF 0 0 0 0/1 Overflow flag Specifies if TPnCCR0 register functions as capture or compare register 0: Compare register 1: Capture register Specifies if TPnCCR1 register functions as capture or compare register 0: Compare register 1: Capture register (g) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. User's Manual U16541EJ5V1UD 301 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Register Setting in Free-Running Timer Mode (3/3) (h) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers function as capture registers or compare registers depending on the setting of the TPnOPT0.TPnCCSm bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIPnm pin is detected. When the registers function as compare registers and when Dm is set to the TPnCCRm register, the INTTPnCCm signal is generated when the counter reaches (Dm + 1), and the output signal of the TOPnm pin is inverted. Remark n = 0 to 5 m = 0, 1 302 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-36. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH D00 D00 D01 16-bit counter D10 D10 D11 D01 D11 D11 0000H TPnCE bit TPnCCR0 register D00 D01 INTTPnCC0 signal TOPn0 pin output D10 TPnCCR1 register D11 INTTPnCC1 signal TOPn1 pin output INTTPnOV signal TPnOVF bit <1> Cleared to 0 by CLR instruction <2> Remark Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <3> <2> n = 0 to 5 User's Manual U16541EJ5V1UD 303 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC0 register, TPnIOC2 register, TPnOPT0 register, TPnCCR0 register, TPnCCR1 register Initial setting of these registers is performed before the TPnCE bit is set to 1. The TPnCKS0 to TPnCKS2 bits can be set when counting starts (TPnCE bit = 1). TPnCE bit = 1 <2> Overflow flag clear flow Read TPnOPT0 register (check overflow flag). TPnOVF bit = 1 No Yes Execute instruction to clear TPnOVF bit (CLR TPnOVF). <3> Count operation stop flow TPnCE bit = 0 Counter is initialized and counting is stopped by clearing TPnCE bit to 0. STOP Remark 304 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH D10 D00 D11 D12 D01 16-bit counter D02 D03 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000 D00 D01 D02 D03 0000 INTTPnCC0 signal TIPn1 pin input 0000 TPnCCR1 register D10 D11 D12 0000 INTTPnCC1 signal INTTPnOV signal TPnOVF bit <1> Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction <2> Remark <3> <2> n = 0 to 5 User's Manual U16541EJ5V1UD 305 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-37. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits) TPnCTL1 register, TPnIOC1 register, TPnOPT0 register Initial setting of these registers is performed before the TPnCE bit is set to 1. The TPnCKS0 to TPnCKS2 bits can be set when counting starts (TPnCE bit = 1). TPnCE bit = 1 <2> Overflow flag clear flow Read TPnOPT0 register (check overflow flag). TPnOVF bit = 1 No Yes Execute instruction to clear TPnOVF bit (CLR TPnOVF). <3> Count operation stop flow TPnCE bit = 0 Counter is initialized and counting is stopped by clearing TPnCE bit to 0. STOP Remark 306 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCm signal has been detected. FFFFH D02 D10 D00 D11 16-bit counter D03 D12 D01 D13 0000H D04 TPnCE bit TPnCCR0 register D00 D01 D02 D03 D04 D05 INTTPnCC0 signal TOPn0 pin output Interval period Interval period Interval period Interval period Interval period (D00 + 1) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TPnCCR1 register D10 D11 D12 D13 D14 INTTPnCC1 signal TOPn1 pin output Interval period Interval period Interval period Interval period (D10 + 1) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TPnCCRm register must be re-set in the interrupt servicing that is executed when the INTTPnCCm signal is detected. The set value for re-setting the TPnCCRm register can be calculated by the following expression, where "Dm" is the interval period. Compare register default value: Dm - 1 Value set to compare register second and subsequent time: Previous set value + Dm (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark n = 0 to 5 m = 0, 1 User's Manual U16541EJ5V1UD 307 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTPnCCm signal has been detected and for calculating an interval. FFFFH D02 D10 D00 D11 16-bit counter D03 D12 D01 D13 0000H D04 TPnCE bit TIPn0 pin input TPnCCR0 register 0000H D00 D01 D02 D03 D04 INTTPnCC0 signal Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval (D00) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TIPn1 pin input TPnCCR1 register 0000H D10 D11 D12 D13 INTTPnCC1 signal Pulse interval Pulse interval Pulse interval Pulse interval (D10) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) INTTPnOV signal TPnOVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TPnCCRm register in synchronization with the INTTPnCCm signal, and calculating the difference between the read value and the previously read value. Remark n = 0 to 5 m = 0, 1 308 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH D11 D10 16-bit counter D01 D00 0000H TPnCE bit TIPn0 pin input TPnCCR0 register D01 D00 TIPn1 pin input D11 D10 TPnCCR1 register INTTPnOV signal TPnOVF bit <1> <2> <3> <4> The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input). <2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input). <3> Read the TPnCCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TPnCCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect). Remark n = 0 to 5 When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below. User's Manual U16541EJ5V1UD 309 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TPnCE bit INTTPnOV signal TPnOVF bit TPnOVF0 flagNote TIPn0 pin input D01 D00 TPnCCR0 register TPnOVF1 flagNote TIPn1 pin input D11 D10 TPnCCR1 register <1> <2> <3> <4> <5> <6> Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software. <1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input). <2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input). <3> An overflow occurs. Set the TPnOVF0 and TPnOVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TPnCCR0 register. Read the TPnOVF0 flag. If the TPnOVF0 flag is 1, clear it to 0. Because the TPnOVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TPnCCR1 register. Read the TPnOVF1 flag. If the TPnOVF1 flag is 1, clear it to 0 (the TPnOVF0 flag is cleared in <4>, and the TPnOVF1 flag remains 1). Because the TPnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> Remark 310 n = 0 to 5 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TPnCE bit INTTPnOV signal TPnOVF bit TPnOVF0 flagNote L TIPn0 pin input D01 D00 TPnCCR0 register TPnOVF1 flagNote TIPn1 pin input D11 D10 TPnCCR1 register <1> <2> <3> <4> <5> <6> Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software. <1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input). <2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TPnCCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TPnOVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TPnCCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TPnOVF1 flag. If the TPnOVF1 flag is 1, clear it to 0. Because the TPnOVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> Remark n = 0 to 5 User's Manual U16541EJ5V1UD 311 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TPnCE bit TIPnm pin input TPnCCRm register Dm0 Dm1 INTTPnOV signal TPnOVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> The following problem may occur when long pulse width is measured in the free-running timer mode. <1> Read the TPnCCRm register (setting of the default value of the TIPnm pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TPnCCRm register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Dm1 - Dm0) (incorrect). Actually, the pulse width must be (20000H + Dm1 - Dm0) because an overflow occurs twice. Remark n = 0 to 5 m = 0, 1 If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. 312 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TPnCE bit TIPnm pin input TPnCCRm register Dm0 Dm1 INTTPnOV signal TPnOVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TPnCCRm register (setting of the default value of the TIPnm pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TPnCCRm register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Dm1 - Dm0). In this example, the pulse width is (20000H + Dm1 - Dm0) because an overflow occurs twice. Clear the overflow counter (0H). Remark n = 0 to 5 m = 0, 1 User's Manual U16541EJ5V1UD 313 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction after reading the TPnOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register after reading the TPnOVF bit when it is 1. <R> (3) Note on capture operation If the capture operation is used and if a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured to the TPnCCRm register if the capture trigger is input immediately after the TPnCTL0.TPnCE bit is set to 1. FFFFH 16-bit counter 0000H Count clock Sampling clock TPnCCR0 register 0000H FFFFH 0001H TPnCE bit TIPn0 pin input Capture trigger input Remark Capture trigger input n = 0 to 5 m = 0, 1 314 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TPnCCRm register after a capture interrupt request signal (INTTPnCCm) occurs. For example, in case of Figure 7-39, select either the TIPn0 or TIPn1 pin as the capture trigger input pin, and specify "No edge detected" by using the TPnIOC1 register for the unused pins. Figure 7-38. Configuration in Pulse Width Measurement Mode <R> Clear Count clock selection INTTPnOV signal 16-bit counter INTTPnCC0 signal TPnCE bit TIPn0 pin (capture trigger input) TIPn1 pin (capture trigger input) Edge detector INTTPnCC1 signal TPnCCR0 register (capture) Edge detector TPnCCR1 register (capture) Caution When in pulse width measurement mode, select the internal clock (set TPnCTL1.TPnEEE bit = 0) as the count clock. Remark n = 0 to 5 m = 0, 1 User's Manual U16541EJ5V1UD 315 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-39. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input TPnCCRm register 0000H D0 D1 D2 D3 INTTPnCCm signal INTTPnOV signal Cleared to 0 by CLR instruction TPnOVF bit Remark n = 0 to 5 m = 0, 1 When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is later detected, the count value of the 16-bit counter is stored in the TPnCCRm register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTPnCCm) is generated. The pulse width is calculated as follows. Pulse width = Captured value x Count clock cycle If the valid edge is not input to the TIPnm pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTPnOV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H x TPnOVF bit set (1) count + Captured value) x Count clock cycle Remark n = 0 to 5 m = 0, 1 316 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-40. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCTL0 0/1 TPnCKS2 TPnCKS1 TPnCKS0 0 0 0 0 0/1 0/1 0/1 <R> Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE <R> TPnCTL1 0 0 0 TPnMD2 TPnMD1 TPnMD0 0 0 1 1 0 1, 1, 0: Pulse width measurement mode 0: Operate with count clock selected by TPnCKS0 to TPnCKS2 bits (c) TMPn I/O control register 1 (TPnIOC1) TPnIOC1 0 0 0 0 TPnIS3 TPnIS2 TPnIS1 TPnIS0 0/1 0/1 0/1 0/1 Select valid edge of TIPn0 pin input Select valid edge of TIPn1 pin input User's Manual U16541EJ5V1UD 317 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-40. Register Setting in Pulse Width Measurement Mode (2/2) (d) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOPT0 0 0 0 0 TPnOVF 0 0 0 0/1 Overflow flag (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIPnm pin is detected. <R> Remarks 1. TMPn I/O control register 0 (TPnIOC0) and TMPn I/O control register 2 (TPnIOC2) are not used in the pulse width measurement mode. 2. n = 0 to 5 m = 0, 1 318 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 7-41. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input 0000H TPnCCR0 register D0 D1 D2 0000H INTTPnCC0 signal <1> <R> <2> <1> Count operation start flow START Register initial setting TPnCTL0 register (TPnCKS0 to TPnCKS2 bits), TPnCTL1 register, TPnIOC1 register, TPnOPT0 register TPnCE bit = 1 Initial setting of these registers is performed before the TPnCE bit is set to 1. The TPnCKS0 to TPnCKS2 bits can be set when counting starts (TPnCE bit = 1). <2> Count operation stop flow TPnCE bit = 0 The counter is initialized and counting is stopped by clearing the TPnCE bit to 0. STOP Remark n = 0 to 5 User's Manual U16541EJ5V1UD 319 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction after reading the TPnOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register after reading the TPnOVF bit when it is 1. <R> (3) Notes If a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured to the TPnCCRm register if the capture trigger is input immediately after the TPnCTL0.TPnCE bit has been set to 1. FFFFH 16-bit counter 0000H Count clock Sampling clock TPnCCR0 register 0000H FFFFH 0002H TPnCE bit TIPn0 pin input Capture trigger input Remark Capture trigger input n = 0 to 5 m = 0, 1 320 User's Manual U16541EJ5V1UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.7 <R> Selector Function In the V850ES/SG2 and V850ES/SG2-H, the TIP input/RXDA input and the TIQ input/TSOUT signal can be used to select the capture trigger input of TMP and TMQ, respectively. By using this function, the following become possible. * The TIQ02 input signal of TMQ0 can be selected from the timer alternate-function pin (TIQ02 pin) of the port and the TSOUT signal of the CAN controller. If the TSOUT signal of CAN0 is selected, the time stamp function of the CAN controller can be used. * The TIP10 and TIP11 input signals of TMP1 can be selected from the timer alternate-function pins (TIP10 and TIP11 pins) of the port and the UARTA reception alternate-function pins (RXDA0 and RXDA1). When the RXDA0 or RXDA1 signal of UART0 or UART1 is selected, the LIN reception transfer rate and baud rate error of UARTA can be calculated. Cautions 1. When using the selector function, set the capture trigger input of TMP or TMQ before connecting the timer. 2. When setting the selector function, first disable the peripheral I/O to be connected (TMP/UARTA or TMQ/CAN controller). The capture input for the selector function is specified by the following register. User's Manual U16541EJ5V1UD 321 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the capture trigger for TMP1, TMP3, and TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H SELCNT0 0 R/W 0 Address: FFFFF308H 0 ISEL4 < > < > ISEL4 ISEL3 < > 0 0 ISEL0 Selection of TIP11 input signal (TMP1) 0 TIP11 pin input 1 RXDA1 pin input ISEL3 Selection of TIP10 input signal (TMP1) 0 TIP10 pin input 1 RXDA0 pin input ISEL0Note Selection of TIQ02 input signal (TMQ0) 0 TIQ02 pin input 1 TSOUT signal of CAN0 Note The ISEL0 bit is valid only for the CAN controller version. Cautions 1. To set the ISEL0, ISEL3, and ISEL4 bits to "1", set the corresponding pin in the capture input mode. 2. Be sure to clear bits 7 to 5, 2, and 1 to "0". 322 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. <R> The V850ES/SG2 and V850ES/SG2-H incorporate TMQ0. 8.1 Overview An outline of TMQ0 is shown below. * Clock selection: 8 ways * Capture/trigger input pins: 4 * External event count input pins: 1 * External trigger input pins: 1 * Timer/counters: 1 * Capture/compare registers: 4 * Capture/compare match interrupt request signals: 4 * Overflow interrupt request signals: 1 * Timer output pins: 4 8.2 Functions TMQ0 has the following functions. * Interval timer * External event counter * External trigger pulse output * One-shot pulse output * PWM output * Free-running timer * Pulse width measurement User's Manual U16541EJ5V1UD 323 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.3 Configuration TMQ0 includes the following hardware. Table 8-1. Configuration of TMQ0 Item Configuration Timer register 16-bit counter Registers TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) TMQ0 counter read buffer register (TQ0CNT) CCR0 to CCR3 buffer registers Timer inputs 4 (TIQ00 Timer outputs Note 1 to TIQ03 pins) 4 (TOQ00 to TOQ03 pins) Note 2 Control registers TMQ0 control registers 0, 1 (TQ0CTL0, TQ0CTL1) TMQ0 I/O control registers 0 to 2 (TQ0IOC0 to TQ0IOC2) TMQ0 option register 0 (TQ0OPT0) Notes 1. The TIQ00 pin functions alternately as a capture trigger input signal, external event count input signal, and external trigger input signal. 2. When using the functions of the TIQ00 to TIQ03 and TOQ00 to TOQ03 pins, see Table 4-15 Using Port Pin as Alternate-Function Pin. Figure 8-1. Block Diagram of TMQ0 Internal bus Selector TQ0CNT Clear TIQ01 TIQ02 TIQ03 Edge detector CCR0 buffer register TIQ00 CCR1 buffer register CCR2 buffer register TQ0CCR0 324 CCR3 buffer register TQ0CCR1 TQ0CCR2 TQ0CCR3 Internal bus Remark INTTQ0OV 16-bit counter Output controller Selector fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX: Main clock frequency User's Manual U16541EJ5V1UD TOQ00 TOQ01 TOQ02 TOQ03 INTTQ0CC0 INTTQ0CC1 INTTQ0CC2 INTTQ0CC3 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TQ0CNT register. When the TQ0CTL0.TQ0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TQ0CNT register is read at this time, 0000H is read. Reset sets the TQ0CE bit to 0. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQ0CCR0 register is used as a compare register, the value written to the TQ0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQ0CC0) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is cleared to 0000H after reset, as the TQ0CCR0 register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQ0CCR1 register is used as a compare register, the value written to the TQ0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQ0CC1) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is cleared to 0000H after reset, as the TQ0CCR1 register is cleared to 0000H. (4) CCR2 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQ0CCR2 register is used as a compare register, the value written to the TQ0CCR2 register is transferred to the CCR2 buffer register. When the count value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQ0CC2) is generated. The CCR2 buffer register cannot be read or written directly. The CCR2 buffer register is cleared to 0000H after reset, as the TQ0CCR2 register is cleared to 0000H. (5) CCR3 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TQ0CCR3 register is used as a compare register, the value written to the TQ0CCR3 register is transferred to the CCR3 buffer register. When the count value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQ0CC3) is generated. The CCR3 buffer register cannot be read or written directly. The CCR3 buffer register is cleared to 0000H after reset, as the TQ0CCR3 register is cleared to 0000H. (6) Edge detector This circuit detects the valid edges input to the TIQ00 and TIQ03 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TQ0IOC1 and TQ0IOC2 registers. (7) Output controller This circuit controls the output of the TOQ00 to TOQ03 pins. The output controller is controlled by the TQ0IOC0 register. User's Manual U16541EJ5V1UD 325 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. 326 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.4 Registers The registers that control TMQ0 are as follows. * TMQ0 control register 0 (TQ0CTL0) * TMQ0 control register 1 (TQ0CTL1) * TMQ0 I/O control register 0 (TQ0IOC0) * TMQ0 I/O control register 1 (TQ0IOC1) * TMQ0 I/O control register 2 (TQ0IOC2) * TMQ0 option register 0 (TQ0OPT0) * TMQ0 capture/compare register 0 (TQ0CCR0) * TMQ0 capture/compare register 1 (TQ0CCR1) * TMQ0 capture/compare register 2 (TQ0CCR2) * TMQ0 capture/compare register 3 (TQ0CCR3) * TMQ0 counter read buffer register (TQ0CNT) Remark When using the functions of the TIQ00 to TIQ03 and TOQ00 to TOQ03 pins, see Table 4-15 Using Port Pin as Alternate-Function Pin. User's Manual U16541EJ5V1UD 327 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) TMQ0 control register 0 (TQ0CTL0) The TQ0CTL0 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TQ0CTL0 register by software. After reset: 00H TQ0CTL0 R/W Address: FFFFF540H <7> 6 5 4 3 TQ0CE 0 0 0 0 TQ0CE 1 0 TQ0CKS2 TQ0CKS1 TQ0CKS0 TMQ0 operation control 0 TMQ0 operation disabled (TMQ0 reset asynchronouslyNote). 1 TMQ0 operation enabled. TMQ0 operation started. TQ0CKS2 TQ0CKS1 TQ0CKS0 <R> 2 Internal count clock selection 0 0 0 fXX 0 0 1 fXX/2 0 1 0 fXX/4 0 1 1 fXX/8 1 0 0 fXX/16 1 0 1 fXX/32 1 1 0 fXX/64 1 1 1 fXX/128 Note The TQ0OPT0.TQ0OVF bit and 16-bit counter are reset at the same time. In addition, the timer output pins (TOQ00 to TOQ03 pins) are reset to the status set by the TQ0IOC0 register when the 16-bit counter is reset. Cautions 1. Set the TQ0CKS2 to TQ0CKS0 bits when the TQ0CE bit = 0. When the value of the TQ0CE bit is changed from 0 to 1, the TQ0CKS2 to TQ0CKS0 bits can be set simultaneously. 2. Be sure to clear bits 3 to 6 to "0". Remark 328 fXX: Main clock frequency User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) TMQ0 control register 1 (TQ0CTL1) The TQ0CTL1 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H 7 TQ0CTL1 0 R/W <6> Address: <5> TQ0EST TQ0EEE TQ0EST <R> FFFFF541H 4 3 0 0 2 1 0 TQ0MD2 TQ0MD1 TQ0MD0 Software trigger control 0 - 1 Generate a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TQ0EST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TQ0EST bit as the trigger. The read value of TQ0EST bit is always 0. TQ0EEE Count clock selection 0 Disable operation with external event count input (TIQ00 pin). (Perform counting with the count clock selected by the TQ0CTL0.TQ0CKS0 to TQ0CKS2 bits.) 1 Enable operation with external event count input (TIQ00pin). (Perform counting at the valid edge of the external event count input signal.) The TQ0EEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. TQ0MD2 TQ0MD1 TQ0MD0 Timer mode selection 0 0 0 Interval timer mode 0 0 1 External event count mode 0 1 0 External trigger pulse output mode 0 1 1 One-shot pulse output mode 1 0 0 PWM output mode 1 0 1 Free-running timer mode 1 1 0 Pulse width measurement mode 1 1 1 Setting prohibited Cautions 1. The TQ0EST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. External event count input is selected in the external event count mode regardless of the value of the TQ0EEE bit. 3. Set the TQ0EEE and TQ0MD2 to TQ0MD0 bits when the TQ0CTL0.TQ0CE bit = 0. (The same value can be written when the TQ0CE bit = 1.) The operation is not guaranteed when rewriting is performed with the TQ0CE bit = 1. If rewriting was mistakenly performed, clear the TQ0CE bit to 0 and then set the bits again. 4. Be sure to clear bits 3, 4, and 7 to "0". User's Manual U16541EJ5V1UD 329 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) TMQ0 I/O control register 0 (TQ0IOC0) The TQ0IOC0 register is an 8-bit register that controls the timer output (TOQ00 to TOQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W <6> 7 TQ0IOC0 Address: 5 3 <2> 1 <0> TOQ0m pin output level setting (m = 0 to 3)Note 0 TOQ0m pin high level start 1 TOQ0m pin low level start TQ0OEm <R> <4> TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0OLm <R> FFFFF542H TOQ0m pin output setting (m = 0 to 3) 0 Timer output disabled * When TQ0OLm bit = 0: Low level is output from the TOQ0m pin * When TQ0OLm bit = 1: High level is output from the TOQ0m pin 1 Timer output enabled (A pulse is output from the TOQ0m pin). Note The output level of the timer output pin (TOQ0m) specified by the TQ0OLm bit is shown below. * When TQ0OLm bit = 0 <R> * When TQ0OLm bit = 1 16-bit counter 16-bit counter TQ0CE bit TQ0CE bit TOQ0m pin output TOQ0m pin output Cautions 1. The pin output changes if the setting of the TQ0IOC0 register is rewritten when the port is set to output TOQ0m. Therefore, note changes in the pin status by setting the port in the input mode and making the output status of the pins a highimpedance state. 2. Rewrite the TQ0OLm TQ0CTL0.TQ0CE bit = 0. and TQ0OEm bits when the (The same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly performed, clear the TQ0CE bit to 0 and then set the bits again. 3. Even if the TQ0OLm bit is manipulated when the TQ0CE and TQ0OEm bits are 0, the TOQ0m pin output level varies. Remark 330 m = 0 to 3 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIQ00 to TIQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H TQ0IOC1 R/W Address: FFFFF543H 7 6 5 4 3 2 1 0 TQ0IS7 TQ0IS6 TQ0IS5 TQ0IS4 TQ0IS3 TQ0IS2 TQ0IS1 TQ0IS0 TQ0IS7 TQ0IS6 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TQ0IS5 TQ0IS4 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TQ0IS3 TQ0IS2 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TQ0IS1 TQ0IS0 0 0 No edge detection (capture operation invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges Capture trigger input signal (TIQ03 pin) valid edge setting Capture trigger input signal (TIQ02 pin) valid edge detection Capture trigger input signal (TIQ01 pin) valid edge setting Capture trigger input signal (TIQ00 pin) valid edge setting Cautions 1. Rewrite the TQ0IS7 to TQ0IS0 bits when the TQ0CTL0.TQ0CE bit = 0. (The same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly performed, clear the TQ0CE bit to 0 and then set the bits again. 2. The TQ0IS7 to TQ0IS0 bits are valid only in the freerunning timer mode (TQ0OPT0.TQ0CCSm bit = 1 only) and the pulse width measurement mode (m = 0 to 3). In all other modes, a capture operation is not possible. User's Manual U16541EJ5V1UD 331 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIQ00 pin) and external trigger input signal (TIQ00 pin). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H TQ0IOC2 R/W Address: FFFFF544H 7 6 5 4 0 0 0 0 3 2 1 0 TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0EES1 TQ0EES0 External event count input signal (TIQ00 pin) valid edge setting 0 0 No edge detection (external event count invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges TQ0ETS1 TQ0ETS0 External trigger input signal (TIQ00 pin) valid edge setting 0 0 No edge detection (external trigger invalid) 0 1 Detection of rising edge 1 0 Detection of falling edge 1 1 Detection of both edges Cautions 1. Rewrite the TQ0EES1, TQ0EES0, TQ0ETS1, and TQ0ETS0 bits when the TQ0CTL0.TQ0CE bit = 0. (The same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly performed, clear the TQ0CE bit to 0 and then set the bits again. 2. The TQ0EES1 and TQ0EES0 bits are valid only when the TQ0CTL1.TQ0EEE bit = 1 or when the external event count mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits = 001) has been set. 3. The TQ0ETS1 and TQ0ETS0 bits are valid only when the external trigger pulse output mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits = 010) or the one-shot pulse output mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 = 011) is set. 332 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (6) TMQ0 option register 0 (TQ0OPT0) The TQ0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: 6 7 TQ0OPT0 R/W 5 4 TQ0CCS3 TQ0CCS2 TQ0CCS1 TQ0CCS0 TQ0CCSm <R> FFFFF545H 3 2 1 <0> 0 0 0 TQ0OVF TQ0CCRm register capture/compare selection 0 Compare register selected 1 Capture register selected (cleared by setting the TQ0CTL0.TQ0CE bit = 0) The TQ0CCSm bit setting is valid only in the free-running timer mode. TQ0OVF <R> TMQ0 overflow detection flag Set (1) Overflow occurred Reset (0) TQ0OVF bit 0 written or TQ0CTL0.TQ0CE bit = 0 * The TQ0OVF bit is set to 1 when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An overflow interrupt request signal (INTTQ0OV) is generated at the same time that the TQ0OVF bit is set to 1. The INTTQ0OV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TQ0OVF bit is not cleared to 0 even when the TQ0OVF bit or the TQ0OPT0 register are read when the TQ0OVF bit = 1. * Before clearing the TQ0OVF bit to 0 after the INTTQ0OV signal has been generated, be sure to confirm (read) that the TQ0OVF bit is set to 1. * The TQ0OVF bit can be both read and written, but the TQ0OVF bit cannot be set to 1 by software. Writing 1 has no influence on the operation of TMQ0. Cautions 1. Rewrite the TQ0CCS3 to TQ0CCS0 bits when the TQ0CTL0.TQ0CE bit = 0. (The same value can be written when the TQ0CE bit = 1.) If rewriting was mistakenly performed, clear the TQ0CE bit to 0 and then set the bits again. 2. Be sure to clear bits 1 to 3 to "0". Remark m = 0 to 3 User's Manual U16541EJ5V1UD 333 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) TMQ0 capture/compare register 0 (TQ0CCR0) The TQ0CCR0 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS0 bit. In the pulse width measurement mode, the TQ0CCR0 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TQ0CCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TQ0CCR0 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 FFFFF546H 9 8 7 6 TQ0CCR0 334 User's Manual U16541EJ5V1UD 5 4 3 2 1 0 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR0 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQ0CC0) is generated. If TOQ00 pin output is enabled at this time, the output of the TOQ00 pin is inverted. When the TQ0CCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. <R> The compare register is not cleared when the TQ0CTL0.TQ0CE bit = 0. (b) Function as capture register When the TQ0CCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TQ0CCR0 register if the valid edge of the capture trigger input pin (TIQ00 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TQ0CCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIQ00 pin) is detected. Even if the capture operation and reading the TQ0CCR0 register conflict, the correct value of the TQ0CCR0 register can be read. <R> The capture register is cleared when the TQ0CTL0.TQ0CE bit = 0. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode <R> <R> Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None <R> Note Triggered by writing to the TQ0CCR1 register <R> Remark Note Note For anytime write and batch write, 8.6 (2) Anytime write and batch write. User's Manual U16541EJ5V1UD 335 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) TMQ0 capture/compare register 1 (TQ0CCR1) The TQ0CCR1 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS1 bit. In the pulse width measurement mode, the TQ0CCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TQ0CCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TQ0CCR1 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 FFFFF548H 9 8 7 6 TQ0CCR1 336 User's Manual U16541EJ5V1UD 5 4 3 2 1 0 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR1 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQ0CC1) is generated. If TOQ01 pin output is enabled at this time, the output of the TOQ01 pin is inverted. <R> The compare register is not cleared when the TQ0CTL0.TQ0CE bit = 0. (b) Function as capture register When the TQ0CCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TQ0CCR1 register if the valid edge of the capture trigger input pin (TIQ01 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TQ0CCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIQ01 pin) is detected. Even if the capture operation and reading the TQ0CCR1 register conflict, the correct value of the TQ0CCR1 register can be read. <R> The capture register is cleared when the TQ0CTL0.TQ0CE bit = 0. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode <R> <R> Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Note Note Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None <R> Note Triggered by writing to the TQ0CCR1 register <R> Remark For anytime write and batch write, see 8.6 (2) Anytime write and batch write. User's Manual U16541EJ5V1UD 337 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (9) TMQ0 capture/compare register 2 (TQ0CCR2) The TQ0CCR2 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS2 bit. In the pulse width measurement mode, the TQ0CCR2 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TQ0CCR2 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TQ0CCR2 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 FFFFF54AH 9 8 7 6 TQ0CCR2 338 User's Manual U16541EJ5V1UD 5 4 3 2 1 0 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR2 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR2 register is transferred to the CCR2 buffer register. When the value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQ0CC2) is generated. If TOQ02 pin output is enabled at this time, the output of the TOQ02 pin is inverted. <R> The compare register is not cleared when the TQ0CTL0.TQ0CE bit = 0. (b) Function as capture register When the TQ0CCR2 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TQ0CCR2 register if the valid edge of the capture trigger input pin (TIQ02 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TQ0CCR2 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIQ02 pin) is detected. Even if the capture operation and reading the TQ0CCR2 register conflict, the correct value of the TQ0CCR2 register can be read. <R> The capture register is cleared when the TQ0CTL0.TQ0CE bit = 0. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode <R> <R> Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Note Note Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None <R> Note Triggered by writing to the TQ0CCR1 register <R> Remark For anytime write and batch write, see 8.6 (2) Anytime write and batch write. User's Manual U16541EJ5V1UD 339 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (10) TMQ0 capture/compare register 3 (TQ0CCR3) The TQ0CCR3 register is a 16-bit register that can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS3 bit. In the pulse width measurement mode, the TQ0CCR3 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TQ0CCR3 register can be read or written during operation. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the TQ0CCR3 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: 11 10 FFFFF54CH 9 8 7 6 TQ0CCR3 340 User's Manual U16541EJ5V1UD 5 4 3 2 1 0 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR3 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR3 register is transferred to the CCR3 buffer register. When the value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQ0CC3) is generated. If TOQ03 pin output is enabled at this time, the output of the TOQ03 pin is inverted. <R> The compare register is not cleared when the TQ0CTL0.TQ0CE bit = 0. (b) Function as capture register When the TQ0CCR3 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TQ0CCR3 register if the valid edge of the capture trigger input pin (TIQ03 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TQ0CCR3 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIQ03 pi) is detected. Even if the capture operation and reading the TQ0CCR3 register conflict, the correct value of the TQ0CCR3 register can be read. <R> The capture register is cleared when the TQ0CTL0.TQ0CE bit = 0. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 8-5. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode <R> <R> Capture/Compare Register How to Write Compare Register Interval timer Compare register Anytime write External event counter Compare register Anytime write External trigger pulse output Compare register Batch write One-shot pulse output Compare register Anytime write PWM output Compare register Batch write Note Note Free-running timer Capture/compare register Anytime write Pulse width measurement Capture register None <R> Note Triggered by writing to the TQ0CCR1 register <R> Remark For anytime write and batch write, see 8.6 (2) Anytime write and batch write. User's Manual U16541EJ5V1UD 341 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (11) TMQ0 counter read buffer register (TQ0CNT) The TQ0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TQ0CTL0.TQ0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TQ0CNT register is cleared to 0000H when the TQ0CE bit = 0. If the TQ0CNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TQ0CNT register is cleared to 0000H after reset, as the TQ0CE bit is cleared to 0. Caution Accessing the TQ0CNT register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R 13 Address: 12 11 10 FFFFF54EH 9 8 7 6 TQ0CNT 342 User's Manual U16541EJ5V1UD 5 4 3 2 1 0 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5 Timer output operations The following table shows the operations and output levels of the TOQ00 and TOQ01 pins. Table 8-6. Timer Output Control in Each Mode Operation Mode TOQ00 Pin TOQ01 Pin Interval timer mode Square wave output External event count mode None External trigger pulse output mode PWM output TOQ02 Pin TOQ03 Pin External trigger pulse output One-shot pulse output mode One-shot pulse output PWM output mode PWM output Free-running timer mode Square wave output (only when compare function is used) Pulse width measurement mode None Table 8-7. Truth Table of TOQ00 to TOQ03 Pins Under Control of Timer Output Control Bits TQ0IOC0.TQ0OLm Bit TQ0IOC0.TQ0OEm Bit TQ0CTL0.TQ0CE Bit 0 0 x 1 Level of TOQ0m Pin Low-level output 0 Low-level output 1 Low level immediately before counting, high level after counting is started 1 0 x High-level output 1 0 High-level output 1 High level immediately before counting, low level after counting is started Remark m = 0 to 3 User's Manual U16541EJ5V1UD 343 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6 Operation TMQ0 can perform the following operations. TQ0CTL1.TQ0EST Bit Operation TIQ00 Pin (Software Trigger Bit) (External Trigger Input) Interval timer mode External event count mode Note 1 External trigger pulse output mode One-shot pulse output mode Note 2 Note 2 PWM output mode Free-running timer mode Pulse width measurement mode Note 2 Capture/Compare Compare Register Register Setting Write Invalid Invalid Compare only Anytime write Invalid Invalid Compare only Anytime write Valid Valid Compare only Batch write Valid Valid Compare only Anytime write Invalid Invalid Compare only Batch write Invalid Invalid Switching enabled Anytime write Invalid Invalid Capture only Not applicable Notes 1. To use the external event count mode, specify that the valid edge of the TIQ00 pin capture trigger input is not detected (by clearing the TQ0IOC1.TQ0IS1 and TQ0IOC1.TQ0IS0 bits to "00"). 2. To use external trigger pulse output mode, one shot pulse output mode or pulse width measurement mode, select the internal clock (set TQ0CTL1.TQ0EEE bit = 0) as the count clock. <R> (1) Counter basic operation This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation in each mode. (a) Counter start operation The 16-bit counter of TMQ0 starts counting from the default value FFFFH in all modes. It counts up from FFFFH to 0000H, 0001H, 0002H, 0003H, and so on. (b) Clear operation The 16-bit counter is cleared to 0000H when its value matches the value of the compare register and when its value is captured. The counting operation from FFFFH to 0000H that takes place immediately after the counter has started counting or when the counter overflows is not a clearing operation. Therefore, the INTTQ0CCm interrupt signal is not generated (m = 0 to 3). (c) Overflow operation The 16-bit counter overflows when the counter counts up from FFFFH to 0000H in the free-running timer mode or pulse width measurement mode. If the counter overflows, the TQ0OPT0.TQ0OVF bit is set to 1 and an interrupt request signal (INTTQ0OV) is generated. Note that the INTTQ0OV signal is not generated under the following conditions. * Immediately after a count operation has been started * If the counter value matches the compare value FFFFH and is cleared * When FFFFH is captured in the pulse width measurement mode and the counter counts up from FFFFH to 0000H Caution After the overflow interrupt request signal (INTTQ0OV) has been generated, be sure to check that the overflow flag (TQ0OVF bit) is set to 1. 344 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Counter read operation during counting operation The value of the 16-bit counter of TMQ0 can be read by using the TQ0CNT register during the count operation. When the TQ0CTL0.TQ0CE bit = 1, the value of the 16-bit counter can be read by reading the TQ0CNT register. When the TQ0CE bit = 0, the 16-bit counter is FFFFH and the TQ0CNT register is 0000H. (e) Interrupt operation TMQ0 generates the following five interrupt request signals. * INTTQ0CC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer register and as a capture interrupt request signal to the TQ0CCR0 register. * INTTQ0CC1 interrupt: This signal functions as a match interrupt request signal of the CCR1 buffer register and as a capture interrupt request signal to the TQ0CCR1 register. * INTTQ0CC2 interrupt: This signal functions as a match interrupt request signal of the CCR2 buffer register and as a capture interrupt request signal to the TQ0CCR2 register. * INTTQ0CC3 interrupt: This signal functions as a match interrupt request signal of the CCR3 buffer register and as a capture interrupt request signal to the TQ0CCR3 register. * INTTQ0OV interrupt: This signal functions as an overflow interrupt request signal. User's Manual U16541EJ5V1UD 345 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> (2) Anytime write and batch write The TQ0CCR0 to TQ0CCR3 registers can be rewritten in the TMQ0 during timer operation (TQ0CTL0.TQ0CE bit = 1), but the write method (anytime write, batch write) of the CCR0 to CCR3 buffer registers differs depending on the mode. (a) Anytime write In this mode, data is transferred at any time from the TQ0CCR0 to TQ0CCR3 registers to the CCR0 to CCR3 buffer registers during the timer operation. Figure 8-2. Flowchart of Basic Operation for Anytime Write START Initial settings * Set values to TQ0CCRm register * Timer operation enable (TQ0CE bit = 1) Transfer values of TQ0CCRm register to CCRm buffer register TQ0CCRm register rewrite Transfer to CCRm buffer register Timer operation * Match between 16-bit counter and CCRk buffer registerNote * Match between 16-bit counter and CCR0 buffer register * 16-bit counter clear & start INTTQ0CCk signal output INTTQ0CC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCRk buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Remarks 1. The above flowchart illustrates an example of the operation in the interval timer mode. 2. k = 1 to 3 m = 0 to 3 346 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-3. Timing of Anytime Write TQ0CE bit = 1 D01 FFFFH D01 D02 D21 16-bit counter D21 D11 D11 D31 D21 D12 D12 D31 D31 D31 0000H TQ0CCR0 register CCR0 buffer register D01 0000H D02 D01 D02 INTTQ0CC0 signal TQ0CCR1 register CCR1 buffer register D11 0000H D12 D11 D12 INTTQ0CC1 signal TQ0CCR2 register CCR2 buffer register D21 0000H D21 INTTQ0CC2 signal TQ0CCR3 register CCR3 buffer register D31 0000H D31 INTTQ0CC3 signal Remarks 1. D01, D02: Setting values of TQ0CCR0 register D11, D12: Setting values of TQ0CCR1 register D21: Setting value of TQ0CCR2 register D31: Setting value of TQ0CCR3 register 2. The above timing chart illustrates an example of the operation in the interval timer mode. User's Manual U16541EJ5V1UD 347 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Batch write In this mode, data is transferred all at once from the TQ0CCR0 to TQ0CCR3 registers to the CCR0 to CCR3 buffer registers during timer operation. This data is transferred upon a match between the value of the CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TQ0CCR1 register. Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TQ0CCR1 register. In order for the setting value when the TQ0CCR0 to TQ0CCR3 registers are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be transferred to the CCR0 to CCR3 buffer registers), it is necessary to rewrite TQ0CCR0 and finally write to the TQ0CCR1 register before the 16-bit counter value and the CCR0 buffer register value match. The values of the TQ0CCR0 to TQ0CCR3 registers are transferred to the CCR0 to CCR3 buffer registers upon a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Thus, even when wishing only to rewrite the value of the TQ0CCR0, TQ0CCR2, or TQ0CCR3 register, also write the same value (same as preset value of the TQ0CCR1 register) to the TQ0CCR1 register. 348 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-4. Flowchart of Basic Operation for Batch Write START Initial settings * Set values to TQ0CCRm register * Timer operation enable (TQ0CE bit = 1) Transfer of values of TQ0CCRm register to CCRm buffer register TQ0CCR0, TQ0CCR2, TQ0CCR3 register rewrite TQ0CCR1 register rewrite Timer operation * Match between 16-bit counter and CCRk buffer registerNote * Match between 16-bit counter and CCR0 buffer register * 16-bit counter clear & start * Transfer of values of TQ0CCRk register to CCRk buffer register Batch write enable INTTQ0CCk signal output INTTQ0CC0 signal output Note The 16-bit counter is not cleared upon a match between the 16-bit counter value and the CCRk buffer register value. It is cleared upon a match between the 16-bit counter value and the CCR0 buffer register value. Caution Writing to the TQ0CCR1 register includes enabling of batch write. Thus, rewrite the TQ0CCR1 register after rewriting the TQ0CCR0, TQ0CCR2, and TQ0CCR3 registers. Remarks 1. The above flowchart illustrates an example of the operation in the PWM output mode. 2. k = 1 to 3 m = 0 to 3 User's Manual U16541EJ5V1UD 349 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-5. Timing of Batch Write TQ0CE bit = 1 D01 FFFFH 16-bit counter D32 D32 D12 D31 D21 D32 D12 D12 D21 D03 D02 D02 D11 D21 D12 D21 D21 0000H TQ0CCR0 register D01 CCR0 buffer register 0000H TQ0CCR1 register D02 D01 0000H D11 D02 Note 1 Note 2 D11 CCR1 buffer register D03 Note 1 D12 TQ0CCR2 register Note 3 D12 Note 1 D03 Same value write D12 D12 Note 1 D21 CCR2 buffer register 0000H TQ0CCR3 register D21 D31 CCR3 buffer register 0000H Note 1 D21 D32 D31 Note 1 D21 Note 1 D33 D32 Note 1 D33 INTTQ0CC0 signal INTTQ0CC1 signal INTTQ0CC2 signal INTTQ0CC3 signal TOQ00 pin output TOQ01 pin output TOQ02 pin output TOQ03 pin output Notes 1. Because the TQ0CCR1 register was not rewritten, D02 is not transferred. 2. Because TQ0CCR1 register has been written (D12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit timer and the value of the TQ0CCR0 register (D01). 3. Because TQ0CCR1 register has been written (D12), data is transferred to the CCR1 buffer register upon a match between the value of the 16-bit timer and the value of the TQ0CCR0 register (D12). Remarks 1. D01, D02, D03: Setting values of TQ0CCR0 register D11, D12: Setting values of TQ0CCR1 register D21: Setting value of TQ0CCR2 register D31, D32, D33: Setting values of TQ0CCR3 register 2. The above timing chart illustrates the operation in the PWM output mode as an example. 350 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> 8.6.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTQ0CC0) is generated at the interval set by the TQ0CCR0 register if the TQ0CTL0.TQ0CE bit is set to 1. A square wave with a duty factor of 50% whose half cycle is equal to the interval can be output from the TOQ00 pin. The TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode. However, the set value of the TQ0CCR1 to TQ0CCR3 registers is transferred to the CCR1 to CCR3 buffer registers and, when the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers, compare match interrupt request signals (INTTQ0CC1 to INTTQ0CC3) are generated. In addition, a square wave with a duty factor of 50%, which is inverted when the INTTQ0CC1 to INTTQ0CC3 signals are generated, can be output from the TOQ01 to TOQ03 pins. The value of the TQ0CCR1 to TQ0CCR3 registers can be rewritten even while the timer is operating. Figure 8-6. Configuration of Interval Timer Clear Count clock selection Output controller 16-bit counter Match signal TQ0CE bit TOQ00 pin INTTQ0CC0 signal CCR0 buffer register TQ0CCR0 register Figure 8-7. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter D0 D0 D0 D0 0000H TQ0CE bit TQ0CCR0 register D0 TOQ00 pin output INTTQ0CC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) User's Manual U16541EJ5V1UD 351 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOQ00 pin is inverted. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOQ00 pin is inverted, and a compare match interrupt request signal (INTTQ0CC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TQ0CCR0 register + 1) x Count clock cycle Figure 8-8. Register Setting for Interval Timer Mode Operation (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CTL0 0/1 TQ0CKS2 TQ0CKS1 TQ0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0CTL1 0 0 Note 0/1 TQ0MD2 TQ0MD1 TQ0MD0 0 0 0 0 0 0, 0, 0: Interval timer mode 0: Operate on count clock selected by bits TQ0CKS0 to TQ0CKS2 1: Count with external event count input signal <R> Note The TQ0EEE bit can be set to 1 only when the timer output (TOQ0k) is used. However, the TQ0CCR0 and TQ0CCRk registers must be set to the same value (k = 1 to 3). 352 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-8. Register Setting for Interval Timer Mode Operation (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output before count operation 0: Low level 1: High level 0: Disable TOQ01 pin output 1: Enable TOQ01 pin output Setting of TOQ01 pin output before count operation 0: Low level 1: High level 0: Disable TOQ02 pin output 1: Enable TOQ02 pin output Setting of TOQ02 pin output before count operation 0: Low level 1: High level 0: Disable TOQ03 pin output 1: Enable TOQ03 pin output Setting of TOQ03 pin output before count operation 0: Low level 1: High level <R> (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 0 0 0 0 0/1Note 0/1Note 0 0 Select valid edge of external event count input (TIQ00 pin). Note The TQ0EES1 and TQ0EES0 bits can be set only when timer outputs (TOQ01 to TOQ03) are used. However, set the TQ0CCR0 to TQ0CCR3 registers to the same value. (e) TMQ0 counter read buffer register (TQ0CNT) By reading the TQ0CNT register, the count value of the 16-bit counter can be read. (f) TMQ0 capture/compare register 0 (TQ0CCR0) If the TQ0CCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle User's Manual U16541EJ5V1UD 353 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-8. Register Setting for Interval Timer Mode Operation (3/3) (g) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3) <R> The TQ0CCR1 to TQ0CCR3 registers are not used in the interval timer mode. However, the set value of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer registers. The TOQ01 to TOQ03 pin outputs are inverted and compare match interrupt request signals (INTTQ0CC1 to INTTQ0CC3) are generated when the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers. When the TQ0CCR1 to TQ0CCR3 registers are not used, it is recommended to set their values to FFFFH. Also mask the registers by the interrupt mask flags (TQ0CCIC0.TQ0CCMK0 to TQ0CCIC3.TQ0CCMK3). <R> Remark TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not used in the interval timer mode. 354 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Interval timer mode operation flow Figure 8-9. Software Processing Flow in Interval Timer Mode FFFFH D0 16-bit counter D0 D0 0000H TQ0CE bit TQ0CCR0 register D0 TOQ00 pin output INTTQ0CC0 signal <1> <2> <1> Count operation start flow START <R> Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC0 register, TQ0IOC2 registerNote, TQ0CCR0 register TQ0CE bit = 1 <R> Initial setting of these registers is performed before setting the TQ0CE bit to 1. The TQ0CKS0 to TQ0CKS2 bits can be set at the same time when counting has been started (TQ0CE bit = 1). Note The TQ0EES1 and TQ0EES0 bits can be set only when timer output (TOQ0k) is used. However, set the TQ0CCR0 and TQ0CCRk registers to the same value (k = 1 to 3). <2> Count operation stop flow TQ0CE bit = 0 The counter is initialized and counting is stopped by clearing the TQ0CE bit to 0. The output level of the TOQ00 pin is as specified by the TQ0IOC0 register. STOP User's Manual U16541EJ5V1UD 355 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Interval timer mode operation timing <R> (a) Operation if TQ0CCR0 register is set to 0000H If the TQ0CCR0 register is set to 0000H, the INTTQ0CC0 signal is generated at each count clock, and the output of the TOQ00 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH 0000H 0000H 0000H 0000H TQ0CE bit TQ0CCR0 register 0000H TOQ00 pin output INTTQ0CC0 signal Interval time Interval time Interval time Count clock cycle Count clock cycle Count clock cycle (b) Operation if TQ0CCR0 register is set to FFFFH If the TQ0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTQ0CC0 signal is generated and the output of the TOQ00 pin is inverted. At this time, an overflow interrupt request signal (INTTQ0OV) is not generated, nor is the overflow flag (TQ0OPT0.TQ0OVF bit) set to 1. FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register FFFFH TOQ00 pin output INTTQ0CC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle 356 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Notes on rewriting TQ0CCR0 register When the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH D1 D1 16-bit counter D2 D2 D2 0000H TQ0CE bit D1 TQ0CCR0 register TQ0OL0 bit D2 L TOQ00 pin output INTTQ0CC0 signal Interval time (1) Remark Interval time (NG) Interval time (2) Interval time (1): (D1 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle Interval time (2): (D2 + 1) x Count clock cycle If the value of the TQ0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TQ0CCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTQ0CC0 signal is generated and the output of the TOQ00 pin is inverted. Therefore, the INTTQ0CC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock period". User's Manual U16541EJ5V1UD 357 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-10. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer register Output controller Match signal TOQ01 pin INTTQ0CC1 signal TQ0CCR2 register Output controller CCR2 buffer register Match signal TOQ02 pin INTTQ0CC2 signal TQ0CCR3 register CCR3 buffer register Output controller Match signal TOQ03 pin INTTQ0CC3 signal Clear Count clock selection 16-bit counter Match signal TQ0CE bit CCR0 buffer register TQ0CCR0 register 358 User's Manual U16541EJ5V1UD Output controller TOQ00 pin INTTQ0CC0 signal CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> If the same value as the set value of the TQ0CCR0 register is set to the TQ0CCRk register, the INTTQ0CCk signal is generated together with the INTTQ0CC0 signal, and the output of the TOQ0k pin is inverted. This means that a square wave with a duty factor of 50% can be output from the TOQ0k pin. If a value different from the set value of the TQ0CCR0 register is set to the TQ0CCRk register, the operation is as follows. If the set value of the TQ0CCRk register is less than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. At the same time, the output of the TOQ0k pin is inverted. The TOQ0k pin outputs a square wave with a duty factor of 50% after it first outputs a short-width pulse. Remark k = 1 to 3 Figure 8-11. Timing Chart When D01 Dk1 FFFFH 16-bit counter D01 D31 D11 D21 D01 D01 D31 D31 D11 D21 D11 D21 D01 D31 D11 D21 0000H TQ0CE bit TQ0CCR0 register D01 TOQ00 pin output INTTQ0CC0 signal TQ0CCR1 register D11 TOQ01 pin output INTTQ0CC1 signal TQ0CCR2 register D21 TOQ02 pin output INTTQ0CC2 signal TQ0CCR3 register D31 TOQ03 pin output INTTQ0CC3 signal User's Manual U16541EJ5V1UD 359 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the count value of the 16-bit counter does not match the value of the TQ0CCRk register. <R> Consequently, the INTTQ0CCk signal is not generated, nor is the output of the TOQ0k pin changed. It is recommended to set FFFFH to the TQ0CCRk register when the TQ0CCRk register is not used. Remark k = 1 to 3 Figure 8-12. Timing Chart When D01 < Dk1 FFFFH D01 D01 D01 16-bit counter 0000H TQ0CE bit D01 TQ0CCR0 register TOQ00 pin output INTTQ0CC0 signal TQ0CCR1 register D11 TOQ01 pin output INTTQ0CC1 signal L D21 TQ0CCR2 register TOQ02 pin output INTTQ0CC2 signal L D31 TQ0CCR3 register TOQ03 pin output INTTQ0CC3 signal 360 L User's Manual U16541EJ5V1UD D01 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> (3) Operation by external event count input (TIQ00) (a) Operation To count the 16-bit counter at the valid edge of external event count input (TIQ00) in the interval timer mode, the valid edge of the external event count input is necessary once because the 16-bit counter is cleared from FFFFH to 0000H immediately after the TQ0CE bit is set from 0 to 1. When 0001H is set to both the TQ0CCR0 and TQ0CCRk registers, the output of the TOQ0k pins is inverted each time the 16-bit counter counts twice (k = 1 to 3). The TQ0CTL0.TQ0EEE bit can be set to 1 in the interval timer mode only when the timer output (TOQ0k) is used with the external event count input. FFFFH 0001H 0001H 16-bit counter 0001H 0000H TQ0CE bit External event count input (TIQ00 pin input) TQ0CCR0 register 0001H 0001H 0001H TQ0CCR1 register 0001H 0001H 0001H 0001H 0001H 0001H 0001H 0001H 0001H TOQ01 pin output TQ0CCR2 register TOQ02 pin output TQ0CCR3 register TOQ03 pin output 2-count width Number of external events: 3 2-count width 2-count width Number of external events: 2 Number of external events: 2 User's Manual U16541EJ5V1UD 361 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input (TIQ00) is counted when the TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified <R> number of edges set by the TQ0CCR0 register have been counted. The TOQ00 to TOQ03 pins cannot be used. When using the TOQ01 and TOQ03 pins for external event count input, set the TQ0CTL1.TQ0EEE bit to 1 in the interval timer mode (see 8.6.1 (3) Operation by external event count input (TIQ00)). The TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. <R> Caution In the external event count mode, the TQ0CCR0 to TQ0CCR3 registers must not be cleared to 0000H. Figure 8-13. Configuration in External Event Count Mode Clear TIQ00 pin (external event count input) Edge detector 16-bit counter Match signal TQ0CE bit CCR0 buffer register TQ0CCR0 register 362 User's Manual U16541EJ5V1UD INTTQ0CC0 signal CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-14. Basic Timing in External Event Count Mode FFFFH 16-bit counter D0 D0 D0 0000H 16-bit counter TQ0CE bit External event count input (TIQ00 pin input) TQ0CCR0 register TQ0CCR0 register D0 <R> D0 0000 0001 D0 NTTQ0CC0 signal INTTQ0CC0 signal Number of external event count (D0) timesNote <R> D0 - 1 Number of external event count (D0 + 1) times Number of external event count (D0 + 1) times Note In the external event count mode, the 16-bit counter is cleared from FFFFH to 0000H as soon as the TQ0CTL0.TQ0CE bit has been set (1) (operation is started). The first counting operation is started from 0001H each time the valid edge of the external event count input has been detected. Therefore, the number of counts of the first counting operation is one less than that of the second counting operation. Remark This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. User's Manual U16541EJ5V1UD 363 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTQ0CC0) is generated. <R> The INTTQ0CC0 signal is generated for the first time when the valid edge of the external event count input has been detected "value set to TQ0CCR0 register" times. After that, the INTTQ0CC0 signal is generated each time the valid edge of the external event count has been detected "value set to TQ0CCR0 register + 1" times. Figure 8-15. Register Setting for Operation in External Event Count Mode (1/2) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CTL0 0/1 TQ0CKS2 TQ0CKS1 TQ0CKS0 0 0 0 0 0 0 0 0: Stop counting 1: Enable counting (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0CTL1 0 0 0 TQ0MD2 TQ0MD1 TQ0MD0 0 0 0 0 1 0, 0, 1: External event count mode (c) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (TIQ00 pin) 364 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-15. Register Setting for Operation in External Event Count Mode (2/2) (d) TMQ0 counter read buffer register (TQ0CNT) The count value of the 16-bit counter can be read by reading the TQ0CNT register. <R> (e) TMQ0 capture/compare register 0 (TQ0CCR0) If the TQ0CCR0 register is set to D0, the count is cleared when the number of external events has reached (D0) and the first compare match interrupt request signal (INTTQ0CC0) is generated. The second compare match interrupt request signal (INTTQ0CC0) is generated when the number of external events has reached (D0 + 1). <R> (f) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3) The TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. However, the set value of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer registers. When the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers, compare match interrupt request signals (INTTQ0CC1 to INTTQ0CC3) are generated. When the TQ0CCR1 to TQ0CCR3 registers are not used, it is recommended to set their values to FFFFH. Also mask the registers by the interrupt mask flags (TQ0CCIC1.TQ0CCMK1 to TQ0CCIC3.TQ0CCMK3). Cautions 1. Set the TQ0IOC0 register to 00H. 2. When the external clock is used as the count clock, the external clock can be input <R> only from the TIQ00 pin. At this time, clear the TQ0IOC1.TQ0IS1 and TQ0IS0 bits to 00 (capture trigger input (TIQ00 pin): No edge detected). Remark The TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not used in the external event count mode. User's Manual U16541EJ5V1UD 365 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) External event count mode operation flow Figure 8-16. Flow of Software Processing in External Event Count Mode FFFFH D0 16-bit counter D0 D0 0000H TQ0CE bit TQ0CCR0 register D0 INTTQ0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting TQ0CTL1 register, TQ0IOC2 register, TQ0CCR0 to TQ0CCR3 registers Initial setting of these registers is performed before setting the TQ0CE bit to 1. TQ0CE bit = 1 <2> Count operation stop flow TQ0CE bit = 0 The counter is initialized and counting is stopped by clearing the TQ0CE bit to 0. STOP 366 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TQ0CCR0 to TQ0CCR3 registers to 0000H. 2. In the external event count mode, use of the timer output (TOQ00 to TOQ03) is disabled. If using the timer outputs (TOQ01 to TOQ03) by the external event count input (TIQ00), set the interval timer mode, and enable operation by the external event count input for the count clock (TQ0CTL1.TQ0EEE bit = 1). Refer to 8.6.1 (3) Operation by external event count input (TIQ00). (a) Operation if TQ0CCR0 register is set to FFFFH If the TQ0CCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTQ0CC0 signal is generated. At this time, the TQ0OPT0.TQ0OVF bit is not set. FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register FFFFH INTTQ0CC0 signal <R> Number of external event count FFFFH times Number of external event count 10000H times User's Manual U16541EJ5V1UD Number of external event count 10000H times 367 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Notes on rewriting the TQ0CCR0 register When the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH D1 16-bit counter D1 D2 D2 D2 0000H TQ0CE bit TQ0CCR0 register D1 D2 INTTQ0CC0 signal Number of external event count (1) (D1) times <R> Number of external event count (NG) (10000H + D2 + 1) times Number of external event count(2) (D2 + 1) times If the value of the TQ0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TQ0CCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTQ0CC0 signal is generated. Therefore, the INTTQ0CC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times". 368 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-17. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer register Match signal INTTQ0CC1 signal TQ0CCR2 register CCR2 buffer register Match signal INTTQ0CC2 signal TQ0CCR3 register CCR3 buffer register Match signal INTTQ0CC3 signal Clear TIQ00 pin (external event count input) Edge detector 16-bit counter Match signal TQ0CE bit INTTQ0CC0 signal CCR0 buffer register TQ0CCR0 register User's Manual U16541EJ5V1UD 369 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is smaller than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. Remark k = 1 to 3 Figure 8-18. Timing Chart When D01 Dk1 FFFFH 16-bit counter D01 D31 D11 D21 D01 D01 D31 D31 D11 D21 D11 D21 0000H TQ0CE bit TQ0CCR0 register D01 INTTQ0CC0 signal TQ0CCR1 register D11 INTTQ0CC1 signal TQ0CCR2 register D21 INTTQ0CC2 signal TQ0CCR3 register D31 INTTQ0CC3 signal 370 User's Manual U16541EJ5V1UD D01 D31 D11 D21 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is not generated because the count value of the 16-bit counter and the value of the TQ0CCRk register do not match. <R> It is recommended to set FFFFH to the TQ0CCRk register when the TQ0CCRk register is not used. Remark k = 1 to 3 Figure 8-19. Timing Chart When D01 < Dk1 FFFFH D01 D01 D01 D01 16-bit counter 0000H TQ0CE bit D01 TQ0CCR0 register INTTQ0CC0 signal TQ0CCR1 register INTTQ0CC1 signal D11 L TQ0CCR2 register INTTQ0CC2 signal D21 L TQ0CCR3 register INTTQ0CC3 signal D31 L User's Manual U16541EJ5V1UD 371 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input signal (TIQ00) is detected, 16-bit timer/event counter Q starts counting, and outputs a PWM waveform (up to 3-phase) from the TOQ01 to TOQ03 pins. <R> Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave with a duty factor of 50% whose half cycle is the set value of the TQ0CCR0 register + 1 can also be output from the TOQ00 pin. Figure 8-20. Configuration in External Trigger Pulse Output Mode TQ0CCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal TOQ01 pin INTTQ0CC1 signal TQ0CCR2 register Transfer S Output R controller CCR2 buffer register Match signal TOQ02 pin INTTQ0CC2 signal TQ0CCR3 register TIQ00 pinNote (external trigger input) Transfer Edge detector CCR3 buffer register Software trigger generation Output S controller R (RS-FF) Match signal TOQ03 pin INTTQ0CC3 signal Clear Count clock selection Count start control 16-bit counter Output controller Match signal TQ0CE bit TOQ00 pinNote INTTQ0CC0 signal CCR0 buffer register Transfer TQ0CCR0 register <R> Note Because the external trigger input pin (TIQ00) and timer output pin (TOQ00) share the same alternatefunction pin, two functions cannot be used at the same time. <R> Caution In external trigger pulse output mode, select the internal clock (set the TQ0CTL1.TQ0EEE bit = 0) as the count clock. 372 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-21. Basic Timing in External Trigger Pulse Output Mode FFFFH D0 D3 D3 D2 16-bit counter D0 D3 D2 D1 D0 D3 D2 D1 D1 D1 D0 D2 D1 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register D0 INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) D1 TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Active level width (D1) Active level width (D1) Active level Active level width width (D1) (D1) TQ0CCR2 register Active level width (D1) D2 INTTQ0CC2 signal TOQ02 pin output Active level width (D2) Active level width (D2) TQ0CCR3 register Active level width (D2) D3 INTTQ0CC3 signal TOQ03 pin output Active level width (D3) Wait Cycle (D0 + 1) for trigger Active level width (D3) Cycle (D0 + 1) User's Manual U16541EJ5V1UD Active level width (D3) Cycle (D0 + 1) 373 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOQ0k pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the TOQ00 pin is inverted. The TOQ0k pin outputs a high-level regardless of low-level output period and high-level output period statuses when a trigger occurs.) The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TQ0CCRk register) x Count clock cycle Cycle = (Set value of TQ0CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1) The compare match request signal INTTQ0CC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTQ0CCk is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. The value set to the TQ0CCRm register is transferred to the CCRm buffer register when the count value of the 16bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input signal (TIQ00), or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is used as the trigger. Remark k = 1 to 3, m = 0 to 3 Figure 8-22. Setting of Registers in External Trigger Pulse Output Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CTL0 0/1 TQ0CKS2 TQ0CKS1 TQ0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clock <R> 0: Stop counting 1: Enable counting 374 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Setting of Registers in External Trigger Pulse Output Mode (2/3) (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE <R> TQ0CTL1 0 0/1 TQ0MD2 TQ0MD1 TQ0MD0 0 0 0 0 1 0 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TQ0CKS0 to TQ0CKS2 bits Generate software trigger when 1 is written (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level in status of waiting for external trigger 0: Low level 1: High level 0: Disable TOQ01 pin output 1: Enable TOQ01 pin output Setting of TOQ01 pin output level in status of waiting for external trigger 0: Low level 1: High level 0: Disable TOQ02 pin output 1: Enable TOQ02 pin output Setting of TOQ02 pin output level in status of waiting for external trigger 0: Low level 1: High level 0: Disable TOQ03 pin output 1: Enable TOQ03 pin output Setting of TOQ03 pin output level in status of waiting for external trigger 0: Low level 1: High level * When TQ0OLk bit = 0 * When TQ0OLk bit = 1 16-bit counter 16-bit counter TOQ0k pin output TOQ0k pin output Note Clear this bit to 0 when the TOQ00 pin is not used in the external trigger pulse output mode. User's Manual U16541EJ5V1UD 375 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Setting of Registers in External Trigger Pulse Output Mode (3/3) (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 <R> TQ0IOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (TIQ00 pin) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D0 is set to the TQ0CCR0 register, D1 to the TQ0CCR1 register, D2 to the TQ0CCR2 register, and D3, to the TQ0CCR3 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle TOQ01 pin PWM waveform active level width = D1 x Count clock cycle TOQ02 pin PWM waveform active level width = D2 x Count clock cycle TOQ03 pin PWM waveform active level width = D3 x Count clock cycle Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not used in the external trigger pulse output mode. 2. Updating TMQ0 capture/compare register 2 (TQ0CCR2) and TMQ0 capture/compare register 3 (TQ0CCR3) is validated by writing TMQ0 capture/compare register 1 (TQ0CCR1). 376 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in external trigger pulse output mode Figure 8-23. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH D01 D00 16-bit counter D30 D10 D20 D00 D31 D21 D31 D21 D11 D11 D00 D00 D31 D21 D30 D20 D10 D10 D00 D31 D21 D11 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) D10 TQ0CCR1 register D11 D11 D10 CCR1 buffer register D10 D11 D11 D10 D10 D11 D10 D11 INTTQ0CC1 signal TOQ01 pin output TQ0CCR2 register D20 CCR2 buffer register D20 D21 D20 D21 D21 D20 D21 INTTQ0CC2 signal TOQ02 pin output TQ0CCR3 register D30 CCR3 buffer register D30 D31 D30 D31 D31 D30 D31 INTTQ0CC3 signal TOQ03 pin output <1> <2> <3> <4> User's Manual U16541EJ5V1UD <5> <6> <7> 377 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-23. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow START Setting of TQ0CCR2, TQ0CCR3 registers Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC0 register, TQ0IOC2 register, TQ0CCR0 to TQ0CCR3 registers Initial setting of these registers is performed before setting the TQ0CE bit to 1. Setting of TQ0CCR1 register Writing of the TQ0CCR1 register must be performed when the set duty factor is only changed after writing the TQ0CCR2 and TQ0CCR3 registers. When the counter is cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer register. <5> TQ0CCR2 and TQ0CCR3 register setting change flow The TQ0CKS0 to TQ0CKS2 bits can be set at the same time when counting is enabled (TQ0CE bit = 1). Trigger wait status TQ0CE bit = 1 Setting of TQ0CCR2, TQ0CCR3 registers Setting of TQ0CCR1 register <2> TQ0CCR0 to TQ0CCR3 register setting change flow Setting of TQ0CCR0, TQ0CCR2, and TQ0CCR3 registers TQ0CCR1 register Writing of the TQ0CCR1 register must be performed after writing the TQ0CCR0, TQ0CCR2, and TQ0CCR3 registers. When the counter is cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer registers. Writing the same value (same as the TQ0CCR1 register already set) to the TQ0CCR1 register is necessary only when the set duty factor of TOQ02 and TOQ03 pin outputs is changed. When the counter is cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer register. <6> TQ0CCR1 register setting change flow Setting of TQ0CCR1 register Only writing of the TQ0CCR1 register must be performed when the set duty factor is only changed. When counter is cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer register. <3> TQ0CCR0 register setting change flow Setting of TQ0CCR0 register Setting of TQ0CCR1 register Remark 378 Writing the same value (same as the TQ0CCR1 register already set) to the TQ0CCR1 <7> Count operation stop flow register is necessary only when the set cycle is changed. TQ0CE bit = 0 When the counter is Counting is stopped. cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer register. STOP m = 0 to 3 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected. FFFFH 16-bit counter 0000H D01 D00 D30 D20 D10 D00 D30 D20 D10 D00 D30 D20 D10 D01 D31 D21 D31 D21 D11 D11 TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register D00 D01 D00 CCR0 buffer register D01 INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) D10 TQ0CCR1 register D11 D10 CCR1 buffer register D11 INTTQ0CC1 signal TOQ01 pin output TQ0CCR2 register D20 D21 D20 CCR2 buffer register D21 INTTQ0CC2 signal TOQ02 pin output TQ0CCR3 register CCR3 buffer register D30 D31 D30 D31 INTTQ0CC3 signal TOQ03 pin output User's Manual U16541EJ5V1UD 379 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level to the TQ0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TQ0CCR0 register, and then write the same value (same as the TQ0CCR1 register already set) to the TQ0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, first set an active level to the TQ0CCR2 and TQ0CCR3 registers and then set an active level to the TQ0CCR1 register. To change only the active level width (duty factor) of the PWM waveform output by the TOQ01 pin, only the TQ0CCR1 register has to be set. To change only the active level width (duty factor) of the PWM waveform output by the TOQ02 and TOQ03 pins, first set an active level width to the TQ0CCR2 and TQ0CCR3 registers, and then write the same value (same as the TQ0CCR1 register already set) to the TQ0CCR1 register. After data is written to the TQ0CCR1 register, the value written to the TQ0CCRm register is transferred to the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TQ0CCR0 to TQ0CCR3 registers again after writing the TQ0CCR1 register once, do so after the INTTQ0CC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because timing of transferring data from the TQ0CCRm register to the CCRm buffer register conflicts with writing the TQ0CCRm register. Remark 380 m = 0 to 3 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform <R> To output a 0% waveform, set the TQ0CCRk register to 0000H. The 16-bit counter is cleared to 0000H and the INTTQ0CC0 and INTTQ0CCk signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the CCR0 buffer register. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TQ0CE bit <R> External trigger input (TIQ00 pin input) TQ0CCR0 register D0 D0 D0 TQ0CCRk register 0000H 0000H 0000H INTTQ0CC0 signal INTTQ0CCk signal TOQ0k pin output Remark L k = 1 to 3 To output a 100% waveform, set a value of (set value of TQ0CCR0 register + 1) to the TQ0CCRk register. If the set value of the TQ0CCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TQ0CE bit <R> External trigger input (TIQ00 pin input) TQ0CCR0 register D0 D0 D0 TQ0CCRk register D0 + 1 D0 + 1 D0 + 1 INTTQ0CC0 signal INTTQ0CCk signal L TOQ0k pin output Remark k = 1 to 3 User's Manual U16541EJ5V1UD 381 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTQ0CCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQ0k pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF Dk - 1 0000 Dk 0000 External trigger input (TIQ00 pin input) Dk CCRk buffer register INTTQ0CCk signal TOQ0k pin output Shortened Remark k = 1 to 3 If the trigger is detected immediately before the INTTQ0CCk signal is generated, the INTTQ0CCk signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOQ0k pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter FFFF 0000 Dk - 2 0000 External trigger input (TIQ00 pin input) CCRk buffer register Dk INTTQ0CCk signal TOQ0k pin output Extended Remark 382 k = 1 to 3 User's Manual U16541EJ5V1UD 0001 Dk - 1 Dk CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOQ0k pin is extended by time from generation of the INTTQ0CC0 signal to trigger detection. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0000 External trigger input (TIQ00 pin input) D0 CCR0 buffer register INTTQ0CC0 signal TOQ0k pin output Extended Remark k = 1 to 3 If the trigger is detected immediately before the INTTQ0CC0 signal is generated, the INTTQ0CC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOQ0k pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter FFFF 0000 D0 - 1 D0 0000 0001 External trigger input (TIQ00 pin input) CCR0 buffer register D0 INTTQ0CC0 signal TOQ0k pin output Shortened Remark k = 1 to 3 User's Manual U16541EJ5V1UD 383 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the external trigger pulse output mode differs from the timing of other mode INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. Count clock 16-bit counter CCRk buffer register Dk - 2 Dk - 1 Dk Dk + 1 Dk + 2 Dk TOQ0k pin output INTTQ0CCk signal Remark k = 1 to 3 Usually, the INTTQ0CCk signal is generated in synchronization with the next count up after the count value of the 16-bit counter matches the value of the CCRk buffer register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOQ0k pin. 384 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input (TIQ00) is detected, 16-bit timer/event counter Q starts counting, and outputs a one-shot pulse from the TOQ01 to TOQ03 pins. Instead of the external trigger, a software trigger can also be generated to output the pulse. the TOQ00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 8-24. Configuration in One-Shot Pulse Output Mode TQ0CCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal TOQ01 pin INTTQ0CC1 signal TQ0CCR2 register Transfer Output S controller R (RS-FF) CCR2 buffer register Match signal TIQ00 pinNote (external trigger input) TOQ02 pin INTTQ0CC2 signal TQ0CCR3 register Edge detector Transfer Software trigger generation Output S controller R (RS-FF) CCR3 buffer register Match signal Count clock selection INTTQ0CC3 signal Clear Count start control Output S controller R (RS-FF) 16-bit counter Match signal TQ0CE bit TOQ03 pin TOQ00 pinNote INTTQ0CC0 signal CCR0 buffer register Transfer TQ0CCR0 register <R> Note Because the external trigger input pin (TIQ00) and timer output pin (TOQ00) share the same alternatefunction pin, two functions cannot be used at the same time. <R> Caution In one-shot pulse output mode, select the internal clock (set the TQ0CTL1.TQ0EEE bit = 0) as the count clock. User's Manual U16541EJ5V1UD 385 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-25. Basic Timing in One-Shot Pulse Output Mode FFFFH D0 D0 D3 16-bit counter D0 D3 D2 D3 D2 D1 D2 D1 D1 0000H TQ0CE bit External trigger input (TIQ00 pin input) D0 TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) TQ0CCR1 register D1 INTTQ0CC1 signal TOQ01 pin output Delay (D1) Active level width (D0 - D1 + 1) TQ0CCR2 register Delay (D1) Active level width (D0 - D1 + 1) Delay (D1) Active level width (D0 - D1 + 1) D2 INTTQ0CC2 signal TOQ02 pin output Delay (D2) TQ0CCR3 register Active level width (D0 - D2 + 1) Delay (D2) Active level width (D0 - D2 + 1) Delay (D2) Active level width (D0 - D2 + 1) D3 INTTQ0CC3 signal TOQ03 pin output Delay (D3) 386 Active level width (D0 - D3 + 1) Delay (D3) User's Manual U16541EJ5V1UD Active level width (D0 - D3 + 1) Delay (D3) Active level width (D0 - D3 + 1) CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0k pin. <R> After the one-shot pulse is output, the 16-bit counter is set to 0000H, stops counting, and waits for a trigger. When the trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TQ0CCRk register) x Count clock cycle Active level width = (Set value of TQ0CCR0 register - Set value of TQ0CCRk register + 1) x Count clock cycle The compare match interrupt request signal INTTQ0CC0 is generated when the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTQ0CCk is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. The valid edge of an external trigger input (TIQ00 pin) or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is used as the trigger. Remark k = 1 to 3 Figure 8-26. Setting of Registers in One-Shot Pulse Output Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CTL0 0/1 TQ0CKS2 TQ0CKS1 TQ0CKS0 0 0 0 0 0/1 0/1 0/1 <R> Select count clock 0: Stop counting 1: Enable counting (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE <R> TQ0CTL1 0 0/1 0 TQ0MD2 TQ0MD1 TQ0MD0 0 0 0 1 1 0, 1, 1: One-shot pulse output mode 0: Operate on count clock selected by TQ0CKS0 to TQ0CKS2 bits Generate software trigger when 1 is written User's Manual U16541EJ5V1UD 387 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Register Setting in One-Shot Pulse Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0/1 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level in status of waiting for external trigger 0: Low level 1: High level 0: Disable TOQ01 pin output 1: Enable TOQ01 pin output Setting of TOQ01 pin output level in status of waiting for external trigger 0: Low level 1: High level 0: Disable TOQ02 pin output 1: Enable TOQ02 pin output Setting of TOQ02 pin output level in status of waiting for external trigger 0: Low level 1: High level 0: Disable TOQ03 pin output 1: Enable TOQ03 pin output Setting of TOQ03 pin output level in status of waiting for external trigger 0: Low level 1: High level * When TQ0OLk bit = 0 * When TQ0OLk bit = 1 16-bit counter 16-bit counter TOQ0k pin output TOQ0k pin output Note Clear this bit to 0 when the TOQ00 pin is not used in the one-shot pulse output mode. (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 <R> TQ0IOC2 0 0 0 0 0 0 0/1 0/1 Select valid edge of external trigger input (TIQ00 pin) 388 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Register Setting in One-Shot Pulse Output Mode (3/3) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D0 is set to the TQ0CCR0 register and Dk to the TQ0CCRk register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D0 - Dk + 1) x Count clock cycle Output delay period = Dk x Count clock cycle <R> Caution If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register in the one-shot pulse output mode, the one-shot pulse is not output. Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not used in the one-shot pulse output mode. 2. k = 1 to 3 User's Manual U16541EJ5V1UD 389 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in one-shot pulse output mode Figure 8-27. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH D00 D01 D30 16-bit counter D31 D20 D10 D11 D21 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register D00 D01 D10 D11 INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output TQ0CCR2 register D20 D21 INTTQ0CC2 signal TOQ02 pin output TQ0CCR3 register D30 D31 INTTQ0CC3 signal TOQ03 pin output <1> 390 <2> User's Manual U16541EJ5V1UD <3> CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-27. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <1> Count operation start flow <2> TQ0CCR0 to TQ0CCR3 register setting change flow START Setting of TQ0CCR0 to TQ0CCR3 registers Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC0 register, TQ0IOC2 register, TQ0CCR0 to TQ0CCR3 registers TQ0CE bit = 1 Initial setting of these registers is performed before setting the TQ0CE bit to 1. As rewriting the TQ0CCRm register immediately forwards to the CCRm buffer register, rewriting immediately after the generation of the INTTQ0CC0 signal is recommended. <3> Count operation stop flow The TQ0CKS0 to TQ0CKS2 bits can be set at the same time when counting has been started (TQ0CE bit = 1). Trigger wait status TQ0CE bit = 0 Count operation is stopped STOP Remark m = 0 to 3 User's Manual U16541EJ5V1UD 391 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TQ0CCRm register When the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. If there is a possibility of overflow, stop counting and then change the set value. FFFFH D00 D00 D01 16-bit counter Dk0 D01 Dk0 Dk1 Dk1 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register D00 D01 INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) TQ0CCRk register Dk0 Dk1 INTTQ0CCk signal TOQ0k pin output Delay (Dk0) Delay (Dk1) Delay (10000H + Dk1) Active level width (D00 - Dk0 + 1) Active level width (D01 - Dk1 + 1) Active level width (D01 - Dk1 + 1) When the TQ0CCR0 register is rewritten from D00 to D01 and the TQ0CCRk register from Dk0 to Dk1 where D00 > D01 and Dk0 > Dk1, if the TQ0CCRk register is rewritten when the count value of the 16-bit counter is greater than Dk1 and less than Dk0 and if the TQ0CCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches Dk1, the counter generates the INTTQ0CCk signal and asserts the TOQ0k pin. When the count value matches D01, the counter generates the INTTQ0CC0 signal, deasserts the TOQ0k pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the one-shot pulse that is originally expected. Remark m = 0 to 3, k = 1 to 3 392 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Generation timing of compare match interrupt request signal (INTTQ0CCk) The generation timing of the INTTQ0CCk signal in the one-shot pulse output mode is different from other mode INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register. Count clock 16-bit counter Dk - 2 Dk - 1 TQ0CCRk register Dk Dk + 1 Dk + 2 Dk TOQ0k pin output INTTQ0CCk signal Usually, the INTTQ0CCk signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TQ0CCRk register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the TOQ0k pin. Remark k = 1 to 3 User's Manual U16541EJ5V1UD 393 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOQ01 to TOQ03 pins when the TQ0CTL0.TQ0CE bit is set to 1. In addition, a square wave with a duty factor of 50% with the set value of the TQ0CCR0 register + 1 as half its cycle is output from the TOQ00 pin. <R> Figure 8-28. Configuration in PWM Output Mode TQ0CCR1 register Transfer Output S controller R (RS-FF) CCR1 buffer register Match signal TOQ01 pin INTTQ0CC1 signal TQ0CCR2 register Transfer S Output controller R (RS-FF) CCR2 buffer register Match signal TOQ02 pin INTTQ0CC2 signal TQ0CCR3 register Transfer CCR3 buffer register Output S controller R (RS-FF) Match signal TOQ03 pin INTTQ0CC3 signal Clear Internal count clock TIQ00 pinNote (external event Edge count input) detector Count clock selection Count start control 16-bit counter Output controller Match signal TQ0CE bit TOQ00 pinNote INTTQ0CC0 signal CCR0 buffer register Transfer TQ0CCR0 register Note Because the external event count input pin (TIQ00) and timer output pin (TOQ00) share the same alternate-function pin, two functions cannot be used at the same time. 394 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-29. Basic Timing in PWM Output Mode FFFFH D3 16-bit counter D1 D0 D3 D0 D3 D2 D2 D0 D3 D2 D1 D0 D2 D1 D1 0000H TQ0CE bit D0 TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register D1 INTTQ0CC1 signal TOQ01 pin output Active level width (D1) Active level width (D1) Active level width (D1) Active level width (D1) D2 TQ0CCR2 register INTTQ0CC2 signal TOQ02 pin output Active level width (D2) Active level width (D2) Active level width (D2) Active level width (D2) D3 TQ0CCR3 register INTTQ0CC3 signal TOQ03 pin output Active level width (D3) Cycle (D0 + 1) Active level width (D3) Cycle (D0 + 1) Active level width (D3) Cycle (D0 + 1) User's Manual U16541EJ5V1UD Active level width (D3) Cycle (D0 + 1) 395 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM waveform from the TOQ0k pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TQ0CCRk register) x Count clock cycle Cycle = (Set value of TQ0CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1) The PWM waveform can be changed by rewriting the TQ0CCRm register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTQ0CC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTQ0CCk is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register. Remark k = 1 to 3, m = 0 to 3 Figure 8-30. Setting of Registers in PWM Output Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CTL0 0/1 TQ0CKS2 TQ0CKS1 TQ0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1. (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0CTL1 0 0 0/1 TQ0MD2 TQ0MD1 TQ0MD0 0 0 1 0 0 1, 0, 0: PWM output mode 0: Operate on count clock selected by TQ0CKS0 to TQ0CKS2 bits 1: Count external event input signal 396 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-30. Setting of Registers in PWM Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1Note 0/1 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of TOQ00 pin output level before count operation 0: Low level 1: High level 0: Disable TOQ01 pin output 1: Enable TOQ01 pin output Setting of TOQ01 pin output level before count operation 0: Low level 1: High level 0: Disable TOQ02 pin output 1: Enable TOQ02 pin output Setting of TOQ02 pin output level before count operation 0: Low level 1: High level 0: Disable TOQ03 pin output 1: Enable TOQ03 pin output Setting of TOQ03 pin output level before count operation 0: Low level 1: High level * When TQ0OLk bit = 0 * When TQ0OLk bit = 1 16-bit counter 16-bit counter TOQ0k pin output TOQ0k pin output Note Clear this bit to 0 when the TOQ00 pin is not used in the PWM output mode. (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (TIQ00 pin). (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. User's Manual U16541EJ5V1UD 397 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-30. Register Setting in PWM Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 and TQ0CCR3) If D0 is set to the TQ0CCR0 register and Dk to the TQ0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = Dk x Count clock cycle Remarks 1. TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not used in the PWM output mode. 2. Updating the TMQ0 capture/compare register 2 (TQ0CCR2) and TMQ0 capture/compare register 3 (TQ0CCR3) is validated by writing the TMQ0 capture/compare register 1 (TQ0CCR1). 398 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in PWM output mode Figure 8-31. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 D00 16-bit counter D30 D10 D20 D00 D31 D21 D31 D21 D11 D11 D00 D00 D31 D21 D30 D20 D10 D10 D00 D31 D21 D11 0000H TQ0CE bit TQ0CCR0 register D00 CCR0 buffer register D01 D00 D00 D01 D00 INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register D10 CCR1 buffer register D11 D11 D10 D10 D11 D11 D10 D10 D11 D10 D11 INTTQ0CC1 signal TOQ01 pin output TQ0CCR2 register D20 CCR2 buffer register D20 D21 D20 D21 D21 D20 D21 INTTQ0CC2 signal TOQ02 pin output TQ0CCR3 register D30 CCR3 buffer register D30 D31 D30 D31 D31 D30 D31 INTTQ0CC3 signal TOQ03 pin output <1> <2> <3> <4> User's Manual U16541EJ5V1UD <5> <6> <7> 399 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow START Setting of TQ0CCR2, TQ0CCR3 registers Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC0 register, TQ0IOC2 register, TQ0CCR0 to TQ0CCR3 registers Initial setting of these registers is performed before setting the TQ0CE bit to 1. Setting of TQ0CCR1 register Only writing of the TQ0CCR1 register must be performed when the set duty factor is only changed after writing the TQ0CCR2 and TQ0CCR3 registers. When the counter is cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer register. <5> TQ0CCR2 and TQ0CCR3 register setting change flow The TQ0CKS0 to TQ0CKS2 bits can be set at the same time when counting is enabled (TQ0CE bit = 1). TQ0CE bit = 1 Setting of TQ0CCR2, TQ0CCR3 registers Setting of TQ0CCR1 register <2> TQ0CCR0 to TQ0CCR3 register setting change flow Setting of TQ0CCR0, TQ0CCR2, and TQ0CCR3 registers TQ0CCR1 register Writing of the TQ0CCR1 register must be performed after writing the TQ0CCR0, TQ0CCR2, and TQ0CCR3 registers. When the counter is cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer registers. Writing the same value (same as the TQ0CCR1 register already set) to the TQ0CCR1 register is necessary only when the set duty factor of the TOQ02 and TOQ03 pin outputs is changed. When the counter is cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer register. <6> TQ0CCR1 register setting change flow Setting of TQ0CCR1 register Only writing of the TQ0CCR1 register must be performed when the set duty factor is only changed. When counter is cleared after setting, the value of the TQ0CCRm register is transferred to the CCRm buffer register. <3> TQ0CCR0 register setting change flow Setting of TQ0CCR0 register Setting of TQ0CCR1 register Remark 400 Writing the same value (same as the TQ0CCR1 register <7> Count operation stop flow already set) to the TQ0CCR1 register is necessary only TQ0CE bit = 0 when the set cycle is changed. Counting is stopped. When the counter is cleared after setting, the value of the TQ0CCRm register is transferred to STOP the CCRm buffer register. m = 0 to 3 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC1 signal is detected. FFFFH 16-bit counter 0000H D01 D00 D30 D20 D10 D00 D30 D20 D10 D00 D30 D20 D10 D01 D31 D21 D31 D21 D11 D11 TQ0CE bit TQ0CCR0 register D00 D01 D00 CCR0 buffer register D01 INTTQ0CC0 signal TOQ00 pin output D10 TQ0CCR1 register D11 D10 CCR1 buffer register D11 INTTQ0CC1 signal TOQ01 pin output TQ0CCR2 register CCR2 buffer register D20 D21 D20 D21 INTTQ0CC2 signal TOQ02 pin output TQ0CCR3 register CCR3 buffer register D30 D30 D31 D31 INTTQ0CC3 signal TOQ03 pin output User's Manual U16541EJ5V1UD 401 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) To transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level width to the TQ0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TQ0CCR0 register, and then write the same value (same as the TQ0CCR1 register already set) to the TQ0CCR1 register. To change only the active level width (duty factor) of PWM wave, first set the active level to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level to the TQ0CCR1 register. To change only the active level width (duty factor) of the PWM waveform output by the TOQ01 pin, only the TQ0CCR1 register has to be set. To change only the active level width (duty factor) of the PWM waveform output by the TOQ02 and TOQ03 pins, first set an active level width to the TQ0CCR2 and TQ0CCR3 registers, and then write the same value (same as the TQ0CCR1 register already set) to the TQ0CCR1 register. After the TQ0CCR1 register is written, the value written to the TQ0CCRm register is transferred to the CCRm buffer register in synchronization with the timing of clearing the 16-bit counter, and is used as a value to be compared with the value of the 16-bit counter. To change only the cycle of the PWM waveform, first set a cycle to the TQ0CCR0 register, and then write the same value to the TQ0CCR1 register. To write the TQ0CCR0 to TQ0CCR3 registers again after writing the TQ0CCR1 register once, do so after the INTTQ0CC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined because the timing of transferring data from the TQ0CCRm register to the CCRm buffer register conflicts with writing the TQ0CCRm register. Remark 402 m = 0 to 3 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform <R> To output a 0% waveform, set the TQ0CCRk register to 0000H. The 16-bit counter is cleared to 0000H and the INTTQ0CC0 and INTQ0CCk signals are generated at the timing following the clock in which the count value of the 16-bit counter matches the value of the CCR0 buffer register. Count clock FFFF 16-bit counter 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TQ0CE bit TQ0CCR0 register D0 D0 D0 TQ0CCRk register 0000H 0000H 0000H INTTQ0CC0 signal INTTQ0CCk signal TOQ0k pin output Remark k = 1 to 3 To output a 100% waveform, set a value of (set value of TQ0CCR0 register + 1) to the TQ0CCRk register. If the set value of the TQ0CCR0 register is FFFFH, 100% output cannot be produced. Count clock FFFF 16-bit counter 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 TQ0CE bit TQ0CCR0 register D0 D0 D0 TQ0CCRk register D0 + 1 D0 + 1 D0 + 1 INTTQ0CC0 signal INTTQ0CCk signal L TOQ0k pin output Remark k = 1 to 3 User's Manual U16541EJ5V1UD 403 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the PWM output mode differs from the timing of other mode INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register. Count clock 16-bit counter CCRk buffer register Dk - 2 Dk - 1 Dk Dk + 1 Dk + 2 Dk TOQ0k pin output INTTQ0CCk signal Remark k = 1 to 3 Usually, the INTTQ0CCk signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TQ0CCRk register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the output signal of the TOQ0k pin. 404 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. At this time, the TQ0CCRm register can be used as a compare register or a capture register, depending on the setting of the TQ0OPT0.TQ0CCSm bit. Remark m = 0 to 3 User's Manual U16541EJ5V1UD 405 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-32. Configuration in Free-Running Timer Mode TQ0CCR3 register (compare) TQ0CCR2 register (compare) TQ0CCR1 register (compare) TQ0CCR0 register (compare) Internal count clock TIQ00 pinNote 1 (external event count input/ capture trigger input) Note 2 TIQ01 pin (capture trigger input) TIQ02 pinNote 2 (capture trigger input) TIQ03 pinNote 2 (capture trigger input) Edge detector Output controller TOQ03 pinNote 2 Output controller TOQ02 pinNote 2 Output controller TOQ01 pinNote 2 Output controller TOQ00 pinNote 1 TQ0CCSm bit (capture/compare selection) Count clock selection INTTQ0OV signal 16-bit counter TQ0CE bit 0 Edge detector INTTQ0CC3 signal 1 TQ0CCR0 register (capture) 0 INTTQ0CC2 signal 1 Edge detector 0 TQ0CCR1 register (capture) Edge detector INTTQ0CC1 signal 1 0 1 INTTQ0CC0 signal TQ0CCR2 register (capture) Edge detector TQ0CCR3 register (capture) <R> Notes 1. Because the external event count input pin (TIQ00), capture trigger input pin (TIQ00), and timer output pin (TOQ00) share the same alternate-function pin, two or more functions cannot be used at the same time. <R> 2. Because the capture trigger input pin (TIQ0k) and timer output pin (TOQ0k) share the same alternate-function pin, two or more functions cannot be used at the same time (k = 1 to 3). 406 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) * Compare operation When the TQ0CE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQ00 to TOQ03 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQ0CCRm register, a compare match interrupt request signal (INTTQ0CCm) is generated, and the output signal of the TOQ0m pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TQ0OPT0.TQ0OVF bit) is also set to 1. Confirm that the overflow flag is set to 1 and then clear it to 0 by executing the CLR instruction via software. The TQ0CCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected immediately and compared with the count value. Remark m = 0 to 3 Figure 8-33. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH 16-bit counter D00 D30 D00 D30 D20 D01 D31 D20 D10 D11 D21 D11 D01 D31 D21 D11 0000H TQ0CE bit D00 TQ0CCR0 register D01 INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register D10 D11 INTTQ0CC1 signal TOQ01 pin output TQ0CCR2 register D20 D21 INTTQ0CC2 signal TOQ02 pin output TQ0CCR3 register D30 D31 INTTQ0CC3 signal TOQ03 pin output INTTQ0OV signal TQ0OVF bit Cleared to 0 by CLR instruction Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction User's Manual U16541EJ5V1UD 407 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) * Capture operation When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request signal (INTTQ0CCm) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TQ0OPT0.TQ0OVF bit) is also set to 1. Confirm that the overflow flag is set to 1 and then clear it to 0 by executing the CLR instruction via software. Remark m = 0 to 3 Figure 8-34. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH 16-bit counter D10 D30 D31 D21 D00 D20 D32 D22 D23 D33 D11 D02 D12 D01 D13 D03 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000 D00 D01 D02 D03 INTTQ0CC0 signal TIQ01 pin input TQ0CCR1 register 0000 D10 D11 D12 D13 INTTQ0CC1 signal TIQ02 pin input TQ0CCR2 register 0000 D20 D21 D22 D23 INTTQ0CC2 signal TIQ03 pin input TQ0CCR3 register 0000 D30 D31 D32 INTTQ0CC3 signal INTTQ0OV signal TQ0OVF bit Cleared to 0 by CLR instruction 408 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction User's Manual U16541EJ5V1UD D33 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Register Setting in Free-Running Timer Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CTL0 0/1 TQ0CKS2 TQ0CKS1 TQ0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1 (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0CTL1 0 0 0/1 TQ0MD2 TQ0MD1 TQ0MD0 0 0 1 0 1 1, 0, 1: Free-running timer mode 0: Operate with count clock selected by TQ0CKS0 to TQ0CKS2 bits 1: Count on external event count input signal (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0IOC0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of output level before TOQ00 pin count operation 0: Low level 1: High level 0: Disable TOQ01 pin output 1: Enable TOQ01 pin output Setting of output level before TOQ01 pin count operation 0: Low level 1: High level 0: Disable TOQ02 pin output 1: Enable TOQ02 pin output Setting of output level before TOQ02 pin count operation 0: Low level 1: High level 0: Disable TOQ03 pin output 1: Enable TOQ03 pin output Setting of output level before TOQ03 pin count operation 0: Low level 1: High level User's Manual U16541EJ5V1UD 409 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Register Setting in Free-Running Timer Mode (2/3) (d) TMQ0 I/O control register 1 (TQ0IOC1) TQ0IOC1 TQ0IS7 TQ0IS6 TQ0IS5 TQ0IS4 TQ0IS3 TQ0IS2 TQ0IS1 TQ0IS0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Select valid edge of TIQ00 pin inputNote <R> Select valid edge of TIQ01 pin input Select valid edge of TIQ02 pin input Select valid edge of TIQ03 pin input <R> Note Set the valid edge selection of the unused alternate external input signals to "No edge detection". (e) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (TIQ00 pin)Note <R> Note Set the valid edge selection of the unused alternate external input signals to "No edge detection". <R> (f) TMQ0 option register 0 (TQ0OPT0) TQ0CCS3 TQ0CCS2 TQ0CCS1 TQ0CCS0 TQ0OPT0 0/1 0/1 0/1 0/1 TQ0OVF 0 0 0 0/1 Overflow flag Specifies if TQ0CCR0 register functions as capture or compare register 0: Compare register 1: Capture register Specifies if TQ0CCR1 register functions as capture or compare register 0: Compare register 1: Capture register Specifies if TQ0CCR2 register functions as capture or compare register 0: Compare register 1: Capture register Specifies if TQ0CCR3 register functions as capture or compare register 0: Compare register 1: Capture register 410 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Register Setting in Free-Running Timer Mode (3/3) (g) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (h) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) These registers function as capture registers or compare registers depending on the setting of the TQ0OPT0.TQ0CCSm bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIQ0m pin is detected. When the registers function as compare registers and when Dm is set to the TQ0CCRm register, the INTTQ0CCm signal is generated when the counter reaches (Dm + 1), and the output signal of the TOQ0m pin is inverted. Remark m = 0 to 3 User's Manual U16541EJ5V1UD 411 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-36. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH D21 D00 D30 D20 16-bit counter D21 D00 D30 D20 D10 D10 D01 D31 D11 D01 D31 D11 D11 0000H TQ0CE bit TQ0CCR0 register D00 D01 D10 D11 D20 D21 D30 D31 INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output TQ0CCR2 register INTTQ0CC2 signal TOQ02 pin output TQ0CCR3 register INTTQ0CC3 signal TOQ03 pin output INTTQ0OV signal TQ0OVF bit <1> Cleared to 0 by CLR instruction <2> 412 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction <2> User's Manual U16541EJ5V1UD <2> <3> CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-36. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Initial setting of these registers is performed before setting the TQ0CE bit to 1. Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC0 register, TQ0IOC2 register, TQ0OPT0 register, TQ0CCR0 to TQ0CCR3 registers The TQ0CKS0 to TQ0CKS2 bits can be set at the same time when counting has been started (TQ0CE bit = 1). TQ0CE bit = 1 <2> Overflow flag clear flow Read TQ0OPT0 register (check overflow flag). TQ0OVF bit = 1 No Yes Execute instruction to clear TQ0OVF bit (CLR TQ0OVF). <3> Count operation stop flow TQ0CE bit = 0 Counter is initialized and counting is stopped by clearing TQ0CE bit to 0. STOP User's Manual U16541EJ5V1UD 413 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) When using capture/compare register as capture register Figure 8-37. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH D10 D30 D31 D21 D00 D20 16-bit counter D32 D22 D23 D33 D11 D02 D12 D01 D13 D03 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000 D00 D01 D02 D03 0000 INTTQ0CC0 signal TIQ01 pin input TQ0CCR1 register 0000 D10 0000 D20 D11 D12 0000 D13 INTTQ0CC1 signal TIQ02 pin input TQ0CCR2 register D21 D22 D23 0000 INTTQ0CC2 signal TIQ03 pin input TQ0CCR3 register 0000 D30 D31 D32 0000 D33 INTTQ0CC3 signal INTTQ0OV signal TQ0OVF bit <1> Cleared to 0 by CLR instruction <2> 414 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction <2> User's Manual U16541EJ5V1UD <2> <3> CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-37. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits) TQ0CTL1 register, TQ0IOC1 register, TQ0OPT0 register Initial setting of these registers is performed before setting the TQ0CE bit to 1. The TQ0CKS0 to TQ0CKS2 bits can be set at the same time when counting has been started (TQ0CE bit = 1). TQ0CE bit = 1 <2> Overflow flag clear flow Read TQ0OPT0 register (check overflow flag). TQ0OVF bit = 1 No Yes Execute instruction to clear TQ0OVF bit (CLR TQ0OVF). <3> Count operation stop flow TQ0CE bit = 0 Counter is initialized and counting is stopped by clearing TQ0CE bit to 0. STOP User's Manual U16541EJ5V1UD 415 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter Q is used as an interval timer with the TQ0CCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTQ0CCm signal has been detected. Remark m = 0 to 3 FFFFH D01 D11 D30 D04 D13 D31 D22 D03 D20 D10 16-bit counter D12 D00 D23 D02 D21 0000H TQ0CE bit TQ0CCR0 register D00 D01 D02 D03 D04 D05 INTTQ0CC0 signal TOQ00 pin output Interval period Interval period Interval period Interval period Interval period (D00 + 1) (D01 - D00) (10000H + (D03 - D02) (D04 - D03) D02 - D01) TQ0CCR1 register D10 D11 D12 D13 D14 INTTQ0CC1 signal TOQ01 pin output Interval period (D10 + 1) TQ0CCR2 register Interval period Interval period Interval period (D11 - D10) (10000H + D12 - D11) (D13 - D12) D20 D21 D22 D23 INTTQ0CC2 signal TOQ02 pin output Interval period Interval period Interval period Interval period (D20 + 1) (10000H + D21 - D20) (D22 - D21) (10000H + D23 - D22) TQ0CCR3 register D30 D31 INTTQ0CC3 signal TOQ03 pin output Interval period (D30 + 1) 416 Interval period (10000H + D31 - D30) User's Manual U16541EJ5V1UD D32 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TQ0CCRm register must be re-set in the interrupt servicing that is executed when the INTTQ0CCm signal is detected. The set value for re-setting the TQ0CCRm register can be calculated by the following expression, where "Dm" is the interval period. Compare register default value: Dm - 1 Value set to compare register second and subsequent time: Previous set value + Dm (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark m = 0 to 3 User's Manual U16541EJ5V1UD 417 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TQ0CCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTQ0CCm signal has been detected and for calculating an interval. FFFFH 16-bit counter D10 D30 D31 D21 D00 D20 D13 D32 D23 D33 D11 D02 D12 D01 D22 D03 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000 D00 D01 D02 Pulse interval (10000H + D02 - D01) Pulse interval (10000H + D03 - D02) D03 INTTQ0CC0 signal Pulse interval Pulse interval (D00 + 1) (10000H + D01 - D00) TIQ01 pin input TQ0CCR1 register 0000 D10 D11 D12 D13 INTTQ0CC1 signal Pulse interval Pulse interval Pulse interval Pulse interval (D10 + 1) (10000H + (10000H + (D13 - D12) D11 - D10) D12 - D11) TIQ02 pin input TQ0CCR2 register 0000 D21 D20 D22 D23 INTTQ0CC2 signal Pulse interval (D20 + 1) Pulse interval (10000H + D21 - D20) Pulse interval (20000H + D22 - D21) Pulse interval (D23 - D22) D31 D32 TIQ03 pin input TQ0CCR3 register 0000 D30 INTTQ0CC3 signal Pulse interval Pulse interval (10000H + (D30 + 1) D31 - D30) Pulse interval (10000H + D32 - D31) Pulse interval (10000H + D33 - D32) INTTQ0OV signal TQ0OVF bit Cleared to 0 by CLR instruction 418 Cleared to 0 by Cleared to 0 by CLR instruction CLR instruction User's Manual U16541EJ5V1UD D33 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TQ0CCRm register in synchronization with the INTTQ0CCm signal, and calculating the difference between the read value and the previously read value. Remark m = 0 to 3 User's Manual U16541EJ5V1UD 419 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two or more capture registers are used FFFFH D11 D10 16-bit counter D01 D00 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register D01 D00 TIQ01 pin input D11 D10 TQ0CCR1 register INTTQ0OV signal TQ0OVF bit <1> <2> <3> <4> The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TQ0CCR0 register (setting of the default value of the TIQ00 pin input). <2> Read the TQ0CCR1 register (setting of the default value of the TIQ01 pin input). <3> Read the TQ0CCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TQ0CCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect). When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below. 420 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit TQ0OVF0 flagNote TIQ00 pin input D01 D00 TQ0CCR0 register TQ0OVF1 flagNote TIQ01 pin input D11 D10 TQ0CCR1 register <1> <2> <3> <4> <5> <6> Note The TQ0OVF0 and TQ0OVF1 flags are set on the internal RAM by software. <1> Read the TQ0CCR0 register (setting of the default value of the TIQ00 pin input). <2> Read the TQ0CCR1 register (setting of the default value of the TIQ01 pin input). <3> An overflow occurs. Set the TQ0OVF0 and TQ0OVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TQ0CCR0 register. Read the TQ0OVF0 flag. If the TQ0OVF0 flag is 1, clear it to 0. Because the TQ0OVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TQ0CCR1 register. Read the TQ0OVF1 flag. If the TQ0OVF1 flag is 1, clear it to 0 (the TQ0OVF0 flag is cleared in <4>, and the TQ0OVF1 flag remains 1). Because the TQ0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> User's Manual U16541EJ5V1UD 421 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 D10 16-bit counter D01 D00 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit TQ0OVF0 flagNote L TIQ00 pin input D01 D00 TQ0CCR0 register TQ0OVF1 flagNote TIQ01 pin input D11 D10 TQ0CCR1 register <1> <2> <3> <4> <5> <6> Note The TQ0OVF0 and TQ0OVF1 flags are set on the internal RAM by software. <1> Read the TQ0CCR0 register (setting of the default value of the TIQ00 pin input). <2> Read the TQ0CCR1 register (setting of the default value of the TIQ01 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TQ0CCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TQ0OVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TQ0CCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TQ0OVF1 flag. If the TQ0OVF1 flag is 1, clear it to 0. Because the TQ0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> 422 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register Dm0 Dm1 INTTQ0OV signal TQ0OVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> The following problem may occur when a long pulse width in the free-running timer mode. <1> Read the TQ0CCRm register (setting of the default value of the TIQ0m pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TQ0CCRm register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Dm1 - Dm0) (incorrect). Actually, the pulse width must be (20000H + Dm1 - Dm0) because an overflow occurs twice. Remark m = 0 to 3 If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. User's Manual U16541EJ5V1UD 423 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Example when capture trigger interval is long FFFFH Dm0 16-bit counter Dm1 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register Dm0 Dm1 INTTQ0OV signal TQ0OVF bit Overflow counterNote 0H 1H 2H 0H 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TQ0CCRm register (setting of the default value of the TIQ0m pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TQ0CCRm register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Dm1 - Dm0). In this example, the pulse width is (20000H + Dm1 - Dm0) because an overflow occurs twice. Clear the overflow counter (0H). Remark m = 0 to 3 (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction after reading TQ0OVF bit = 1 and by writing 8-bit data (bit 0 is 0) to the TQ0OPT0 register after reading TQ0OVF bit = 1. 424 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) <R> (3) Note on capture operation If the capture operation is used and if a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured to the TQ0CCRm register if the capture trigger is input immediately after the TQ0CTL0.TQ0CE bit is set to 1 (m = 0 to 3). FFFFH 16-bit counter 0000H Count clock Sampling clock TQ0CCR0 register 0000H FFFFH 0001H TQ0CE bit TIQ00 pin input Capture trigger input Capture trigger input User's Manual U16541EJ5V1UD 425 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.6.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. Each time the valid edge input to the TIQ0m pin has been detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TQ0CCRm register after a capture interrupt request signal (INTTQ0CCm) occurs. In case of Figure 8-39, select either of the TIQ00 to TIQ03 pins as the capture trigger input pin. Specify "No edge detected" by using the TQ0IOC1 register for the unused pins. Remark m = 0 to 3 k = 1 to 3 Figure 8-38. Configuration in Pulse Width Measurement Mode <R> Count clock selection TIQ00 pin (capture trigger input) TIQ01 pin (capture trigger input) TIQ02 pin (capture trigger input) TIQ03 pin (capture trigger input) Clear 16-bit counter TQ0CE bit Edge detector INTTQ0OV signal INTTQ0CC0 signal TQ0CCR0 register (capture) INTTQ0CC1 signal Edge detector TQ0CCR1 register (capture) INTTQ0CC2 signal INTTQ0CC3 signal Edge detector TQ0CCR2 register (capture) Edge detector TQ0CCR3 register (capture) Caution In the pulse width measurement mode, select the internal clock (set the TQ0CTL1.TQ0EEE bit = 0) as the count clock. 426 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-39. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register 0000H D0 D1 D2 D3 INTTQ0CCm signal INTTQ0OV signal Cleared to 0 by CLR instruction TQ0OVF bit Remark m = 0 to 3 When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is later detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTQ0CCm) is generated. The pulse width is calculated as follows. Pulse width = Captured value x Count clock cycle If the valid edge is not input to the TIQ0m pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTQ0OV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TQ0OPT0.TQ0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. Pulse width = (10000H x TQ0OVF bit set (1) count + Captured value) x Count clock cycle Remark m = 0 to 3 User's Manual U16541EJ5V1UD 427 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-40. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CTL0 0/1 TQ0CKS2 TQ0CKS1 TQ0CKS0 0 0 0 0 0/1 0/1 0/1 <R> Select count clock 0: Stop counting 1: Enable counting (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE <R> TQ0CTL1 0 0 0 TQ0MD2 TQ0MD1 TQ0MD0 0 0 1 1 0 1, 1, 0: Pulse width measurement mode 0: Operate with count clock selected by TQ0CKS0 to TQ0CKS2 bits (c) TMQ0 I/O control register 1 (TQ0IOC1) TQ0IOC1 TQ0IS7 TQ0IS6 TQ0IS5 TQ0IS4 TQ0IS3 TQ0IS2 TQ0IS1 TQ0IS0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Select valid edge of TIQ00 pin input Select valid edge of TIQ01 pin input Select valid edge of TIQ02 pin input Select valid edge of TIQ03 pin input 428 User's Manual U16541EJ5V1UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-40. Register Setting in Pulse Width Measurement Mode (2/2) (d) TMQ0 option register 0 (TQ0OPT0) TQ0CCS3 TQ0CCS2 TQ0CCS1 TQ0CCS0 TQ0OPT0 0 0 0 0 TQ0OVF 0 0 0 0/1 Overflow flag (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) These registers store the count value of the 16-bit counter when the valid edge input to the TIQ0m pin is detected. <R> Remarks 1. TMQ0 I/O control register 0 (TQ0IOC0) and TMQ0 I/O control register 2 (TQ0IOC2) are not used in the pulse width measurement mode. 2. m = 0 to 3 User's Manual U16541EJ5V1UD 429 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in pulse width measurement mode Figure 8-41. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input 0000H TQ0CCR0 register D0 D1 D2 INTTQ0CC0 signal <1> <R> <2> <1> Count operation start flow START Register initial setting TQ0CTL0 register (TQ0CKS0 to TQ0CKS2 bits), TQ0CTL1 register, TQ0IOC1 register, TQ0OPT0 register TQ0CE bit = 1 Initial setting of these registers is performed before setting the TQ0CE bit to 1. The TQ0CKS0 to TQ0CKS2 bits can be set at the same time when counting has been started (TQ0CE bit = 1). <2> Count operation stop flow TQ0CE bit = 0 The counter is initialized and counting is stopped by clearing the TQ0CE bit to 0. STOP 430 User's Manual U16541EJ5V1UD 0000H CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction after reading the TQ0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TQ0OPT0 register after reading the TQ0OVF bit when it is 1. <R> (3) Note If a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured to the TQ0CCRm register if the capture trigger is input immediately after the TQ0CTL0.TQ0CE bit is set to 1 (m = 0 to 3). FFFFH 16-bit counter 0000H Count clock Sampling clock TQ0CCR0 register 0000H FFFFH 0002H TQ0CE bit TIQ00 pin input Capture trigger input Capture trigger input 8.7 Selector Function For the selector function, see 7.7 Selector Function. User's Manual U16541EJ5V1UD 431 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Timer M (TMM) is a 16-bit interval timer. The V850ES/SG2 and V850ES/SG2-H incorporate TMM0. 9.1 Overview The TMM0 has the following functions. * Interval function * 8 clocks selectable * 16-bit counter x 1 (The 16-bit counter cannot be read during timer count operation.) * Compare register x 1 (The compare register cannot be written during timer count operation.) * Compare match interrupt x 1 Timer M supports only the clear & start mode. The free-running timer mode is not supported. 432 User's Manual U16541EJ5V1UD CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.2 Configuration TMM0 includes the following hardware. Table 9-1. Configuration of TMM0 Item Configuration Timer register 16-bit counter Register TMM0 compare register 0 (TM0CMP0) Control register TMM0 control register 0 (TM0CTL0) Figure 9-1. Block Diagram of TMM0 Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1TM0CKS0 TM0CMP0 Match Remark Selector fXX fXX/2 fXX/4 fXX/64 fXX/512 INTWT fR/8 fXT 16-bit counter Controller fXX: Main clock frequency fR: Internal oscillation clock frequency fXT: Subclock frequency INTTM0EQ0 Clear INTWT: Watch timer interrupt request signal (1) 16-bit counter This is a 16-bit counter that counts the internal clock. The 16-bit counter cannot be read or written. (2) TMM0 compare register 0 (TM0CMP0) The TM0CMP0 register is a 16-bit compare register. This register can be read or written in 16-bit units. Reset input clears this register to 0000H. The same value can always be written to the TM0CMP0 register by software. During the TMM0 operation (TM0CTL0.TM0CE bit = 1), rewriting the TM0CMP0 register is prohibited. After reset: 0000H 15 14 R/W 13 12 Address: FFFFF694H 11 10 9 8 7 6 5 4 3 2 1 0 TM0CMP0 User's Manual U16541EJ5V1UD 433 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.3 Register (1) TMM0 control register (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the TMM0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TM0CTL0 register by software. After reset: 00H TM0CTL0 R/W Address: FFFFF690H <7> 6 5 4 3 TM0CE 0 0 0 0 TM0CE 2 1 0 TM0CKS2 TM0CKS1 TM0CKS0 Internal clock operation enable/disable specification 0 TMM0 operation disabled (16-bit counter reset asynchronously). Operation clock application stopped. 1 TMM0 operation enabled. Operation clock application started. TMM0 operation started. The internal clock control and internal circuit reset for TMM0 are performed asynchronously with the TM0CE bit. When the TM0CE bit is cleared to 0, the internal clock of TMM0 is disabled (fixed to low level) and 16-bit counter is reset asynchronously. TM0CKS2 TM0CKS1 TM0CKS0 Count clock selection 0 0 0 0 0 1 fXX/2 0 1 0 fXX/4 0 1 1 fXX/64 1 0 0 fXX/512 1 0 1 INTWT 1 1 0 fR/8 1 1 1 fXT fXX Cautions 1. Set the TM0CKS2 to TM0CKS0 bits when TM0CE bit = 0. When changing the value of TM0CE from 0 to 1, it is not possible to set the value of the TM0CKS2 to TM0CKS0 bits simultaneously. 2. Be sure to clear bits 3 to 6 to "0". Remark fXX: Main clock frequency fR: Internal oscillation clock frequency fXT: Subclock frequency 434 User's Manual U16541EJ5V1UD CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.4 Operation Caution 9.4.1 Do not set the TM0CMP0 register to FFFFH. Interval timer mode In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the interval set by the TM0CM0P register if the TM0CTL0.TM0CE bit is set to 1. Figure 9-2. Configuration of Interval Timer Clear Count clock selection INTTM0EQ0 signal 16-bit counter Match signal TM0CE bit TM0CMP0 register Figure 9-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter D0 D0 D0 D0 Interval (D0 + 1) Interval (D0 + 1) 0000H TM0CE bit TM0CMP0 register D0 INTTM0EQ0 signal <R> Interval (D0 + 2) Interval (D0 + 1) When the TM0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. When the count value of the 16-bit counter matches the value of the TM0CMP0 register, the 16-bit counter is cleared to 0000H and a compare match interrupt request signal (INTTM0EQ0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TM0CMP0 register + 1) x Count clock cycle User's Manual U16541EJ5V1UD 435 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Figure 9-4. Register Setting for Interval Timer Mode Operation (a) TMM0 control register 0 (TM0CTL0) TM0CE TM0CTL0 0/1 TM0CKS2 TM0CKS1 TM0CKS0 0 0 0 0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMM0 compare register 0 (TM0CMP0) If the TM0CMP0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle 436 User's Manual U16541EJ5V1UD CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 9-5. Software Processing Flow in Interval Timer Mode FFFFH D0 16-bit counter D0 D0 0000H TM0CE bit TM0CMP0 register D0 INTTM0EQ0 signal <1> <2> <1> Count operation start flow START Register initial setting TM0CTL0 register (TM0CKS0 to TM0CKS2 bits) TM0CMP0 register TM0CE bit = 1 Initial setting of these registers is performed before the TM0CE bit is set to 1. The TM0CKS0 to TM0CKS2 bits cannot be set when counting starts (TM0CE bit = 1). <2> Count operation stop flow TM0CE bit = 0 The counter is initialized and counting is stopped by clearing the TM0CE bit to 0. STOP User's Manual U16541EJ5V1UD 437 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing Caution Do not set the TM0CMP0 register to FFFFH. (a) Operation if TM0CMP0 register is set to 0000H <R> If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter FFFFH 0000H 0000H 0000H 0000H TM0CE bit TM0CMP0 register 0000H INTTM0EQ0 signal Interval time Count clock cycle Interval time Count clock cycle x 2 Interval time Count clock cycle (b) Operation if TM0CMP0 register is set to N If the TM0CMP0 register is set to N, the 16-bit counter counts up to N. The counter is cleared to 0000H in synchronization with the next count-up timing and the INTTM0EQ0 signal is generated. FFFFH N 16-bit counter 0000H TM0CE bit TM0CMP0 register N INTTM0EQ0 signal Interval time (N + 2) x count clock cycle <R> Remark 438 Interval time (N + 1) x count clock cycle 0000H < N < FFFFH User's Manual U16541EJ5V1UD Interval time (N + 1) x count clock cycle CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.4.2 Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1, depending on the count clock selected. Selected Count Clock Maximum Time Before Counting Start fXX 2/fXX fXX/2 6/fXX fXX/4 24/fXX fXX/64 128/fXX fXX/512 1024/fXX INTWT Second rising edge of INTWT signal fR/8 16/fR fXT 2/fXT (2) Rewriting the TM0CMP0 and TM0CTL0 registers is prohibited while TMM0 is operating. If these registers are rewritten while the TM0CE bit is 1, the operation cannot be guaranteed. If they are rewritten by mistake, clear the TM0CTL0.TM0CE bit to 0, and re-set the registers. <R> (3) Do not set the TM0CMP0 register to FFFFH. User's Manual U16541EJ5V1UD 439 CHAPTER 10 WATCH TIMER FUNCTIONS 10.1 Functions The watch timer has the following functions. * Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock. * Interval timer: An interrupt request signal (INTWTI) is generated at set intervals. The watch timer and interval timer functions can be used at the same time. 440 User's Manual U16541EJ5V1UD CHAPTER 10 WATCH TIMER FUNCTIONS 10.2 Configuration The block diagram of the watch timer is shown below. Figure 10-1. Block Diagram of Watch Timer Internal bus PRSM0 register BGCE0 BGCS01 BGCS00 Clear PRSCM0 register 2 Match Selector fX/8 fX/4 fX/2 fX fBGCS 8-bit counter Clear Selector fBRG 11-bit prescaler 5-bit counter INTWT Clear fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 Selector fXT fW 1/2 Selector 3-bit prescaler Selector Clock control fX INTWTI 3 WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fX: Main clock oscillation frequency fBGCS: Watch timer source clock frequency fBRG: Watch timer count clock frequency fXT: Subclock frequency fW: Watch timer clock frequency INTWT: Watch timer interrupt request signal INTWTI: Interval timer interrupt request signal User's Manual U16541EJ5V1UD 441 CHAPTER 10 WATCH TIMER FUNCTIONS (1) Clock control This block controls supplying and stopping the operating clock (fX) when the watch timer operates on the main clock. (2) 3-bit prescaler This prescaler divides fX to generate fX/2, fX/4, or fX/8. (3) 8-bit counter This 8-bit counter counts the source clock (fBGCS). (4) 11-bit prescaler This prescaler divides fW to generate a clock of fW/24 to fW/211. (5) 5-bit counter This counter counts fW or fW/29, and generates a watch timer interrupt request signal at intervals of 24/fW, 25/fW, 212/fW, or 214/fW. (6) Selector The watch timer has the following five selectors. * Selector that selects one of fX, fX/2, fX/4, or fX/8 as the source clock of the watch timer * Selector that selects the main clock (fX) or subclock (fXT) as the clock of the watch timer * Selector that selects fW or fW/29 as the count clock frequency of the 5-bit counter 4 13 5 14 * Selector that selects 2 /fW, 2 /fW, 2 /fW, or 2 /fW as the INTWT signal generation time interval * Selector that selects 24/fW to 211/fW as the interval timer interrupt request signal (INTWTI) generation time interval (7) PRSCM register This is an 8-bit compare register that sets the interval time. (8) PRSM register This register controls clock supply to the watch timer. (9) WTM register This is an 8-bit register that controls the operation of the watch timer/interval timer, and sets the interrupt request signal generation interval. 442 User's Manual U16541EJ5V1UD CHAPTER 10 WATCH TIMER FUNCTIONS 10.3 Control Registers The following registers are provided for the watch timer. * Prescaler mode register 0 (PRSM0) * Prescaler compare register 0 (PRSCM0) * Watch timer operation mode register (WTM) (1) Prescaler mode register 0 (PRSM0) The PRSM0 register controls the generation of the watch timer count clock. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF8B0H < > PRSM0 0 0 0 BGCE0 BGCE0 0 0 BGCS01 BGCS00 Main clock operation enable 0 Disabled 1 Enabled Selection of watch timer source clock (fBGCS) BGCS01 BGCS00 5 MHz 4 MHz fX 200 ns 250 ns 0 0 0 1 fX/2 400 ns 500 ns 1 0 fX/4 800 ns 1 s 1 1 fX/8 1.6 s 2 s Cautions 1. Do not change the values of the BGCS00 and BGCS01 bits during watch timer operation. 2. Set the PRSM0 register before setting the BGCE0 bit to 1. 3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used so as to obtain an fBRG frequency of 32.768 kHz. User's Manual U16541EJ5V1UD 443 CHAPTER 10 WATCH TIMER FUNCTIONS (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H PRSCM0 R/W Address: FFFFF8B1H PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00 Cautions 1. Do not rewrite the PRSCM0 register during watch timer operation. 2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1. 3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used so as to obtain an fBRG frequency of 32.768 kHz. The calculation for fBRG is shown below. fBRG = fBGCS/2N Remark fBGCS: Watch timer source clock set by the PRSM0 register N: Set value of the PRSCM0 register = 1 to 256 However, N = 256 when the PRSCM0 register is set to 00H. 444 User's Manual U16541EJ5V1UD CHAPTER 10 WATCH TIMER FUNCTIONS (3) Watch timer operation mode register (WTM) The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. Set the PRSM0 register before setting the WTM register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. (1/2) After reset: 00H WTM WTM7 R/W WTM6 Address: FFFFF680H WTM5 WTM4 WTM3 WTM2 < > < > WTM1 WTM0 WTM7 WTM6 WTM5 WTM4 Selection of interval time of prescaler 0 0 0 0 24/fW (488 s: fW = fXT) 0 0 0 1 25/fW (977 s: fW = fXT) 0 0 1 0 26/fW (1.95 ms: fW = fXT) 0 0 1 1 27/fW (3.91 ms: fW = fXT) 0 1 0 0 28/fW (7.81 ms: fW = fXT) 0 1 0 1 29/fW (15.6 ms: fW = fXT) 0 1 1 0 210/fW (31.3 ms: fW = fXT) 0 1 1 1 211/fW (62.5 ms: fW = fXT) 1 0 0 0 24/fW (488 s: fW = fBRG) 1 0 0 1 25/fW (977 s: fW = fBRG) 1 0 1 0 26/fW (1.95 ms: fW = fBRG) 1 0 1 1 27/fW (3.91 ms: fW = fBRG) 1 1 0 0 28/fW (7.81 ms: fW = fBRG) 1 1 0 1 29/fW (15.6 ms: fW = fBRG) 1 1 1 0 210/fW (31.3 ms: fW = fBRG) 1 1 1 1 211/fW (62.5 ms: fW = fBRG) User's Manual U16541EJ5V1UD 445 CHAPTER 10 WATCH TIMER FUNCTIONS (2/2) WTM7 WTM3 Selection of set time of watch flag WTM2 14 0 0 0 2 /fW (0.5 s: fW = fXT) 0 0 1 213/fW (0.25 s: fW = fXT) 0 1 0 25/fW (977 s: fW = fXT) 0 1 1 24/fW (488 s: fW = fXT) 1 0 0 214/fW (0.5 s: fW = fBRG) 1 0 1 213/fW (0.25 s: fW = fBRG) 1 1 0 25/fW (977 s: fW = fBRG) 1 1 1 24/fW (488 s: fW = fBRG) WTM1 Control of 5-bit counter operation 0 Clears after operation stops 1 Starts WTM0 Watch timer operation enable 0 Stops operation (clears both prescaler and 5-bit counter) 1 Enables operation Caution Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0. Remarks 1. fW: Watch timer clock frequency 2. Values in parentheses apply to operation with fW = 32.768 kHz 446 User's Manual U16541EJ5V1UD CHAPTER 10 WATCH TIMER FUNCTIONS 10.4 Operation 10.4.1 Operation as watch timer The watch timer generates an interrupt request signal (INTWT) at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz) or main clock. The count operation starts when the WTM.WTM1 and WTM.WTM0 bits are set to 11. When the WTM0 bit is cleared to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops. The time of the watch timer can be adjusted by clearing the WTM1 bit to 0 and then the 5-bit counter when operating at the same time as the interval timer. At this time, an error of up to 15.6 ms may occur for the watch timer, but the interval timer is not affected. If the main clock is used as the count clock of the watch timer, set the count clock using the PRSM0.BGCS01 and BGCS00 bits, the 8-bit comparison value using the PRSCM0 register, and the count clock frequency (fBRG) of the watch timer to 32.768 kHz. When the PRSM0.BGCE0 bit is set (1), fBRG is supplied to the watch timer. fBRG can be calculated by the following expression. fBRG = fX/(2m+1 x N) To set fBRG to 32.768 kHz, perform the following calculation and set the BGCS01 and BGCS00 bits and the PRSCM0 register. <1> Set N = fX/65,536. Set m = 0. <2> When the value resulting from rounding up the first decimal place of N is even, set N before the roundup as N/2 and m as m + 1. <3> Repeat <2> until N is odd or m = 3. <4> Set the value resulting from rounding up the first decimal place of N to the PRSCM0 register and m to the BGCS01 and BGCS00 bits. Example: When fX = 4.00 MHz <1> N = 4,000,000/65,536 = 61.03..., m = 0 <2>, <3> Because N (round up the first decimal place) is odd, N = 61, m = 0. <4> Set value of PRSCM0 register: 3DH (61), set value of BGCS01 and BGCS00 bits: 00 At this time, the actual fBRG frequency is as follows. fBRG = fX/(2m+1 x N) = 4,000,000/(2 x 61) = 32.787 kHz Remark m: Division value (set value of BGCS01 and BGCS00 bits) = 0 to 3 N: Set value of PRSCM0 register = 1 to 256 However, N = 256 when PRSCM0 register is set to 00H. fX: Main clock oscillation frequency User's Manual U16541EJ5V1UD 447 CHAPTER 10 WATCH TIMER FUNCTIONS 10.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (INTWTI) at intervals specified by a preset count value. The interval time can be selected by the WTM.WTM4 to WTM7 bits. Table 10-1. Interval Time of Interval Timer WTM7 0 0 0 0 0 0 0 0 0 1 WTM5 0 0 1 1 0 WTM4 Interval Time 0 2 x 1/fw 488 s (operating at fW = fXT = 32.768 kHz) 1 2 x 1/fw 977 s (operating at fW = fXT = 32.768 kHz) 0 2 x 1/fw 1.95 ms (operating at fW = fXT = 32.768 kHz) 1 2 x 1/fw 3.91 ms (operating at fW = fXT = 32.768 kHz) 0 2 x 1/fw 7.81 ms (operating at fW = fXT = 32.768 kHz) 4 5 6 7 8 0 1 0 1 2 x 1/fw 15.6 ms (operating at fW = fXT = 32.768 kHz) 0 1 1 0 2 x 1/fw 31.3 ms (operating at fW = fXT = 32.768 kHz) 1 2 x 1/fw 62.5 ms (operating at fW = fXT = 32.768 kHz) 0 2 x 1/fw 488 s (operating at fW = fBRG = 32.768 kHz) 1 2 x 1/fw 977 s (operating at fW = fBRG = 32.768 kHz) 0 2 x 1/fw 1.95 ms (operating at fW = fBRG = 32.768 kHz) 1 2 x 1/fw 3.91 ms (operating at fW = fBRG = 32.768 kHz) 0 2 x 1/fw 7.81 ms (operating at fW = fBRG = 32.768 kHz) 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 9 10 11 4 5 6 7 8 1 1 0 1 2 x 1/fw 15.6 ms (operating at fW = fBRG = 32.768 kHz) 1 1 1 0 2 x 1/fw 31.3 ms (operating at fW = fBRG = 32.768 kHz) 1 2 x 1/fw 62.5 ms (operating at fW = fBRG = 32.768 kHz) 1 Remark 448 WTM6 1 1 9 10 11 fW: Watch timer clock frequency User's Manual U16541EJ5V1UD CHAPTER 10 WATCH TIMER FUNCTIONS Figure 10-2. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Overflow Start Overflow Count clock fW or fW/29 Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) Interval time (T) nT nT Remarks 1. When 0.5 seconds of the watch timer interrupt time is set. 2. fW: Watch timer clock frequency Values in parentheses apply to operation with fW = 32.768 kHz. n: Number of interval timer operations 10.4.3 Cautions Some time is required before the first watch timer interrupt request signal (INTWT) is generated after operation is enabled (WTM.WTM1 and WTM.WTM0 bits = 1). Figure 10-3. Example of Generation of Watch Timer Interrupt Request Signal (INTWT) (When Interrupt Cycle = 0.5 s) It takes 0.515625 seconds (max.) for the first INTWT signal to be generated (29 x 1/32768 = 0.015625 seconds longer (max.)). The INTWT signal is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s 0.5 s INTWT User's Manual U16541EJ5V1UD 449 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.1 Functions Watchdog timer 2 has the following functions. * Default-start watchdog timerNote 1 Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of INTWDT2 signal)Note 2 * Input selectable from main clock, internal oscillation clock, and subclock as the source clock Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release. When watchdog timer 2 is not used, either stop its operation before reset is executed via this function, or clear watchdog timer 2 once and stop it within the next interval time. Also, write to the WDTM2 register for verification purposes only once, even if the default settings (reset mode, interval time: fR/219) do not need to be changed. 2. For the non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT2), see 22.2.2 (2) INTWDT2 signal. 450 User's Manual U16541EJ5V1UD CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 11-1. Block Diagram of Watchdog Timer 2 fXX/2 9 fXT fR/23 Clock input controller 16-bit counter 2 fXX/218 to fXX/225, fXT/29 to fXT/216, fR/212 to fR/219 Selector 3 Clear 0 Watchdog timer enable register (WDTE) Output controller INTWDT2 WDT2RES (internal reset signal) 3 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Watchdog timer mode register 2 (WDTM2) Internal bus Remark fXX: Main clock frequency fXT: Subclock frequency fR: Internal oscillation clock frequency INTWDT2: Non-maskable interrupt request signal from watchdog timer 2 WDTRES2: Watchdog timer 2 reset signal Watchdog timer 2 consists of the following hardware. Table 11-1. Configuration of Watchdog Timer 2 Item Control registers Configuration Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) User's Manual U16541EJ5V1UD 451 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release. Reset sets this register to 67H. Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 67H WDTM2 R/W Address: FFFFF6D0H 0 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 WDM21 WDM20 0 0 Stops operation 0 1 Non-maskable interrupt request mode (generation of INTWDT2 signal) 1 - Reset mode (generation of WDT2RES signal) Selection of operation mode of watchdog timer 2 Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 11-2 Watchdog Timer 2 Clock Selection. 2. Although watchdog timer 2 can be stopped just by stopping operation of the internal oscillator, clear the WDTM2 register to 00H to securely stop the timer (to avoid selection of the main clock or subclock due to an erroneous write operation). 3. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly <R> generated and the counter is reset. 4. To intentionally generate an overflow signal, write data to the WDTM2 register only twice, <R> or write a value other than "ACH" to the WDTE register only once. However, when watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is written to the WDTM2 register only twice, or a value other than "ACH" is written to the WDTE register only once. 5. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop the internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP bit cannot be set to 1, set the WDCS23 bit to 1 (2n/fXX is selected and the clock can be stopped in the IDLE1, IDLW2, sub-IDLE, and subclock operation modes). 452 User's Manual U16541EJ5V1UD CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 <R> Table 11-2. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected 100 kHz (MIN.) 200 kHz (TYP.) 400 kHz (MAX.) Clock 0 0 0 0 0 12 41.0 ms 13 14 2 /fR 20.5 ms 10.2 ms 81.9 ms 41.0 ms 20.5 ms 163.8 ms 81.9 ms 41.0 ms 15 327.7 ms 163.8 ms 81.9 ms 16 655.4 ms 327.7 ms 163.8 ms 17 1310.7 ms 655.4 ms 327.7 ms 18 2621.4 ms 1310.7 ms 655.4 ms 19 5242.9 ms 2621.47 ms 1310.7 ms 0 0 0 0 1 2 /fR 0 0 0 1 0 2 /fR 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 2 /fR 2 /fR 2 /fR 2 /fR 2 /fR fXX = 32 MHz 0 1 0 0 0 13.1 ms 16.4 ms 26.2 ms 16.4 ms 26.2 ms 32.8 ms 52.4 ms 20 32.8 ms 52.4 ms 65.5 ms 104.9 ms 21 65.5 ms 104.9 ms 131.1 ms 209.7 ms 22 131.1 ms 209.7 ms 262.1 ms 419.4 ms 23 262.1 ms 419.4 ms 524.3 ms 838.9 ms 24 524.3 ms 838.9 ms 1048.6 ms 1677.7 ms 25 1048.6 ms 1677.7 ms 2097.2 ms 3355.4 ms 0 0 1 2 /fXX 1 0 1 0 2 /fXX 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 fXX = 10 MHz 8.2 ms 1 0 fXX = 16 MHz 19 2 /fXX 0 1 fXX = 20 MHz 18 0 0 Note 2 /fXX 2 /fXX 2 /fXX 2 /fXX 0 1 2 /fXX 1 x 1 x 0 0 1 2 /fXT 1 x 0 1 0 2 /fXT 1 x 1 x 1 x 1 x 1 x fXT = 32.768 kHz 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 9 15.625 ms 10 31.25 ms 11 62.5 ms 12 125 ms 13 250 ms 14 500 ms 15 1000 ms 16 2000 ms 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT Note V850ES/SG2-H only User's Manual U16541EJ5V1UD 453 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing "ACH" to the WDTE register. The WDTE register can be read or written in 8-bit units. Reset sets this register to 9AH. After reset: 9AH R/W Address: FFFFF6D1H WDTE Cautions 1. When a value other than "ACH" is written to the WDTE register, an overflow signal is forcibly output. 2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an overflow signal is forcibly output. 3. To intentionally generate an overflow signal, write to the WDTM2 register only twice or <R> write a value other than "ACH" to the WDTE register once. However, when the watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is written to the WDTM2 register only twice, or a value other than "ACH" is written to the WDTE register only once. 4. The read value of the WDTE register is "9AH" (which differs from written value "ACH"). 11.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this, the operation of watchdog timer 2 cannot be stopped. The WDCS24 to WDCS20 bits of the WDTM2 register are used to select the watchdog timer 2 loop detection time interval. Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After the count operation has started, write ACH to WDTE within the loop detection time interval. If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a nonmaskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDM21 and WDTM2.WDM20 bits. When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization after a reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock. To not use watchdog timer 2, write 00H to the WDTM2 register. For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 22.2.2 (2) INTWDT2 signal. 454 User's Manual U16541EJ5V1UD CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.1 Function The real-time output function transfers preset data to the RTBL0 and RTBH0 registers, and then transfers this data by hardware to an external device via the output latches, upon occurrence of a timer interrupt. The pins through which the data is output to an external device constitute a port called the real-time output function (RTO). Because RTO can output signals without jitter, it is suitable for controlling a stepper motor. <R> In the V850ES/SG2 and V850ES/SG2-H, one 6-bit real-time output port channel is provided. The real-time output port can be set to the port mode or real-time output port mode in 1-bit units. User's Manual U16541EJ5V1UD 455 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.2 Configuration The block diagram of RTO is shown below. Internal bus Figure 12-1. Block Diagram of RTO Real-time output buffer register 0H (RTBH0) Real-time output latch 0H 2 Real-time output buffer register 0L (RTBL0) Real-time output latch 0L 4 RTP04, RTP05 RTP00 to RTP03 INTTP0CC0 Transfer trigger (H) Selector INTTP5CC0 Transfer trigger (L) INTTP4CC0 2 RTPOE0 RTPEG0 BYTE0 EXTR0 Real-time output port control register 0 (RTPC0) 4 RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00 Real-time output port mode register 0 (RTPM0) RTO consists of the following hardware. Table 12-1. Configuration of RTO Item Configuration Registers Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) Control registers Real-time output port mode register 0 (RTPM0) Real-time output port control register 0 (RTPC0) 456 User's Manual U16541EJ5V1UD CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) The RTBL0 and RTBH0 registers are 4-bit registers that hold preset output data. These registers are mapped to independent addresses in the peripheral I/O register area. These registers can be read or written in 8-bit or 1-bit units. Reset input clears these registers to 00H. If an operation mode of 4 bits x 1 channel or 2 bits x 1 channel is specified (RTPC0.BYTE0 bit = 0), data can be individually set to the RTBL0 and RTBH0 registers. The data of both these registers can be read at once by specifying the address of either of these registers. If an operation mode of 6 bits x 1 channel is specified (BYTE0 bit = 1), 8-bit data can be set to both the RTBL0 and RTBH0 registers by writing the data to either of these registers. Moreover, the data of both these registers can be read at once by specifying the address of either of these registers. Table 12-2 shows the operation when the RTBL0 and RTBH0 registers are manipulated. After reset: 00H R/W Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H RTBL0 RTBL03 0 RTBH0 0 RTBL02 RTBL01 RTBL00 RTBH05 RTBH04 Cautions 1. When writing to bits 6 and 7 of the RTBH0 register, always write 0. 2. Accessing the RTBL0 and RTBH0 registers is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock Table 12-2. Operation During Manipulation of RTBL0 and RTBH0 Registers Operation Mode Register to Be Manipulated Read Higher 4 Bits Write Lower 4 Bits Higher 4 Bits Note Lower 4 Bits 4 bits x 1 channel, RTBL0 RTBH0 RTBL0 Invalid RTBL0 2 bits x 1 channel RTBH0 RTBH0 RTBL0 RTBH0 Invalid RTBL0 RTBH0 RTBL0 RTBH0 RTBL0 RTBH0 RTBH0 RTBL0 RTBH0 RTBL0 6 bits x 1 channel Note After setting the real-time output port, set output data to the RTBL0 and RTBH0 registers by the time a real-time output trigger is generated. User's Manual U16541EJ5V1UD 457 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.3 Registers RTO is controlled using the following two registers. * Real-time output port mode register 0 (RTPM0) * Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) The RTPM0 register selects the real-time output port mode or port mode in 1-bit units. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H RTPM0 0 RTPM0m R/W 0 Address: FFFFF6E4H RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00 Control of real-time output port (m = 0 to 5) 0 Real-time output disabled 1 Real-time output enabled Cautions 1. By enabling the real-time output operation (RTPC0.RTPOE0 bit = 1), the bits enabled to real-time output among the RTP00 to RTP05 signals perform real-time output, and the bits set to port mode output 0. 2. If real-time output is disabled (RTPOE0 bit = 0), the real-time output pins (RTP00 to RTP05) all output 0, regardless of the RTPM0 register setting. 3. In order to use this register as the real-time output pins (RTP00 to RTP05), set these pins as real-time output port pins using the PMC and PFC registers. 458 User's Manual U16541EJ5V1UD CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 12-3. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF6E5H < > RTPC0 RTPOE0 RTPEG0 BYTE0 RTPOE0 EXTR0 0 0 0 0 Control of real-time output operation 0 Disables operation 1 Enables operation Note 1 Valid edge of INTTP0CC0 signal RTPEG0 Note 2 0 Falling edge 1 Rising edge BYTE0 Specification of channel configuration for real-time output 0 4 bits x 2 channels, 2 bits x 2 channels 1 6 bits x 2 channels Notes 1. When the real-time output operation is disabled (RTPOE0 bit = 0), all the bits of the real-time output signals (RTP00 to RTP05) output "0". 2. The INTTP0CC0 signal is output for 1 clock of the count clock selected by TMP0. Caution Set the RTPEG0, BYTE0, and EXTR0 bits only when RTPOE0 bit = 0. Table 12-3. Operation Modes and Output Triggers of Real-Time Output Port BYTE0 EXTR0 0 0 4 bits x 1 channel, INTTP5CC0 INTTP4CC0 1 2 bits x 1 channel INTTP4CC0 INTTP0CC0 0 6 bits x 1 channel INTTP4CC0 1 1 Operation Mode RTBH0 (RTP04, RTP05) RTBL0 (RTP00 to RTP03) INTTP0CC0 User's Manual U16541EJ5V1UD 459 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits). Of the transferred data, only the data of the bits for which real-time output is enabled by the RTPM0 register is output from the RTP00 to RTP05 bits. The bits for which real-time output is disabled by the RTPM0 register output 0. If the real-time output operation is disabled by clearing the RTPOE0 bit to 0, the RTP00 to RTP05 signals output 0 regardless of the setting of the RTPM0 register. Figure 12-2. Example of Operation Timing of RTO0 (When EXTR0 Bit = 0, BYTE0 Bit = 0) INTTP5CC0 (internal) INTTP4CC0 (internal) CPU operation A B RTBH0 D01 RTBL0 RT output latch 0 (H) RT output latch 0 (L) A B D02 A B D03 D11 D13 D02 D11 D14 D03 D12 A: Software processing by INTTP5CC0 interrupt request (RTBH0 write) B: Software processing by INTTP4CC0 interrupt request (RTBL0 write) Remark 460 For the operation during standby, see CHAPTER 24 STANDBY FUNCTION. User's Manual U16541EJ5V1UD B D04 D12 D01 A D04 D13 D14 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. * Set the alternate-function pins of port 5 Set the PFC5.PFC5m bit and PFCE5.PFCE5m bit to 1, and then set the PMC5.PMC5m bit to 1 (m = 0 to 5). * Specify the real-time output port mode or port mode in 1-bit units. Set the RTPM0 register. * Channel configuration: Select the trigger and valid edge. Set the RTPC0.EXTR0, RTPC0.BYTE0, and RTPC0.RTPEG0 bits. * Set the initial values to the RTBH0 and RTBL0 registersNote 1. (3) Enable real-time output. Set the RTPOE0 bit = 1. (4) Set the next output value to the RTBH0 and RTBL0 registers by the time the selected transfer trigger is generatedNote 2. (5) Set the next real-time output value to the RTBH0 and RTBL0 registers via interrupt servicing corresponding to the selected trigger. Notes 1. If the RTBH0 and RTBL0 registers are written when the RTPOE0 bit = 0, that value is transferred to real-time output latches 0H and 0L, respectively. 2. Even if the RTBH0 and RTBL0 registers are written when the RTPOE0 bit = 1, data is not transferred to real-time output latches 0H and 0L. 12.6 Cautions (1) Prevent the following conflicts by software. * Conflict between real-time output disable/enable switching (RTPOE0 bit) and selected real-time output trigger. * Conflict between writing to the RTBH0 and RTBL0 registers in the real-time output enabled status and the selected real-time output trigger. (2) Before performing initialization, disable real-time output (RTPOE0 bit = 0). (3) Once real-time output has been disabled (RTPOE0 bit = 0), be sure to initialize the RTBH0 and RTBL0 registers before enabling real-time output again (RTPOE0 bit = 0 1). User's Manual U16541EJ5V1UD 461 CHAPTER 13 A/D CONVERTER 13.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 analog input signal channels (ANI0 to ANI11). The A/D converter has the following features. { 10-bit resolution { 12 channels { Successive approximation method { Operating voltage: AVREF0 = 3.0 to 3.6 V { Analog input voltage: 0 V to AVREF0 { The following functions are provided as operation modes. * Continuous select mode * Continuous scan mode * One-shot select mode * One-shot scan mode { The following functions are provided as trigger modes. * Software trigger mode * External trigger mode (external, 1) * Timer trigger mode { Power-fail monitor function (conversion result compare function) 13.2 Functions (1) 10-bit resolution A/D conversion An analog input channel is selected from ANI0 to ANI11, and an A/D conversion operation is repeated at a resolution of 10 bits. Each time A/D conversion has been completed, an interrupt request signal (INTAD) is generated. (2) Power-fail detection function This function is used to detect a drop in the battery voltage. The result of A/D conversion (the value of the ADA0CRnH register) is compared with the value of the ADA0PFT register, and the INTAD signal is generated only when a specified comparison condition is satisfied (n = 0 to 11). 462 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER 13.3 Configuration The block diagram of the A/D converter is shown below. Figure 13-1. Block Diagram of A/D Converter AVREF0 ANI0 ANI1 ANI2 : : Series resistor string ADA0CE bit Selector Tap selector Sample & hold circuit ANI9 ANI10 ANI11 AVSS ADA0CE bit Voltage comparator SAR ADA0TMD1 bit ADA0TMD0 bit INTTP2CC0 INTTP2CC1 ADTRG Edge detection Selector INTAD Controller ADA0CR0 ADA0CR1 ADA0CR2 : : ADA0CR10 ADA0ETS0 bit ADA0ETS1 bit ADA0M0 Controller ADA0PFE bit ADA0PFC bit ADA0M1 ADA0M2 ADA0S ADA0CR11 Voltage comparator ADA0PFT ADA0PFM Internal bus The A/D converter includes the following hardware. Table 13-1. Configuration of A/D Converter Item Configuration Analog inputs 12 channels (ANI0 to ANI11 pins) Registers Successive approximation register (SAR) A/D conversion result registers 0 to 11 (ADA0CR0 to ADA0CR11) A/D conversion result registers 0H to 11H (ADCR0H to ADCR11H): Only higher 8 bits can be read Control registers A/D converter mode registers 0 to 2 (ADA0M0 to ADA0M2) A/D converter channel specification register 0 (ADA0S) Power fail compare mode register (ADA0PFM) Power fail compare threshold value register (ADA0PFT) User's Manual U16541EJ5V1UD 463 CHAPTER 13 A/D CONVERTER (1) Successive approximation register (SAR) The SAR register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the comparison result starting from the most significant bit (MSB). When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is complete), the contents of the SAR register are transferred to the ADA0CRn register. Remark n = 0 to 11 (2) A/D conversion result register n (ADA0CRn), A/D conversion result register nH (ADA0CRnH) The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0ARn consist of 12 registers and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to analog input. (The lower 6 bits are fixed to 0.) (3) A/D converter mode register 0 (ADA0M0) This register specifies the operation mode and controls the conversion operation by the A/D converter. (4) A/D converter mode register 1 (ADA0M1) This register sets the conversion time of the analog input signal to be converted. (5) A/D converter mode register 2 (ADA0M2) This register sets the hardware trigger mode. (6) A/D converter channel specification register (ADA0S) This register sets the input port that inputs the analog voltage to be converted. (7) Power-fail compare mode register (ADA0PFM) This register sets the power-fail monitor mode. (8) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets a threshold value that is compared with the value of A/D conversion result register nH (ADA0CRnH). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion result register (ADA0CRnH). (9) Controller The controller compares the result of the A/D conversion (the value of the ADA0CRnH register) with the value of the ADA0PFT register when A/D conversion is completed or when the power-fail detection function is used, and generates the INTAD signal only when a specified comparison condition is satisfied. (10) Sample & hold circuit The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during A/D conversion. (11) Voltage comparator The voltage comparator compares a voltage value that has been sampled and held with the voltage value of the series resistor string. 464 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER (12) Series resistor string This series resistor string is connected between AVREF0 and AVSS and generates a voltage for comparison with the analog input signal. (13) ANI0 to ANI11 pins These are analog input pins for the 12 A/D converter channels and are used to input analog signals to be converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register can be used as input port pins. Caution Make sure that the voltages input to the ANI0 to ANI11 pins do not exceed the rated values. In particular if a voltage of AVREF0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. (14) AVREF0 pin This is the pin used to input the reference voltage of the A/D converter. Always make the potential at this pin the same as that at the VDD pin even when the A/D converter is not used. The signals input to the ANI0 to ANI11 pins are converted to digital signals based on the voltage applied between the AVREF0 and AVSS pins. (15) AVSS pin This is the ground pin of the A/D converter. Always make the potential at this pin the same as that at the VSS pin even when the A/D converter is not used. User's Manual U16541EJ5V1UD 465 CHAPTER 13 A/D CONVERTER 13.4 Registers The A/D converter is controlled by the following registers. * A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) * A/D converter channel specification register 0 (ADA0S) * Power-fail compare mode register (ADA0PFM) The following registers are also used. * A/D conversion result register n (ADA0CRn) * A/D conversion result register nH (ADA0CRnH) * Power-fail compare threshold value register (ADA0PFT) (1) A/D converter mode register 0 (ADA0M0) The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations. This register can be read or written in 8-bit or 1-bit units. However, ADA0EF bit is read-only. Reset sets this register to 00H. Caution Accessing the ADA0M0 register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock (1/2) After reset: 00H R/W Address: FFFFF200H < > < > ADA0M0 ADA0CE 0 ADA0MD1 ADA0MD0 ADA0ETS1 ADA0ETS0 ADA0TMD A/D conversion control ADA0CE 0 Stops A/D conversion 1 Enables A/D conversion ADA0MD1 ADA0MD0 466 Specification of A/D converter operation mode 0 0 Continuous select mode 0 1 Continuous scan mode 1 0 One-shot select mode 1 1 One-shot scan mode User's Manual U16541EJ5V1UD ADA0EF CHAPTER 13 A/D CONVERTER (2/2) ADA0ETS1 ADA0ETS0 Specification of external trigger (ADTRG pin) input valid edge 0 0 No edge detection 0 1 Falling edge detection 1 0 Rising edge detection 1 1 Detection of both rising and falling edges Trigger mode specification ADA0TMD 0 Software trigger mode 1 External trigger mode/timer trigger mode A/D converter status display ADA0EF 0 A/D conversion stopped 1 A/D conversion in progress Cautions 1. If bit 0 is written, this is ignored. 2. Changing the ADA0M1.ADA0FR2 to ADA0M1.ADA0FR0 bits is prohibited while A/D conversion is enabled (ADA0CE bit = 1). <R> 3. In the following modes, write data to the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers while A/D conversion is stopped (ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode of high-speed conversion mode If data is written to the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers in any other modes during A/D conversion (ADA0EF bit = 1), the operation is performed as follows, depending on the mode. * In software trigger mode A/D conversion is stopped and started again from the beginning. * In hardware trigger mode A/D conversion is stopped, and the trigger standby state is set. <R> 4. To select the external trigger mode/timer trigger mode (ADA0TMD bit = 1), set the highspeed conversion mode (ADA0M1.ADA0HS1 bit = 1). Do not input a trigger during stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0CE bit = 1). 5. When not using the A/D converter, stop the operation by setting the ADA0CE bit to 0 to reduce the power consumption. User's Manual U16541EJ5V1UD 467 CHAPTER 13 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this bit to 00H. After reset: 00H <R> ADA0M1 ADA0HS1 R/W Address: FFFFF201H 0 0 0 ADA0FR3Note ADA0FR2 ADA0FR1 ADA0FR0 ADA0HS1 Specification of normal conversion mode/high-speed mode (A/D conversion time) <R> 0 Normal conversion mode 1 High-speed conversion mode Note V850ES/SG2-H only Cautions 1. Changing the ADA0M1 register is prohibited while A/D conversion is enabled (ADA0M0.ADA0CE bit = 1). <R> 2. To select the external trigger mode/timer trigger mode (ADA0M0.ADA0TMD bit = 1), set the high-speed conversion mode (ADA0M1.ADA0HS1 bit = 1). Do not input a trigger during stabilization time that is inserted only once after the A/D conversion operation is enabled (ADA0CE bit = 1). <R> 3. In the V850ES/SG2, be sure to set bits 6 to 3 to "0", and in the V850ES/SG2-H, be sure to set bits 6 to 4 to "0". Remark 468 For A/D conversion time setting examples, see Tables 13-2 and 13-3. User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER <R> Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) ADA0FR3 to ADA0FR0 BitsNote 1 A/D Conversion Time Stabilization Time + Conversion Time + Note 2 fXX = 32 MHz fXX = 20 MHz fXX = 16 MHz fXX = 4 MHz Trigger Response Time Wait Time 0000 66/fXX (13/fXX + 26/fXX + 27/fXX) Setting prohibited Setting prohibited Setting prohibited 16.50 s 3/fXX 0001 131/fXX (26/fXX + 52/fXX + 53/fXX) Setting prohibited 6.55 s 8.19 s Setting prohibited 3/fXX 0010 196/fXX (39/fXX + 78/fXX + 79/fXX) Setting prohibited 9.80 s 12.25 s Setting prohibited 3/fXX 0011 259/fXX (50/fXX + 104/fXX + 105/fXX) 8.09 s 12.95 s 16.19 s Setting prohibited 3/fXX 0100 311/fXX (50/fXX + 130/fXX + 131/fXX) 9.72 s 15.55 s 19.44 s Setting prohibited 3/fXX 0101 363/fXX (50/fXX + 156/fXX + 157/fXX) 11.34 s 18.15 s 22.69 s Setting prohibited 3/fXX 0110 415/fXX (50/fXX + 182/fXX + 183/fXX) 12.97 s 20.75 s Setting prohibited Setting prohibited 3/fXX 0111 467/fXX (50/fXX + 208/fXX + 209/fXX) 14.59 s 23.35 s Setting prohibited Setting prohibited 3/fXX 1000 519/fXX (50/fXX + 234/fXX + 235/fXX) 16.22 s Setting prohibited Setting prohibited Setting prohibited 3/fXX 1001 571/fXX (50/fXX + 260/fXX + 261/fXX) 17.84 s Setting prohibited Setting prohibited Setting prohibited 3/fXX 1010 623/fXX (50/fXX + 286/fXX + 287/fXX) 19.47 s Setting prohibited Setting prohibited Setting prohibited 3/fXX 1011 675/fXX (50/fXX + 312/fXX + 313/fXX) 21.09 s Setting prohibited Setting prohibited Setting prohibited 3/fXX Other than above Setting prohibited Notes 1. V850ES/SG2: ADA0FR2 to ADA0FR0 bits V850ES/SG2-H: ADA0FR3 to ADA0FR0 bits 2. V850ES/SG2-H only Remark Stabilization time: A/D converter setup time (1 s or longer) Conversion time: Actual A/D conversion time (2.6 to 10.4 s) Wait time: Wait time inserted before the next conversion Trigger response time: If a software trigger, external trigger, or timer trigger is generated after the stabilization time, it is inserted before the conversion time. In the normal conversion mode, the conversion is started after the stabilization time elapsed from the ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.6 to 10.4 s). Operation is stopped after the conversion ends and the A/D conversion end interrupt request signal (INTAD) is generated after the wait time is elapsed. Because the conversion operation is stopped during the wait time, operation current can be reduced. Caution Set as 2.6 s conversion time 10.4 s. User's Manual U16541EJ5V1UD 469 CHAPTER 13 A/D CONVERTER <R> Table 13-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) ADA0FR3 to ADA0FR0 A/D Conversion Time Conversion Time Note 1 Bits fXX = 32 MHz Note 2 fXX = 20 MHz fXX = 16 MHz fXX = 4 MHz Trigger Response Time (+ Stabilization Time) 0000 26/fXX (+ 13/fXX) Setting prohibited Setting prohibited Setting prohibited 6.5 s (+ 3.25 s) 3/fXX 0001 52/fXX (+ 26/fXX) Setting prohibited 2.6 s (+ 1.3 s) Setting prohibited 3/fXX Setting prohibited 3/fXX Setting prohibited 3/fXX Setting prohibited 3/fXX 0010 0011 0100 0101 0110 0111 1000 78/fXX (+ 39/fXX) 104/fXX (+ 50/fXX) 130/fXX (+ 50/fXX) 156/fXX (+ 50/fXX) 182/fXX (+ 50/fXX) 208/fXX (+ 50/fXX) 234/fXX (+ 50/fXX) Setting prohibited 3.9 s (+ 1.95 s) 3.25 s (+ 1.625 s) 4.875 s (+ 2.4375 s) 3.25 s 5.2 s 6.5 s (+ 1.5625 s) (+ 2.5 s) (+ 3.125 s) 4.0625 s 6.5 s 8.125 s (+ 1.5625 s) (+ 2.5 s) (+ 3.125 s) 4.875 s 7.8 s 9.75 s Setting prohibited 3/fXX (+ 1.5625 s) (+ 2.5 s) (+ 3.125 s) 5.6875 s 9.1 s Setting prohibited Setting prohibited 3/fXX (+ 1.5625 s) (+ 2.5 s) 6.5 s 10.4 s Setting prohibited Setting prohibited 3/fXX (+ 1.5625 s) (+ 2.5 s) 7.3125 s Setting prohibited Setting prohibited Setting prohibited 3/fXX Setting prohibited Setting prohibited Setting prohibited 3/fXX Setting prohibited Setting prohibited Setting prohibited 3/fXX Setting prohibited Setting prohibited Setting prohibited 3/fXX (+ 1.5625 s) 1001 260/fXX (+ 50/fXX) 8.125 s (+ 1.5625 s) 1010 286/fXX (+ 50/fXX) 8.9375 s (+ 1.5625 s) 1011 312/fXX (+ 50/fXX) 9.75 s (+ 1.5625 s) Other than Setting prohibited above Notes 1. V850ES/SG2: ADA0FR2 to ADA0FR0 bits V850ES/SG2-H: ADA0FR3 to ADA0FR0 bits 2. V850ES/SG2-H only Remark Conversion time: Actual A/D conversion time (2.6 to 10.4 s) Stabilization time: A/D converter setup time (1 s or longer) Trigger response time: If a software trigger, external trigger, or timer trigger is generated after the stabilization time, it is inserted before the conversion time. In the high-speed conversion mode, the conversion is started after the stabilization time elapsed from the ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.6 to 10.4 s). The A/D conversion end interrupt request signal (INTAD) is generated immediately after the conversion ends. In continuous conversion mode, the stabilization time is inserted only before the first conversion, and not inserted after the second conversion (the A/D converter remains running). Caution 470 Set as 2.6 s conversion time 10.4 s. User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H ADA0M2 R/W Address: FFFFF203H 7 6 5 4 3 2 0 0 0 0 0 0 ADA0TMD1 ADA0TMD0 <R> 1 0 ADA0TMD1 ADA0TMD0 Specification of hardware trigger mode 0 0 External trigger mode (when ADTRG pin valid edge detected) 0 1 Timer trigger mode 0 (when INTTP2CC0 interrupt request generated) 1 0 Timer trigger mode 1 (when INTTP2CC1 interrupt request generated) 1 1 Setting prohibited Cautions 1. In the following modes, write data to the ADA0M2 register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode of the high-speed conversion mode 2. Be sure to clear bits 7 to 2 to "0". User's Manual U16541EJ5V1UD 471 CHAPTER 13 A/D CONVERTER (4) Analog input channel specification register (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H ADA0S 0 R/W 0 Address: FFFFF202H 0 0 ADA0S3 ADA0S2 ADA0S1 ADA0S0 ADA0S3 ADA0S2 ADA0S1 ADA0S0 Select mode Scan mode 0 0 0 0 ANI0 ANI0 0 0 0 1 ANI1 ANI0, ANI1 0 0 1 0 ANI2 ANI0 to ANI2 0 0 1 1 ANI3 ANI0 to ANI3 0 1 0 0 ANI4 ANI0 to ANI4 0 1 0 1 ANI5 ANI0 to ANI5 0 1 1 0 ANI6 ANI0 to ANI6 0 1 1 1 ANI7 ANI0 to ANI7 1 0 0 0 ANI8 ANI0 to ANI8 1 0 0 1 ANI9 ANI0 to ANI9 1 0 1 0 ANI10 ANI0 to ANI10 1 0 1 1 ANI11 ANI0 to ANI11 1 1 0 0 Setting prohibited Setting prohibited 1 1 0 1 Setting prohibited Setting prohibited 1 1 1 0 Setting prohibited Setting prohibited 1 1 1 1 Setting prohibited Setting prohibited Cautions 1. In the following modes, write data to the ADA0S register while A/D conversion is <R> stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode of the high-speed conversion mode 2. Be sure to clear bits 7 to 4 to "0". 472 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access. The 10 bits of the conversion result are read from the higher 10 bits of the ADA0CRn register, and 0 is read from the lower 6 bits. The higher 8 bits of the conversion result are read from the ADA0CRnH register. Caution Accessing the ADA0CRn and ADA0CRnH registers is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: Undefined R Address: ADA0CR0 FFFFF210H, ADA0CR1 FFFFF212H, ADA0CR2 FFFFF214H, ADA0CR3 FFFFF216H, ADA0CR4 FFFFF218H, ADA0CR5 FFFFF21AH, ADA0CR6 FFFFF21CH, ADA0CR7 FFFFF21EH, ADA0CR8 FFFFF220H, ADA0CR9 FFFFF222H, ADA0CR10 FFFFF224H, ADA0CR11 FFFFF226H ADA0CRn (n = 0 to 11) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 After reset: Undefined R 0 0 0 0 0 0 Address: ADA0CR0H FFFFF211H, ADA0CR1H FFFFF213H, ADA0CR2H FFFFF215H, ADA0CR3H FFFFF217H, ADA0CR4H FFFFF219H, ADA0CR5H FFFFF21BH, ADA0CR6H FFFFF21DH, ADA0CR7H FFFFF21FH, ADA0CR8H FFFFF221H, ADA0CR9H FFFFF223H, ADA0CR10H FFFFF225H, ADA0CR11H FFFFF227H ADA0CRnH 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 (n = 0 to 11) Caution A write operation to the ADA0M0 and ADA0S registers may cause the contents of the ADA0CRn register to become undefined. After the conversion, read the conversion result before writing to the ADA0M0 and ADA0S registers. Correct conversion results may not be read if a sequence other than the above is used. User's Manual U16541EJ5V1UD 473 CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion result (ADA0CRn register) is as follows. ADA0CR = INT ( ADA0CR Note VIN AVREF0 x 1,024 + 0.5) = SAR x 64 Or, (SAR - 0.5) x AVREF0 1,024 VIN < (SAR + 0.5) x AVREF0 1,024 INT( ): Function that returns the integer of the value in ( ) VIN: Analog input voltage AVREF0: AVREF0 pin voltage ADA0CR: Value of ADA0CRn register Note The lower 6 bits of the ADA0CRn register are fixed to 0. The following shows the relationship between the analog input voltage and the A/D conversion results. Figure 13-2. Relationship Between Analog Input Voltage and A/D Conversion Results ADA0CRn SAR A/D conversion results 1,023 FFC0H 1,022 FF80H 1,021 FF40H 3 00C0H 2 0080H 1 0040H 0 0000H 1 1 3 2 5 3 2,048 1,024 2,048 1,024 2,048 1,024 2,043 1,022 2,045 1,023 2,047 1 2,048 1,024 2,048 1,024 2,048 Input voltage/AVREF0 474 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W <7> ADA0PFM Address: FFFFF204H 6 ADA0PFE ADA0PFC 5 4 3 2 1 0 0 0 0 0 0 0 Selection of power-fail compare enable/disable ADA0PFE 0 Power-fail compare disabled 1 Power-fail compare enabled ADA0PFC Selection of power-fail compare mode 0 Generates an interrupt request signal (INTAD) when ADA0CRnH ADA0PFT 1 Generates an interrupt request signal (INTAD) when ADA0CRnH < ADA0PFT Cautions 1. In the select mode, the 8-bit data set to the ADA0PFT register is compared with the value of the ADA0CRnH register specified by the ADA0S register. If the result matches the condition specified by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register and the INTAD signal is generated. If it does not match, however, the interrupt signal is not generated. 2. In the scan mode, the 8-bit data set to the ADA0PFT register is compared with the contents of the ADA0CR0H register. If the result matches the condition specified by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated. If it does not match, however, the INTAD signal is not generated. Regardless of the comparison result, the scan operation is continued and the conversion result is stored in the ADA0CRn register until the scan operation is completed. However, the INTAD signal is not generated after the scan operation has been completed. <R> 3. In the following modes, write data to the ADA0PFM register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode of the high-speed conversion mode User's Manual U16541EJ5V1UD 475 CHAPTER 13 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W 7 Address: FFFFF205H 6 5 4 3 2 1 0 ADA0PFT <R> Caution In the following modes, write data to the ADA0PFT register while A/D conversion is stopped (ADA0M0.ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode of the high-speed conversion mode 476 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER 13.5 Operation 13.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode. <2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and holds the input analog voltage until A/D conversion is complete. <4> Set bit 9 of the successive approximation register (SAR). The tap selector selects (1/2) AVREF0 as the voltage tap of the series resistor string. <5> The voltage difference between the voltage of the series resistor string and the analog input voltage is compared by the voltage comparator. If the analog input voltage is higher than (1/2) AVREF0, the MSB of the SAR register remains set. If it is lower than (1/2) AVREF0, the MSB is reset. <6> Next, bit 8 of the SAR register is automatically set and the next comparison is started. Depending on the value of bit 9, to which a result has been already set, the voltage tap of the series resistor string is selected as follows. * Bit 9 = 1: (3/4) AVREF0 * Bit 9 = 0: (1/4) AVREF0 This voltage tap and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. Analog input voltage Voltage tap: Bit 8 = 1 Analog input voltage Voltage tap: Bit 8 = 0 <7> This comparison is continued to bit 0 of the SAR register. <8> When comparison of the 10 bits is complete, the valid digital result is stored in the SAR register, which is then transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal (INTAD) is generated. <9> In one-shot select mode, conversion is stoppedNote. In one-shot scan mode, conversion is stopped after scanning onceNote. In continuous select mode, repeat steps <2> to <8> until the ADA0M0.ADA0CE bit is cleared to 0. In continuous scan mode, repeat steps <2> to <8> for each channel. Note In the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status is entered. <R> Remark The trigger standby status means the status after the stabilization time has elapsed. User's Manual U16541EJ5V1UD 477 CHAPTER 13 A/D CONVERTER 13.5.2 Conversion operation timing <R> Figure 13-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit First conversion Setup Processing state Sampling Second conversion A/D conversion Wait Setup Conversion time Wait time Sampling INTAD signal Stabilization time 2/fXX (MAX.) Sampling time 0.5/fXX (2) Operation in high-speed conversion mode (ADA0HS1 bit = 1) ADA0M0.ADA0CE bit First conversion Setup Processing state Sampling Second conversion A/D conversion Sampling A/D conversion INTAD signal Stabilization time 2/fXX (MAX.) ADA0FR3 to ADA0FR0 bits Note Conversion time Sampling time 0.5/fXX Stabilization time Conversion time (sampling time) 0000 13/fXX 26/fXX (4/fXX) 27/fXX 3/fXX 0001 26/fXX 52/fXX (8/fXX) 53/fXX 3/fXX 0010 39/fXX 78/fXX (12/fXX) 79/fXX 3/fXX 0011 50/fXX 104/fXX (16/fXX) 105/fXX 3/fXX 0100 50/fXX 130/fXX (20/fXX) 131/fXX 3/fXX 0101 50/fXX 156/fXX (24/fXX) 157/fXX 3/fXX 0110 50/fXX 182/fXX (28/fXX) 183/fXX 3/fXX 0111 50/fXX 208/fXX (32/fXX) 209/fXX 3/fXX 1000 50/fXX 234/fXX (36/fXX) 235/fXX 3/fXX 1001 50/fXX 260/fXX (40/fXX) 261/fXX 3/fXX 1010 50/fXX 286/fXX (44/fXX) 287/fXX 3/fXX 1011 50/fXX 312/fXX (48/fXX) 313/fXX 3/fXX Other than above Wait time Trigger response time Setting prohibited Note V850ES/SG2: ADA0FR2 to ADA0FR0 bits V850ES/SG2-H: ADA0FR3 to ADA0FR0 bits Remark The above timings are when a trigger generates within the stabilization time. If the trigger generates after the stabilization time, a trigger response time is inserted. 478 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER 13.5.3 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. The ADA0M0.ADA0TMD bit is used to set the trigger mode. The hardware trigger modes are set by the ADA0M2.ADA0TMD1 and ADA0M2.ADA0TMD0 bits. (1) Software trigger mode When the ADA0M0.ADA0CE bit is set to 1, the signal of the analog input pin (ANI0 to ANI11 pin) specified by the ADA0S register is converted. When conversion is complete, the result is stored in the ADA0CRn register. At the same time, the A/D conversion end interrupt request signal (INTAD) is generated. If the operation mode specified by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits is the continuous select/scan mode, the next conversion is started, unless the ADA0CE bit is cleared to 0 after completion of the first conversion. Conversion is performed once and ends if the operation mode is the one-shot select/scan mode. When conversion is started, the ADA0M0.ADA0EF bit is set to 1 (indicating that conversion is in progress). If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the <R> conversion is aborted and started again from the beginning. However, writing these registers is prohibited in the normal conversion mode and one-shot select mode/one-shot scan mode of the high-speed conversion mode. (2) External trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI11) specified by the ADA0S register is started when an external trigger is input (to the ADTRG pin). Which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the ADA0M0.ADA0ETS1 and ADA0M0.ATA0ETS0 bits. When the ADA0CE bit is set to 1, the A/D converter waits for the trigger, and starts conversion after the external trigger has been input. When conversion is completed, the result of conversion is stored in the ADA0CRn register, regardless of whether the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits. At the same time, the INTAD signal is generated, and the A/D converter waits for the trigger again. When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during the conversion operation, <R> the conversion is not aborted, and the A/D converter waits for the trigger again. However, writing these registers is prohibited in the one-shot select mode/one-shot scan mode. <R> Caution To select the external trigger mode, set the high-speed conversion mode. Do not input a trigger during stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1). <R> Remark The trigger standby status means the status after the stabilization time has elapsed. User's Manual U16541EJ5V1UD 479 CHAPTER 13 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI11) specified by the ADA0S register is started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare register connected to the timer. The INTTP2CC0 or INTTP2CC1 signal is selected by the ADA0TMD1 and ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal. When the ADA0CE bit is set to 1, the A/D converter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. When conversion is completed, regardless of whether the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits, the result of the conversion is stored in the ADA0CRn register. At the same time, the INTAD signal is generated, and the A/D converter waits for the trigger again. When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion is stopped and the A/D converter waits for the trigger again. However, writing these registers is <R> prohibited in the one-shot select mode/one-shot scan mode. <R> Caution To select the timer trigger mode, set the high-speed conversion mode. Do not input a trigger during stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1). <R> Remark 480 The trigger standby status means the status after the stabilization time has elapsed. User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER 13.5.4 Operation mode Four operation modes are available as the modes in which to set the ANI0 to ANI11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin corresponds to an ADA0CRn register on a one-to-one basis. Each time A/D conversion is completed, the A/D conversion end interrupt request signal (INTAD) is generated. After completion of conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 11). Figure 13-4. Timing Example of Continuous Select Mode Operation (ADA0S Register = 01H) ANI1 Data 4 Data 1 A/D conversion Data 1 (ANI1) Data 2 Data 3 Data 2 (ANI1) Data 3 (ANI1) Data 1 (ANI1) ADA0CR1 Data 2 (ANI1) Data 4 (ANI1) Data 3 (ANI1) Data 5 Data 5 (ANI1) Data 4 (ANI1) Data 6 Data 7 Data 6 (ANI1) Data 7 (ANI1) Data 6 (ANI1) INTAD Conversion start Set ADA0CE bit = 1 Conversion start Set ADA0CE bit = 1 (2) Continuous scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S register, and their values are converted into digital values. The result of each conversion is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated, and A/D conversion is started again from the ANI0 pin, unless the ADA0CE bit is cleared to 0 (n = 0 to 11). User's Manual U16541EJ5V1UD 481 CHAPTER 13 A/D CONVERTER Figure 13-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data 5 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 (ANI0) A/D conversion Data 2 (ANI1) Data 1 (ANI0) ADA0CRn Data 3 (ANI2) Data 2 (ANI1) Data 4 (ANI3) Data 3 (ANI2) Data 5 (ANI0) Data 4 (ANI3) Data 6 (ANI1) Data 5 (ANI0) INTAD Conversion start Set ADA0CE bit = 1 (b) Block diagram Analog input pin ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 482 ADA0CRn register A/D converter ADA0CR3 ANI4 ADA0CR4 ANI5 . . . . ADA0CR5 . . . ANI9 ADA0CR9 ANI10 ADA0CR10 ANI11 ADA0CR11 User's Manual U16541EJ5V1UD Data 7 (ANI2) Data 6 (ANI1) CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the voltage on the analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis. When A/D conversion has been completed once, the INTAD signal is generated. The A/D conversion operation is stopped after it has been completed (n = 0 to 11). Figure 13-6. Timing Example of One-Shot Select Mode Operation (ADA0S Register = 01H) ANI1 Data 4 Data 1 Data 2 Data 3 Data 1 (ANI1) A/D conversion Data 5 Data 6 Data 7 Data 6 (ANI1) Data 1 (ANI1) ADA0CR1 Data 6 (ANI1) INTAD Conversion end Conversion start Set ADA0CE bit = 1 Conversion end Conversion start Set ADA0CE bit = 1 (4) One-shot scan mode In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S register, and their values are converted into digital values . Each conversion result is stored in the ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated. A/D conversion is stopped after it has been completed (n = 0 to 11). User's Manual U16541EJ5V1UD 483 CHAPTER 13 A/D CONVERTER Figure 13-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 5 Data 1 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 (ANI0) A/D conversion Data 2 (ANI1) Data 1 (ANI0) ADA0CRn Data 3 (ANI2) Data 2 (ANI1) Data 4 (ANI3) Data 3 (ANI2) Data 4 (ANI3) INTAD Conversion end Conversion start Set ADA0CE bit = 1 (b) Block diagram Analog input pin ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 484 ADA0CRn register A/D converter ADA0CR3 ANI4 ADA0CR4 ANI5 . . . . ADA0CR5 ANI9 ADA0CR9 ANI10 ADA0CR10 ANI11 ADA0CR11 . . . User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER 13.5.5 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. * When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter). * When the ADA0PFE bit = 1 and when the ADA0PFM.ADA0PFC bit = 0, the value of the ADA0CRnH register is compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if ADA0CRnH ADA0PFT. * When the ADA0PFE bit = 1 and when the ADA0PFC bit = 1, the value of the ADA0CRnH register is compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if ADA0CRnH < ADA0PFT. Remark n = 0 to 11 In the power-fail compare mode, four modes are available as modes in which to set the ANI0 to ANI11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. User's Manual U16541EJ5V1UD 485 CHAPTER 13 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is not generated. After completion of the first conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 11). Figure 13-8. Timing Example of Continuous Select Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 01H) ANI1 Data 4 Data 1 A/D conversion Data 1 (ANI1) ADA0CR1 Data 2 Data 3 Data 2 (ANI1) Data 3 (ANI1) Data 4 (ANI1) Data 1 (ANI1) Data 2 (ANI1) Data 3 (ANI1) ADA0PFT unmatch ADA0PFT unmatch ADA0PFT match Data 5 Data 5 (ANI1) Data 4 (ANI1) Data 6 Data 7 Data 6 (ANI1) Data 7 (ANI1) Data 6 (ANI1) INTAD Conversion start Set ADA0CE bit = 1 ADA0PFT ADA0PFT match match Conversion start Set ADA0CE bit = 1 (2) Continuous scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of channel 0 is compared with the value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD signal is not generated. After the result of the first conversion has been stored in the ADA0CR0 register, the results of sequentially converting the voltages on the analog input pins up to the pin specified by the ADA0S register are continuously stored. After completion of conversion, the next conversion is started from the ANI0 pin again, unless the ADA0CE bit is cleared to 0. 486 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER Figure 13-9. Timing Example of Continuous Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (b) Timing example ANI0 Data 1 Data 5 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 (ANI0) A/D conversion Data 2 (ANI1) Data 1 (ANI0) ADA0CRn Data 3 (ANI2) Data 2 (ANI1) Data 4 (ANI3) Data 3 (ANI2) Data 5 (ANI0) Data 4 (ANI3) Data 6 (ANI1) Data 5 (ANI0) Data 7 (ANI2) Data 6 (ANI1) INTAD ADA0PFT match ADA0PFT unmatch Conversion start Set ADA0CE bit = 1 (b) Block diagram Analog input pin ADA0CRn register ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 A/D converter ADA0CR3 ANI4 ADA0CR4 ANI5 . . . . ADA0CR5 ANI9 ADA0CR9 ANI10 ADA0CR10 ANI11 ADA0CR11 . . . User's Manual U16541EJ5V1UD 487 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the INTAD signal is not generated. Conversion is stopped after it has been completed. Figure 13-10. Timing Example of One-Shot Select Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 01H) ANI1 Data 4 Data 1 Data 2 Data 3 Data 1 (ANI1) A/D conversion Data 5 Data 6 Data 6 (ANI1) Data 1 (ANI1) ADA0CR1 Data 7 Data 6 (ANI1) INTAD ADA0PFT unmatch Conversion end Conversion start Set ADA0CE bit = 1 ADA0PFT match Conversion end Conversion start Set ADA0CE bit = 1 (4) One-shot scan mode In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0 pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of channel 0 is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and the INTAD0 signal is not generated. After the result of the first conversion has been stored in the ADA0CR0 register, the results of converting the signals on the analog input pins specified by the ADA0S register are sequentially stored. The conversion is stopped after it has been completed. 488 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER Figure 13-11. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data 5 Data 1 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 (ANI0) A/D conversion Data 2 (ANI1) Data 1 (ANI0) ADA0CRn Data 3 (ANI2) Data 2 (ANI1) Data 4 (ANI3) Data 3 (ANI2) Data 4 (ANI3) INTAD Conversion start Set ADA0CE bit = 1 ADA0PFT match Conversion end (b) Block diagram Analog input pin ADA0CRn register ANI0 ADA0CR0 ANI1 ADA0CR1 ANI2 ADA0CR2 ANI3 A/D converter ADA0CR3 ANI4 ADA0CR4 ANI5 . . . . ADA0CR5 . . . ANI9 ADA0CR9 ANI10 ADA0CR10 ANI11 ADA0CR11 User's Manual U16541EJ5V1UD 489 CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI11 pins Input the voltage within the specified range to the ANI0 to ANI11 pins. If a voltage equal to or higher than AVREF0 or equal to or lower than AVSS (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) Countermeasures against noise To maintain the 10-bit resolution, the ANI0 to ANI11 pins must be effectively protected from noise. The influence of noise increases as the output impedance of the analog input source becomes higher. To lower the noise, connecting an external capacitor as shown in Figure 13-12 is recommended. Figure 13-12. Processing of Analog Input Pin Clamp with a diode with a low VF (0.3 V or less) if noise equal to or higher than AVREF0 or equal to or lower than AVSS may be generated. VDD AVREF0 ANI0 to ANI11 AVSS VSS 490 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER <R> (4) Alternate I/O The analog input (ANI0 to ANI11) pins are multiplexed with port pins. The AVREF0 power pin is multiplexed with the reference power supply to the A/D converter and the I/O buffer power supply of port 7. If any of the following processings is performed during A/D conversion, therefore, the expected A/D conversion value may not be obtained. (a) If a digital pulse is applied to a pin adjacent to a pin whose input analog signal is converted into a digital signal (for example, P72 and P74 pins during ANI3 conversion) (cause: influence of coupling noise) (b) If AVREF0 power supply fluctuates as a result of executing an instruction to read the P7H or P7L register to the input port during A/D conversion or an instruction to write data to the output port (cause: influence on the AVREF0 power supply) (c) If a current flows through a pin of port 7 (P70 to P711) that is set in the output mode because of the influence of the external circuit connected to the port pin and, as a result, the AVREF0 power supply fluctuates (cause: influence on the AVREF0 power supply) If there is a possibility that any of the above processings may be executed during A/D conversion, be sure to execute A/D conversion more than once, check the A/D conversion value, and eliminate any abnormal value by program. User's Manual U16541EJ5V1UD 491 CHAPTER 13 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten. If the ADIF flag is read immediately after the ADA0S register is rewritten, the ADIF flag may be set even though the A/D conversion of the newly selected analog input pin has not been completed. When A/D conversion is stopped, clear the ADIF flag before resuming conversion. Figure 13-13. Generation Timing of A/D Conversion End Interrupt Request ADA0S rewriting (ANIn conversion start) ADA0S rewriting (ANIm conversion start) ANIn A/D conversion ADIF is set, but ANIm conversion does not end ANIn ADA0CRn ANIn ANIm ANIm ANIn ANIm INTAD Remark n = 0 to 11 m = 0 to 11 (6) Internal equivalent circuit The following shows the equivalent circuit of the analog input block. Figure 13-14. Internal Equivalent Circuit of ANIn Pin RIN ANIn CIN <R> RIN CIN 2.9 k 4.0 pF Remarks 1. The above values are reference values. 2. n = 0 to 11 492 User's Manual U16541EJ5V1UD ANIm CHAPTER 13 A/D CONVERTER (7) AVREF0 pin (a) The AVREF0 pin is used as the power supply pin of the A/D converter and also supplies power to the alternate-function ports. In an application where a backup power supply is used, be sure to supply the same voltage as VDD to the AVREF0 pin as shown in Figure 13-15. (b) The AVREF0 pin is also used as the reference voltage pin of the A/D converter. If the source supplying power to the AVREF0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately after the conversion operation enable bit ADA0CE has been set to 1). As a result, the conversion accuracy may drop. To avoid this, it is recommended to connect a capacitor across the AVREF0 and AVSS pins to suppress the reference voltage fluctuation as shown in Figure 13-15. (c) If the source supplying power to the AVREF0 pin has a high DC resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the A/D conversion current. Figure 13-15. AVREF0 Pin Processing Example Note AVREF0 Main power supply AVSS Note Parasitic inductance <R> (8) Reading ADA0CRn register When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written, the contents of the ADA0CRn register may be undefined. Read the conversion result after completion of conversion and before writing to the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register. Also, when an external/timer trigger is acknowledged, the contents of the ADA0CRn register may be undefined. Read the conversion result after completion of conversion and before the next external/timer trigger is acknowledged. The correct conversion result may not be read at a timing different from the above. (9) Standby mode Because the A/D converter stops operating in the STOP mode, conversion results are invalid, so power consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D conversion results after the STOP mode is released are invalid. When using the A/D converter after the STOP mode is released, before setting the STOP mode or releasing the STOP mode, clear the ADA0M0.ADA0CE bit to 0 then set the ADA0CE bit to 1 after releasing the STOP mode. In the IDLE1, IDLE2, or subclock operation mode, operation continues. To lower the power consumption, therefore, clear the ADA0M0.ADA0CE bit to 0. In the IDLE1 and IDLE2 modes, since the analog input voltage value cannot be retained, the A/D conversion results after the IDLE1 and IDLE2 modes are released are invalid. The results of conversions before the IDLE1 and IDLE2 modes were set are valid. User's Manual U16541EJ5V1UD 493 CHAPTER 13 A/D CONVERTER <R> (10) Restriction for each mode (a) To select the external trigger mode/timer trigger mode, set the high-speed conversion mode. Do not input a trigger during stabilization time that is inserted once after the A/D conversion operation is enabled (ADA0M0.ADA0CE bit = 1). (b) In the following modes, write data to the A/D control register while A/D conversion is stopped (ADA0CE bit = 0), and then enable the A/D conversion operation (ADA0CE bit = 1). * Normal conversion mode * One-shot select mode/one-shot scan mode of high-speed conversion mode Remark A/D control registers: ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers (12) Variation of A/D conversion results The results of the A/D conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. To reduce the variation, take counteractive measures with the program such as averaging the A/D conversion results. (13) A/D conversion result hysteresis characteristics The successive comparison type A/D converter holds the analog input voltage in the internal sample & hold capacitor and then performs A/D conversion. After the A/D conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. As a result, the following phenomena may occur. * When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous value. Thus, even if the conversion is performed at the same potential, the result may vary. * When switching the analog input channel, hysteresis characteristics may appear where the conversion result is affected by the previous channel value. This is because one A/D converter is used for the A/D conversions. Thus, even if the conversion is performed at the same potential, the result may vary. 494 User's Manual U16541EJ5V1UD CHAPTER 13 A/D CONVERTER 13.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR (full-scale range). %FSR is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%FSR = (Maximum value of convertible analog input voltage - Minimum value of convertible analog input voltage)/100 = (AVREF0 - 0)/100 = AVREF0/100 When the resolution is 10 bits, 1 LSB is as follows: 1 LSB = 1/210 = 1/1,024 = 0.098%FSR The accuracy is determined by the overall error, independently of the resolution. (2) Overall error This is the maximum value of the difference between an actually measured value and a theoretical value. It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. The overall error in the characteristics table does not include the quantization error. Figure 13-16. Overall Error 1......1 Digital output Ideal line Overall error 0......0 0 AVREF0 Analog input User's Manual U16541EJ5V1UD 495 CHAPTER 13 A/D CONVERTER (3) Quantization error This is an error of 1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of 1/2 LSB into the same digital codes, a quantization error is unavoidable. This error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. Figure 13-17. Quantization Error Digital output 1......1 1/2 LSB Quantization error 1/2 LSB 0......0 0 AVREF0 Analog input (4) Zero-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0...000 to 0...001 (1/2 LSB). Figure 13-18. Zero-Scale Error Digital output (lower 3 bits) 111 Ideal line 100 Zero-scale error 011 010 001 000 -1 0 1 2 3 Analog input (LSB) 496 User's Manual U16541EJ5V1UD AVREF0 CHAPTER 13 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1...110 to 1...111 (full scale - 3/2 LSB). Figure 13-19. Full-Scale Error Digital output (lower 3 bits) Full-scale error 111 100 011 010 000 0 AVREF0 - 3 AVREF0 - 2 AVREF0 - 1 AVREF0 Analog input (LSB) (6) Differential linearity error Ideally, the width to output a specific code is 1 LSB. This error indicates the difference between the actually measured value and its theoretical value when a specific code is output. This indicates the basic characteristics of the A/D conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from AVSS to AVREF0. When the input voltage is increased or decreased, or when two or more channels are used, see 13.7 (2) Overall error. Figure 13-20. Differential Linearity Error 1......1 Digital output Ideal width of 1 LSB Differential linearity error 0......0 AVREF0 Analog input User's Manual U16541EJ5V1UD 497 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. Figure 13-21. Integral Linearity Error 1......1 Digital output Ideal line Integral linearity error 0......0 0 AVREF0 Analog input (8) Conversion time This is the time required to obtain a digital output after each trigger has been generated. The conversion time in the characteristics table includes the sampling time. (9) Sampling time This is the time for which the analog switch is ON to load an analog voltage to the sample & hold circuit. Figure 13-22. Sampling Time Sampling time Conversion time 498 User's Manual U16541EJ5V1UD CHAPTER 14 D/A CONVERTER 14.1 Functions The D/A converter has the following functions. { 8-bit resolution x 2 channels (DA0CS0, DA0CS1) { R-2R ladder method { Settling time: 3 s max. (when AVREF1 is 3.0 to 3.6 V and external load is 20 pF) { Analog output voltage: AVREF1 x m/256 (m = 0 to 255; value set to DA0CSn register) { Operation modes: Normal mode, real-time output mode Remark n = 0, 1 14.2 Configuration The D/A converter configuration is shown below. Figure 14-1. Block Diagram of D/A Converter DA0CS0 register write DA0M.DA0MD0 bit DA0CS0 register INTTP2CC0 signal ANO0 pin DA0M.DA0CE0 bit AVREF1 pin Selector AVSS pin ANO1 pin Selector DA0M.DA0CE1 bit DA0CS1 register write DA0M.DA0MD1 bit DA0CS1 register INTTP3CC0 signal Cautions 1. DA converters 0 and 1 share the AVREF1 pin. 2. DA converters 0 and 1 share the AVSS pin. The AVSS pin is also shared by the A/D converter. User's Manual U16541EJ5V1UD 499 CHAPTER 14 D/A CONVERTER The D/A converter consists of the following hardware. Table 14-1. Configuration of D/A Converter Item Configuration Control registers D/A converter mode register (DA0M) D/A converter conversion value setting registers 0, 1 (DA0CS0, DA0CS1) 14.3 Registers The registers that control the D/A converter are as follows. * D/A converter mode register (DA0M) * D/A converter conversion value setting registers 0, 1 (DA0CS0, DA0CS1) (1) D/A converter mode register (DA0M) The DA0M register controls the operation of the D/A converter. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF282H < > DA0M 0 DA0CEn 0 DA0CE1 DA0CE0 0 0 DA0MD1 DA0MD0 Control of D/A converter operation enable/disable (n = 0, 1) 0 Disables operation 1 Enables operation DA0MDn < > Selection of D/A converter operation mode (n = 0, 1) 0 Normal mode 1 Real-time output modeNote Note The output trigger in the real-time output mode (DA0MDn bit = 1) is as follows. * When n = 0: INTTP2CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)) * When n = 1: INTTP3CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)) 500 User's Manual U16541EJ5V1UD CHAPTER 14 D/A CONVERTER (2) D/A converter conversion value setting registers 0, 1 (DA0CS0, DA0CS1) The DA0CS0 and DA0CS1 registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H DA0CSn Caution R/W Address: DA0CS0 FFFFF280H, DA0CS1 FFFFF281H DA0CSn7 DA0CSn6 DA0CSn5 DA0CSn4 DA0CSn3 DA0CSn2 DA0CSn1 DA0CSn0 In the real-time output mode (DA0M.DA0MDn bit = 1), set the DA0CSn register before the INTTP2CC0/INTTP3CC0 signals are generated. D/A conversion starts when the INTTP2CC0/INTTP3CC0 signals are generated. Remark n = 0, 1 User's Manual U16541EJ5V1UD 501 CHAPTER 14 D/A CONVERTER 14.4 Operation 14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CSn register as the trigger. The setting method is described below. <1> Set the DA0M.DA0MDn bit to 0 (normal mode). <2> Set the analog voltage value to be output to the ANOn pin to the DA0CSn register. Steps <1> and <2> above constitute the initial settings. <3> Set the DA0M.DA0CEn bit to 1 (D/A conversion enable). D/A conversion starts when this setting is performed. <4> To perform subsequent D/A conversions, write to the DA0CSn register. The previous D/A conversion result is held until the next D/A conversion is performed. Remarks 1. For the alternate-function pin settings, see Table 4-15 Using Port Pin as Alternate-Function Pin. 2. n = 0, 1 14.4.2 Operation in real-time output mode D/A conversion is performed using the interrupt request signals (INTTP2CC0 and INTTP3CC0) of TMP2 and TMP3 as triggers. The setting method is described below. <1> Set the DA0M.DA0MDn bit to 1 (real-time output mode). <2> Set the analog voltage value to be output to the ANOn pin to the DA0CSn register. <3> Set the DA0M.DA0CEn bit to 1 (D/A conversion enable). Steps <1> to <3> above constitute the initial settings. <4> Operate TMP2 and TMP3. <5> D/A conversion starts when the INTTP2CC0 and INTTP3CC0 signals are generated. <6> After that, the value set in DA0CSn register is output every time the INTTP2CC0 and INTTP3CC0 signals are generated. Remarks 1. The output values of the ANO0 and ANO1 pins up to <5> above are undefined. 2. For the output values of the ANO0 and ANO1 pins in the HALT, IDLE1, IDLE2, and STOP modes, see CHAPTER 24 STANDBY FUNCTION. 3. For the alternate-function pin settings, see Table 4-15 Using Port Pin as Alternate-Function Pin. 502 User's Manual U16541EJ5V1UD CHAPTER 14 D/A CONVERTER 14.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/SG2. (1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output mode. (2) Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0. (3) When using one of the P10/AN00 and P11/AN01 pins as an I/O port and the other as a D/A output pin, do so in an application where the port I/O level does not change during D/A output. (4) Make sure that AVREF0 = VDD = AVREF1 = 3.0 to 3.6 V. If this range is exceeded, the operation is not guaranteed. (5) Apply power to AVREF1 at the same timing as AVREF0. (6) No current can be output from the ANOn pin (n = 0, 1) because the output impedance of the D/A converter is high. When connecting a resistor of 2 M or less, insert a JFET input operational amplifier between the resistor and the ANOn pin. Figure 14-2. External Pin Connection Example - Output ANOn + AVREF0 AVSS AVREF1 JFET input operational amplifier 0.1 F 10 F 0.1 F 10 F VDD (7) Because the D/A converter stops operation in the STOP mode, the ANO0 and ANO1 pins go into a highimpedance state, and the power consumption can be reduced. In the IDLE1, IDLE2, or subclock operation mode, however, the operation continues. To lower the power consumption, therefore, clear the DA0M.DA0CEn bit to 0. User's Manual U16541EJ5V1UD 503 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1 Mode Switching of UARTA and Other Serial Interfaces 15.1.1 CSIB4 and UARTA0 mode switching <R> In the V850ES/SG2 and V850ES/SG2-H, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA0 in advance, using the PMC3 and PFC3 registers, before use. Caution The transmit/receive operation of CSIB4 and UARTA0 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 15-1. CSIB4 and UARTA0 Mode Switch Settings After reset: 0000H R/W Address: FFFFF446H, FFFFF447H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PMC39 PMC38 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC3 After reset: 0000H R/W Address: FFFFF466H, FFFFF467H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PFC39 PFC38 PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 0 PFCE32 0 0 PFC3 After reset: 00H PFCE3L R/W Address: FFFFF706H 0 0 0 PMC32 PFCE32 PFC32 0 Operation mode 0 x x Port I/O mode 1 0 0 ASCKA0 mode 1 0 1 SCKB4 mode PMC3n PFC3n 0 x Port I/O mode 1 0 UARTA0 mode 1 1 CSIB4 mode Operation mode Remarks 1. n = 0, 1 2. x = don't care 504 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1.2 UARTA2 and I2C00 mode switching <R> In the I2C bus versions (Y products) of the V850ES/SG2 and V850ES/SG2-H, UARTA2 and I2C00 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA2 in advance, using the PMC3 and PFC3 registers, before use. Caution The transmit/receive operation of UARTA2 and I2C00 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 15-2. UARTA2 and I2C00 Mode Switch Settings After reset: 0000H PMC3 Address: FFFFF446H, FFFFF447H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PMC39 PMC38 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 After reset: 0000H PFC3 R/W R/W Address: FFFFF466H, FFFFF467H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PFC39 PFC38 PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 PMC3n PFC3n 0 x Port I/O mode 1 0 UARTA2 mode 1 1 I2C00 mode Operation mode Remarks 1. n = 8, 9 2. x = don't care User's Manual U16541EJ5V1UD 505 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1.3 UARTA1 and I2C02 mode switching <R> In the I2C bus versions (Y products) of the V850ES/SG2 and V850ES/SG2-H, UARTA1 and I2C02 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA1 in advance, using the PMC9, PFC9, and PMCE9 registers, before use. Caution The transmit/receive operation of UARTA1 and I2C02 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 15-3. UARTA1 and I2C02 Mode Switch Settings After reset: 0000H 15 PMC9 9 8 PMC99 PMC98 PMC97 PMC91 PMC90 9 8 506 R/W PMC95 12 PMC94 11 10 PMC93 PMC92 Address: FFFFF472H, FFFFF473H 14 PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98 PFC97 PFC96 PFC95 PFC93 PFC91 PFC90 15 Remark PMC96 13 15 After reset: 0000H PFCE9 14 Address: FFFFF452H, FFFFF453H PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 After reset: 0000H PFC9 R/W R/W 14 PFCE915 PFCE914 13 12 PFC94 11 10 PFC92 Address: FFFFF712H, FFFFF713H 13 12 11 10 9 8 0 0 0 0 0 0 PFCE91 PFCE90 PFCE97 PFCE96 PFCE95 PFCE94 PFCE93 PFCE92 PMC9n PFCE9n PFC9n 1 1 0 UARTA1 mode 1 1 1 I2C02 mode Operation mode n = 0, 1 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.2 Features <R> { Transfer rate: 300 bps to 312.5 kbps (V850ES/SG2: using internal system clock of 20 MHz, V850ES/SG2-H: using internal system clock of 32 MHz, and dedicated baud rate generator) { Full-duplex communication: Internal UARTAn receive data register (UAnRX) Internal UARTAn transmit data register (UAnTX) { 2-pin configuration: TXDAn: Transmit data output pin RXDAn: Receive data input pin { Reception error output function * Parity error * Framing error * Overrun error { Interrupt sources: 2 * Reception completion interrupt (INTUAnR): This interrupt occurs upon transfer of receive data from the receive shift register to the UAnRX register after serial transfer completion, in the reception enabled status. * Transmission enable interrupt (INTUAnT): This interrupt occurs upon transfer of transmit data from the UAnTX register to the transmit shift register in the transmission enabled status. { Character length: 7, 8 bits { Parity function: Odd, even, 0, none { Transmission stop bit: 1, 2 bits { On-chip dedicated baud rate generator { MSB-/LSB-first transfer selectable { Transmit/receive data inverted input/output possible { SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format * 13 to 20 bits selectable for the SBF transmission * Recognition of 11 bits or more possible for SBF reception * SBF reception flag provided Remark n = 0 to 2 User's Manual U16541EJ5V1UD 507 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.3 Configuration The block diagram of the UARTAn is shown below. <R> Figure 15-4. Block Diagram of Asynchronous Serial Interface An Internal bus INTUAnT INTUAnR UAnRX Reception unit Transmission unit UAnTX Receive shift register Reception controller Transmission controller Transmit shift register Filter Baud rate generator Baud rate generator Selector RXDAn Clock selector Selector fXX to fXX/210 ASCKA0Note UAnCTL0 UAnCTL1 UAnCTL2 UAnSTR UAnOPT0 Internal bus Note UARTA0 only Remarks 1. n = 0 to 2 2. For the configuration of the baud rate generator, see Figure 15-16. UARTAn consists of the following hardware units. Table 15-1. Configuration of UARTAn Item Registers Configuration UARTAn control register 0 (UAnCTL0) UARTAn control register 1 (UAnCTL1) UARTAn control register 2 (UAnCTL2) UARTAn option control register 0 (UAnOPT0) UARTAn status register (UAnSTR) UARTAn receive shift register UARTAn receive data register (UAnRX) UARTAn transmit shift register UARTAn transmit data register (UAnTX) 508 TXDAn User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn. (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register used to control the baud rate for the UARTAn. (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register used to control serial transfer for the UARTAn. (5) UARTAn status register (UAnSTR) The UAnSTRn register consists of flags indicating the error contents when a reception error occurs. Each one of the reception error flags is set (to 1) upon occurrence of a reception error. (6) UARTAn receive shift register This is a shift register used to convert the serial data input to the RXDAn pin into parallel data. Upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the UAnRX register. This register cannot be manipulated directly. (7) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in the highest bit (when data is received LSB first). In the reception enabled status, receive data is transferred from the UARTAn receive shift register to the UAnRX register in synchronization with the completion of shift-in processing of 1 frame. Transfer to the UAnRX register also causes the reception completion interrupt request signal (INTUAnR) to be output. (8) UARTAn transmit shift register The transmit shift register is a shift register used to convert the parallel data transferred from the UAnTX register into serial data. When 1 byte of data is transferred from the UAnTX register, the shift register data is output from the TXDAn pin. This register cannot be manipulated directly. (9) UARTAn transmit data register (UAnTX) The UAnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the UAnTX register. When data can be written to the UAnTX register (when data of one frame is transferred from the UAnTX register to the UARTAn transmit shift register), the transmission enable interrupt request signal (INTUAnT) is generated. User's Manual U16541EJ5V1UD 509 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.4 Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H. (1/2) After reset: 10H R/W Address: UA0CTL0 FFFFFA00H, UA1CTL0 FFFFFA10H, UA2CTL0 FFFFFA20H <7> UAnCTL0 <6> <5> <4> UAnPWR UAnTXE UAnRXE UAnDIR 3 2 UAnPS1 UAnPS0 1 0 UAnCL UAnSL (n = 0 to 2) UAnPWR UARTAn operation control 0 Disable UARTAn operation (UARTAn reset asynchronously) 1 Enable UARTAn operation The UARTAn operation is controlled by the UAnPWR bit. The TXDAn pin output is fixed to high level by clearing the UAnPWR bit to 0 (fixed to low level if UAnOPT0.UAnTDL bit = 1). UAnTXE Transmission operation enable 0 Disable transmission operation 1 Enable transmission operation * To start transmission, set the UAnPWR bit to 1 and then set the UAnTXE bit to 1. * To initialize the transmission unit, clear the UAnTXE bit to 0, wait for two cycles of the base clock (fUCLK), and then set the UAnTXE bit to 1 again. Otherwise, initialization may not be executed (for the base clock, see 15.7 (1) (a) Base clock). * When the operation is enabled (UAnPWR bit = 1), the transmission operation is enabled after two or more cycles of the base clock (fUCLK) have elapsed since UAnTXE = 1. * When the UAnPWR bit is cleared to 0, the status of the internal circuit becomes the same status as UAnTXE bit = 0 by the UAnPWR bit even if the UAnTXE bit is 1. The transmission operation is enabled when the UAnPWR bit is set to 1 again. <R> <R> <R> 510 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnRXE <R> Reception operation enable 0 Disable reception operation 1 Enable reception operation * To start reception, set the UAnPWR bit to 1 and then set the UAnRXE bit to 1. * To initialize the reception unit, clear the UAnRXE bit to 0, wait for two cycles of the base clock, and then set the UAnRXE bit to 1 again. Otherwise, initialization may not be executed (for the base clock, see 15.7 (1) (a) Base clock). * When the operation is enabled (UAnPWR bit = 1), the reception operation is enabled after two or more cycles of the base clock (fUCLK) have elapsed since UAnRXE = 1. If the start bit is received before the reception operation is enabled, the start bit is ignored. * When the UAnPWR bit is cleared to 0, the status of the internal circuit becomes the same status as UAnRXE bit = 0 by the UAnPWR bit even if the UAnRXE bit is 1. The reception operation is enabled when the UAnPWR bit is set to 1 again. <R> <R> UAnDIRNote <R> <R> Transfer direction selection 0 MSB-first transfer 1 LSB-first transfer UAnPS1Note UAnPS0Note Parity selection during transmission Parity selection during reception 0 0 No parity output Reception with no parity 0 1 0 parity output Reception with 0 parity 1 0 Odd parity output Odd parity check 1 1 Even parity output Even parity check * If "Reception with 0 parity" is selected during reception, a parity check is not performed. Therefore, the UAnSTR.UAnPE bit is not set. * When transmission and reception are performed in the LIN format, clear the UAnPS1 and UAnPS0 bits to 00. <R> UAnCLNote Specification of data character length of 1 frame of transmit/receive data 7 bits 1 8 bits UAnSLNote <R> <R> <R> 0 Specification of length of stop bit for transmit data 0 1 bit 1 2 bits Only the first bit of the receive data stop bits is checked, regardless of the value of the UAnSL bit. Note This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = UAnRXE bit = 0. However, setting any or all of the UAnPWR, UAnTXE, and UAnRXE bits to 1 at the same time is possible. Remark For details of parity, see 15.6.9 Parity types and operations. User's Manual U16541EJ5V1UD 511 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) For details, see 15.7 (2) UARTAn control register 1 (UAnCTL1). (3) UARTAn control register 2 (UAnCTL2) For details, see 15.7 (3) UARTAn control register 2 (UAnCTL2). (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 14H. Caution Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception (UAnSRF bit = 1). (1/2) After reset: 14H R/W <7> 6 Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H, UA2OPT0 FFFFFA23H UAnOPT0 5 4 3 2 1 0 UAnSRF UAnSRT UAnSTT UAnSLS2 UAnSLS1 UAnSLS0 UAnTDL UAnRDL (n = 0 to 2) UAnSRF SBF reception flag 0 When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set. Also upon normal end of SBF reception. 1 During SBF reception * SBF (Sync Brake Field) reception is judged during LIN communication. * The UAnSRF bit is held at 1 when an SBF reception error occurs, and then SBF reception is started again. UAnSRT SBF reception trigger - 0 1 SBF reception trigger * This is the SBF reception trigger bit during LIN communication, and when read, "0" is always read. For SBF reception, set the UAnSRT bit (to 1) to enable SBF reception. * Set the UAnSRT bit after setting both the UAnPWR bit and UAnRXE bit to 1. * Set the UAnSRT bit (to 1) during a period of 1 bit after the reception end interrupt request signal (INTUAnR) has been generated. (If this bit is set (to 1) during reception operation, the UAnSRF bit is cleared when reception of the current data is completed, even if SBF is not received.) * Writing 0 to the UAnSRT bit is valid. If 0 is written to the UAnSRT bit before SBF reception is started, therefore, SBF is not received but normal UART reception is executed. If 0 is written to the UAnOPT0 register during SBF reception, data that has already been received is received as SBF. If the data being received is not SBF, however, the following data operate as the receive data of UART, starting from the next receive data. The UAnSRF bit is cleared when 0 is written to the UAnSRT bit. <R> <R> 512 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnSTT SBF transmission trigger - 0 1 <R> SBF transmission trigger * This is the SBF transmission trigger bit during LIN communication, and when read, "0" is always read. * Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1. * Writing 0 to the UAnSTT bit is valid. If 0 is written to this bit after 1 has been written to it and before it is sampled with the base clock, SBF transmission is therefore not executed. If 0 is written to the UAnSTT bit during SBF transmission, the UAnSTR.UAnTSF bit is cleared to 0 even though SBF transmission is executed. UAnSLS2 UAnSLS1 UAnSLS0 SBF transmit length selection 1 0 1 13-bit output (reset value) 1 1 0 14-bit output 1 1 1 15-bit output 0 0 0 16-bit output 0 0 1 17-bit output 0 1 0 18-bit output 0 1 1 19-bit output 1 0 0 20-bit output This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0. UAnTDL Transmit data level bit 0 Normal output of transfer data 1 Inverted output of transfer data * The output level of the TXDAn pin can be inverted using the UAnTDL bit. * This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0. UAnRDL <R> Receive data level bit 0 Normal input of transfer data 1 Inverted input of transfer data * The input level of the RXDAn pin can be inverted using the UAnRDL bit. * This register can be set when the UAnPWR bit = 0 or the UAnRXE bit = 0. * When the UAnRDL bit is set to 1 (inverted input of receive data), reception must be enabled (UAnCTL0.UAnRXE bit = 1) after setting the data reception pin to the UART reception pin (RXDAn) when reception is started. When the pin mode is changed after reception is enabled, the start bit will be mistakenly detected if the pin level is high. User's Manual U16541EJ5V1UD 513 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (5) UARTAn status register (UAnSTR) The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents. This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the UAnPE, UAnFE, and UAnOVE bits can both be read and written. However, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). The initialization conditions are shown below. Register/Bit UAnSTR register Initialization Conditions * Reset * UAnCTL0.UAnPWR = 0 UAnTSF bit * UAnCTL0.UAnTXE = 0 UAnPE, UAnFE, UAnOVE bits * 0 write * UAnCTL0.UAnRXE = 0 <R> Caution Be sure to read the error flags of the UAnPE, UAnFE, and UAnOVE bits to check the flag status, and then clear the flags by writing "0" to them. 514 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H R/W Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H, UA2STR FFFFFA24H UAnSTR <7> 6 5 4 3 <2> <1> <0> UAnTSF 0 0 0 0 UAnPE UAnFE UAnOVE (n = 0 to 2) UAnTSF Transfer status flag 0 * When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set. * When, following transfer completion, there was no next data transfer from UAnTX register 1 Write to UAnTX register The UAnTSF bit is always 1 when performing continuous transmission. When initializing the transmission unit, check that the UAnTSF bit = 0 before performing initialization. The transmit data is not guaranteed when initialization is performed while the UAnTSF bit = 1. UAnPE Parity error flag 0 * When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set. * When 0 has been written 1 When parity of data and parity bit do not match during reception. * The operation of the UAnPE bit is controlled by the settings of the UAnCTL0.UAnPS1 and UAnCTL0.UAnPS0 bits. * The UAnPE bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained. UAnFE Framing error flag 0 * When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set * When 0 has been written 1 When no stop bit is detected during reception * Only the first bit of the receive data stop bits is checked, regardless of the value of the UAnCTL0.UAnSL bit. * The UAnFE bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained. UAnOVE Overrun error flag 0 * When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set. * When 0 has been written 1 When receive data has been set to the UAnRX register and the next receive operation is completed before that receive data has been read * When an overrun error occurs, the data is discarded without the next receive data being written to the UAnRX register. * The UAnOVE bit can be both read and written, but it can only be cleared by writing 0 to it. When 1 is written to this bit, the value is retained. User's Manual U16541EJ5V1UD 515 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception <R> of 1 byte of data. The reception end interrupt request signal (INTUAnR) is generated in this timing. During LSB-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits 6 to 0 of the UAnRX register and the MSB always becomes 0. During MSB-first reception, the receive data is transferred to bits 7 to 1 of the UAnRX register and the LSB always becomes 0. When an overrun error occurs (UAnSTR.UAnOVE bit = 1), the receive data at this time is not transferred to the UAnRX register and is discarded. This register is read-only, in 8-bit units. In addition to reset input, the UAnRX register can be set to FFH by clearing the UAnCTL0.UAnPWR bit to 0. After reset: FFH R Address: UA0RX FFFFFA06H, UA1RX FFFFFA16H, UA2RX FFFFFA26H 6 7 5 4 3 2 1 0 UAnRX (n = 0 to 2) (7) UARTAn transmit data register (UAnTX) The UAnTX register is an 8-bit register used to set transmit data. Transmission starts when transmit data is written to the UAnTX register in the transmission enabled status <R> (UAnCTL0.UAnTXE bit = 1). When the data of the UAnTX register has been transferred to the transmit shift register, the transmission enable interrupt request signal (INTUAnT) is generated. This register can be read or written in 8-bit units. Reset sets this register to FFH. After reset: FFH R/W Address: UA0TX FFFFFA07H, UA1TX FFFFFA17H, UA2TX FFFFFA27H 7 6 5 4 3 UAnTX (n = 0 to 2) 516 User's Manual U16541EJ5V1UD 2 1 0 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. * Reception completion interrupt request signal (INTUAnR) * Transmission enable interrupt request signal (INTUAnT) The default priority for these two interrupt request signals is reception completion interrupt request signal then transmission enable interrupt request signal. Table 15-2. Interrupts and Their Default Priorities Interrupt Priority Reception complete High Transmission enable Low (1) Reception completion interrupt request signal (INTUAnR) A reception completion interrupt request signal is output when data is shifted into the receive shift register and transferred to the UAnRX register in the reception enabled status. When a reception completion interrupt request signal is received and the data is read, read the UAnSTR register and check that the reception result is not an error. No reception completion interrupt request signal is generated in the reception disabled status. (2) Transmission enable interrupt request signal (INTUAnT) If transmit data is transferred from the UAnTX register to the UARTAn transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated. User's Manual U16541EJ5V1UD 517 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6 Operation 15.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-5, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UAnCTL0 register. Moreover, control of UART output/inverted output for the TXDAn bit is performed using the UAnOPT0.UAnTDL bit. * Start bit..................1 bit * Character bits ........7 bits/8 bits * Parity bit ................Even parity/odd parity/0 parity/no parity * Stop bit ..................1 bit/2 bits 518 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-5. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop bit bit (c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDAn inversion 1 data frame <R> Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop bit bit (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity Stop bit bit Stop bit (e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 User's Manual U16541EJ5V1UD D7 Stop bit 519 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.2 SBF transmission/reception format <R> The V850ES/SG2 and V850ES/SG2-H have an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 15-6 and 15-7 outline the transmission and reception manipulations of LIN. Figure 15-6. LIN Transmission Manipulation Outline Wake-up signal frame Sync break field Sync field Identifier field Note 2 13 bits 55H transmission DATA field DATA field Check SUM field Data transmission Data transmission Data transmission LIN bus Note 3 8 bits Note 1 Data transmission TXDAn (output) SBF transmissionNote 4 INTUAnT interrupt Notes 1. The interval between each field is controlled by software. 2. SBF output is performed by hardware. The output width is the bit length set by the UAnOPT0.UAnSBL2 to UAnOPT0.UAnSBL0 bits. If even finer output width adjustments are required, such adjustments can be performed using the UAnCTLn.UAnBRS7 to UAnCTLn.UAnBRS0 bits. 3. 80H transfer in the 8-bit mode is substituted for the wakeup signal frame. 4. A transmission enable interrupt request signal (INTUAnT) is output at the start of each transmission. The INTUAnT signal is also output at the start of each SBF transmission. 520 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-7. LIN Reception Manipulation Outline Wake-up signal frame Sync break field Sync field Identifier field DATA field Note 2 13 bits SF reception ID reception Data transmission DATA field Check SUM field LIN bus RXDAn (input) SBF reception Enable Disable Data Note 5 transmission Data transmission Note 3 Reception interrupt (INTUAnR) Note 1 Edge detection Note 4 Capture timer Disable Enable Notes 1. The wakeup signal is sent by the pin edge detector, UARTAn is enabled, and the SBF reception mode is set. 2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon detection of SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal is output, and the mode returns to the SBF reception mode. 3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF reception completion interrupt. Moreover, error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed and UART communication error detection processing and UARTAn receive shift register and data transfer of the UAnRX register are not performed. The UARTAn receive shift register holds the initial value, FFH. 4. The RXDAn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the baud rate error is calculated. The value of the UAnCTL2 register obtained by correcting the baud rate error after dropping UARTA enable is set again, causing the status to become the reception status. 5. Check-sum field distinctions are made by software. UARTAn is initialized following CSF reception, and the processing for setting the SBF reception mode again is performed by software. User's Manual U16541EJ5V1UD 521 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.3 SBF transmission When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSLS2 to UAnOPT0.UAnSLS0 bits is output. A transmission enable interrupt request signal (INTUAnT) is generated upon SBF transmission start. Following the end of SBF transmission, the UAnSTT bit is automatically cleared. Thereafter, the UART transmission mode is restored. Transmission is suspended until the data to be transmitted next is written to the UAnTX register, or until the SBF transmission trigger (UAnSTT bit) is set. Figure 15-8. SBF Transmission TXDAn 1 2 3 4 5 6 7 8 INTUAnT interrupt Setting of UAnSTT bit 522 User's Manual U16541EJ5V1UD 9 10 11 12 13 Stop bit CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.4 SBF reception The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start bit detection is performed. Following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception completion interrupt request signal (INTUAnR) is output. The UAnOPT0.UAnSRF bit is automatically cleared and SBF reception ends. Error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed and UART communication error detection processing is not performed. Moreover, data transfer of the UARTAn reception shift register and UAnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to. The UAnSRF bit is not cleared at this time. <R> Caution The LIN function does not assume that SBF is transmitted while data is being received. Consequently, if SBF is transmitted while data is being received, a framing error occurs (UAnSTR.UAnFE bit = 1). User's Manual U16541EJ5V1UD 523 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-9. SBF Reception (a) Normal SBF reception (detection of stop bit in more than 10.5 bits) RXDAn 1 2 3 4 5 6 7 8 9 10 11 11.5 UAnSRF INTUAnR interrupt (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) RXDAn 1 2 3 4 5 6 7 10.5 UAnSRF INTUAnR interrupt 524 User's Manual U16541EJ5V1UD 8 9 10 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.5 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register. The start bit, parity bit, and stop bit are automatically added. Since the CTS (transmit enable signal) input pin is not provided in UARTAn, use a port to check that reception is enabled at the transmit destination. The data in the UAnTX register is transferred to the UARTAn transmit shift register upon the start of the transmit operation. A transmission enable interrupt request signal (INTUAnT) is generated upon completion of transmission of the data of the UAnTX register to the UARTAn transmit shift register, and thereafter the contents of the UARTAn transmit shift register are output to the TXDAn pin. Write of the next transmit data to the UAnTX register is enabled after the INTUAnT signal is generated. Figure 15-10. UART Transmission TXDAn Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit INTUAnT Remark LSB first User's Manual U16541EJ5V1UD 525 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.6 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT). An efficient communication rate is realized by writing the data to be transmitted next to the UAnTX register during transfer. Caution When initializing transmissions during the execution of continuous transmissions, make sure that the UAnSTR.UAnTSF bit is 0, then perform the initialization. Transmit data that is initialized when the UAnTSF bit is 1 cannot be guaranteed. Figure 15-11. Continuous Transmission Processing Flow Start Register settings UAnTX write Occurrence of transmission interrupt? No Yes Required number of writes performed? No Yes End 526 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-12. Continuous Transmission Operation Timing (a) Transmission start Start TXDAn UAnTX Parity Stop Data (1) Transmission shift register <R> Data (1) Start Data (2) Parity Data (2) Stop Start Data (3) Data (2) Data (1) INTUAnT UAnTSF (b) Transmission end TXDAn UAnTX Transmission shift register <R> Parity Stop Start Data (n - 1) Parity Data (n - 1) Stop Start Data (n) Parity Stop Data (n) Data (n - 1) Data (n) FF INTUAnT UAnTSF UAnPWR or UAnTXE bit User's Manual U16541EJ5V1UD 527 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.7 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine. First the rising edge of the RXDAn pin is detected and sampling is started at the falling edge. The start bit is recognized if the RXDAn pin is low level at the start bit sampling point. After a start bit has been recognized, the receive operation starts, and serial data is saved to the UARTAn receive shift register according to the set baud rate. When the reception completion interrupt request signal (INTUAnR) is output upon reception of the stop bit, the data of the UARTAn receive shift register is written to the UAnRX register. However, if an overrun error occurs (UAnSTR.UAnOVE bit = 1), the receive data at this time is not written to the UAnRX register and is discarded. Even if a parity error (UAnSTR.UAnPE bit = 1) or a framing error (UAnSTR.UAnFE bit = 1) occurs during reception, reception continues until the reception position of the first stop bit, and INTUAnR is output following reception completion. Figure 15-13. UART Reception RXDAn Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit INTUAnR UAnRX Remark V: Sampling point of start bit Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. The operation during reception is performed assuming that there is only one stop bit. A second stop bit is ignored. 3. When reception is completed, read the UAnRX register after the reception completion interrupt request signal (INTUAnR) has been generated, and clear the UAnPWR or UAnRXE bit to 0. If the UAnPWR or UAnRXE bit is cleared to 0 before the INTUAnR signal is generated, the read value of the UAnRX register cannot be guaranteed. 4. If receive completion processing (INTUAnR signal generation) of UARTAn and the UAnPWR bit = 0 or UAnRXE bit = 0 conflict, the INTUAnR signal may be generated in spite of these being no data stored in the UAnRX register. To complete reception without waiting INTUAnR signal generation, be sure to clear (0) the interrupt request flag (UAnRIF) of the UAnRIC register, after setting (1) the interrupt mask flag (UAnRMK) of the interrupt control register (UAnRIC) and then set (1) the UAnPWR bit = 0 or UAnRXE bit = 0. 528 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception completion interrupt request signal (INTUAnR) is output when an error occurs. It is possible to ascertain which error occurred during reception by reading the contents of the UAnSTR register. Clear the reception error flag by writing 0 to it after reading it. * Receive data read flow START INTUAnR signal generated? No Yes Read UAnRX register Read UAnSTR register No Error occurs? Yes Error processing END Caution When an INTUAnR signal is generated, the UAnSTR register must be read to check for errors. * Reception error causes Error Flag Reception Error Cause UAnPE Parity error Received parity bit does not match the setting UAnFE Framing error Stop bit not detected UAnOVE Overrun error Reception of next data completed before data was read from UAnRX register User's Manual U16541EJ5V1UD 529 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) When reception errors occur, perform the following procedures depending upon the kind of error. * Parity error If false data is received due to problems such as noise in the reception line, discard the received data and retransmit. * Framing error A baud rate error may have occurred between the reception side and transmission side or the start bit may have been erroneously detected. Since this is a fatal error for the communication format, check the operation stop in the transmission side, perform initialization processing each other, and then start the communication again. * Overrun error Since the next reception is completed before reading receive data, 1 frame of data is discarded. If this data was needed, do a retransmission. Caution If a receive error interrupt occurs during continuous reception, read the contents of the UAnSTR register must be read before the next reception is completed, then perform error processing. 530 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.9 Parity types and operations Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity bit is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no parity, errors cannot be detected. (a) Even parity (i) During transmission The number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so as to be an even number. The parity bit values are as follows. * Odd number of bits whose value is "1" among transmit data: 1 * Even number of bits whose value is "1" among transmit data: 0 (ii) During reception The number of bits whose value is "1" among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (b) Odd parity (i) During transmission Opposite to even parity, the number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so that it is an odd number. The parity bit values are as follows. * Odd number of bits whose value is "1" among transmit data: 0 * Even number of bits whose value is "1" among transmit data: 1 (ii) During reception The number of bits whose value is "1" among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity During transmission, the parity bit is always made 0, regardless of the transmit data. During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the parity bit is 0 or 1. (d) No parity No parity bit is added to the transmit data. Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit. User's Manual U16541EJ5V1UD 531 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.10 Receive data noise filter This filter samples the RXDAn pin using the base clock (fUCLK) of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 15-15). See 15.7 (1) (a) Base clock regarding the base clock. Moreover, since the circuit is as shown in Figure 15-14, the processing that goes on within the receive operation is delayed by 3 clocks in relation to the external signal status. Figure 15-14. Noise Filter Circuit Base clock (fUCLK) RXDAn In Q Internal signal A In Q Internal signal B In Match detector Q Internal signal C LD_EN Figure 15-15. Timing of RXDAn Signal Judged as Noise Base clock (fUCLK) RXDAn (input) Internal signal A Internal signal B Match Mismatch (judged as noise) Internal signal C 532 User's Manual U16541EJ5V1UD Match Mismatch (judged as noise) CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. There is an 8-bit counter for transmission and another one for reception. (1) Baud rate generator configuration Figure 15-16. Configuration of Baud Rate Generator UAnPWR fXX fXX/2 fXX/4 fXX/8 UAnPWR, UAnTXEn bus (or UAnRXE bit) fXX/16 fXX/32 fXX/64 Selector 8-bit counter fUCLK fXX/128 fXX/256 fXX/512 Output clock fXX/1024 Match detector ASCKA0Note UAnCTL1: UAnCKS3 to UAnCKS0 Baud rate 1/2 UAnCTL2: UAnBRS7 to UAnBRS0 Note Only UARTA0 is valid; setting UARTA1 and UARTA2 is prohibited. <R> Caution UARTAn cannot be used if the CPU clock (fCPU) is slower than fUCLK. Remarks 1. n = 0 to 2 2. fXX: Main clock frequency fUCLK: Base clock frequency (a) Base clock When the UAnCTL0.UAnPWR bit is 1, the clock selected by <R> the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (fUCLK). The base clock fUCLK is fixed to the low level when the UAnPWR bit is 0. (b) Serial clock generation A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register (n = 0 to 2). The base clock (fUCLK) is selected by UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits. The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits. User's Manual U16541EJ5V1UD 533 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register. After reset: 00H R/W Address: UA0CTL1 FFFFFA01H, UA1CTL1 FFFFFA11H, UA2CTL1 FFFFFA21H UAnCTL1 7 6 5 4 0 0 0 0 3 2 1 (n = 0 to 2) UAnCKS3 UAnCKS2 UAnCKS1UAnCKS0 Base clock (fUCLK) selection 0 0 0 0 fXX 0 0 0 1 fXX/2 0 0 1 0 fXX/4 0 0 1 1 fXX/8 0 1 0 0 fXX/16 0 1 0 1 fXX/32 0 1 1 0 fXX/64 0 1 1 1 fXX/128 1 0 0 0 fXX/256 1 0 0 1 fXX/512 1 0 1 0 fXX/1,024 1 0 1 1 External clockNote (ASCKA0 pin) Other than above Setting prohibited Note Only UARTA0 is valid; setting UARTA1 and UARTA2 is prohibited. Remark 534 0 UAnCKS3 UAnCKS2 UAnCKS1 UAnCKS0 fXX: Main clock frequency User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset sets this register to FFH. Caution Clear the UAnCTL0.UAnPWR bit to 0 or clear the UAnTXE and UAnRXE bits to 00 before rewriting the UAnCTL2 register. After reset FFH R/W Address: UA0CTL2 FFFFFA02H, UA1CTL2 FFFFFA12H, UA2CTL2 FFFFFA22H 6 7 UAnCTL2 5 4 3 2 1 0 UAnBRS7 UAnBRS6 UAnBRS5 UAnBRS4 UAnBRS3 UAnBRS2 UAnBRS1 UAnBRS0 (n = 0 to 2) Remark UAn BRS7 UAn BRS6 UAn BRS5 UAn BRS4 UAn BRS3 UAn BRS2 UAn BRS1 UAn Default BRS0 (k) Serial clock 0 0 0 0 0 0 x x x Setting prohibited 0 0 0 0 0 1 0 0 4 fUCLK/4 0 0 0 0 0 1 0 1 5 fUCLK/5 0 0 0 0 0 1 1 0 6 fUCLK/6 : : : : : : : : : : 1 1 1 1 1 1 0 0 252 fUCLK/252 1 1 1 1 1 1 0 1 253 fUCLK/253 1 1 1 1 1 1 1 0 254 fUCLK/254 1 1 1 1 1 1 1 1 255 fUCLK/255 fUCLK: Frequency of base clock frequency selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits User's Manual U16541EJ5V1UD 535 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. Baud rate = fUCLK 2xk [bps] When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at UARTA0, calculate using the above equation). Baud rate = fXX m+1 2 Remark xk [bps] fUCLK = Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits fXX: Main clock frequency m = Value set using the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits (m = 0 to 10) k = Value set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (k = 4 to 255) The baud rate error is obtained by the following equation. Error (%) = = Actual baud rate (baud rate with error) Target baud rate (correct baud rate) fUCLK 2 x k x Target baud rate - 1 x 100 [%] - 1 x 100 [%] When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at UARTA0, calculate the baud rate error using the above equation). fXX Error (%) = 2m+1 x k x Target baud rate - 1 x 100 [%] Cautions 1. The baud rate error during transmission must be within the error tolerance on the receiving side. 2. The baud rate error during reception must satisfy the range indicated in (5) Allowable baud rate range during reception. 536 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) To set the baud rate, perform the following calculation and set the UAnCTL1 and UAnCTL2 registers (when using internal clock). <1> Set k = fXX/(2 x Target baud rate). Set m = 0. <2> Set k = k/2 and m = m + 1 where k 256. <3> Repeat <2> until k < 256. <4> Roundup the first decimal place of k. If k = 256 by the roundup, perform <2> again (k will become 128). <5> Set m to the UAnCTL1 register and k to the UAnCTL2 register. Example: When fXX = 20 MHz and target baud rate = 153,600 bps <1> k = 20,000,000/(2 x 153,600) = 65.10..., m = 0 <2>, <3> k = 65.10... < 256, m = 0 <4> Set value of UAnCTL2 register: k = 65 = 41H, set value of UAnCTL1 register: m = 0 Actual baud rate = 20,000,000/(2 x 104) = 153,846 [bps] Baud rate error = {20,000,000/(2 x 65 x 153,600) - 1} x 100 = 0.160 [%] The representative examples of baud rate settings are shown below. <R> Table 15-3. Baud Rate Generator Setting Data (1/2) Baud Rate (bps) fXX = 32 MHz Note fXX = 20 MHz fXX = 18.874 MHz UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) 300 08H D0H 0.16 08H 82H 0.16 07H F6H -0.10 600 07H D0H 0.16 07H 82H 0.16 06H F6H -0.10 1,200 06H D0H 0.16 06H 82H 0.16 05H F6H -0.10 2,400 05H D0H 0.16 05H 82H 0.16 04H F6H -0.10 4,800 04H D0H 0.16 04H 82H 0.16 03H F6H -0.10 9,600 03H D0H 0.16 03H 82H 0.16 02H F6H -0.10 19,200 02H D0H 0.16 02H 82H 0.16 01H F6H -0.10 31,250 02H 80H 0.00 01H A0H 0.00 01H 97H -0.01 38,400 01H D0H 0.16 01H 82H 0.16 00H F6H -0.10 76,800 00H D0H 0.16 00H 82H 0.16 00H 7BH -0.10 153,600 00H 68H 0.16 00H 41H 0.16 00H 3DH 0.72 312,500 00H 33H 0.39 00H 20H 0.00 00H 1EH 0.66 Note V850ES/SG2-H only Remark fXX: Main clock frequency ERR: Baud rate error (%) User's Manual U16541EJ5V1UD 537 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Table 15-3. Baud Rate Generator Setting Data (2/2) Baud Rate fXX = 16 MHz (bps) fXX = 10 MHz UAnCTL1 UAnCTL2 ERR (%) UAnCTL1 UAnCTL2 ERR (%) 300 07H D0H 0.16 07H 82H 0.16 600 06H D0H 0.16 06H 82H 0.16 1,200 05H D0H 0.16 05H 82H 0.16 2,400 04H D0H 0.16 04H 82H 0.16 4,800 03H D0H 0.16 03H 82H 0.16 9,600 02H D0H 0.16 02H 82H 0.16 19,200 01H D0H 0.16 01H 82H 0.16 31,250 01H 80H 0.00 00H A0H 0.00 38,400 00H D0H 0.16 00H 82H 0.16 76,800 00H 68H 0.16 00H 41H 0.16 153,600 00H 34H 0.16 00H 21H -1.36 312,500 00H 1AH -1.54 00H 10H 0.00 Remark fXX: Main clock frequency ERR: Baud rate error (%) (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation. Figure 15-17. Allowable Baud Rate Range During Reception Latch timing UARTAn transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Minimum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 FLmax Remark 538 n = 0 to 2 User's Manual U16541EJ5V1UD Parity bit Stop bit CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) As shown in Figure 15-17, the receive data latch timing is determined by the counter set using the UAnCTL2 register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. When this is applied to 11-bit reception, the following is the theoretical result. FL = (Brate)-1 Brate: UARTAn baud rate (n = 0 to 2) k: Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 2) FL: 1-bit data length Latch timing margin: 2 clocks Minimum allowable transfer rate: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 FL 2k Therefore, the maximum baud rate that can be received by the destination is as follows. BRmax = (FLmin/11)-1 = 22k Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 10 k+2 x FLmax = 11 x FL - 2xk 11 FLmax = 21k - 2 x FL = 21k - 2 2xk FL FL x 11 20 k Therefore, the minimum baud rate that can be received by the destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate Obtaining the allowable baud rate error for UARTAn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. User's Manual U16541EJ5V1UD 539 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Table 15-4. Maximum/Minimum Allowable Baud Rate Error Division Ratio (k) Maximum Allowable Baud Rate Error Minimum Allowable Baud Rate Error 4 +2.32% -2.43% 8 +3.52% -3.61% 20 +4.26% -4.30% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.72% Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). The higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 2) (6) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result. Figure 15-18. Transfer Rate During Continuous Transfer Start bit of 2nd byte 1 data frame Start bit FL Bit 0 Bit 1 Bit 7 FL FL FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Assuming 1 bit data length: FL; stop bit length: FLstp; and base clock frequency: fUCLK, we obtain the following equation. FLstp = FL + 2/fUCLK Therefore, the transfer rate during continuous transmission is as follows. Transfer rate = 11 x FL + (2/fUCLK) 540 User's Manual U16541EJ5V1UD CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.8 Cautions (1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped. However, the operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply is resumed, the circuits should be initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXEn, and UAnCTL0.UAnTXEn bits to 000. (2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin. To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear PFCE91 bit to 0). (3) In UARTAn, the interrupt caused by a communication error does not occur. When performing the transfer of transmit data and receive data using DMA transfer, error processing cannot be performed even if errors (parity, overrun, framing) occur during transfer. Either read the UAnSTR register after DMA transfer has been completed to make sure that there are no errors, or read the UAnSTR register during communication to check for errors. (4) Start up the UARTAn in the following sequence. <1> Set the UAnCTL0.UAnPWR bit to 1. <2> Set the ports. <3> Set the UAnCTL0.UAnTXE bit to 1, UAnCTL0.UAnRXE bit to 1. (5) Stop the UARTAn in the following sequence. <1> Set the UAnCTL0.UAnTXE bit to 0, UAnCTL0.UAnRXE bit to 0. <2> Set the ports and set the UAnCTL0.UAnPWR bit to 0 (it is not a problem if port setting is not changed). (6) In transmit mode (UAnCTL0.UAnPWR bit = 1 and UAnCTL0.UAnTXE bit = 1), do not overwrite the same value to the UAnTX register by software because transmission starts by writing to this register. To transmit the same value continuously, overwrite the same value. (7) In continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base clocks more than usual. However, the reception side initializes the timing by detecting the start bit, so the reception result is not affected. User's Manual U16541EJ5V1UD 541 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.1 Mode Switching of CSIB and Other Serial Interfaces 16.1.1 CSIB4 and UARTA0 mode switching <R> In the V850ES/SG2 and V850ES/SG2-H, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously. Set CSIB4 in advance, using the PMC3 and PFC3 registers, before use. Caution The transmit/receive operation of CSIB4 and UARTA0 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 16-1. CSIB4 and UARTA0 Mode Switch Settings After reset: 0000H PMC3 14 13 12 11 10 9 8 0 0 0 0 0 0 PMC39 PMC38 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 R/W Address: FFFFF466H, FFFFF467H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PFC39 PFC38 PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 0 PFCE32 0 0 After reset: 00H PFCE3L Address: FFFFF446H, FFFFF447H 15 After reset: 0000H PFC3 R/W R/W Address: FFFFF706H 0 0 0 0 PMC32 PFCE32 PFC32 0 x x Port I/O mode 1 0 0 ASCKA0 mode 1 0 1 SCKB4 mode PMC3n PFC3n 0 x Port I/O mode 1 0 UARTA0 mode 1 1 CSIB4 mode Operation mode Operation mode Remarks 1. n = 0, 1 2. x = don't care 542 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.1.2 CSIB0 and I2C01 mode switching <R> In the I2C bus versions (Y products) of the V850ES/SG2 and V850ES/SG2-H, CSIB0 and I2C01 are alternate functions of the same pin and therefore cannot be used simultaneously. Set CSIB0 in advance, using the PMC4 and PFC4 registers, before use. Caution The transmit/receive operation of CSIB0 and I2C01 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 16-2. CSIB0 and I2C01 Mode Switch Settings After reset: 00H PMC4 0 After reset: 00H PFC4 R/W 0 R/W Address: FFFFF448H 0 0 0 PMC42 PMC41 PMC40 0 0 PFC41 PFC40 Address: FFFFF468H 0 0 0 PMC4n PFC4n 0 x Port I/O mode 1 0 CSIB0 mode 1 1 I2C01 mode 0 Operation mode Remarks 1. n = 0, 1 2. x = don't care User's Manual U16541EJ5V1UD 543 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.2 Features <R> { Transfer rate: 8 Mbps MAX. (V850ES/SG2: fXX = 20 MHz, V850ES/SG2-H: fXX = 32 MHz, using internal clock) { Master mode and slave mode selectable { 8-bit to 16-bit transfer, 3-wire serial interface { Interrupt request signals (INTCBnT, INTCBnR) { Serial clock and data phase switchable { Transfer data length selectable in 1-bit units between 8 and 16 bits { Transfer data MSB-first/LSB-first switchable { 3-wire transfer SOBn: SIBn: Serial data output Serial data input SCKBn: Serial clock output Transmission mode, reception mode, and transmission/reception mode specifiable Remark 544 n = 0 to 4 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.3 Configuration The following shows the block diagram of CSIBn. Figure 16-3. Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 Selector Controller fCCLK INTCBnR Phase control fBRGm CBnTX SCKBn SO latch SIBn Shift register Phase control SOBn CBnRX Remark fCCLK: Communication clock fXX: Main clock frequency fBRGm: BRGm count clock n = 0 to 4 m = 1 (n = 0, 1) m = 2 (n = 2, 3) m = 3 (n = 4) CSIBn includes the following hardware. Table 16-1. Configuration of CSIBn Item Registers Configuration CSIBn receive data register (CBnRX) CSIBn transmit data register (CBnTX) Control registers CSIBn control register 0 (CBnCTL0) CSIBn control register 1 (CBnCTL1) CSIBn control register 2 (CBnCTL2) CSIBn status register (CBnSTR) User's Manual U16541EJ5V1UD 545 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register. Reset sets this register to 0000H. In addition to reset input, the CBnRX register can be initialized by clearing (to 0) the CBnPWR bit of the CBnCTL0 register. After reset: 0000H R Address: CB0RX FFFFFD04H, CB1RX FFFFFD14H, CB2RX FFFFFD24H, CB3RX FFFFFD34H, CB4RX FFFFFD44H CBnRX (n = 0 to 4) (2) CSIBn transmit data register (CBnTX) The CBnTX register is a 16-bit buffer register used to write the CSIBn transfer data. This register can be read or written in 16-bit units. The transmit operation is started by writing data to the CBnTX register in the transmission enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnTXL register. Reset sets this register to 0000H. After reset 0000H R/W Address: CB0TX FFFFFD06H, CB1TX FFFFFD16H, CB2TX FFFFFD26H, CB3TX FFFFFD36H, CB4TX FFFFFD46H CBnTX (n = 0 to 4) Remark The communication start conditions are shown below. Transmission mode (CBnTXE bit = 1, CBnRXE bit = 0): Write to CBnTX register Transmission/reception mode (CBnTXE bit = 1, CBnRXE bit = 1): Write to CBnTX register Reception mode (CBnTXE bit = 0, CBnRXE bit = 1): 546 User's Manual U16541EJ5V1UD Read from CBnRX register CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.4 Registers The following registers are used to control CSIBn. * CSIBn control register 0 (CBnCTL0) * CSIBn control register 1 (CBnCTL1) * CSIBn control register 2 (CBnCTL2) * CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) CBnCTL0 is a register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. (1/3) After reset: 01H R/W Address: CB0CTL0 FFFFFD00H, CB1CTL0 FFFFFD10H, CB2CTL0 FFFFFD20H, CB3CTL0 FFFFFD30H, CB4CTL0 FFFFFD40H < > CBnCTL0 < > < > Note CBnPWR CBnTXE < > < > Note CBnRXE Note CBnDIR 0 0 Note CBnTMS CBnSCE (n = 0 to 4) CBnPWR Specification of CSIBn operation disable/enable 0 Disable CSIBn operation and reset the CBnSTR register 1 Enable CSIBn operation * The CBnPWR bit controls the CSIBn operation and resets the internal circuit. CBnTXENote Specification of transmit operation disable/enable 0 Disable transmit operation 1 Enable transmit operation * The SOBn output is low level when the CBnTXE bit is 0. CBnRXENote Specification of receive operation disable/enable 0 Disable receive operation 1 Enable receive operation * When the CBnRXE bit is cleared to 0, no reception completion interrupt is output even when the prescribed data is transferred in order to disable the receive operation, and the receive data (CBnRX register) is not updated. Note These bits can only be rewritten when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be set at the same time as rewriting these bits. Cautions 1. To forcibly suspend transmission/reception, clear the CBnPWR bit instead of the CBnTXE and CBnRxE bits to 0. At this time, the clock output is stopped. <R> 2. Be sure to set bits 3 and 2 to "0". User's Manual U16541EJ5V1UD 547 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/3) CBnDIRNote Specification of transfer direction mode (MSB/LSB) 0 MSB-first transfer 1 LSB-first transfer CBnTMSNote Transfer mode specification 0 Single transfer mode 1 Continuous transfer mode [In single transfer mode] The reception completion interrupt (INTCBnR) occurs when communication is complete. Even if transmission is enabled (CBnTXE bit = 1), the transmission enable interrupt (INTCBnT) does not occur. If the next transmit data is written during communication (CBnSTR.CBnTSF bit = 1), it is ignored and the next communication is not started. Also, if receive-only communication is set (CBnTXE bit = 0, CBnRXE bit = 1), the next communication is not started even if the receive data is read during communication (CBnSTR. CBnTSF bit = 1). [In continuous transfer mode] The continuous transmission is enabled by writing the next transmit data during communication (CBnSTR.CBnTSF bit = 1). Writing the next transmission data is enabled after a transmission enable interrupt (INTCBnT) occurrence. If receive-only communication is set (CBnTXE bit = 0, CBnRXE bit = 1) in the continuous transfer mode, the next reception is started continuously after a reception completion interrupt (INTCBnR) regardless of the read operation of the CBnRX register. Therefore, read immediately the receive data from the CBnRX register. If this read operation is delayed, an overrun error (CBnOVE bit = 1) occurs. Note These bits can only be rewritten when the CBnPWR bit = 0. However, the CBnPWR can be set to 1 at the same time as these bits are rewritten. 548 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3/3) CBnSCE <R> Specification of start transfer disable/enable 0 Communication start trigger invalid 1 Communication start trigger valid * In master mode This bit enables or disables the communication start trigger. (a) In single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode The setting of the CBnSCE bit has no influence on communication operation. (b) In single reception mode Clear the CBnSCE bit to 0 before reading the last receive data because reception is started by reading the receive data (CBnRX register) to disable the reception startupNote 1. (c) In continuous reception mode Clear the CBnSCE bit to 0 one communication clock before reception of the last data is completed to disable the reception startup after the last data is receivedNote 2. * In slave mode This bit enables or disables the communication start trigger. Set the CBnSCE bit to 1.Note 3 Notes 1. If the CBnSCE bit is read while it is 1, the next communication operation is started. 2. The CBnSCE bit is not cleared to 0 one communication clock before the completion of the last data reception, the next communication operation is automatically started. <R> To start the communication operation again after the last data has been read, set the CBnSCE bit to "1" and dummy-read the CBnRX register. <R> 3. To start the reception, dummy reading is necessary. User's Manual U16541EJ5V1UD 549 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> (a) How to use CBnSCE bit (i) In single reception mode <1> When the reception of the last data is completed with INTCBnR interrupt servicing, clear the CBnSCE bit to 0, and then read the CBnRX register. <2> When the reception is disabled after the reception of the last data has been completed, check that the CBnSTR.CBnTSF bit is 0, and then clear the CBnPWR and CBnRXE bits to 0. To continue reception, set the CBnSCE bit to 1 and start the next receive operation by performing a dummy read of the CBnRX register. (ii) In continuous reception mode <1> Clear the CBnSCE bit to 0 during reception of the last data with INTCBnR interrupt servicing by the reception before the last reception, and then read the CBnRX register. <2> After receiving the INTCBnR signal of the last reception, read the last data from the CBnRX register. <3> When the reception is disabled after the reception of the last data has been completed, check that the CBnSTR.CBnTSF bit is 0, and then clear the CBnPWR and CBnRXE bits to 0. To continue reception, set the CBnSCE bit to 1 and start the next receive operation by performing a dummy read of the CBnRX register. Caution In continuous reception mode, the serial clock is not stopped until the reception executed when the CBnSCE bit is cleared to 0 is completed after the reception is started by a dummy read. 550 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) CSIBn control register 1 (CBnCTL1) CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0. After reset 00H R/W Address: CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD11H, CB2CTL1 FFFFFD21H, CB3CTL1 FFFFFD31H, CB4CTL1 FFFFFD41H CBnCTL1 0 0 0 CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0 (n = 0 to 4) Specification of data transmission/ reception timing in relation to SCKBn CBnCKP CBnDAP 0 Communication type 1 0 SCKBn (I/O) D7 SOBn (output) D6 D5 D4 D3 D2 D1 D0 SIBn capture 0 Communication type 2 1 SCKBn (I/O) SOBn (output) D7 D6 D5 D4 D3 D2 D1 D0 SIBn capture 1 Communication type 3 0 SCKBn (I/O) D7 (output) D6 D5 D4 D3 D2 D1 D0 SIBn capture 1 Communication type 4 1 SCKBn (I/O) (output) D7 D6 D5 D4 D3 D2 D1 D0 SIBn capture CBnCKS2 CBnCKS1 CBnCKS0 Communication clock (fCCLK)Note <R> <R> Mode 0 0 0 fXX/2 Master mode 0 0 1 fXX/4 Master mode 0 1 0 fXX/8 Master mode 0 1 1 fXX/16 Master mode 1 0 0 fXX/32 Master mode 1 0 1 fXX/64 Master mode 1 1 0 fBRGm Master mode 1 1 1 External clock (SCKBn) Slave mode Note Set the communication clock (fCCLK) to 8 MHz or lower. Remark When n = 0, 1, m = 1 When n = 2, 3, m = 2 When n = 4, m = 3 For details of fBRGm, see 16.8 Baud Rate Generator. User's Manual U16541EJ5V1UD 551 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when both the CBnTXE and CBnRXE bits = 0. After reset: 00H R/W Address: CB0CTL2 FFFFFD02H, CB1CTL2 FFFFFD12H, CB2CTL2 FFFFFD22H, CB3CTL2 FFFFFD32H, CB4CTL2 FFFFFD42H CBnCTL2 0 0 0 0 CBnCL3 CBnCL2 CBnCL1 CBnCL0 (n = 0 to 4) CBnCL3 CBnCL2 CBnCL1 CBnCL0 Serial register bit length 0 0 0 0 8 bits 0 0 0 1 9 bits 0 0 1 0 10 bits 0 0 1 1 11 bits 0 1 0 0 12 bits 0 1 0 1 13 bits 0 1 1 0 14 bits 0 1 1 1 15 bits 1 x x x 16 bits Remarks 1. If the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the LSB of the CBnTX and CBnRX registers. 2. x: don't care 552 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB. Any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. (i) Transfer bit length = 10 bits, MSB first SOBn SIBn 15 10 9 0 Insertion of 0 (ii) Transfer bit length = 12 bits, LSB first SIBn 15 12 SOBn 11 0 Insertion of 0 User's Manual U16541EJ5V1UD 553 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only. Reset sets this register to 00H. In addition to reset input, the CBnSTR register can be initialized by clearing (0) the CBnCTL0.CBnPWR bit. After reset 00H R/W Address: CB0STR FFFFFD03H, CB1STR FFFFFD13H, CB2STR FFFFFD23H, CB3STR FFFFFD33H, CB4STR FFFFFD43H < > < > CBnSTR CBnTSF 0 0 0 0 0 0 CBnOVE (n = 0 to 4) CBnTSF Communication status flag 0 Communication stopped 1 Communicating * During transmission, this register is set when data is prepared in the CBnTX register, and during reception, it is set when a dummy read of the CBnRX register is performed. When transfer ends, this flag is cleared to 0 at the last edge of the clock. CBnOVE Overrun error flag 0 No overrun 1 Overrun * An overrun error occurs when the next reception starts without reading the value of the CBnRX register by CPU, upon completion of the receive operation. The CBnOVE flag displays the overrun error occurrence status in this case. * The CBnOVE bit is valid also in the single transfer mode. Therefore, when only using transmission, note the following. * Do not check the CBnOVE flag. (recommended) * Read this bit even if reading the reception data is not required. * The CBnOVE flag is cleared by writing 0 to it. It cannot be set even by writing 1 to it. <R> Caution In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1 is ignored. This has no influence on the operation during transfer. For example, if the next data is written to the CBnTX register when DMA is started by generating the INTCBnR signal, the written data is not transferred because the CBnTSF bit is set to 1. Use the continuous transfer mode, not the single transfer mode, for such applications. 554 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.5 Interrupt Request Signals CSIBn can generate the following two types of interrupt request signals. * Reception completion interrupt request signal (INTCBnR) * Transmission enable interrupt request signal (INTCBnT) Of these two interrupt request signals, the reception completion interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. Table 16-2. Interrupts and Their Default Priority Interrupt Priority Reception complete High Transmission enable Low (1) Reception completion interrupt request signal (INTCBnR) When receive data is transferred to the CBnRX register while reception is enabled, the reception completion interrupt request signal is generated. This interrupt request signal can also be generated if an overrun error occurs. When the reception completion interrupt request signal is acknowledged and the data is read, read the CBnSTR register to check that the result of reception is not an error. In the single transfer mode, the INTCBnR interrupt request signal is generated upon completion of transmission, even when only transmission is executed. (2) Transmission enable interrupt request signal (INTCBnT) In the continuous transmission or continuous transmission/reception mode, transmit data is transferred from the CBnTX register and, as soon as writing to CBnTX has been enabled, the transmission enable interrupt request signal is generated. In the single transmission and single transmission/reception modes, the INTCBnT interrupt is not generated. User's Manual U16541EJ5V1UD 555 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6 Operation <R> 16.6.1 Single transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CBnCTL1 register 00H CBnCTL2 register 00H CBnCTL0 register C1H (4) Write CBnTX register (5) Start transmission (6) INTCBnR interrupt generated? No Yes Transmission completed? No (7) Yes (8) CBnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 556 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 (1) (2) (3) (4) Bit 6 Bit 5 (5) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (7) Bit 2 Bit 1 Bit 0 (8) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write C1H to the CBnCTL0 register, and select the transmission mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and transmission is started. (5) When transmission is started, output the serial clock to the SCKBn pin, and output the transmit data from the SOBn pin in synchronization with the serial clock. (6) When transmission of the transfer data length set with the CBnCTL2 register is completed, stop the serial clock output and transmit data output, generate the reception completion interrupt request signal (INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0. (7) To continue transmission, start the next transmission by writing the transmit data to the CBnTX register again after the INTCBnR signal is generated. (8) To end transmission, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnTXE bit = 0. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 557 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CBnCTL1 register 00H CBnCTL2 register 00H CBnCTL0 register A1H (4) CBnRX register dummy read (5) Start reception (6) INTCBnR interrupt generated? No Yes Reception completed? Yes (8) CBnSCE bit = 0 (CBnCTL0) (9) Read CBnRX register (10) CBnCTL0 register 00H No (7) Read CBnRX register END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 558 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write A1H to the CBnCTL0 register, and select the reception mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and reception is started. (5) When reception is started, output the serial clock to the SCKBn pin, and capture the receive data of the SIBn pin in synchronization with the serial clock. (6) When reception of the transfer data length set with the CBnCTL2 register is completed, stop the serial clock output and data capturing, generate the reception completion interrupt request signal (INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0. (7) To continue reception, read the CBnRX register with the CBnCTL0.CBnSCE bit = 1 remained after the INTCBnR signal is generated. (8) To read the CBnRX register without starting the next reception, write the CBnSCE bit = 0. (9) Read the CBnRX register. (10) To end reception, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnRXE bit = 0. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 559 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) (4) CBnCTL1 register 07H CBnCTL2 register 00H CBnCTL0 register E1H Write CBnTX register Yes (5) Start transmission/reception (6) INTCBnR interrupt generated? No Yes (7), (9) Read CBnRX register Transmission/reception completed? No (8) Yes (10) CBnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 560 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9)(10) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write E1H to the CBnCTL0 register, and select the transmission/reception mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and transmission/reception is started. (5) When transmission/reception is started, output the serial clock to the SCKBn pin, output the transmit data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn pin. (6) When transmission/reception of the transfer data length set with the CBnCTL2 register is completed, stop the serial clock output, transmit data output, and data capturing, generate the reception completion interrupt request signal (INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0. (7) Read the CBnRX register. (8) To continue transmission/reception, write the transmit data to the CBnTX register again. (9) Read the CBnRX register. (10) To end transmission/reception, write the CBnCTL0.CBnPWR bit = 0, the CBnCTL0.CBnTXE bit = 0, and the CBnCTL0.CBnRXE bit = 0. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 561 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.4 Single transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CBnCTL1 register 07H CBnCTL2 register 00H CBnCTL0 register C1H (4) Write CBnTX register (4) SCKBn pin input started? No Yes (5) Start transmission (6) INTCBnR interrupt generated? No Yes Transmission completed? No (7) Yes (8) CBnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 562 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 (1) (2) (3) (4) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (5) Bit 0 (6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (7) Bit 2 Bit 1 Bit 0 (8) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write C1H to the CBnCTL0 register, and select the transmission mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device waits for a serial clock input. (5) When a serial clock is input, output the transmit data from the SOBn pin in synchronization with the serial clock. (6) When transmission of the transfer data length set with the CBnCTL2 register is completed, stop the serial clock input and transmit data output, generate the reception completion interrupt request signal (INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0. (7) To continue transmission, write the transmit data to the CBnTX register again after the INTCBnR signal is generated, and wait for a serial clock input. (8) To end transmission, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnTXE bit = 0. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 563 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.5 Single transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CBnCTL1 register 07H CBnCTL2 register 00H CBnCTL0 register A1H (4) CBnRX register dummy read (4) SCKBn pin input started? No Yes (5) Start reception (6) INTCBnR interrupt generated? No Yes (6) Reception completed? Yes (8) CBnSCE bit = 0 (CBnCTL0) (9) Read CBnRX register (10) CBnCTL0 register 00H No (7) Read CBnRX register END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 564 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write A1H to the CBnCTL0 register, and select the reception mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and the device waits for a serial clock input. (5) When a serial clock is input, capture the receive data of the SIBn pin in synchronization with the serial clock. (6) When reception of the transfer data length set with the CBnCTL2 register is completed, stop the serial clock input and data capturing, generate the reception completion interrupt request signal (INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0. (7) To continue reception, read the CBnRX register with the CBnCTL0.CBnSCE bit = 1 remained after the INTCBnR signal is generated, and wait for a serial clock input. (8) To end reception, write the CBnSCE bit = 0. (9) Read the CBnRX register. (10) To end reception, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnRXE bit = 0. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 565 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CBnCTL1 register 07H CBnCTL2 register 00H CBnCTL0 register E1H (4) Write CBnTX register (4) SCKBn pin input started? No Yes (5) Start transmission/reception (6) INTCBnR interrupt generated? No Yes (7), (9) Read CBnRX register Transmission/reception completed? No (8) Yes (10) CBnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 566 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (2) (3) (4) (5) (6) (7) (8) (9)(10) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write E1H to the CBnCTL0 register, and select the transmission/reception mode and MSB first at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device waits for a serial clock input. (5) When a serial clock is input, output the transmit data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn pin. (6) When transmission/reception of the transfer data length set with the CBnCTL2 register is completed, stop the serial clock input, transmit data output, and data capturing, generate the reception completion interrupt request signal (INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0. (7) Read the CBnRX register. (8) To continue transmission/reception, write the transmit data to the CBnTX register again, and wait for a serial clock input. (9) Read the CBnRX register. (10) To end transmission/reception, write the CBnCTL0.CBnPWR bit = 0, the CBnCTL0.CBnTXE bit = 0, and the CBnCTL0.CBnRXE bit = 0. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 567 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.7 Continuous transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) (4), (8) CBnCTL1 register 00H CBnCTL2 register 00H CBnCTL0 register C3H Write CBnTX register (5) Start transmission (6), (9) INTCBnT interrupt generated? No Yes Transmission completed? No (7) Yes (10) CBnTSF bit = 0? (CBnSTR register) No Yes (11) CBnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 568 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal INTCBnR signal L SCKBn pin SOBn pin Bit 7 (1) (2) (3) (4) (5) Bit 6 Bit 5 (6) Bit 4 Bit 3 Bit 2 (7) Bit 1 Bit 0 Bit 7 (8) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (9) (10) (11) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write C3H to the CBnCTL0 register, and select the transmission mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and transmission is started. (5) When transmission is started, output the serial clock to the SCKBn pin, and output the transmit data from the SOBn pin in synchronization with the serial clock. (6) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is generated. (7) To continue transmission, write the transmit data to the CBnTX register again after the INTCBnT signal is generated. (8) When a new transmit data is written to the CBnTX register before communication completion, the next communication is started following communication completion. (9) The transfer of the transmit data from the CBnTX register to the shift register is completed and the INTCBnT signal is generated. To end continuous transmission with the current transmission, do not write to the CBnTX register. (10) When the next transmit data is not written to the CBnTX register before transfer completion, stop the serial clock output to the SCKBn pin after transfer completion, and clear the CBnTSF bit to 0. (11) To release the transmission enable status, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnTXE bit = 0 after checking that the CBnTSF bit = 0. Caution In continuous transmission mode, the reception completion interrupt request signal (INTCBnR) is not generated. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 569 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) 570 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START (1), (2), (3) CBnCTL1 register 00H CBnCTL2 register 00H CBnCTL0 register A3H (4) CBnRX register dummy read (5) Start reception No INTCBnR interrupt generated? Yes CBnOVE bit = 1? (CBnSTR) No (6) Yes (8) Is data being received last data? CBnSCE bit = 0 (CBnCTL0) No (7) Yes (9) Read CBnRX register (12) CBnOVE bit = 0 (CBnSTR) (8) CBnSCE bit = 0 (CBnCTL0) (9) (9) Read CBnRX register (10) INTCBnR interrupt generated? Read CBnRX register No Yes (11) (13) CBnTSF bit = 0? (CBnSTR) Read CBnRX register No Yes (13) CBnCTL0 register 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 User's Manual U16541EJ5V1UD 571 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SOBn pin L SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (3) (4) (2) (5) (6) (7) (8) (9) (10) (11) (13) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write A3H to the CBnCTL0 register, and select the reception mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and reception is started. (5) When reception is started, output the serial clock to the SCKBn pin, and capture the receive data of the SIBn pin in synchronization with the serial clock. (6) When reception is completed, the reception completion interrupt request signal (INTCBnR) is generated, and reading of the CBnRX register is enabled. (7) When the CBnCTL0.CBnSCE bit = 1 upon communication completion, the next communication is started following communication completion. (8) To end continuous reception with the current reception, write the CBnSCE bit = 0. (9) Read the CBnRX register. (10) When reception is completed, the INTCBnR signal is generated, and reading of the CBnRX register is enabled. When the CBnSCE bit = 0 is set before communication completion, stop the serial clock output to the SCKBn pin, and clear the CBnTSF bit to 0, to end the receive operation. (11) Read the CBnRX register. (12) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag. (13) To release the reception enable status, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnRXE bit = 0 after checking that the CBnTSF bit = 0. Remark 572 n = 0 to 4 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = fXX/2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User's Manual U16541EJ5V1UD 573 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START (1), (2), (3) CBnCTL1 register 00H CBnCTL2 register 00H CBnCTL0 register E3H (4) Write CBnTX register (5) Start transmission/reception (6), (11) INTCBnT interrupt generated? No Yes (7) Is data being transmitted last data? Yes (11) No (7) No Write CBnTX register INTCBnR interrupt generated? (8) Yes No (9) CBnOVE bit = 1? (CBnSTR) (10) Read CBnRX register Yes (13) (13) Read CBnRX register Is receive data last data? (14) (15) CBnOVE bit = 0 (CBnSTR) CBnTSF bit = 0? (CBnSTR) No Yes (12) No Yes (15) CBnCTL0 register 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 574 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (15) (1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = fXX/2, and master mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write E3H to the CBnCTL0 register, and select the transmission/reception mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and transmission/reception is started. (5) When transmission/reception is started, output the serial clock to the SCKBn pin, output the transmit data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn pin. (6) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is generated. (7) To continue transmission/reception, write the transmit data to the CBnTX register again after the INTCBnT signal is generated. (8) When one transmission/reception is completed, the reception completion interrupt request signal (INTCBnR) is generated, and reading of the CBnRX register is enabled. (9) When a new transmit data is written to the CBnTX register before communication completion, the next communication is started following communication completion. (10) Read the CBnRX register. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 575 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (11) The transfer of the transmit data from the CBnTX register to the shift register is completed and the INTCBnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CBnTX register. (12) When the next transmit data is not written to the CBnTX register before transfer completion, stop the serial clock output to the SCKBn pin after transfer completion, and clear the CBnTSF bit to 0. (13) When the reception error interrupt request signal (INTCBnR) is generated, read the CBnRX register. (14) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag. (15) To release the transmission/reception enable status, write the CBnCTL0.CBnPWR bit = 0, the CBnCTL0.CBnTXE bit = 0, and the CBnCTL0.CBnRXE bit = 0 after checking that the CBnTSF bit = 0. Remark 576 n = 0 to 4 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow START (1), (2), (3) CBnCTL1 register 07H CBnCTL2 register 00H CBnCTL0 register C3H (4) Write CBnTX register (4) SCKBn pin input started? No Yes (5), (8) Start transmission (6), (9) INTCBnT interrupt generated? No Yes (9) Transmission completed? No (7) Yes (10) CBnTSF bit = 0? (CBnSTR register) No Yes (11) CBnCTL0 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 User's Manual U16541EJ5V1UD 577 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal SCKBn pin SOBn pin Bit 7 (1) (2) (3) (4) (5) Bit 6 (6) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (7) Bit 0 Bit 7 (8) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (9) Bit 0 (10) (11) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write C3H to the CBnCTL0 register, and select the transmission mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device waits for a serial clock input. (5) When a serial clock is input, output the transmit data from the SOBn pin in synchronization with the serial clock. (6) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is generated. (7) To continue transmission, write the transmit data to the CBnTX register again after the INTCBnT signal is generated. (8) When a serial clock is input following completion of the transmission of the transfer data length set with the CBnCTL2 register, continuous transmission is started. (9) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to the CBnTX register is enabled, the INTCBnT signal is generated. To end continuous transmission with the current transmission, do not write to the CBnTX register. (10) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the CBnTX register, clear the CBnTSF bit to 0 to end transmission. (11) To release the transmission enable status, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnTXE bit = 0 after checking that the CBnTSF bit = 0. Caution In continuous transmission mode, the reception completion interrupt request signal (INTCBnR) is not generated. Remark 578 n = 0 to 4 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User's Manual U16541EJ5V1UD 579 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START (1), (2), (3) CBnCTL1 register 07H CBnCTL2 register 00H CBnCTL0 register A3H (4) CBnRX register dummy read (4) SCKBn pin input started? No Yes (5) Reception start No INTCBnR interrupt generated? Yes CBnOVE bit = 1? (CBnSTR) No (6) Yes (8) (9) (12) CBnSCE bit = 0 (CBnCTL0) Is data being received last data? Read CBnRX register No (7) Yes (8) CBnSCE bit = 0 (CBnCTL0) (9) Read CBnRX register (10) INTCBnR interrupt generated? CBnOVE bit = 0 (CBnSTR) (9) Read CBnRX register No Yes (11) (13) CBnTSF bit = 0? (CBnSTR) Read CBnRX register No Yes (13) CBnCTL0 register 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 580 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (1) (3) (4) (2) (5) (6) (7) (8) (9) (10) (11) (13) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write A3H to the CBnCTL0 register, and select the reception mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and the device waits for a serial clock input. (5) When a serial clock is input, capture the receive data of the SIBn pin in synchronization with the serial clock. (6) When reception is completed, the reception completion interrupt request signal (INTCBnR) is generated, and reading of the CBnRX register is enabled. (7) When a serial clock is input in the CBnCTL0.CBnSCE bit = 1 status, continuous reception is started. (8) To end continuous reception with the current reception, write the CBnSCE bit = 0. (9) Read the CBnRX register. (10) When reception is completed, the INTCBnR signal is generated, and reading of the CBnRX register is enabled. When the CBnSCE bit = 0 is set before communication completion, clear the CBnTSF bit to 0 to end the receive operation. (11) Read the CBnRX register. (12) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag. (13) To release the reception enable status, write the CBnCTL0.CBnPWR bit = 0 and the CBnCTL0.CBnRXE bit = 0 after checking that the CBnTSF bit = 0. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 581 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (fCCLK) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) 582 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START (1), (2), (3) CBnCTL1 register 07H CBnCTL2 register 00H CBnCTL0 register E3H (4) Write CBnTX register (4) SCKBn pin input started? No Yes (5) (6), (11) Start transmission/reception INTCBnT interrupt generated? No Yes (7) Is data being transmitted last data? Yes (11) No (7) No Write CBnTX register INTCBnR interrupt generated? (8) Yes No (9) CBnOVE bit = 1? (CBnSTR) (10) Yes (13) (13) Read CBnRX register (14) CBnOVE bit = 0 (CBnSTR) Read CBnRX register Is receive data last data? No Yes (12) (15) CBnTSF bit = 0? (CBnSTR) No Yes (15) CBnCTL0 register 00H END Remarks 1. The broken lines indicate the hardware processing. 2. The numbers in this figure correspond to the processing numbers in (2) Operation timing. 3. n = 0 to 4 User's Manual U16541EJ5V1UD 583 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIBn pin capture timing (4) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (15) (1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (fCCLK) = external clock (SCKBn), and slave mode. (2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits. (3) Write E3H to the CBnCTL0 register, and select the transmission/reception mode, MSB first, and continuous transfer mode at the same time as enabling the operation of the communication clock (fCCLK). (4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device waits for a serial clock input. (5) When a serial clock is input, output the transmit data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn pin. (6) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is generated. (7) To continue transmission, write the transmit data to the CBnTX register again after the INTCBnT signal is generated. (8) When reception of the transfer data length set with the CBnCTL2 register is completed, the reception completion interrupt request signal (INTCBnR) is generated, and reading of the CBnRX register is enabled. (9) When a serial clock is input continuously, continuous transmission/reception is started. (10) Read the CBnRX register. (11) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to the CBnTX register is enabled, the INTCBnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CBnTX register. Remark 584 n = 0 to 4 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (12) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the CBnTX register, the INTCBnR signal is generated. Clear the CBnTSF bit to 0 to end transmission/reception. (13) When the INTCBnR signal is generated, read the CBnRX register. (14) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag. (15) To release the transmission/reception enable status, write the CBnCTL0.CBnPWR bit = 0, the CBnCTL0.CBnTXE bit = 0, and the CBnCTL0.CBnRXE bit = 0 after checking that the CBnTSF bit = 0. Remark n = 0 to 4 User's Manual U16541EJ5V1UD 585 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) <R> 16.6.13 Reception error When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (INTCBnR) is generated again when the next receive operation is completed before the CBnRX register is read after the INTCBnR signal is generated, and the overrun error flag (CBnSTR.CBnOVE) is set to 1. Even if an overrun error has occurred, the previous receive data is lost since the CBnRX register is updated. Even if a reception error has occurred, the INTCBnR signal is generated again upon the next reception completion if the CBnRX register is not read. To avoid an overrun error, complete reading the CBnRX register until one half clock before sampling the last bit of the next receive data from the INTCBnR signal generation. (1) Operation timing CBnRX register read signal INTCBnR signal CBnOVE bit CBnRX register AAH Shift register 01H 02H 05H 0AH 15H 2AH 55H AAH 00H 01H 55H 02H 05H 0AH 15H 2AH 55H SCKBn pin SIBn pin SIBn pin capture timing (1) (2) (3)(4) (1) Start continuous transfer. (2) Completion of the first transfer (3) The CBnRX register cannot be read until one half clock before the completion of the second transfer. (4) An overrun error occurs, and the reception completion interrupt request signal (INTCBnR) is generated, and then the overrun error flag (CBnSTR.CBnOVE) is set to 1. overwritten. Remark 586 n = 0 to 4 User's Manual U16541EJ5V1UD The receive data is CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.14 Clock timing (1/2) (i) Communication type 1 (CBnCKP and CBnDAP bits = 00) SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit (ii) Communication type 3 (CBnCKP and CBnDAP bits = 10) SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit Notes 1. The INTCBnT interrupt is set when the data written to the CBnTX register is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. In the single transmission or single transmission/reception mode, the INTCBnT interrupt request signal is not generated, but the INTCBnR interrupt request signal is generated upon end of communication. <R> 2. The INTCBnR interrupt occurs if reception is correctly ended and receive data is ready in the CBnRX register while reception is enabled. In the single mode, the INTCBnR interrupt request signal is generated even in the transmission mode, upon end of communication. <R> Caution In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1 is ignored. This has no influence on the operation during transfer. For example, if the next data is written to the CBnTX register when DMA is started by generating the INTCBnR signal, the written data is not transferred because the CBnTSF bit is set to 1. Use the continuous transfer mode, not the single transfer mode, for such applications. User's Manual U16541EJ5V1UD 587 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (iii) Communication type 2 (CBnCKP and CBnDAP bits = 01) SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit (iv) Communication type 4 (CBnCKP and CBnDAP bits = 11) SCKBn pin SIBn capture SOBn pin D7 D6 D5 D4 D3 D2 D1 D0 Reg-R/W INTCBnT interruptNote 1 INTCBnR interruptNote 2 CBnTSF bit Notes 1. The INTCBnT interrupt is set when the data written to the CBnTX register is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. In the single transmission or single transmission/reception modes, the INTCBnT interrupt request signal is not generated, but the INTCBnR interrupt request signal is generated upon end of communication. 2. The INTCBnR interrupt occurs if reception is correctly ended and receive data is ready in the <R> CBnRX register while reception is enabled. In the single mode, the INTCBnR interrupt request signal is generated even in the transmission mode, upon end of communication. <R> Caution In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1 is ignored. This has no influence on the operation during transfer. For example, if the next data is written to the CBnTX register when DMA is started by generating the INTCBnR signal, the written data is not transferred because the CBnTSF bit is set to 1. Use the continuous transfer mode, not the single transfer mode, for such applications. 588 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.7 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 0 1 1 1 Other than above 1 1 1 High impedance Fixed to high level 1 Other than above SCKBn Pin Output High impedance Fixed to low level Remarks 1. The output level of the SCKBn pin changes if any of the CBnCTL1.CBnCKP and CBnCKS2 to CBnCKS0 bits is rewritten. 2. n = 0 to 4 (2) SOBn pin When CSIBn operation is disabled (CBnPWR bit = 0), the SOBn pin output status is as follows. CBnTXE CBnDAP CBnDIR SOBn Pin Output 0 x x Fixed to low level 1 0 x SOBn latch value (low level) 1 0 CBnTX0 value (MSB) 1 CBnTX0 value (LSB) Remarks 1. The SOBn pin output changes when any one of the CBnCTL0.CBnTXE, CBnCTL0.CBnDIR bits, and CBnCTL1.CBnDAP bit is rewritten. 2. x: Don't care 3. n = 0 to 4 User's Manual U16541EJ5V1UD 589 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.8 Baud Rate Generator The BRG1 to BRG3 and CSIB0 to CSIB4 baud rate generators are connected as shown in the following block diagram. fX fBRG1 BRG1 CSIB0 CSIB1 fX fBRG2 BRG2 CSIB2 CSIB3 fX fBRG3 BRG3 CSIB4 (1) BRGm Prescaler mode registers (PRSM) The PRSM1 to PRSM3 registers control generation of the baud rate signal for CSIB. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. After reset: 00H R/W Address: PRSM1 FFFFF320H, PRSM2 FFFFF324H, PRSM3 FFFFF328H < > PRSMm (m = 1 to 3) 0 0 0 BGCEm BGCEm 0 0 Baud rate output 0 Disabled 1 Enabled Input clock selection (fBGCSm) BGCSm1 BGCSm0 Setting value (k) 0 0 fXX 0 0 1 fXX/2 1 1 0 fXX/4 2 1 1 fXX/8 3 Cautions 1. Do not rewrite the PRSMm register during operation. 2. Set the PRSMm register before setting the BGCEm bit to 1. 590 BGCSm1 BGCSm0 User's Manual U16541EJ5V1UD CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) BRGm Prescaler compare registers m (PRSCMm) The PRSCM1 to PRSCM3 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H R/W Address: PRSCM1 FFFFF321H, PRSCM2 FFFFF325H, PRSCM3 FFFFF329H PRSCMm PRSCMm7 PRSCMm6 PRSCMm5 PRSCMm4 PRSCMm3 PRSCMm2 PRSCMm1 PRSCMm0 Cautions 1. Do not rewrite the PRSCMm register during operation. 2. Set the PRSCMm register before setting the PRSMm.BGCEm bit to 1. 16.8.1 Baud rate generation The transmission/reception clock is generated by dividing the main clock. The baud rate generated from the main clock is obtained by the following equation. fXX fBRGm = k+1 2 <R> xN Caution Set fBRGm to 8 MHz or lower. Remark fBRGm: BRGm count clock fXX: Main clock frequency k: PRSMm register setting value = 0 to 3 N: PRSCMm register setting value = 1 to 256 However, N = 256 only when PRSCMm register is set to 00H. m = 1 to 3 User's Manual U16541EJ5V1UD 591 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.9 Cautions (1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CBnSTR.CBnOVE bit after DMA transfer has been completed. (2) In regards to registers that are forbidden from being rewritten during operations (CBnCTL0.CBnPWR bit is 1), if rewriting has been carried out by mistake during operations, set the CBnCTL0.CBnPWR bit to 0 once, then initialize CSIBn. Registers to which rewriting during operation are prohibited are shown below. * CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bits * CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2 to CBnCKS0 bits * CBnCTL2 register: CBnCL3 to CBnCL0 bits (3) In communication type 2 or 4 (CBnCTL1.CBnDAP bit = 1), the CBnSTR.CBnTSF bit is cleared half an SCKBn clock after occurrence of a reception completion interrupt (INTCBnR). In the single transfer mode, writing the next transmit data is ignored during communication (CBnTSF bit = 1), and the next communication is not started. Also if receive-only communication (CBnCTL0.CBnTXE bit = 0, CBnCTL0.CBnRXE bit = 1) is set, the next communication is not started even if the receive data is read during communication (CBnTSF bit = 1). Therefore, when using the single transfer mode with communication type 2 or 4 (CBnDAP bit = 1), pay particular attention to the following. * To start the next transmission, confirm that CBnTSF bit = 0 and then write the transmit data to the CBnTX register. * To perform the next reception continuously when receive-only communication (CBnTXE bit = 0, CBnRXE bit = 1) is set, confirm that CBnTSF bit = 0 and then read the CBnRX register. Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode is recommended especially for using DMA. Remark 592 n = 0 to 4 User's Manual U16541EJ5V1UD CHAPTER 17 I2C BUS The contents of this chapter only apply to I2C bus version (Y products). To use the I2C bus function, use the P38/SDA00, P40/SDA01, and P90/SDA02 pins as the serial tranmit/receive data I/O pins, and the P39/SCL00, P41/SCL01, and P91/SCL02 pins as the serial clock I/O pins, and set them to N-ch open-drain output. 17.1 Mode Switching of I2C Bus and Other Serial Interfaces 17.1.1 UARTA2 and I2C00 mode switching <R> In the V850ES/SG2 and V850ES/SG2-H, UARTA2 and I2C00 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I2C00 in advance, using the PMC3 and PFC3 registers, before use. Caution The transmit/receive operation of UARTA2 and I2C00 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 17-1. UARTA2 and I2C00 Mode Switch Settings After reset: 0000H PMC3 Address: FFFFF446H, FFFFF447H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PMC39 PMC38 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 After reset: 0000H PFC3 R/W R/W Address: FFFFF466H, FFFFF467H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 PFC39 PFC38 PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 PMC3n PFC3n Operation mode 0 x Port I/O mode 1 0 UARTA2 mode 1 1 I2C00 mode Remarks 1. n = 8, 9 2. x = don't care User's Manual U16541EJ5V1UD 593 2 CHAPTER 17 I C BUS 17.1.2 CSIB0 and I2C01 mode switching <R> In the V850ES/SG2 and V850ES/SG2-H, CSIB0 and I2C01 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I2C01 in advance, using the PMC4 and PFC4 registers, before use. Caution The transmit/receive operation of CSIB0 and I2C01 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 17-2. CSIB0 and I2C01 Mode Switch Settings After reset: 00H PMC4 0 After reset: 00H PFC4 R/W 0 R/W Address: FFFFF448H 0 0 0 PMC42 PMC41 PMC40 0 0 PFC41 PFC40 Address: FFFFF468H 0 0 0 PMC4n PFC4n 0 x Port I/O mode 1 0 CSIB0 mode 1 1 I2C01 mode 0 Operation mode Remarks 1. n = 0, 1 2. x = don't care 594 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.1.3 UARTA1 and I2C02 mode switching <R> In the V850ES/SG2 and V850ES/SG2-H, UARTA1 and I2C02 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I2C02 in advance, using the PMC9, PFC9, and PMCE9 registers, before use. Caution The transmit/receive operation of UARTA1 and I2C02 is not guaranteed if these functions are switched during transmission or reception. Be sure to disable the one that is not used. Figure 17-3. UARTA1 and I2C02 Mode Switch Settings After reset: 0000H 15 PMC9 8 PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 PMC97 PMC91 PMC90 9 8 R/W PMC95 12 PMC94 11 10 PMC93 PMC92 Address: FFFFF472H, FFFFF473H 14 PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98 PFC97 PFC96 PFC95 PFC93 PFC91 PFC90 15 Remark PMC96 13 15 After reset: 0000H PFCE9 14 Address: FFFFF452H, FFFFF453H 9 After reset: 0000H PFC9 R/W R/W 14 PFCE915 PFCE914 13 12 PFC94 11 10 PFC92 Address: FFFFF712H, FFFFF713H 13 12 11 10 9 8 0 0 0 0 0 0 PFCE91 PFCE90 PFCE97 PFCE96 PFCE95 PFCE94 PFCE93 PFCE92 PMC9n PFCE9n PFC9n 1 1 0 UARTA1 mode 1 1 1 I2C02 mode Operation mode n = 0, 1 User's Manual U16541EJ5V1UD 595 2 CHAPTER 17 I C BUS 17.2 Features I2C00 to I2C02 have the following two modes. * Operation stopped mode * I2C (Inter IC) bus mode (multimasters supported) (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) I2C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (SCL0n) and a serial data bus pin (SDA0n). This mode complies with the I2C bus format and the master device can generate "start condition", "address", "transfer direction specification", "data", and "stop condition" data to the slave device via the serial data bus. The slave device automatically detects the received statuses and data by hardware. This function can simplify the part of an application program that controls the I2C bus. Since SCL0n and SDA0n pins are used for N-ch open-drain outputs, I2C0n requires pull-up resistors for the serial clock line and the serial data bus line. Remark 596 n = 0 to 2 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.3 Configuration The block diagram of the I2C0n is shown below. Figure 17-4. Block Diagram of I2C0n Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn Slave address register n (SVAn) SDA0n Set Match signal Noise eliminator IIC shift register n (IICn) DFCn D Q Stop condition generator SO latch CLn1, CLn0 Data retention time correction circuit TRCn N-ch open-drain output Start condition generator Clear Acknowledge generator Output control Wakeup controller Acknowledge detector Start condition detector Stop condition detector SCL0n Noise eliminator Interrupt request signal generator Serial clock counter DFCn Serial clock controller IIC shift register n (IICn) IICCn.STTn, SPTn IICSn.MSTSn, EXCn, COIn fxx Prescaler IICSn.MSTSn, EXCn, COIn Serial clock wait controller N-ch open-drain output INTIICn Bus status detector Prescaler fxx to fxx/5 OCKSENm OCKSTHm OCKSm1 OCKSm0 CLDn DADn SMCn DFCn CLn1 CLn0 IIC division clock select register m (OCKSm) CLXn IIC clock select register n (IICCLn) STCFn IICBSYn STCENn IICRSVn IIC function expansion register n (IICXn) IIC flag register n (IICFn) Internal bus Remark n = 0 to 2 m = 0, 1 User's Manual U16541EJ5V1UD 597 2 CHAPTER 17 I C BUS A serial bus configuration example is shown below. Figure 17-5. Serial Bus Configuration Example Using I2C Bus +VDD +VDD Master CPU1 SDA Slave CPU1 Address 1 598 SCL Serial data bus Serial clock User's Manual U16541EJ5V1UD SDA Master CPU2 Slave CPU2 SCL Address 2 SDA Slave CPU3 SCL Address 3 SDA Slave IC SCL Address 4 SDA Slave IC SCL Address N 2 CHAPTER 17 I C BUS I2C0n includes the following hardware (n = 0 to 2). Table 17-1. Configuration of I2C0n Item Configuration Registers IIC shift register n (IICn) Slave address register n (SVAn) Control registers IIC control register n (IICCn) IIC status register n (IICSn) IIC flag register n (IICF0n) IIC clock select register n (IICCLn) IIC function expansion register n (IICXn) IIC division clock select registers 0, 1 (OCKS0, OCKS1) (1) IIC shift register n (IICn) The IICn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both transmission and reception (n = 0 to 2). Write and read operations to the IICn register are used to control the actual transmit and receive operations. This register can be read or written in 8-bit units. Reset input clears this register to 00H. (2) Slave address register n (SVAn) The SVAn register sets local addresses when in slave mode (n = 0 to 2). This register can be read or written in 8-bit units. Reset input clears this register to 00H. (3) SO latch The SO latch is used to retain the output level of the SDA0n pin (n = 0 to 2). (4) Wakeup controller This circuit generates an interrupt request signal (INTIICn) when the address received by this register matches the address value set to the SVAn register or when an extension code is received (n = 0 to 2). (5) Prescaler This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. User's Manual U16541EJ5V1UD 599 2 CHAPTER 17 I C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I2C interrupt is generated following either of two triggers. * Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit) * Interrupt occurrence due to stop condition detection (set by IICCn.SPIEn bit) Remark n = 0 to 2 (8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0n pin from the sampling clock (n = 0 to 2). (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits are used to generate and detect various statuses. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the SCL0n pin. (12) Start condition generator A start condition is generated when the IICCn.STTn bit is set. However, in the communication reservation disabled status (IICFn.IICRSVn bit = 1), this request is ignored and the IICFn.STCFn bit is set to 1 if the bus is not released (IICFn.IICBSYn bit = 1). (13) Stop condition generator A stop condition is generated when the IICCn.SPTn bit is set (1). (14) Bus status detector Whether the bus is released or not is ascertained by detecting a start condition and stop condition. However, the bus status cannot be detected immediately after operation, so set the bus status detector to the initial status by using the IICFn.STCENn bit. 600 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.4 Registers I2C00 to I2C02 are controlled by the following registers. * IIC control registers 0 to 2 (IICC0 to IICC2) * IIC status registers 0 to 2 (IICS0 to IICS2) * IIC flag registers 0 to 2 (IICF0 to IICF2) * IIC clock select registers 0 to 2 (IICCL0 to IICCL2) * IIC function expansion registers 0 to 2 (IICX0 to IICX2) * IIC division clock select registers 0, 1 (OCKS0, OCKS1) The following registers are also used. * IIC shift registers 0 to 2 (IIC0 to IIC2) * Slave address registers 0 to 2 (SVA0 to SVA2) Remark For the alternate-function pin settings, see Table 4-15 Using Port Pin as Alternate-Function Pin. (1) IIC control registers 0 to 2 (IICC0 to IICC2) The IICC0 to IICC2 registers enable/stop I2C0n operations, set the wait timing, and set other I2C operations (n = 0 to 2). These registers can be read or written in 8-bit or 1-bit units. However, set the SPIEn, WTIMn, and ACKEn bits when the IICEn bit is 0 or during the wait period. When setting the IICEn bit from "0" to "1", these bits can also be set at the same time. Reset sets these registers to 00H. User's Manual U16541EJ5V1UD 601 2 CHAPTER 17 I C BUS (1/4) After reset: 00H IICCn R/W Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H, IICC2 FFFFFDA2H <7> <6> <5> <4> <3> <2> <1> <0> IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0 to 2) 2 IICEn Specification of I Cn operation enable/disable Note 1 0 Operation stopped. IICSn register reset 1 Operation enabled. . Internal operation stopped. Be sure to set this bit to 1 when the SCL0n and SDA0n lines are high level. Condition for clearing (IICEn bit = 0) Condition for setting (IICEn bit = 1) * Cleared by instruction * Set by instruction * After reset LRELn Note 2 Exit from communications 0 Normal operation 1 This exits from the current communication operation and sets standby mode. This setting is automatically cleared after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCL0n and SDA0n lines are set to high impedance. The STTn and SPTn bits and the MSTSn, EXCn, COIn, TRCn, ACKDn, and STDn bits of the IICSn register are cleared. The standby mode following exit from communications remains in effect until the following communication entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match occurs or an extension code is received after the start condition. Condition for clearing (LRELn bit = 0) Condition for setting (LRELn bit = 1) * Automatically cleared after execution * Set by instruction * After reset WRELn Note 2 Wait state cancellation control 0 Wait state not canceled 1 Wait state canceled. This setting is automatically cleared after wait state is canceled. Condition for clearing (WRELn bit = 0) Condition for setting (WRELn bit = 1) * Automatically cleared after execution * Set by instruction * After reset Notes 1. The IICSn register, IICFn.STCFn and IICFn.IICBSYn bits, and IICCLn.CLDn and IICCLn.DADn bits are reset. 2. This flag's signal is invalid when the IICEn bit = 0. Caution 2 If the I Cn operation is enabled (IICEn bit = 1) when the SCL0n line is high level and the SDA0n line is low level, the start condition is detected immediately. To avoid this, after enabling the I2Cn operation, immediately set the LRELn bit to 1 with a bit manipulation instruction. Remark 602 The LRELn and WRELn bits are 0 when read after the data has been set. User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (2/4) Note SPIEn Enable/disable generation of interrupt request when stop condition is detected 0 Disabled 1 Enabled Condition for clearing (SPIEn bit = 0) Condition for setting (SPIEn bit = 1) * Cleared by instruction * Set by instruction * After reset Note WTIMn 0 Control of wait state and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and the wait state is set. Slave mode: After input of eight clocks, the clock is set to low level and the wait state is set for the master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and the wait state is set. Slave mode: After input of nine clocks, the clock is set to low level and the wait state is set for the master device. During address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. This bit setting becomes valid when the address transfer is completed. In master mode, a wait state is inserted at the falling edge of the ninth clock during address transfer. For a slave device that has received a local address, a wait state is inserted at the falling edge of the ninth clock after ACK is generated. When the slave device has received an extension code, however, a wait state is inserted at the falling edge of the eighth clock. Condition for clearing (WTIMn bit = 0) Condition for setting (WTIMn bit = 1) * Cleared by instruction * Set by instruction * After reset Note ACKEn <R> Acknowledgment control 0 Acknowledgment disabled. 1 Acknowledgment enabled. During the ninth clock period, the SDA0n line is set to low level. The ACKEn bit setting is invalid for address reception. In this case, ACK is generated when the addresses match. However, the ACKEn bit setting is valid for reception of the extension code. Condition for clearing (ACKEn bit = 0) Condition for setting (ACKEn bit = 1) * Cleared by instruction * Set by instruction * After reset Note This flag's signal is invalid when the IICEn bit = 0. Remark n = 0 to 2 User's Manual U16541EJ5V1UD 603 2 CHAPTER 17 I C BUS (3/4) STTn Start condition trigger 0 Start condition is not generated. 1 When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level while the SCLn line is high level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCL0n line is changed to low level (wait state). During communication with a third party: * If the communication reservation function is enabled (IICFn.IICRSVn bit = 0) * This trigger functions as a start condition reserve flag. When set to 1, it releases the bus and then automatically generates a start condition. * If the communication reservation function is disabled (IICRSVn = 1) * The IICFn.STCFn bit is set to 1 and information set (1) to the STTn bit is cleared. This trigger does not generate a start condition. In the wait state (when master device): A restart condition is generated after the wait state is released. Cautions concerning set timing For master reception: Cannot be set to 1 during transfer. Can be set to 1 only when the ACKEn bit has been set to 0 and the slave has been notified of final reception. For master transmission: A start condition cannot be generated normally during the ACK period. Set to 1 during the wait period that follows output of the ninth clock. For slave: Even when the communication reservation function is disabled (IICRSVn bit = 1), the communication reservation status is entered. * Setting to 1 at the same time as the SPTn bit is prohibited. * When the STTn bit is set to 1, setting the STTn bit to 1 again is disabled until the setting is cleared to 0. Condition for clearing (STTn bit = 0) Condition for setting (STTn bit = 1) * When the STTn bit is set to 1 in the communication * Set by instruction reservation disabled status * Cleared by loss in arbitration * Cleared by start condition generation in the master device * When the LRELn bit = 1 (communication save) * When the IICEn bit = 0 (operation stop) * After reset Remarks 1. The STTn bit is 0 if it is read immediately after data setting. 2. n = 0 to 2 604 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (4/4) SPTn Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device's transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed from low level to high level and a stop condition is generated. Cautions concerning set timing For master reception: Cannot be set to 1 during transfer. Can be set to 1 only when the ACKEn bit has been set to 0 and during the wait period after the slave has been notified of final reception. For master transmission: A stop condition cannot be generated normally during the ACK reception period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as the STTn bit. * The SPTn bit can be set to 1 only when in master mode Note . * When the WTIMn bit has been set to 0, if the SPTn bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIMn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the SPTn bit should be set to 1 during the wait period that follows output of the ninth clock. * When the SPTn bit is set to 1, setting the SPTn bit to 1 again is disabled until the setting is cleared to 0. Condition for clearing (SPTn bit = 0) Condition for setting (SPTn bit = 1) * Cleared by loss in arbitration * Set by instruction * Automatically cleared after stop condition is detected * When the LRELn bit = 1 (communication save) * When the IICEn bit = 0 (operation stop) * After reset Note Set the SPTn bit to 1 only in master mode. However, when the IICRSVn bit is 0, the SPTn bit must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. For details, see 17.15 Cautions. Caution When the TRCn bit = 1, the WRELn bit is set to 1 during the ninth clock and the wait state is canceled, after which the TRCn bit is cleared to 0 and the SDA0n line is set to high impedance. Remarks 1. The SPTn bit is 0 if it is read immediately after data setting. 2. n = 0 to 2 User's Manual U16541EJ5V1UD 605 2 CHAPTER 17 I C BUS (2) IIC status registers 0 to 2 (IICS0 to IICS2) The IICS0 to IICS2 registers indicate the status of the I2C0n bus (n = 0 to 2). These registers are read-only, in 8-bit or 1-bit units. However, the IICSn register can only be read when the IICCn.STTn bit is 1 or during the wait period. Reset sets these registers to 00H. Caution Accessing the IICSn register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock (1/3) After reset: 00H IICSn R Address: IICS0 FFFFFD86H, IICS1 FFFFFD96H, IICS2 FFFFFDA6H <7> <6> <5> <4> <3> <2> <1> <0> MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn (n = 0 to 2) MSTSn Master device status 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing (MSTSn bit = 0) Condition for setting (MSTSn bit = 1) * When a stop condition is detected * When the ALDn bit = 1 (arbitration loss) * Cleared by LRELn bit = 1 (communication save) * When the IICEn bit changes from 1 to 0 (operation stop) * After reset * When a start condition is generated ALDn Arbitration loss detection 0 This status means either that there was no arbitration or that the arbitration result was a "win". 1 This status indicates the arbitration result was a "loss". The MSTSn bit is cleared to 0. Condition for clearing (ALDn bit = 0) Condition for setting (ALDn bit = 1) * Automatically cleared after the IICSn register is Note read * When the IICEn bit changes from 1 to 0 (operation stop) * After reset * When the arbitration result is a "loss". EXCn Detection of extension code reception 0 Extension code was not received. 1 Extension code was received. Condition for clearing (EXCn bit = 0) Condition for setting (EXCn bit = 1) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn bit = 1 (communication save) * When the IICEn bit changes from 1 to 0 (operation stop) * After reset * When the higher four bits of the received address data are either "0000" or "1111" (set at the rising edge of the eighth clock). Note The ALDn bit is also cleared when a bit manipulation instruction is executed for another bit in the IICSn register. 606 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (2/3) COIn Matching address detection 0 Addresses do not match. 1 Addresses match. Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1) * When a start condition is detected * When the received address matches the local * When a stop condition is detected address (SVAn register) (set at the rising edge of the * Cleared by LRELn bit = 1 (communication save) eighth clock). * When the IICEn bit changes from 1 to 0 (operation stop) * After reset TRCn 0 1 Transmit/receive status detection Receive status (other than transmit status). The SDA0n line is set to high impedance. Transmit status. The value in the SO latch is enabled for output to the SDA0n line (valid starting at the falling edge of the first byte's ninth clock). Condition for clearing (TRCn bit = 0) Condition for setting (TRCn bit = 1) * When a stop condition is detected Master * Cleared by LRELn bit = 1 (communication save) * When a start condition is generated * When the IICEn bit changes from 1 to 0 (operation * When "0" is output to the first byte's LSB (transfer stop) direction specification bit) * Cleared by IICCn.WRELn bit = 1 Slave * When the ALDn bit changes from 0 to 1 (arbitration * When "1" is input by the first byte's LSB (transfer Note loss) direction specification bit) * After reset Master * When "1" is output to the first byte's LSB (transfer direction specification bit) Slave * When a start condition is detected When not used for communication ACKDn ACK detection 0 ACK was not detected. 1 ACK was detected. Condition for clearing (ACKDn bit = 0) Condition for setting (ACKD bit = 1) * When a stop condition is detected * After the SDA0n bit is set to low level at the rising * At the rising edge of the next byte's first clock edge of the SCL0n pin's ninth clock * Cleared by LRELn bit = 1 (communication save) * When the IICEn bit changes from 1 to 0 (operation stop) * After reset Note The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when the WRELn bit is set to 1 and the wait state is canceled to 0 at the ninth clock by TRCn bit = 1. Remark n = 0 to 2 User's Manual U16541EJ5V1UD 607 2 CHAPTER 17 I C BUS (3/3) STDn Start condition detection 0 Start condition was not detected. 1 Start condition was detected. This indicates that the address transfer period is in effect Condition for clearing (STDn bit = 0) Condition for setting (STDn bit = 1) * When a stop condition is detected * When a start condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LRELn bit = 1 (communication save) * When the IICEn bit changes from 1 to 0 (operation stop) * After reset SPDn Stop condition detection 0 Stop condition was not detected. 1 Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for clearing (SPDn bit = 0) Condition for setting (SPDn bit = 1) * At the rising edge of the address transfer byte's first * When a stop condition is detected clock following setting of this bit and detection of a start condition * When the IICEn bit changes from 1 to 0 (operation stop) * After reset Remark 608 n = 0 to 2 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (3) IIC flag registers 0 to 2 (IICF0 to IICF2) The IICF0 to IICF2 registers set the I2C0n operation mode and indicate the I2C bus status. These registers can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are readonly. IICRSVn enables/disables the communication reservation function (see 17.14 Communication Reservation). The initial value of the IICBSYn bit is set by using the STCENn bit (see 17.15 Cautions). The IICRSVn and STCENn bits can be written only when operation of I2C0n is disabled (IICCn.IICEn bit = 0). After operation is enabled, IICFn can be read (n = 0 to 2). Reset sets these registers to 00H. User's Manual U16541EJ5V1UD 609 2 CHAPTER 17 I C BUS After reset: 00H IICFn R/W Note Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH, IICF2 FFFFFDAAH <7> <6> 5 4 3 2 <1> <0> STCFn IICBSYn 0 0 0 0 STCENn IICRSVn (n = 0 to 2) STCFn STTn bit clear 0 Start condition issued 1 Start condition cannot be issued, STTn bit cleared Condition for clearing (STCFn bit = 0) Condition for setting (STCFn bit = 1) * Cleared by IICCn.STTn bit = 1 * When the IICCn.IICEn bit = 0 * After reset * When start condition is not issued and STTn flag is cleared to 0 during communication reservation is disabled (IICRSVn bit = 1). 2 IICBSYn I C0n bus status 0 Bus released status (default communication status when STCENn bit = 1) 1 Bus communication status (default communication status when STCENn bit = 0) Condition for clearing (IICBSYn bit = 0) Condition for setting (IICBSYn bit = 1) * When stop condition is detected * When the IICEn bit = 0 * After reset * When start condition is detected * By setting the IICEn bit when the STCENn bit = 0 STCENn Initial start enable trigger 0 Start conditions cannot be generated until a stop condition is detected following operation enable (IICEn bit = 1). 1 Start conditions can be generated even if a stop condition is not detected following operation enable (IICEn bit = 1). Condition for clearing (STCENn bit = 0) Condition for setting (STCENn bit = 1) * When start condition is detected * After reset * Setting by instruction IICRSVn Communication reservation function disable bit 0 Communication reservation enabled 1 Communication reservation disabled Condition for clearing (IICRSVn bit = 0) Condition for setting (IICRSVn bit = 1) * Clearing by instruction * After reset * Setting by instruction Note Bits 6 and 7 are read-only bits. Cautions 1. Write the STCENn bit only when operation is stopped (IICEn bit = 0). 2. When the STCENn bit = 1, the bus released status (IICBSYn bit = 0) is recognized regardless of the actual bus status immediately after the I2Cn bus operation is enabled. Therefore, to issue the first start condition (STTn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. 3. Write the IICRSVn bit only when operation is stopped (IICEn bit = 0). 610 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2) The IICCL0 to IICCL2 registers set the transfer clock for the I2C0n bus. These registers can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. Set the IICCLn register when the IICCn.IICEn bit = 0. The SMCn, CLn1, and CLn0 bits are set by the combination of the IICXn.CLXn bit and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 17.4 (6) I2C0n transfer clock setting method) (n = 0 to 2, m = 0, 1). Reset sets these registers to 00H. After reset: 00H R/W IICCLn Note Address: IICCL0 FFFFFD84H, IICCL1 FFFFFD94H, IICCL2 FFFFFDA4H 7 6 <5> <4> 3 2 1 0 0 0 CLDn DADn SMCn DFCn CLn1 CLn0 (n = 0 to 2) CLDn Detection of SCL0n pin level (valid only when IICCn.IICEn bit = 1) 0 The SCL0n pin was detected at low level. 1 The SCL0n pin was detected at high level. Condition for clearing (CLDn bit = 0) Condition for setting (CLDn bit = 1) * When the SCL0n pin is at low level * When the SCL0n pin is at high level * When the IICEn bit = 0 (operation stop) * After reset DADn Detection of SDA0n pin level (valid only when IICEn bit = 1) 0 The SDA0n pin was detected at low level. 1 The SDA0n pin was detected at high level. Condition for clearing (DADn bit = 0) Condition for setting (DAD0n bit = 1) * When the SDA0n pin is at low level * When the SDA0n pin is at high level * When the IICEn bit = 0 (operation stop) * After reset SMCn Operation mode switching 0 Operation in standard mode. 1 Operation in high-speed mode. DFCn Digital filter operation control 0 Digital filter off. 1 Digital filter on. The digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of the DFCn bit setting (on/off). The digital filter is used to eliminate noise in high-speed mode. Note Bits 4 and 5 of IICCLn are read-only bits. Caution Be sure to clear bits 7 and 6 of IICCLn to 0. Remark When the IICCn.IICEn bit = 0, 0 is read when reading the CLDn and DADn bits. User's Manual U16541EJ5V1UD 611 2 CHAPTER 17 I C BUS (5) IIC function expansion registers 0 to 2 (IICX0 to IICX2) The IICX0 to IICS2 registers set I2C0n function expansion (valid only in the high-speed mode). These registers can be read or written in 8-bit or 1-bit units. Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 17.4 (6) I2C0n transfer clock setting method) (m = 0, 1). Set the IICXn register when the IICCn.IICEn bit = 0. Reset sets these registers to 00H. After reset: 00H R/W Address: IICX0 FFFFFD85H, IICX1 FFFFFD95H, IICX2 FFFFFDA5H < > IICXn 0 0 0 0 0 0 0 CLXn (n = 0 to 2) (6) I2C0n transfer clock setting method The I2C0n transfer clock frequency (fSCL) is calculated using the following expression (n = 0 to 2). fSCL = 1/(m x T + tR + tF) m = 12, 18, 24, 36, 44, 48, 54, 60, 66, 72, 86, 88, 90, 96, 120, 132, 172, 176, 198, 220, 258, 264, 330, <R> 344, 430 (see Table 17-2 Clock Settings). T: 1/fXX tR: SCL0n pin rise time tF: SCL0n pin fall time For example, the I2C0n transfer clock frequency (fSCL) when fXX = 19.2 MHz, m = 198, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(198 x 52 ns + 200 ns + 50 ns) 94.7 kHz m x T + tR + tF tR m/2 x T tF m/2 x T SCL0n SCL0n inversion SCL0n inversion SCL0n inversion The clock to be selected can be set by the combination of the SMCn, CLn1, and CLn0 bits of the IICCLn register, the CLXn bit of the IICXn register, and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (n = 0 to 2, m = 0, 1). 612 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS Table 17-2. Clock Settings (1/2) IICX0 IICCL0 Selection Clock Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 0 0 0 0 Transfer Settable Main Clock Operating Clock Frequency (fXX) Range Mode fXX (when OCKS0 = 18H set) fXX/44 2.00 MHz fXX 4.19 MHz Standard fXX/2 (when OCKS0 = 10H set) fXX/88 4.00 MHz fXX 8.38 MHz mode fXX/3 (when OCKS0 = 11H set) fXX/132 6.00 MHz fXX 12.57 MHz fXX/4 (when OCKS0 = 12H set) fXX/176 8.00 MHz fXX 16.76 MHz fXX/5 (when OCKS0 = 13H set) fXX/220 10.00 MHz fXX 20.95 MHz fXX (when OCKS0 = 18H set) fXX/86 4.19 MHz fXX 8.38 MHz fXX/2 (when OCKS0 = 10H set) fXX/172 8.38 MHz fXX 16.76 MHz <R> fXX/3 (when OCKS0 = 11H set) fXX/258 12.57 MHz fXX 25.14 MHz <R> fXX/4 (when OCKS0 = 12H set) fXX/344 16.76 MHz fXX 32.00 MHz <R> fXX/5 (when OCKS0 = 13H set) fXX/430 20.95 MHz fXX 32.00 MHz <R> 0 0 0 1 Note 1 Note 1 Note 1 Note 2 0 0 1 0 fXX fXX/86 4.19 MHz fXX 8.38 MHz 0 0 1 1 fXX (when OCKS0 = 18H set) fXX/66 6.40 MHz fXX/2 (when OCKS0 = 10H set) fXX/132 12.80 MHz Note 3 (SMC0 bit = 0) fXX/3 (when OCKS0 = 11H set) fXX/198 19.20 MHz <R> fXX/4 (when OCKS0 = 12H set) fXX/264 25.60 MHz <R> fXX/5 (when OCKS0 = 13H set) fXX/330 32.00 MHz fXX (when OCKS0 = 18H set) fXX/24 4.19 MHz fXX 8.38 MHz High-speed fXX/2 (when OCKS0 = 10H set) fXX/48 8.00 MHz fXX 16.76 MHz mode <R> fXX/3 (when OCKS0 = 11H set) fXX/72 12.00 MHz fXX 25.14 MHz <R> fXX/4 (when OCKS0 = 12H set) fXX/96 16.00 MHz fXX 32.00 MHz <R> fXX/5 (when OCKS0 = 13H) fXX/120 20.00 MHz fXX 32.00 MHz 0 1 0 x Note 2 Note 2 Note 1 Note 1 Note 2 0 1 1 0 fXX fXX/24 4.00 MHz fXX 8.38 MHz 0 1 1 1 fXX (when OCKS0 = 18H set) fXX/18 6.40 MHz fXX/2 (when OCKS0 = 10H set) fXX/36 12.80 MHz fXX/3 (when OCKS0 = 11H set) fXX/54 19.20 MHz <R> fXX/4 (when OCKS0 = 12H set) fXX/72 25.60 MHz <R> fXX/5 (when OCKS0 = 13H set) fXX/90 32.00 MHz fXX (when OCKS0 = 18H set) fXX/12 4.00 MHz fXX 4.19 MHz fXX/2 (when OCKS0 = 10H set) fXX/24 8.00 MHz fXX 8.38 MHz fXX/3 (when OCKS0 = 11H set) fXX/36 12.00 MHz fXX 12.57 MHz fXX/4 (when OCKS0 = 12H set) fXX/48 16.00 MHz fXX 16.67 MHz fXX/5 (when OCKS0 = 13H set) fXX/60 20.00 MHz fXX 20.95 MHz fXX/12 4.00 MHz fXX 4.19 MHz 1 1 0 x <R> 1 1 1 0 Other than above <R> <R> Note 3 Note 3 fXX Setting prohibited - (SMC0 bit = 1) Note 2 Note 2 Note 1 - - Notes 1. fXX > 20 MHz is settable only in the V850ES/SG2-H. 2. Settable only in the V850ES/SG2-H 3. Since the selection clock is fXX regardless of the value set to the OCKS0 register, clear the OCKS0 register to 00H (I2C division clock stopped status). Remark x: don't care User's Manual U16541EJ5V1UD 613 2 CHAPTER 17 I C BUS Table 17-2. Clock Settings (2/2) IICXm Bit 0 Bit 1 CLXm SMCm CLm1 0 Selection Clock IICCLm Bit 3 0 0 Bit 0 0 0 Operating Mode Settable Main Clock Frequency (fXX) Range CLm0 0 <R> 0 Transfer Clock 1 fXX (when OCKS1 = 18H set) fXX/44 2.00 MHz fXX 4.19 MHz fXX/2 (when OCKS1 = 10H set) fXX/88 4.00 MHz fXX 8.38 MHz fXX/3 (when OCKS1 = 11H set) fXX/132 6.00 MHz fXX 12.57 MHz fXX/4 (when OCKS1 = 12H set) fXX/176 8.00 MHz fXX 16.76 MHz fXX/5 (when OCKS1 = 13H set) fXX/220 10.00 MHz fXX 20.95 MHz fXX (when OCKS1 = 18H set) fXX/86 4.19 MHz fXX 8.38 MHz Standard mode (SMCm bit = 0) Note 1 fXX/2 (when OCKS1 = 10H set) fXX/172 8.38 MHz fXX 16.76 MHz <R> fXX/3 (when OCKS1 = 11H set) fXX/258 12.57 MHz fXX 25.14 MHz <R> fXX/4 (when OCKS1 = 12H set) fXX/344 16.76 MHz fXX 32.00 MHz <R> fXX/5 (when OCKS1 = 13H set) fXX/430 20.95 MHz fXX 32.00 MHz Note 1 Note 1 Note 2 0 0 1 0 fXX fXX/86 4.19 MHz fXX 8.38 MHz 0 0 1 1 fXX (when OCKS1 = 18H set) fXX/66 6.40 MHz fXX/2 (when OCKS1 = 10H set) fXX/132 12.80 MHz Note 3 fXX/3 (when OCKS1 = 11H set) fXX/198 19.20 MHz <R> fXX/4 (when OCKS1 = 12H set) fXX/264 25.60 MHz <R> fXX/5 (when OCKS1 = 13H set) fXX/330 32.00 MHz fXX (when OCKS1 = 18H set) fXX/24 4.19 MHz fXX 8.38 MHz 0 1 0 x Note 2 Note 2 fXX/2 (when OCKS1 = 10H set) fXX/48 8.00 MHz fXX 16.76 MHz <R> fXX/3 (when OCKS1 = 11H set) fXX/72 12.00 MHz fXX 25.14 MHz <R> fXX/4 (when OCKS1 = 12H set) fXX/96 16.00 MHz fXX 32.00 MHz <R> fXX/5 (when OCKS1 = 13H set) fXX/120 20.00 MHz fXX 32.00 MHz Note 1 Note 1 Note 2 0 1 1 0 fXX fXX/24 4.00 MHz fXX 8.38 MHz 0 1 1 1 fXX (when OCKS1 = 18H set) fXX/18 6.40 MHz fXX/2 (when OCKS1 = 10H set) fXX/36 12.80 MHz fXX/3 (when OCKS1 = 11H set) fXX/54 19.20 MHz <R> fXX/4 (when OCKS1 = 12H set) fXX/72 25.60 MHz <R> fXX/5 (when OCKS1 = 13H set) fXX/90 32.00 MHz fXX (when OCKS1 = 18H set) fXX/12 4.00 MHz fXX 4.19 MHz fXX/2 (when OCKS1 = 10H set) fXX/24 8.00 MHz fXX 8.38 MHz fXX/3 (when OCKS1 = 11H set) fXX/36 12.00 MHz fXX 12.57 MHz fXX/4 (when OCKS1 = 12H set) fXX/48 16.00 MHz fXX 16.67 MHz fXX/5 (when OCKS1 = 13H set) fXX/60 20.00 MHz fXX 20.95 MHz fXX/12 4.00 MHz fXX 4.19 MHz 1 1 0 x <R> 1 1 1 0 Other than above Note 3 Note 3 fXX Setting prohibited - High-speed mode (SMCm bit = 1) Note 2 Note 2 Note 1 - - <R> Notes 1. fXX > 20 MHz is settable only in the V850ES/SG2-H. <R> 2. Settable only in the V850ES/SG2-H 3. Since the selection clock is fXX regardless of the value set to the OCKS1 register, clear the OCKS1 register to 00H (I2C division clock stopped status). Remarks 1. m = 1, 2 2. x: don't care 614 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (7) IIC division clock select registers 0, 1 (OCKS0, OCKS1) The OCKS0 and OCKS1 registers control the I2C0n division clock (n = 0 to 2). These registers control the I2C00 division clock via the OCKS0 register and the I2C01 and I2C02 division clocks via the OCKS1 register. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H OCKSm R/W 0 Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H 0 0 OCKSENm OCKSTHm 0 OCKSm1 OCKSm0 (m = 0, 1) Operation setting of I2C division clock OCKSENm 2 0 Disable I C division clock operation 1 Enable I2C division clock operation Selection of I2C division clock OCKSTHm OCKSm1 OCKSm0 0 0 0 fXX/2 0 0 1 fXX/3 0 1 0 fXX/4 0 1 1 fXX/5 1 0 0 fXX Other than above Setting prohibited (8) IIC shift registers 0 to 2 (IIC0 to IIC2) The IIC0 to IIC2 registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. These registers can be read or written in 8-bit units, but data should not be written to the IICn register during a data transfer. Access (read/write) the IICn register only during the wait period. Accessing this register in communication states other than the wait period is prohibited. However, for the master device, the IICn register can be written once only after the transmission trigger bit (IICCn.STTn bit) has been set to 1. A wait state is released by writing the IICn register during the wait period, and data transfer is started (n = 0 to 2). Reset sets these registers to 00H. After reset: 00H R/W 7 Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H, IIC2 FFFFFDA0H 6 5 4 3 2 1 0 IICn (n = 0 to 2) User's Manual U16541EJ5V1UD 615 2 CHAPTER 17 I C BUS (9) Slave address registers 0 to 2 (SVA0 to SVA2) The SVA0 to SVA2 registers hold the I2C bus's slave addresses. These registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. However, rewriting these registers is prohibited when the IICSn.STDn bit = 1 (start condition detection). Reset sets these registers to 00H. After reset: 00H R/W 7 Address: SVA0 FFFFFD83H, SVA1 FFFFFD93H, SVA2 FFFFFDA3H 6 5 4 3 SVAn 1 0 0 (n = 0 to 2) 616 2 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.5 I2C Bus Mode Functions 17.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows (n = 0 to 2). SCL0n ................ This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA0n ................ This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 17-6. Pin Configuration Diagram VDD Slave device Master device SCL0n SCL0n Clock output (Clock output) VDD (Clock input) Clock input SDA0n SDA0n Data output Data output Data input Data input User's Manual U16541EJ5V1UD 617 2 CHAPTER 17 I C BUS 17.6 I2C Bus Definitions and Control Methods The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. The transfer timing for the "start condition", "address", "transfer direction specification", "data", and "stop condition" generated on the I2C bus's serial data bus is shown below. Figure 17-7. I2C Bus Serial Data Transfer Timing 1 to 7 SCL0n 8 9 1 to 8 9 1 to 8 9 R/W ACK Data ACK Data ACK SDA0n Start Address condition Stop condition The master device generates the start condition, slave address, and stop condition. ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8bit data). The serial clock (SCL0n) is continuously output by the master device. However, in the slave device, the SCL0n pin's low-level period can be extended and a wait state can be inserted (n = 0 to 2). 17.6.1 Start condition A start condition is met when the SCL0n pin is high level and the SDA0n pin changes from high level to low level. The start condition for the SCL0n and SDA0n pins is generated that the master device to the slave device when starting a serial transfer. The slave device can defect the start condition (n = 0 to 2). Figure 17-8. Start Condition H SCL0n SDA0n A start condition is generated when the IICCn.STTn bit is set (1) after a stop condition has been detected (IICSn.SPDn bit = 1). When a start condition is detected, the IICSn.STDn bit is set (1) (n = 0 to 2). <R> Caution When the IICCn.IICEn bit of the V850ES/SG2 and V850ES/SG2-H is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level. 618 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the SVAn register. If the address data matches the values of the SVAn register, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition (n = 0 to 2). Figure 17-9. Address SCL0n 1 2 3 4 5 6 7 8 SDA0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W Address 9 Note INTIICn Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received during slave device operation. Remark n = 0 to 2 The slave address and the eighth bit, which specifies the transfer direction as described in 17.6.3 Transfer direction specification below, are written together to IIC shift register n (IICn) and then output. Received addresses are written to the IICn register (n = 0 to 2). The slave address is assigned to the higher 7 bits of the IICn register. User's Manual U16541EJ5V1UD 619 2 CHAPTER 17 I C BUS 17.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 17-10. Transfer Direction Specification SCL0n 1 2 3 4 5 6 7 8 SDA0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W 9 Transfer direction specification Note INTIICn Note The INTIICn signal is generated if a local address or extension code is received during slave device operation. Remark 620 n = 0 to 2 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.6.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues. The detection of ACK is confirmed with the IICSn.ACKDn bit. When the master device is the receiving device, after receiving the final data, it does not return ACK and generates the stop condition. When the slave device is the receiving device and does not return ACK, the master device generates either a stop condition or a restart condition, and then stops the current transmission. Failure to return ACK may be caused by the following factors. (a) Reception was not performed normally. (b) The final data was received. (c) The receiving device (slave) does not exist for the specified address. When the receiving device sets the SDA0n line to low level during the ninth clock, ACK is generated (normal reception). When the IICCn.ACKEn bit is set to 1, automatic ACK generation is enabled. Transmission of the eighth bit following the 7 address data bits causes the IICSn.TRCn bit to be set. Normally, set the ACKEn bit to 1 for reception (TRCn bit = 0). When the slave device is receiving (when TRCn bit = 0), if the slave device cannot receive data, clear the ACKEn bit to 0 to indicate to the master that no more data can be received. Similarly, when the master device is receiving (when TRCn bit = 0) and the subsequent data is not needed, clear the ACKEn bit to 0 to prevent ACK from being generated. This notifies the slave device (transmitting device) of the end of the data transmission (transmission stopped). Figure 17-11. ACK Remark SCL0n 1 2 3 4 5 6 7 SDA0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 8 9 R/W ACK n = 0 to 2 When the local address is received, ACK is automatically generated regardless of the value of the ACKEn bit. No ACK is generated if the received address is not a local address (NACK). When receiving the extension code, set the ACKEn bit to 1 in advance to generate ACK. The ACK generation method during data reception is based on the wait timing setting, as described by the following. * When 8-clock wait is selected (IICCn.WTIMn bit = 0): ACK is generated at the falling edge of the SCL0n pin's eighth clock if the ACKEn bit is set to 1 before the wait state cancellation. * When 9-clock wait is selected (IICCn.WTIMn bit = 1): ACK is generated if the ACKEn bit is set to 1 in advance. Remark n = 0 to 2 User's Manual U16541EJ5V1UD 621 2 CHAPTER 17 I C BUS 17.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition (n = 0 to 2). A stop condition is generated when the master device outputs to the slave device when serial transfer has been completed. When used as the slave device, the start condition can be detected. Figure 17-12. Stop Condition H SCL0n SDA0n Remark n = 0 to 2 A stop condition is generated when the IICCn.SPTn bit is set to 1. When the stop condition is detected, the IICSn.SPDn bit is set to 1 and the interrupt request signal (INTIICn) is generated when the IICCn.SPIEn bit is set to 1 (n = 0 to 2). 622 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.6.6 Wait state A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2). Figure 17-13. Wait State (1/2) (a) When master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and IICCn.ACKEn bit = 1) Master Master returns to high Wait after output impedance but slave is in wait state (low level). of ninth clock. IICn data write (cancel wait state) IICn 6 SCL0n 7 8 1 9 2 3 Slave Wait after output of eighth clock. FFH is written to IICn register or IICCn.WRELn bit is set to 1. IICn SCL0n ACKEn H Transfer lines Wait state from master Wait state from slave Remark SCL0n 6 7 8 SDA0n D2 D1 D0 9 ACK 1 2 3 D7 D6 D5 n = 0 to 2 User's Manual U16541EJ5V1UD 623 2 CHAPTER 17 I C BUS Figure 17-13. Wait State (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait after output of ninth clock. IICn data write (cancel wait state) Master IICn 6 SCL0n 7 8 1 9 2 3 Slave FFH is written to IICn register or WRELn bit is set to 1. IICn SCL0n ACKEn H Transfer lines Wait state Wait state from master/ from slave slave SCL0n 6 7 8 9 SDA0n D2 D1 D0 ACK 1 D7 2 3 D6 D5 Generate according to previously set ACKEn bit value Remark <R> n = 0 to 2 A wait state is automatically generated after generation of the start condition. A wait state is also automatically generated depending on the setting of the IICCn.WTIMn bit. Normally, when the IICCn.WRELn bit is set to 1 or when FFH is written to the IICn register on the receiving side, the wait state is canceled and the transmitting side writes data to the IICn register to cancel the wait state. The master device can also cancel the wait state via either of the following methods. * By setting the IICCn.STTn bit to 1 * By setting the IICCn.SPTn bit to 1 624 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.6.7 Wait state cancellation method In the case of I2C0n, wait state can be canceled normally in the following ways (n = 0 to 2). * By writing data to the IICn register * By setting the IICCn.WRELn bit to 1 (wait state cancellation) <R> * By setting the IICCn.STTn bit to 1 (start condition generation)Note <R> * By setting the IICCn.SPTn bit to 1 (stop condition generation)Note <R> Note Master only If any of these wait state cancellation actions is performed, I2C0n will cancel wait state and restart communication. When canceling wait state and sending data (including address), write data to the IICn register. To receive data after canceling wait state, or to complete data transmission, set the WRELn bit to 1. To generate a restart condition after canceling wait state, set the STTn bit to 1. To generate a stop condition after canceling wait state, set the SPTn bit to 1. Execute cancellation only once for each wait state. For example, if data is written to the IICn register following wait state cancellation by setting the WRELn bit to 1, conflict between the SDAn line change timing and IICn register write timing may result in the data output to the SDAn line may be incorrect. Even in other operations, if communication is stopped halfway, clearing the IICCn.IICEn bit to 0 will stop communication, enabling wait state to be cancelled. If the I2C bus dead-locks due to noise, etc., setting the IICCn.LRELn bit to 1 causes the communication operation to be exited, enabling wait state to be cancelled. User's Manual U16541EJ5V1UD 625 2 CHAPTER 17 I C BUS 17.7 I2C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing. Remarks 1. ST: Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK: Acknowledge D7 to D0: Data SP: Stop condition 2. n = 0 to 2 626 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When IICCn.WTIMn bit = 0 IICCn.SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK S3 SP S4 5 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B S3: IICSn register = 1000X000B (WTIMn bit = 1 Note ) S4: IICSn register = 1000XX00B 5: IICSn register = 00000001B <R> Note Set the WTIMn bit (1) and change the timing of generating the interrupt request signal (INTIICn) to generate the stop condition. Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP S3 4 S1: IICSn register = 1000X110B S2: IICSn register = 1000X100B S3: IICSn register = 1000XX00B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 627 2 CHAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 ST AD6 to AD0 R/W ACK S3 D7 to D0 S4 ACK S5 SP S6 7 S1: IICSn register = 1000X110B <R> S2: IICSn register = 1000X000B (WTIMn bit = 1 <R> S3: IICSn register = 1000XX00B (WTIMn bit = 0 <R> S4: IICSn register = 1000X110B <R> S5: IICSn register = 1000X000B (WTIMn bit = 1 Note 1 ) Note 2 ) Note 3 ) S6: IICSn register = 1000XX00B 7: IICSn register = 00000001B Notes 1. Set the WTIMn bit (1) and change the timing of generating the interrupt request signal <R> (INTIICn) to generate the start condition. <R> 2. Clear the WTIMn bit (0) to restore the original setting. <R> 3. Set the WTIMn bit (1) and change the timing of generating the interrupt request signal (INTIICn) to generate the stop condition. Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 STTn bit = 1 SPTn bit = 1 ACK S1 ST AD6 to AD0 S2 S1: IICSn register = 1000X110B S2: IICSn register = 1000XX00B S3: IICSn register = 1000X110B S4: IICSn register = 1000XX00B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 628 User's Manual U16541EJ5V1UD R/W ACK D7 to D0 S3 ACK SP S4 5 2 CHAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK S3 SP S4 5 S1: IICSn register = 1010X110B S2: IICSn register = 1010X000B <R> S3: IICSn register = 1010X000B (WTIMn bit = 1 Note ) S4: IICSn register = 1010XX00B 5: IICSn register = 00000001B <R> Note Set the WTIMn bit (1) and change the timing of generating the interrupt request signal (INTIICn) to generate the stop condition. Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP S3 4 S1: IICSn register = 1010X110B S2: IICSn register = 1010X100B S3: IICSn register = 1010XX00B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 629 2 CHAPTER 17 I C BUS 17.7.2 Slave device operation (when receiving slave address (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 4 S3 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X000B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when IICCn.SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 S1: IICSn register = 0001X110B S2: IICSn register = 0001X100B S3: IICSn register = 0001XX00B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 630 User's Manual U16541EJ5V1UD ACK SP S3 4 2 CHAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 S3 ACK SP 5 S4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X110B S4: IICSn register = 0001X000B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 ACK S1 ST AD6 to AD0 S2 R/W ACK D7 to D0 S3 ACK SP S4 5 S1: IICSn register = 0001X110B S2: IICSn register = 0001XX00B S3: IICSn register = 0001X110B S4: IICSn register = 0001XX00B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 631 2 CHAPTER 17 I C BUS (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (extension code reception)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W S2 ACK D7 to D0 S3 ACK SP 5 S4 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B S3: IICSn register = 0010X010B S4: IICSn register = 0010X000B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 (after restart, address mismatch (extension code reception)) ST AD6 to AD0 R/W ACK D7 to D0 ACK S1 ST AD6 to AD0 S2 S1: IICSn register = 0001X110B S2: IICSn register = 0001XX00B S3: IICSn register = 0010X010B S4: IICSn register = 0010X110B S5: IICSn register = 0010XX00B 6: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 632 User's Manual U16541EJ5V1UD R/W ACK S3 D7 to D0 S4 ACK SP S5 6 2 CHAPTER 17 I C BUS (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 ACK SP 4 S3 S1: IICSn register = 0001X110B S2: IICSn register = 0001X000B <R> S3: IICSn register = 00000110B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK S1 ST AD6 to AD0 S2 R/W ACK D7 to D0 S3 ACK SP 4 S1: IICSn register = 0001X110B S2: IICSn register = 0001XX00B <R> S3: IICSn register = 00000110B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 633 2 CHAPTER 17 I C BUS 17.7.3 Slave device operation (when receiving extension code) <R> The device always participates in communication when it receives the extension code. (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 4 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X000B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when IICCn.SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK S1 D7 to D0 S2 ACK D7 to D0 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010X100B S4: IICSn register = 0010XX00B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 634 User's Manual U16541EJ5V1UD ACK SP S4 5 2 CHAPTER 17 I C BUS (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 S3 ACK SP 5 S4 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0001X110B S4: IICSn register = 0001X000B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 (after restart, address match) ST AD6 to AD0 R/W ACK S1 D7 to D0 ACK S2 ST AD6 to AD0 S3 R/W ACK D7 to D0 S4 ACK SP S5 6 S1: IICSn register = 0010X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010XX00B S4: IICSn register = 0001X110B S5: IICSn register = 0001XX00B 6: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 635 2 CHAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W S2 ACK D7 to D0 S3 ACK SP 5 S4 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X010B S4: IICSn register = 0010X000B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 (after restart, extension code reception) ST AD6 to AD0 R/W ACK S1 D7 to D0 ACK S2 ST AD6 to AD0 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010XX00B S4: IICSn register = 0010X010B S5: IICSn register = 0010X110B S6: IICSn register = 0010XX00B 7: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 636 User's Manual U16541EJ5V1UD R/W ACK S4 D7 to D0 S5 ACK SP S6 7 2 CHAPTER 17 I C BUS (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK ST AD6 to AD0 R/W ACK S2 D7 to D0 ACK SP 4 S3 S1: IICSn register = 0010X010B S2: IICSn register = 0010X000B S3: IICSn register = 00000110B <R> 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 (after restart, address mismatch (= not extension code)) ST AD6 to AD0 R/W ACK S1 D7 to D0 ACK S2 ST AD6 to AD0 S3 R/W ACK D7 to D0 S4 ACK SP 5 S1: IICSn register = 0010X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010XX00B <R> S4: IICSn register = 00000110B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 637 2 CHAPTER 17 I C BUS 17.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICSn register = 00000001B Remarks 1. : Generated only when SPIEn bit = 1 2. n = 0 to 2 638 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.7.5 Arbitration loss operation (operation as slave after arbitration loss) <R> When the device is used as the master in a multi-master system, read the IICSn.MSTSn bit to check the arbitration result each time the INTIICn interrupt has been generated. (1) When arbitration loss occurs during transmission of slave address data <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 4 S3 S1: IICSn register = 0101X110B S2: IICSn register = 0001X000B S3: IICSn register = 0001X000B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when IICCn.SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP S3 4 S1: IICSn register = 0101X110B S2: IICSn register = 0001X100B S3: IICSn register = 0001XX00B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 639 2 CHAPTER 17 I C BUS (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK SP 4 S3 S1: IICSn register = 0110X010B S2: IICSn register = 0010X000B S3: IICSn register = 0010X000B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK S1 D7 to D0 S2 ACK D7 to D0 S3 S1: IICSn register = 0110X010B S2: IICSn register = 0010X110B S3: IICSn register = 0010X100B S4: IICSn register = 0010XX00B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 640 User's Manual U16541EJ5V1UD ACK SP S4 5 2 CHAPTER 17 I C BUS 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) <R> When the device is used as the master in a multi-master system, read the IICSn.MSTSn bit to check the arbitration result each time the INTIICn interrupt has been generated. (1) When arbitration loss occurs during transmission of slave address data ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 2 S1 S1: IICSn register = 01000110B 2: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when IICCn.SPIEn bit = 1 2. n = 0 to 2 (2) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 SP 2 S1 S1: ACK IICSn register = 0110X010B IICCn.LRELn bit is set to 1 by software 2: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 641 2 CHAPTER 17 I C BUS (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 ACK SP 3 S2 S1: IICSn register = 10001110B S2: IICSn register = 01000000B 3: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 2. n = 0 to 2 <2> When WTIMn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 S1: IICSn register = 10001110B S2: IICSn register = 01000100B 3: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 2. n = 0 to 2 642 User's Manual U16541EJ5V1UD ACK SP 3 2 CHAPTER 17 I C BUS (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK S1 D7 to D0 ACK SP 3 S2 S1: IICSn register = 1000X110B S2: IICSn register = 01000110B 3: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. Dn = D6 to D0 n = 0 to 2 <2> Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 S1 R/W ACK S2 D7 to D0 ACK SP 3 S1: IICSn register = 1000X110B S2: IICSn register = 0110X010B IICCn.LRELn bit is set to 1 by software 3: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. Dn = D6 to D0 n = 0 to 2 User's Manual U16541EJ5V1UD 643 2 CHAPTER 17 I C BUS (5) When arbitration loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn SP 2 S1 S1: IICSn register = 1000X110B 2: IICSn register = 01000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. Dn = D6 to D0 n = 0 to 2 644 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1> When WTIMn bit = 0 IICCn.STTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 D7 to D0 S3 ACK D7 to D0 ACK SP 5 S4 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) <R> S3: IICSn register = 1000X100B (WTIMn bit = 0) S4: IICSn register = 01000000B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 IICCn.STTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK D7 to D0 S3 ACK SP 4 S1: IICSn register = 1000X110B <R> S2: IICSn register = 1000X100B S3: IICSn register = 01000100B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 645 2 CHAPTER 17 I C BUS (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIMn bit = 0 STTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 SP 4 S3 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) S3: IICSn register = 1000XX00B 4: IICSn register = 01000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 STTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK SP S2 3 S1: IICSn register = 1000X110B S2: IICSn register = 1000XX00B 3: IICSn register = 01000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 646 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1> When WTIMn bit = 0 IICCn.SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK S2 D7 to D0 S3 ACK D7 to D0 ACK SP 5 S4 S1: IICSn register = 1000X110B S2: IICSn register = 1000X000B (WTIMn bit = 1) <R> S3: IICSn register = 1000X100B (WTIMn bit = 0) <R> S4: IICSn register = 01000100B 5: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 <2> When WTIMn bit = 1 IICCn.SPTn bit = 1 ST AD6 to AD0 R/W ACK D7 to D0 S1 ACK D7 to D0 S2 ACK D7 to D0 S3 ACK SP 4 S1: IICSn register = 1000X110B <R> S2: IICSn register = 1000X100B <R> S3: IICSn register = 01000100B 4: IICSn register = 00000001B Remarks 1. S: Always generated : Generated only when SPIEn bit = 1 X: don't care 2. n = 0 to 2 User's Manual U16541EJ5V1UD 647 2 CHAPTER 17 I C BUS 17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below (n = 0 to 2). Table 17-3. INTIICn Generation Timing and Wait Control WTIMn Bit During Slave Device Operation Address 0 1 Notes 1. 9 Notes 1, 2 9 Notes 1, 2 Data Reception 8 Note 2 9 Note 2 During Master Device Operation Data Transmission Address Data Reception Data Transmission 8 Note 2 9 8 8 9 Note 2 9 9 9 The slave device's INTIICn signal and wait period occur at the falling edge of the ninth clock only when there is a match with the address set to the SVAn register. At this point, the ACK is generated regardless of the value set to the IICCn.ACKEn bit. For a slave device that has received an extension code, the INTIICn signal occurs at the falling edge of the eighth clock. When the address does not match after restart, the INTIICn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. If the received address does not match the contents of the SVAn register and an extension code is not received, neither the INTIICn signal nor a wait occurs. Remarks 1. The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0 to 2 (1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined regardless of the WTIMn bit. * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIMn bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing is determined according to the WTIMn bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing is determined according to the WTIMn bit. 648 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS (4) Wait cancellation method The four wait cancellation methods are as follows. * By writing data to the IICn register * By setting the IICCn.WRELn bit to 1 (wait cancellation) * By setting the IICCn.STTn bit to 1 (start condition generation)Note * By setting the IICCn.SPTn bit to 1 (stop condition generation)Note Note Master only When an 8-clock wait has been selected (WTIMn bit = 0), whether or not the ACK has been generated must be determined prior to wait cancellation. Remark n = 0 to 2 (5) Stop condition detection The INTIICn signal is generated when a stop condition is detected. Remark n = 0 to 2 17.9 Address Match Detection Method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the master device, or when an extension code has been received (n = 0 to 2). 17.10 Error Detection In I2C bus mode, the status of the serial data bus pin (SDA0n) during data transmission is captured by the IICn register of the transmitting device, so the data of the IICn register prior to transmission can be compared with the transmitted IICn data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match (n = 0 to 2). User's Manual U16541EJ5V1UD 649 2 CHAPTER 17 I C BUS 17.11 Extension Code (1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn bit) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth clock (n = 0 to 2). The local address stored in the SVAn register is not affected. (2) If 11110xx0 is set to the SVAn register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. Note that the INTIICn signal occurs at the falling edge of the eighth clock (n = 0 to 2) * Higher four bits of data match: EXCn bit = 1 * Seven bits of data match: IICSn.COIn bit = 1 (3) Since the processing after the interrupt request signal occurs differs according to the data that follows the extension code, such processing is performed by software. <R> The device participates in communication when it receives the extension code while it is operating as a slave, even if the address does not match. For example, when operation as a slave is not desired after the extension code is received, set the IICCn.LRELn bit to 1 and the CPU will enter the next communication wait state. Table 17-4. Extension Code Bit Definitions Slave Address 650 R/W Bit Description 0000 000 0 General call address 0000 000 1 Start byte 0000 001 X CBUS address 0000 010 X Address that is reserved for different bus format 1111 0xx X 10-bit slave address specification User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.12 Arbitration When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs. This kind of operation is called arbitration (n = 0 to 2). When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.ALDn bit) is set to 1 via the timing by which the arbitration loss occurred, and the SCL0n and SDA0n lines are both set to high impedance, which releases the bus (n = 0 to 2). Arbitration loss is detected based on the timing of the next interrupt request signal (INTIICn) (the eighth or ninth clock, when a stop condition is detected, etc.) and the setting of the ALDn bit to 1, which is made by software (n = 0 to 2). For details of interrupt request timing, see 17.7 I2C Interrupt Request Signals (INTIICn). Figure 17-14. Arbitration Timing Example Master 1 Hi-Z SCL0n Hi-Z SDA0n Master 1 loses arbitration Master 2 SCL0n SDA0n Transfer lines SCL0n SDA0n Remark n = 0 to 2 User's Manual U16541EJ5V1UD 651 2 CHAPTER 17 I C BUS Table 17-5. Status During Arbitration and Interrupt Request Signal Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 Transmitting address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission Transmitting extension code Read/write data after extension code transmission Transmitting data ACK transfer period after data reception When restart condition is detected during data transfer Note 2 When stop condition is detected during data transfer When stop condition is generated (when IICCn.SPIEn bit = 1) When SDA0n pin is low level while attempting to generate At falling edge of eighth or ninth clock following byte transfer Note 1 restart condition When stop condition is detected while attempting to Note 2 When stop condition is generated (when IICCn.SPIEn bit = 1) generate restart condition When DSA0n pin is low level while attempting to generate Note 1 At falling edge of eighth or ninth clock following byte transfer stop condition When SCL0n pin is low level while attempting to generate restart condition Notes 1. When the IICCn.WTIMn bit = 1, an INTIICn signal occurs at the falling edge of the ninth clock. When the WTIMn bit = 0 and the extension code's slave address is received, an INTIICn signal occurs at the falling edge of the eighth clock (n = 0 to 2). 2. When there is a possibility that arbitration will occur, set the SPIEn bit to 1 for master device operation (n = 0 to 2). 17.13 Wakeup Function The I2C bus slave function is a function that generates an interrupt request signal (INTIICn) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary the INTIICn signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. However, when a stop condition is detected, the IICCn.SPIEn bit is set regardless of the wakeup function, and this determines whether INTIICn signal is enabled or disabled (n = 0 to 2). 652 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.14 Communication Reservation 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when the IICCn.LRELn bit was set to 1) (n = 0 to 2). If the IICCn.STTn bit is set to 1 while the bus is not used, a start condition is automatically generated and a wait status is set after the bus is released (after a stop condition is detected). <R> The device automatically starts communication as the master when an address is written to the IICn register after the IICCn.SPIEn bit has been set (1) and release of the bus has been detected (i.e., the stop condition has been detected) by generation of an interrupt request (INTIICn). Data written to the IICn register is invalid before the stop condition is detected. When the STTn bit has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status (n = 0 to 2). If the bus has been released ............................................. A start condition is generated If the bus has not been released (standby mode) ............. Communication reservation To detect which operation mode has been determined for the STTn bit, set the STTn bit to 1, wait for the wait period, then check the IICSn.MSTSn bit (n = 0 to 2). The wait periods, which should be set via software, are listed in Table 17-6. These wait periods can be set by the SMCn, CLn1, and CLn0 bits of the IICCLn register and the IICXn.CLXn bit (n = 0 to 2). User's Manual U16541EJ5V1UD 653 2 CHAPTER 17 I C BUS Table 17-6. Wait Periods Clock Selection <R> <R> <R> <R> CLXn SMCn CLn1 CLn0 fXX (when OCKSm = 18H set) 0 0 0 0 26 clocks fXX/2 (when OCKSm = 10H set) 0 0 0 0 52 clocks fXX/3 (when OCKSm = 11H set) 0 0 0 0 78 clocks fXX/4 (when OCKSm = 12H set) 0 0 0 0 104 clocks fXX/5 (when OCKSm = 13H set) 0 0 0 0 130 clocks fXX (when OCKSm = 18H set) 0 0 0 1 47 clocks fXX/2 (when OCKSm = 10H set) 0 0 0 1 94 clocks fXX/3 (when OCKSm = 11H set) 0 0 0 1 141 clocks fXX/4 (when OCKSm = 12H set) 0 0 0 1 188 clocks fXX/5 (when OCKSm = 13H set) 0 0 0 1 235 clocks fXX 0 0 1 0 47 clocks fXX (when OCKSm = 18H set) 0 1 0 x 16 clocks fXX/2 (when OCKSm = 10H set) 0 1 0 x 32 clocks fXX/3 (when OCKSm = 11H set) 0 1 0 x 48 clocks fXX/4 (when OCKSm = 12H set) 0 1 0 x 64 clocks fXX/5 (when OCKSm = 13H set) 0 1 0 x 80 clocks fXX 0 1 1 0 16 clocks fXX (when OCKSm = 18H set) 1 1 0 x 10 clocks fXX/2 (when OCKSm = 10H set) 1 1 0 x 20 clocks fXX/3 (when OCKSm = 11H set) 1 1 0 x 30 clocks fXX/4 (when OCKSm = 12H set) 1 1 0 x 40 clocks fXX/5 (when OCKSm = 13H set) 1 1 0 x 50 clocks fXX 1 1 1 0 10 clocks Note V850ES/SG2-H only Remarks 1. n = 0 to 2 m = 0, 1 2. x = don't care The communication reservation timing is shown below. 654 User's Manual U16541EJ5V1UD Wait Period Note Note Note 2 CHAPTER 17 I C BUS Figure 17-15. Communication Reservation Timing Program processing Hardware processing <R> SCL0n <R> SDA0n 1 2 3 Write to IICn STTn =1 Set SPDn and INTIICn Communication reservation 4 5 6 7 8 9 Set STDn 1 2 3 4 5 6 Generated by master with bus access Remark n = 0 to 2 IICn: IICCn shift register n STTn: Bit of IICCn register STDn: Bit of IICSn register SPDn: Bit of IICSn register Communication reservations are accepted via the following timing. After the IICSn.STDn bit is set to 1, a communication reservation can be made by setting the IICCn.STTn bit to 1 before a stop condition is detected (n = 0 to 2). Figure 17-16. Timing for Accepting Communication Reservations SCL0n SDA0n STDn SPDn Standby mode Remark n = 0 to 2 User's Manual U16541EJ5V1UD 655 2 CHAPTER 17 I C BUS The communication reservation flowchart is illustrated below. Figure 17-17. Communication Reservation Flowchart DI SET1 STTn Define communication reservation Wait Sets STTn bit (communication reservation). Defines that communication reservation is in effect (defines and sets user flag to any part of RAM). Secures wait period set by software (see Table 17-6). Note (Communication reservation) Yes MSTSn bit = 0? Confirmation of communication reservation No (Generate start condition) Cancel communication reservation IICn register xxH Clears user flag. IICn register write operation EI Note The communication reservation operation executes a write to the IICn register when a stop condition interrupt request occurs. Remark 656 n = 0 to 2 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. There are two modes in which the bus is not used * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released when the IICCn.LRELn bit was set to 1) (n = 0 to 2). To confirm whether the start condition was generated or request was rejected, check the IICFn.STCFn flag. The time shown in Table 17-7 is required until the STCFn flag is set after setting the STTn bit to 1. Therefore, secure the time by software. <R> Table 17-7. Wait Periods Selection Clock OCKSE OCKSTH OCKSm OCKSm Nm m 1 0 CLn1 CLn0 Wait Period fXX/2 (when setting OCKSm = 10H) 1 0 0 0 0 X 6 clocks fXX/3 (when setting OCKSm = 11H) 1 0 0 1 0 X 9 clocks fXX/4 (when setting OCKSm = 12H) 1 0 1 0 0 X 12 clocks fXX/5 (when setting OCKSm = 13H) 1 0 1 1 0 X 15 clocks fXX (when setting OCKSm = 18H) 1 1 0 0 0 X 3 clocks fXX 0 0 0 0 1 0 3 clocks fXX/2 (when setting OCKSm = 10H) 1 0 0 0 1 1 6 clocks fXX/3 (when setting OCKSm = 11H) 1 0 0 1 1 1 9 clocks fXX/4 (when setting OCKSm = 12H) 1 0 1 0 1 1 12 clocks fXX/5 (when setting OCKSm = 13H) 1 0 1 1 1 1 15 clocks fXX (when setting OCKSm = 18H) 1 1 0 0 1 1 3 clocks Remarks 1. x: don't care 2. n = 0 to 2 m = 0, 1 3. Clock = fXX (main clock frequency) User's Manual U16541EJ5V1UD 657 2 CHAPTER 17 I C BUS 17.15 Cautions (1) When IICFn.STCENn bit = 0 Immediately after the I2C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. Use the following sequence for generating a stop condition. <1> Set the IICCLn register. <2> Set the IICCn.IICEn bit. <3> Set the IICCn.SPTn bit. (2) When IICFn.STCENn bit = 1 Immediately after I2C0n operation is enabled, the bus released status (IICBSYn bit = 0) is recognized regardless of the actual bus status. To generate the first start condition (IICCn.STTn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. <R> (3) When the IICCn.IICEn bit of the V850ES/SG2 and V850ES/SG2-H is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level. (4) Determine the operation clock frequency by the IICCLn, IICXn, and OCKSm registers before enabling the operation (IICCn.IICEn bit = 1). To change the operation clock frequency, clear the IICCn.IICEn bit to 0 once. (5) After the IICCn.STTn and IICCn.SPTn bits have been set to 1, they must not be re-set without being cleared to 0 first. (6) If transmission has been reserved, set the IICCN.SPIEn bit to 1 so that an interrupt request is generated by the detection of a stop condition. After an interrupt request has been generated, the wait status will be released by writing communication data to I2Cn, then transferring will begin. If an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait status because an interrupt request was not generated. However, it is not necessary to set the SPIEn bit to 1 for the software to detect the IICSn.MSTSn bit. Remark 658 n = 0 to 2 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS <R> 17.16 Communication Operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the V850ES/SG2 or V850ES/SG2-H as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup. If communication with the slave is required, prepare the communication and then execute communication processing. (2) Master operation in multimaster system In the I2C0n bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a certain period (1 frame), the V850ES/SG2 or V850ES/SG2-H takes part in a communication with bus released state. This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the V850ES/SG2 or V850ES/SG2-H looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave. The actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) Slave operation An example of when the V850ES/SG2 or V850ES/SG2-H is used as the slave of the I2C0n bus is shown below. When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the INTIICn interrupt occurrence (communication waiting). When the INTIICn interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. By checking the flags, necessary communication processing is performed. Remark n = 0 to 2 User's Manual U16541EJ5V1UD 659 2 CHAPTER 17 I C BUS 17.16.1 Master operation in single master system Figure 17-18. Master Operation in Single Master System START Initialize I2C busNote See Table 4-15 Using Port Pin as Alternate-Function Pin to set the I2C mode before this function is used. Initial settings Set ports IICXn 0XH IICCLn XXH Transfer clock selection SVAn XXH Local address setting IICFn 0XH Set STCENn, IICRSVn = 0 Start condition setting IICCn XXH ACKEn = WTIMn = SPIEn = 1 IICEn = 1 STCENn = 1? Yes No SPTn = 1 INTIICn interrupt occurred? Communication start preparation (stop condition generation) No Waiting for stop condition detection Yes STTn = 1 Communication start preparation (start condition generation) IICn write Communication start (address, transfer direction specification) INTIICn interrupt occurred? No Waiting for ACK detection Yes No ACKDn = 1? Yes TRCn = 1? No Communication processing ACKD bit = 1? ACKEn = 1 WTIMn = 0 Yes IICn Write INTIIC interrupt occurred? Transmission start WRELn = 1 No Waiting for data transmission INTIIC interrupt occurred? Yes Yes ACKDn = 1? No Reception start No Waiting for data reception IIC Read Yes No Transfer completed? No Transfer completed? Yes Yes Restarted? Yes ACKEn = 0 WTIMn = WRELn = 1 No SPTn = 1 INTIIC interrupt occurred? No Waiting for ACK detection Yes END Note Release the I2C0n bus (SCL0n, SDA0n pins = high level) in conformity with the specifications of the product in communication. For example, when the EEPROMTM outputs a low level to the SDA0n pin, set the SCL0n pin to the output port and output clock pulses from that output port until when the SDA0n pin is constantly high level. Remarks 1. For the transmission and reception formats, conform to the specifications of the product in communication. 2. n = 0 to 2 660 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS 17.16.2 Master operation in multimaster system Figure 17-19. Master Operation in Multimaster System (1/3) START See Table 4-15 Using Port Pin as Alternate-Function Pin to set the I2C mode before this function is used. Set ports IICXn 0XH IICCLn XXH Transfer clock selection SVAn XXH Local address setting IICFn 0XH Set STCENn, set IICRSVn bit Start condition setting Initial settings IICCn XXH ACKEn = WTIMn = SPIEn = 1 IICEn = 1 Confirm bus statusNote Bus release status for a certain period Confirmation of bus status is in progress No INTIICn interrupt occurred? No STCENn = 1? Yes SPDn = 1? Communication start preparation (stop condition generation) SPTn = 1 Yes INTIICn interrupt occurred? No No Waiting for stop condition detection Yes Yes Slave operation SPDn = 1? Yes No Slave operation * Waiting for slave specification from another master * Waiting for communication start request (depending on user program) 1 Master operation started? No (no communication start request) Communication waiting Yes (communication start request issued) SPIEn = 0 INTIICn interrupt occurred? SPIEn = 1 No Waiting for communication request Yes IICRSVn = 0? No Slave operation Yes A Communication reservation enable B Communication reservation disable Note Confirm that the bus release status (IICCLn.CLDn bit = 1, IICCLn.DADn bit = 1) has been maintained for a certain period (1 frame, for example). When the SDA0n pin is constantly low level, determine whether to release the I2C0n bus (SCL0n, SDA0n pins = high level) by referring to the specifications of the product in communication. Remark n = 0 to 2 User's Manual U16541EJ5V1UD 661 2 CHAPTER 17 I C BUS Figure 17-19. Master Operation in Multimaster System (2/3) A Communication reservation enabled Communication start preparation (start condition generation) STTn = 1 Securing wait time by software (see Table 17-6) Communication processing Wait MSTSn = 1? No Yes INTIICn interrupt occurred? Yes No Wait status after stop condition detection and start condition generation by communication reservation function C EXCn = 1 or COIn =1? Yes Slave operation B Communication reservation disabled IICBSYn = 0? No Yes D STTn = 1 Communication processing No Waiting for bus release (communication reserved) Wait STCFn = 0? Yes Communication start preparation (start condition generation) Securing wait time by software (see Table 17-7) No INTIICn interrupt occurred? No Waiting for bus release Yes C EXCn = 1 or COIn =1? No D Remark 662 n = 0 to 2 User's Manual U16541EJ5V1UD Yes Stop condition detection Slave operation 2 CHAPTER 17 I C BUS Figure 17-19. Master Operation in Multimaster System (3/3) C IICn write INTIICn interrupt occurred? Communication start (address, transfer direction specification) No Waiting for ACK detection Yes MSTSn = 1? No Yes No 2 ACKDn = 1? Yes TRCn = 1? No ACKEn = 1 WTIMn = 0 Yes WTIMn = 1 Communication processing WRELn = 1 IICn write INTIICn interrupt occurred? INTIICn interrupt occurred? No Waiting for data transmission Yes MSTSn = 1? Yes MSTSn = 1? No Waiting for data transmission No No Yes Yes ACKDn = 1? Reception start Transmission start 2 2 IICn read No Transfer completed? No Yes Yes No WTIMn = WRELn = 1 ACKEn = 0 Transfer completed? Yes INTIICn interrupt occurred? Restarted? No Waiting for ACK detection No Yes SPTn = 1 Yes MSTSn = 1? STTn = 1 END Yes No 2 Communication processing C 2 EXCn = 1 or COIn = 1? No Yes Slave operation 1 Not in communication Remarks 1. Conform the transmission and reception formats to the specifications of the product in communication. 2. When using the V850ES/SG2, V850ES/SG2-H as the master in the multimaster system, read the IICSn.MSTSn bit for each INTIICn interrupt occurrence to confirm the arbitration result. 3. When using the V850ES/SG2, V850ES/SG2-H as the slave in the multimaster system, confirm the status using the IICSn and IICFn registers for each INTIICn interrupt occurrence to determine the next processing. 4. n = 0 to 2 User's Manual U16541EJ5V1UD 663 2 CHAPTER 17 I C BUS 17.16.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary. The following description assumes that data communication does not support extension codes. Also, it is assumed that the INTIICn interrupt servicing performs only status change processing and that the actual data communication is performed during the main processing. Figure 17-20. Software Outline During Slave Operation Flag INTIICn signal Interrupt servicing Setting, etc. Main processing I2C Data Setting, etc. Therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main processing instead of INTIICn signal. (1) Communication mode flag This flag indicates the following communication statuses. Clear mode: Data communication not in progress Communication mode: Data communication in progress (valid address detection stop condition detection, ACK from master not detected, address mismatch) (2) Ready flag This flag indicates that data communication is enabled. This is the same status as an INTIICn interrupt during normal data transfer. This flag is set in the interrupt processing block and cleared in the main processing block. The ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clear processing (the address match is regarded as a request for the next data). (3) Communication direction flag This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit. 664 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS The following shows the operation of the main processing block during slave operation. Start I2C0n and wait for the communication enabled status. When communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). For transmission, repeat the transmission operation until the master device stops returning ACK. When the master device stops returning ACK, transfer is complete. For reception, receive the required number of data and do not return ACK for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications. User's Manual U16541EJ5V1UD 665 2 CHAPTER 17 I C BUS <R> Figure 17-21. Slave Operation Flowchart (1) START See Table 4-15 Using Port Pin as Alternate-Function Pin to set the I2C mode before this function is used. Set ports IICXn 0XH Transfer clock selection Initial settings IICCLn XXH SVAn XXH Local address setting IICFn 0XH Start condition setting Set IICRSVn IICCn XXH ACKEn = WTIMn = 1 SPIEn = 0, IICEn = 1 No Communication mode flag = 1? Yes No Communication direction flag = 1? Yes WRELn = 1 Transmission start Communication processing IICn write Communication mode flag = 1? No Communication mode flag = 1? Communication direction flag = 0? Communication direction flag = 1? Yes No Yes No Ready flag = 1? Ready flag = 1? Yes Yes IICn read Clear ready flag Yes ACKDn = 1? No Clear communication mode flag WRELn = 1 Remark 666 No Yes Yes No Reception start n = 0 to 2 User's Manual U16541EJ5V1UD Clear ready flag No 2 CHAPTER 17 I C BUS The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here). During an INTIICn interrupt, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated. If the address matches, the communication mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> For data transmission/reception, when the ready flag is set, operation returns from the interrupt while the I2C0n bus remains in the wait status. Remark <1> to <3> in the above correspond to <1> to <3> in Figure 17-22 Slave Operation Flowchart (2). Figure 17-22. Slave Operation Flowchart (2) <R> INTIICn occurred Yes <1> Yes <2> SPDn = 1? No STDn = 1? No No <3> COIn = 1? Yes Set ready flag Communication direction flag TRCn Set communication mode flag Clear ready flag Clear communication direction flag, ready flag, and communication mode flag Interrupt servicing completed Remark n = 0 to 2 User's Manual U16541EJ5V1UD 667 2 CHAPTER 17 I C BUS 17.17 Timing of Data Communication When using I2C bus mode, the master device generates an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device. The shift operation of the IICn register is synchronized with the falling edge of the serial clock pin (SCL0n). The transmit data is transferred to the SO latch and is output (MSB first) via the SDA0n pin. Data input via the SDA0n pin is captured by the IICn register at the rising edge of the SCL0n pin. The data communication timing is shown below. Remark 668 n = 0 to 2 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS <R> Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ Address Processing by master device IICn address IICn IICn data ACKDn STDn SPDn WTIMn H ACKEn H MSTSn STTn SPTn L WRELn L INTIICn TRCn H Transmit Transfer lines 1 SCL0n 2 3 4 5 6 7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n 8 9 1 2 3 4 W ACK D7 D6 D5 D4 Start condition Processing by slave device IICn FFH Note IICn ACKDn STDn SPDn WTIMn H ACKEn H MSTSn L STTn L SPTn L Note WRELn INTIICn (When EXCn = 1) TRCn L Receive Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0 to 2 User's Manual U16541EJ5V1UD 669 2 CHAPTER 17 I C BUS <R> Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn data IICn IICn data ACKDn STDn L SPDn L WTIMn H ACKEn H MSTSn H STTn L SPTn L WRELn L INTIICn TRCn Transmit H Transfer lines SCL0n 8 9 1 2 3 4 5 6 7 8 9 SDA0n D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 D7 D6 D5 Processing by slave device IICn FFH IICn Note IICn FFH ACKDn STDn L SPDn L WTIMn H ACKEn H MSTSn L STTn L SPTn L Note WRELn Note INTIICn TRCn L Receive Note To cancel slave wait, write FFH to IICn or set WRELn. Remark 670 n = 0 to 2 User's Manual U16541EJ5V1UD Note 2 CHAPTER 17 I C BUS <R> Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IICn data IICn IICn data ACKDn STDn SPDn WTIMn H ACKEn H MSTSn STTn SPTn WRELn L INTIICn (When SPIEn = 1) TRCn H Transmit Transfer lines SCL0n 1 2 3 4 5 6 7 8 9 SDA0n D7 D6 D5 D4 D3 D2 D1 D0 ACK IICn FFH IICn FFH Note 2 AD6 AD5 Stop condition Processing by slave device IICn 1 Start condition Note ACKDn STDn SPDn WTIMn H ACKEn H MSTSn L STTn L SPTn L Note WRELn Note INTIICn (When SPIEn = 1) TRCn L Receive Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0 to 2 User's Manual U16541EJ5V1UD 671 2 CHAPTER 17 I C BUS <R> Figure 17-24. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ Address Processing by master device IICn address IICn IICn FFH Note ACKDn STDn SPDn WTIMn L ACKEn H MSTSn STTn L SPTn Note WRELn INTIICn TRCn Transfer lines 1 SCL0n 2 3 4 5 6 7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n 8 9 R ACK 1 D7 2 3 4 5 6 D6 D5 D4 D3 D2 Start condition Processing by slave device IICn data IICn ACKDn STDn SPDn WTIMn H ACKEn H MSTSn L STTn L SPTn L WRELn L INTIICn TRCn Note To cancel master wait, write FFH to IICn or set WRELn. Remark 672 n = 0 to 2 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS <R> Figure 17-24. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn FFH IICn IICn FFH Note Note ACKDn STDn L SPDn L WTIMn L ACKEn H MSTSn H STTn L SPTn L Note WRELn Note INTIICn TRCn L Receive Transfer lines SCL0n 8 9 SDA0n D0 ACK 1 D7 2 3 4 5 6 7 8 9 D6 D5 D4 D3 D2 D1 D0 ACK 1 D7 2 3 D6 D5 Processing by slave device IICn data IICn IICn data ACKDn STDn L SPDn L WTIMn H ACKEn H MSTSn L STTn L SPTn L WRELn L INTIICn TRCn H Transmit Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0 to 2 User's Manual U16541EJ5V1UD 673 2 CHAPTER 17 I C BUS <R> Figure 17-24. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IICn address IICn FFH IICn Note ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCL0n 1 2 3 4 5 6 7 8 SDA0n D7 D6 D5 D4 D3 D2 D1 D0 9 1 NACK Stop condition Processing by slave device AD6 Start condition IICn data IICn ACKDn STDn SPDn WTIMn H ACKEn H MSTSn L STTn L SPTn L WRELn INTIICn (When SPIEn = 1) TRCn Note To cancel master wait, write FFH to IICn or set WRELn. Remark 674 n = 0 to 2 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER IEBus (Inter Equipment Bus) is a small-scale digital data transfer system that transfers data between units. To <R> implement IEBus with the V850ES/SG2 and V850ES/SG2-H, an external IEBus driver and receiver are necessary because they are not provided. <R> The internal IEBus controller of the V850ES/SG2 and V850ES/SG2-H is of negative logic. <R> The following models of the V850ES/SG2 and V850ES/SG2-H have an on-chip IEBus controller. <R> * PD703270, 703270Y, 703271, 703271Y, 703272, 703272Y, 703273, 703273Y, 70F3271, 70F3271Y, 70F3273, 70F3273Y, 703272HY, 703273HY, 70F3273HY 18.1 Functions 18.1.1 Communication protocol of IEBus The communication protocol of the IEBus is as follows. (1) Multi-task mode All the units connected to the IEBus can transfer data to the other units. (2) Broadcasting communication function Communication between one unit and multiple units can be performed as follows. * Group-unit broadcast communication: Broadcast communication to group units * All-unit broadcast communication: Broadcast communication to all units. (3) Effective transfer rate <R> The effective transfer rate is in mode 1 or mode 2 (the V850ES/SG2 and V850ES/SG2-H do not support mode 0 for the effective transfer rate). * Mode 1: Approx. 17 kbps * Mode 2: Approx. 26 kbps Caution Different modes must not be mixed on one IEBus. (4) Communication mode Data transfer is executed in half-duplex asynchronous communication mode. (5) Access control: CSMA/CD (Carrier Sense Multiple Access with Collision Detection) The priority of the IEBus is as follows: <1> Broadcast communication takes precedence over individual communication (communication from one unit to another). <2> The lower master address takes precedence. (6) Communication scale The communication scale of IEBus is as follows. * Number of units: 50 MAX. * Cable length: Caution 150 m MAX. (when twisted pair cable is used) The communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the IEBus driver/receiver and IEBus. User's Manual U16541EJ5V1UD 675 CHAPTER 18 IEBus CONTROLLER 18.1.2 Determination of bus mastership (arbitration) An operation to occupy the bus is performed when a unit connected to the IEBus controls the other units. This operation is called arbitration. When two or more units simultaneously start transmission, arbitration is used to grant one of the units the permission to occupy the bus. Because only one unit is granted the bus mastership as a result of arbitration, the priority conditions of the bus are predetermined as follows. Caution The bus mastership is released if communication is aborted. (1) Priority by communication type Broadcast communication (communication from one unit to multiple units) takes precedence over normal communication (communication from one unit to another). (2) Priority by master address If the communication type is the same, communication with the lower master address takes precedence. A master address consists of 12 bits, with unit 000H having the highest priority and unit FFFH having the lowest priority. 18.1.3 Communication mode The IEBus has three communication modes each having a different transfer rate. The V850ES/SG2 and <R> V850ES/SG2-H support communication modes 1 and 2. The transfer rate and the maximum number of transfer bytes in one communication frame in communication modes 1 and 2 are as shown in Table 18-1. Table 18-1. Transfer Rate and Maximum Number of Transfer Bytes in Each Communication Mode Communication Mode Maximum Number of Transfer Bytes (Bytes/Frame) Effective Transfer Rate (kbps) 1 32 Approx. 17 2 128 Approx. 26 Note Note The effective transfer rate when the maximum number of transfer bytes is transmitted. Select the communication mode for each unit connected to the IEBus before starting communication. If the communication mode of the master unit and that of the partner unit (slave unit) are not the same, communication is not correctly executed. 18.1.4 Communication address With the IEBus, each unit is assigned a specific 12-bit address. This communication address consists of the following identification numbers. * Higher 4 bits: Group number (number to identify the group to which each unit belongs) * Lower 8 bits: Unit number (number to identify each unit in a group) 676 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER 18.1.5 Broadcast communication Normally, transmission or reception is performed between the master unit and its partner slave unit on a one-toone basis. During broadcast communication, however, two or more slave units exist and the master unit executes transmission to these slave units. Because two or more slave units exist, the NACK signal is returned by the communicating slave unit as an acknowledge bit. Whether broadcast communication or normal communication is to be executed is selected by the broadcast bit (for this bit, see 18.1.6 (2) Broadcast bit). Broadcast communication is classified into two types: group-unit broadcast communication and all-unit broadcast communication. Group-unit broadcast and all-unit broadcast are identified by the value of the slave address (for the slave address, see 18.1.6 (4) Slave address field). (1) Group-unit broadcast communication Broadcast communication is performed to the units in a group identified by the group number indicated by the higher 4 bits of the communication address. (2) All-unit broadcast communication Broadcast communication is performed to all the units, regardless of the value of the group number. 18.1.6 Transfer format of IEBus Figure 18-1 shows the transfer signal format of the IEBus. Figure 18-1. IEBus Transfer Signal Format Header Frame format Master address field Slave address field Telegraph Control field length field Slave Broad- Master Start Control cast address P address P A PA bit bit bit bit bit Data field TeleData graph PA length P A bit bit Data PA bit Remarks 1. P: Parity bit A: Acknowledge (ACK/NACK) bit 2. The master unit ignores the acknowledge bit during broadcast communication. (1) Start bit The start bit is a signal that informs the other units of the start of data transfer. The unit that is to start data transfer outputs a high-level signal (start bit) from the IETX pin for a specific time, and then starts outputting the broadcast bit. If another unit has already output its start bit when one unit is to output the start bit, this unit does not output the start bit but waits for completion of output of the start bit by the other unit. When the output of the start bit by the other unit is complete, the unit starts outputting the broadcast bit in synchronization with the completion of the start bit output by the other unit. The units other than the one that has started communication detect this start bit, and enter the reception status. User's Manual U16541EJ5V1UD 677 CHAPTER 18 IEBus CONTROLLER (2) Broadcast bit This bit indicates whether the master selects one slave (individual communication) or multiple slaves (broadcast communication) as the other party of communication. When the broadcast bit is 0, it indicates broadcast communication; when it is 1, individual communication is indicated. Broadcast communication is classified into two types: group-unit communication and all-unit communication. These communication types are identified by the value of the slave address (for the slave address, see 18.1.6 (4) Slave address field). Because two or more slave units exist as a partner slave unit of communication in the case of broadcast communication, the NACK signal is returned as an acknowledge bit in each field subsequent to the master address field. If two or more units start transmitting a communication frame at the same time, broadcast communication takes precedence over individual communication, and wins in arbitration. If one unit occupies the bus as the master, the value set to the broadcast request flag (BCR.ALLRQ bit) is output. (3) Master address field The master address field is output by the master to inform a slave of the master's address. The configuration of the master address field is as shown in Figure 18-2. If two or more units start transmitting the broadcast bit at the same time, the master address field makes a judgment of arbitration. The master address field compares the data it outputs with the data on the bus each time it has output one bit. If the master address output by the master address field is found to be different from the data on the bus as a result of comparison, it is assumed that the master has lost in arbitration. As a result, the master stops transmission and enters the reception status. Because the IEBus is configured of wired AND, the unit having the minimum master address of the units participating in arbitration (arbitration masters) wins in arbitration. After a 12-bit master address has been output, only one unit remains in the transmission status as one master unit. Next, this master unit outputs a parity bit, determines the master address of other unit, and starts outputting a slave address field. If one unit occupies the bus as the master, the address set by the UAR register is output. Figure 18-2. Master Address Field Master address field Master address (12 bits) MSB 678 Parity LSB User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (4) Slave address field The master outputs the address of the unit with which it is to communicate. Figure 18-3 shows the configuration of the slave address field. A parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake. Next, the master unit detects an ACK signal from the slave unit to confirm that the slave unit exists on the bus. When the master has detected the ACK signal, it starts outputting the control field. During broadcast communication, however, the master does not confirm the acknowledge bit but starts outputting the control field. The slave unit outputs the ACK signal if its slave address matches and if the slave detects that the parities of both the master address and slave address are even. The slave unit judges that the master address or slave address has not been correctly received and outputs the NACK signal if the parities are odd. At this time, the master unit is in the standby (monitor) status, and communication ends. During broadcast communication, the slave address is used to identify group-unit broadcast or all-unit broadcast, as follows:. If slave address is FFFH: All-unit broadcast communication If slave address is other than FFFH: Group-unit broadcast communication Remark The group No. during group-unit broadcasting communication is the value of the higher 4 bits of the slave address. If one unit occupies the bus as the master, the address set by the SAR register is output. Figure 18-3. Slave Address Field Slave address field Slave address (12 bits) Group No. Parity ACK Unit No. MSB LSB (5) Control field The master outputs the operation it requires the slave to perform, by using this field. The configuration of the control field is as shown in Figure 18-4. If the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an ACK signal and starts outputting the telegraph length field. If the slave unit cannot execute the function required by the master unit even if the parity is even, or if the parity is odd, the slave unit outputs the NACK signal, and returns to the standby (monitor) status. The master unit starts outputting the telegraph field after detecting the ACK signal. If the master can detect the NACK signal, the master unit enters the standby status, and communication ends. During broadcast communication, however, the master unit does not confirm the acknowledge bit, and starts outputting the telegraph length field. The contents of the control bits are shown below. User's Manual U16541EJ5V1UD 679 CHAPTER 18 IEBus CONTROLLER Table 18-2. Contents of Control Bits Bit 3 Note 1 Bit 2 Bit 1 Bit 0 Function 0 0 0 0 Read slave status 0 0 0 1 Undefined 0 0 1 0 Undefined 0 0 1 1 Read data and lock 0 1 0 0 Read lock address (lower 8 bits) 0 1 0 1 Read lock address (higher 4 bits) 0 1 1 0 Read slave status and unlock 0 1 1 1 Read data 1 0 0 0 Undefined 1 0 0 1 Undefined 1 0 1 0 Write command and lock 1 0 1 1 Write data and lock 1 1 0 0 Undefined 1 1 0 1 Undefined 1 1 1 0 Write command 1 1 1 1 Write data Note 2 Note 3 Note 3 Note 2 Note 2 Note 2 Notes 1. The telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 (MSB). If bit 3 is `1': Transfer from master unit to slave unit If bit 3 is `0': Transfer from slave unit to master unit 2. This is a control bit that specifies locking or unlocking (see 18.1.7 (4) Locking and unlocking). 3. The lock address is transferred in 1-byte (8-bit) units and is configured as follows: MSB LSB Control bit: 4H Control bit: 5H 680 Lower 8 bits Undefined User's Manual U16541EJ5V1UD Higher 4 bits CHAPTER 18 IEBus CONTROLLER If the control bit received from the master unit is not as shown in Table 18-3, the unit locked by the master unit rejects acknowledging the control bit, and outputs the NACK signal. Table 18-3. Control Field for Locked Slave Unit Bit 3 Bit 2 Bit 1 Bit 0 Function 0 0 0 0 Read slave status 0 1 0 0 Read lock address (lower 8 bits) 0 0 0 1 Read lock address (higher 4 bits) Moreover, units for which lock is not set by the master unit reject acknowledgment and output a NACK signal when the control data shown in Table 18-4 is acknowledged. Table 18-4. Control Field for Unlocked Slave Unit Bit 3 Bit 2 Bit 1 Bit 0 Function 0 1 0 0 Lock address read (lower 8 bits) 0 1 0 1 Lock address read (higher 4 bits) If one unit occupies the bus as the master, the value set to the CDR register is output. Figure 18-4. Control Field Control field Control bit (4 bits) MSB Parity ACK LSB User's Manual U16541EJ5V1UD 681 682 Table 18-5. Acknowledge Signal Output Condition of Control Field (a) If received control data is AH, BH, EH, or FH Communication Type (USR.ALLTRANS bit) Individual Communication = 0 Broadcast Communication = 1 Communication Target (USR.SLVRQ bit) Slave Specification = 1 No Specification = 0 Lock Status (USR.LOCK bit) Lock = 1 Unlock = 0 Master Unit Identification (Match with PAR register) Lock Request Unit = 1 Other = 0 Slave Transmission Enable (BCR.ENSLVTX bit) Slave Reception Enable (BCR.ENSLVRX bit) 0 1 0 don't care don't care 1 1 1 Received Control Data AH BH EH FH { x Other than above Communication Type (USR.ALLTRANS bit) Individual Communication = 0 Broadcast Communication = 1 Communication Target (USR.SLVRQ bit) Slave Specification = 1 No Specification = 0 Lock Status (USR.LOCK bit) Lock = 1 Unlock = 0 Master Unit Identification (Match with PAR register) Lock Request Unit = 1 Other = 0 0 1 0 don't care 0 1 1 Slave Transmission Enable (BCR.ENSLVTX bit) Slave Reception Enable (BCR.ENSLVRX bit) 0 don't care Received Control Data 0H 3H 4H 5H 6H 7H { x x x { x 1 { { x x { { don't care { x { { x x 0 { x { { { x 1 { { { { { { Other than above Caution If the received control data is other than the data shown in Table 18-5, x (NACK signal is returned) is unconditionally assumed. Remark {: ACK signal is returned. x: NACK signal is returned. x CHAPTER 18 IEBus CONTROLLER User's Manual U16541EJ5V1UD (b) If received control data is 0H, 3H, 4H, 5H, 6H, or 7H CHAPTER 18 IEBus CONTROLLER (6) Telegraph length field This field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. The configuration of the telegraph length field is as shown in Figure 18-5. Table 18-6 shows the relationship between the telegraph length bit and the number of transmit data. Figure 18-5. Telegraph Length Field Telegraph length field Telegraph length bit (8 bits) MSB Parity ACK LSB Table 18-6. Contents of Telegraph Length Bit Telegraph Length Bit (Hex) Number of Transmit Data Bytes 01H 1 byte 02H 2 bytes | | FFH 255 bytes 00H 256 bytes The operation of the telegraph length field differs depending on whether the master transmits data (when control bit 3 is 1) or receives data (when control bit 3 is 0). (a) When master transmits data The telegraph length bit and parity bit are output by the master unit and the synchronization signals of bits are output by the master unit. When the slave unit detects that the parity is even, it outputs the ACK signal, and starts outputting the data field. During broadcast communication, however, the slave unit outputs the NACK signal. If the parity is odd, the slave unit judges that the telegraph length bit has not been correctly received, outputs the NACK signal, and returns to the standby (monitor) status. At this time, the master unit also returns to the standby status, and communication ends. (b) When master receives data The telegraph length bit and parity bit are output by the slave unit and the synchronization signals of bits are output by the master unit. If the master unit detects that the parity bit is even, it outputs the ACK signal. If the parity bit is odd, the master unit judges that the telegraph length bit has not been correctly received, outputs the NACK signal, and returns to the standby status. At this time, the slave unit also returns to the standby status, and communication ends. User's Manual U16541EJ5V1UD 683 CHAPTER 18 IEBus CONTROLLER (7) Data field This is data output by the transmission side. The master unit transmits or receives data to or from a slave unit by using the data field. The configuration of the data field is as shown below. Figure 18-6. Data Field Data field (number specified by telegraph length field) One data Data bit (8 bits) MSB Parity ACK Parity ACK LSB Following the data bit, the parity bit and acknowledge bit are respectively output by the master unit and slave unit. Use broadcast communication only for when the master unit transmits data. At this time, the acknowledge bit is ignored. The operation differs as follows depending on whether the master transmits or receives data. (a) When master transmits data When the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit. If the parity is even and the receive data is not stored in the DR register when the slave unit has received the data bit and parity bit, the slave unit outputs an ACK signal. If the parity is odd or if the receive data is stored in the DR register, the slave unit rejects receiving the data, and outputs the NACK signal. If the slave unit outputs the NACK signal, the master unit transmits the same data again. This operation continues until the master detects the ACK signal from the slave unit, or the data exceeds the maximum number of transmit bytes. If there is more data and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the ACK signal, the master unit transmits the next data. During broadcast communication, the slave unit outputs the NACK signal, and the master unit transfers 1 byte of data at a time. If the parity is odd or the DR register is storing receive data after the slave unit has received the data bit and parity bit during broadcast communication, the slave unit judges that reception has not been performed correctly, and stops reception. 684 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (b) When master receives data When the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. The slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit. The master unit reads the data and parity bits output by the slave unit, and checks the parity. If the parity is odd, or if the DR register is storing a receive data, the master unit rejects accepting the data, and outputs the NACK signal. If the maximum number of transmit bytes is within the value that can be transmitted in one communication frame, the master unit repeats reading the same data. If the parity is even and the DR register is not storing a receive data, the master unit accepts the data and outputs the ACK signal. If the maximum number of transmit bytes is within the value that can be transmitted in one frame, the master unit reads the next data. Caution Do not operate master reception in broadcast communication, because the slave unit cannot be defined and data transfer cannot be performed correctly. (8) Parity bit The parity bit is used to check to see if the transmit data has no error. The parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits. The parity is an even parity. If the number of bits in data that are `1' is odd, the parity bit is `1'. If the number of bits in the data that are `1' is even, the parity bit is `0'. (9) Acknowledge bit During normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to check if the data has been correctly received. * End of slave address field * End of control field * End of telegraph length field * End of data field The definition of the acknowledge bit is as follows. * 0: Indicates that the transmit data is recognized (ACK signal). * 1: Indicates that the transmit data is not recognized (NACK signal). During broadcast communication, however, the contents of the acknowledge bit are ignored. (a) Last acknowledge bit of slave field The last acknowledge bit of the slave field serves as a NACK signal in any of the following cases, and transmission is stopped. * If the parity of the master address bit or slave address bit is incorrect * If a timing error (error in bit format) occurs * If a slave unit does not exist User's Manual U16541EJ5V1UD 685 CHAPTER 18 IEBus CONTROLLER (b) Last acknowledge bit of control field The last acknowledge bit of the control field serves as a NACK signal in any of the following cases, and transmission is stopped. * If the parity of the control bit is incorrect * If control bit 3 is `1' (write operation) when the slave reception enable flag (BCR.ENSLVRX bit) is not set (1)Note * If the control bit indicates reading of data (3H or 7H) when the slave transmission enable flag (BCR.ENSLVTX bit) is not set (1) * If a unit other than that has set locking requests 3H, 6H, 7H, AH, BH, EH, or FH of the control bit when locking is set * If the control bit indicates reading of lock addresses (4H, 5H) even when locking is not set * If a timing error occurs * If the control bit is undefined Cautions 1. The ACK signal is always returned when the control data of the slave status request is received, even if the ENSLVTX bit = 0. 2. The NACK signal is returned by the acknowledge bit in the control field when the control data for data/command writing is received, even if the ENSLVRX bit = 0. Slave reception can be disabled (communication stopped) by ENSLVRX bit only in the case of individual communication. In the case of broadcast communication, communication is maintained and the data request interrupt request signal (INTIE1) or IEBus end interrupt request signal (INTIE2) is generated. (c) Last acknowledge bit of telegraph length field The last acknowledge bit of the telegraph length field serves as a NACK signal in any of the following cases, and transmission is stopped. * If the parity of the telegraph length bit is incorrect * If a timing error occurs (d) Last acknowledge bit of data field The last acknowledge bit of the data field serves as a NACK signal in any of the following cases, and transmission is stopped. * If the parity of the data bit is incorrectNote * If a timing error occurs after the preceding acknowledge bit has been transmitted * If the receive data is stored in the DR register and no more data can be receivedNote Note In this case, when the communication executed is individual communication, if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the transmission side executes transmission of that data field again. For broadcast communication, the transmission side does not execute transmission again, a communication error occurs on the reception side and reception stops. 686 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER 18.1.7 Transfer data (1) Slave status The master unit can learn why the slave unit did not return the ACK signal by reading the slave status. The slave status is determined according to the result of the last communication the slave unit has executed. All the slave units can supply information on the slave status. The configuration of the slave status is shown below. Figure 18-7. Bit Configuration of Slave Status MSB Bit 7 Bit 0 LSB Bit 6 Bit 5 Bit 4 Note 1 Bit 3 Transmit data is not written in DR register 1 Transmit data is written in DR register Note 2 Receive data is not stored in DR register 1 Receive data is stored in DR register Bit 2 Meaning 0 Unit is not locked 1 Unit is locked Bit 3 Bit 4 Meaning Fixed to 0 Note 3 Meaning 0 Slave transmission is stopped 1 Slave transmission is ready Bit 5 0 Bit 0 Meaning 0 0 Bit 1 Meaning 0 Bit 1 Bit 2 Meaning Fixed to 0 Bit 7 Bit 6 Meaning 0 0 Mode 0 0 1 Mode 1 1 0 Mode 2 1 1 Not used Indicates the highest mode supported by the Note 4 unit . Notes 1. After reset: Bit 0 is set to 1. 2. The receive buffer size is 1 byte. 3. When the V850ES/SG2 serves as a slave unit, this bit corresponds to the status indicated by BCR.ENSLVTX bit. <R> 4. Bits 7 and 6 are fixed to "10" because the V850ES/SG2 and V850ES/SG2-H can support modes 1 and 2. User's Manual U16541EJ5V1UD 687 CHAPTER 18 IEBus CONTROLLER (2) Lock address When the lock address is read (control bit: 4H or 5H), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. Figure 18-8. Configuration of Lock Address MSB LSB Control bit: 4H Control bit: 5H Lower 8 bits Undefined Higher 4 bits (3) Data If the control bit indicates reading of data (3H or 7H), the data in the data buffer of the slave unit is read by the master unit. If the control bit indicates writing of data (BH or FH), the data received by the slave unit is processed according to the operation rule of that slave unit. (4) Locking and unlocking The lock function is used when a message is transferred in two or more communication frames. The unit that is locked does not receive data from units other than the one that has locked the unit (does not receive broadcast communication). A unit is locked or unlocked as follows. (a) Locking If the communication frame is completed without succeeding to transmit or receive data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received (ACK = 0) by the control bit that specifies locking (3H, AH, or BH), the slave unit is locked by the master unit. At this time, the bit (bit 2) in the byte indicating the slave status is set to `1'. (b) Unlocking After transmitting or receiving data of the number of data bytes specified by the telegraph length bit in one communication frame by the control bit that has specified locking (3H, AH, or BH), or the control bit that has specified unlocking (6H), the slave unit is unlocked by the master unit. At this time, the bit related to locking (bit 2) in the byte indicating the slave status is reset to `0'. Locking or unlocking is not performed during broadcast communication. Locking and unlocking conditions are shown below. 688 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER Table 18-7. Lock Setting Conditions Control Data Broadcast Communication Communication End Frame End Note 3H, 6H Individual Communication Communication End Frame End Cannot be locked Lock set AH, BH Cannot be locked Cannot be locked Cannot be locked Lock set 0H, 4H, 5H, EH, FH Cannot be locked Cannot be locked Cannot be locked Cannot be locked Note The frame end of control data 6H (slave status read/unlock) occurs when the parity in the data field is odd, and when the NACK signal from the IEBus unit is repeated up to the maximum number of transfer bytes with being output. Table 18-8. Unlock Release Conditions (While Locked) Control Data Broadcast Communication from Lock Request Unit Communication End Frame End Note 3H, 6H Individual Communication from Lock Request Unit Communication End Frame End Unlocked Remains locked AH, BH Unlocked Unlocked Unlocked Remains locked 0H, 4H, 5H, EH, FH Remains locked Remains locked Remains locked Remains locked Note The frame end of control data 6H (slave status read/unlock) occurs when the parity in the data field is odd, and when the NACK signal from the IEBus unit is repeated up to the maximum number of transfer bytes with being output. 18.1.8 Bit format The format of the bits constituting the communication frame of the IEBus is shown below. Figure 18-9. Bit Format of IEBus Logic "1" Logic "0" Preparation period Preparation period: Synchronization Data period period Stop period First low-level (logic "1") period Synchronization period: Next high-level (logic "0") period Data period: Period indicating value of bit Stop period: Last low-level (logic "1") period The synchronization period and data period are almost equal to each other in length. The IEBus synchronizes each bit. The specifications on the time of the entire bit and the time related to the period allocated to that bit differ depending on the type of the transmit bit, or whether the unit is the master unit or a slave unit. The master and slave units monitor whether each period (preparation period, synchronization period, data period, and stop period) is output for specified time while they are in communication. If a period is not output for the specified time, the master and slave units report a timing error, immediately terminate communication and enter the standby status. User's Manual U16541EJ5V1UD 689 CHAPTER 18 IEBus CONTROLLER 18.2 Configuration The block diagram of the IEBus controller is shown below. Figure 18-10. IEBus Controller Block Diagram Internal bus 8 RAR, RSA OCKS2 SSR, USR, FSR, SCR, CCR UAR, SAR BCR, PSR, ISR ESR, CDR, DLR, DR Internal register block fXX to fXX/5Note Prescaler block Noise filter IETX0 IERX0 Transmission block <R> Transmit shift register Reception block Prescaler Receive shift register Bit processing block Field processing block IEBus interface block Interrupt control block IEBus controller <R> Note fXX/4 and fXX/5 can be selected only in the V850ES/SG2-H. (1) Hardware configuration and functions IEBus mainly consists of the following six internal blocks. * Interrupt control block * Internal registers * Bit processing block * Field processing block * IEBus interface block * Prescaler block 690 User's Manual U16541EJ5V1UD Interrupt request signal CHAPTER 18 IEBus CONTROLLER (a) Interrupt control block This control block transfers interrupt request signals from the IEBus controller to the CPU. (b) Internal registers These registers set data to the control registers and fields that control IEBus (for the internal registers, see 18.3 Registers). (c) Bit processing block This block generates and breaks down bit timing, and mainly consists of a bit sequence ROM, 8-bit preset timer, and comparator. (d) Field processing block This block generates each field in the communication frame, and mainly consists of a field sequence ROM, 4-bit down counter, and comparator. (e) IEBus interface block This is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, and transmission/reception block (collision detector, parity detector, parity generator, and ACK/NACK generator). (f) Prescaler block This block selects the clock to be supplied to the IEBus controller. User's Manual U16541EJ5V1UD 691 CHAPTER 18 IEBus CONTROLLER 18.3 Registers The registers that control the IEBus controller are shown below. Table 18-9. Control Registers of IEBus Controller Address Function Register Name Symbol R/W Bit Unit for Manipulation 1 8 16 R/W After Reset 00H FFFFF348H IEBus clock select register OCKS2 FFFFF360H IEBus control register BCR FFFFF361H IEBus power save register PSR FFFFF362H IEBus slave status register SSR 81H FFFFF363H IEBus unit status register USR 00H FFFFF364H IEBus interrupt status register ISR FFFFF365H IEBus error status register ESR FFFFF366H IEBus unit address register UAR FFFFF368H IEBus slave address register SAR FFFFF36AH IEBus partner address register PAR FFFFF36CH IEBus receive slave address register RSA FFFFF36EH IEBus control data register CDR FFFFF36FH IEBus telegraph length register FFFFF370H R R/W 0000H R 00H DLR 01H IEBus data register DR 00H FFFFF371H IEBus field status register FSR FFFFF372H IEBus success count register SCR 01H FFFFF373H IEBus communication count register CCR 20H 692 User's Manual U16541EJ5V1UD R/W R CHAPTER 18 IEBus CONTROLLER (1) IEBus control register (BCR) The BCR register is an 8-bit register that controls the operations of the IEBus controller. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H BCR R/W Address: FFFFF360H <7> <6> <5> ENIEBUS MSTRQ ALLRQ ENIEBUS <4> <3> ENSLVTX ENSLVRX IEBus unit stopped 1 IEBus unit active MSTRQ 0 0 0 0 Master request flag 0 IEBus unit not requested as master 1 IEBus unit requested as master ALLRQ Broadcast request flag 0 Individual communication requested 1 Broadcast communication requested Slave transmission enable flag 0 Slave transmission disabled 1 Slave transmission enabled ENSLVRX 1 Communication enable flag 0 ENSLVTX 2 Slave reception enable flag 0 Slave reception disabled 1 Slave reception enabled Cautions 1. While IEBus is operating as the master, writing to the BCR register (including bit manipulation instructions) is disabled until either the end of that communication or frame, or until communication is stopped by the occurrence of an arbitration-loss communication error. Master requests cannot therefore be multiplexed. However, the case when communication has been forcibly stopped (ENIEBUS flag = 0) is not problem. 2. If a bit manipulation instruction for the BCR register conflicts with a hardware reset of the MSTRQ bit, the BCR register may not operate normally. The following countermeasures are recommended in this case. * Because the hardware reset is instigated in the acknowledgment period of the slave address field, be sure to observe Caution 1 of (b) Master request flag (MSTRQ) below. * Be sure to observe the caution above regarding writing to the BCR register. User's Manual U16541EJ5V1UD 693 CHAPTER 18 IEBus CONTROLLER (a) Communication enable flag (ENIEBUS)...Bit 7 <Set/clear conditions> Set: By software Clear: By software The IEBus controller participates in communication differently depending on the timing of setting the ENIEBUS bit (1), as follows. Table 18-10. Timing of Setting ENIEBUS Bit and Participation in Communication Timing of Setting ENIEBUS Bit How IEBus Controller Participates in Communication If communication is not performed on IEBus Participates in communication from the next frame or starts communication. If other bus master is communicating start bit while communication is in progress on IEBus Participates in communication from that frame if the start bit is detected. If the start bit is not detected, participates in communication from the next frame. If communication is in progress on IEBus after start bit from other bus master is detected Participates in communication from the next frame. If the ENIEBUS bit is cleared (0), communication is immediately stopped even while it is in progress, and the internal flags and registers are reset, with some exceptions. The registers that are not reset by the ENIEBUS bit are listed in the table below. The IEBus controller does not respond even if another unit starts communication when the ENIEBUS bit = 0. Table 18-11. Registers That Are Not Reset by ENIEBUS Bit Registers Not Reset by ENIEBUS Bit Remark UAR Not reset SAR Not reset CDR Data written from CPU is not reset but data received during communication is reset. DLR Data written from CPU is not reset but data received during communication is reset. DR Data written from CPU is not reset but data received during communication is reset. Caution Before setting the ENIEBUS bit (1), the following registers must be set depending on the mode of communication to be started. Table 18-12. Registers That Must Be Set Before Each Communication Mode of Communication Registers That Must Be Set in Advance Master transmission UAR, SAR, CDR, DLR, DR (first 1-byte data) Master reception UAR, SAR, CDR Slave transmission Slave reception Note Note UAR, DLR, DR (first 1-byte data) UAR Note When starting slave transmission, information such as the value to be set to the DLR register and which data is to be returned (value to be set to the DR register) must be assigned in advance. 694 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (b) Master request flag (MSTRQ)...Bit 6 <Set/clear conditions> Set: By software Clear: Cleared (0) by hardware when master communication is started and immediately before the start interrupt of the master occurs. Cleared (0) by hardware before a communication error occurs. When the ENIEBUS bit is cleared. When the MSTRQ bit is set (1), the IEBus controller starts communication on IEBus as the master. If communication is in progress on IEBus (if the start bit cannot be detected while the start bit is being communicated or if communication is in progress after the start bit has been detected), however, the controller waits until the current frame ends (holds the master request pending), outputs the start bit after the frame has ended, and starts communication as the master. Cautions 1. If the IEBus controller has lost in arbitration, issue the master request again by software. In doing so, set (1) the MSTRQ bit at a timing other than that illustrated below. Figure 18-11. Timing at Which MSTRQ Bit Cannot Be Set MSTRQ bit MSTRQ bit clear signal Start interrupt request signal (INTIE2, INTSTA) MSTRQ bit cannot be set (1) (approx. 167 ns (mode 1, at 6.29 MHz)). 2. When a master request has been sent and bus mastership acquired, do not set the MSTRQ, ENSLVTX, or ENSLVRX bit until the end of communication (i.e. the communication end flag (ISR.ENDTRNS bit) or frame end flag (ISR.ENDFRAM bit) is set (1)) as setting these flags disables interrupt request signal generation. However, these flags can be set if communication has been aborted. (c) Broadcast request flag (ALLRQ)...Bit 5 <Set/clear conditions> Set: By software Clear: By software Caution When requesting broadcast communication, always set (1) the ALLRQ bit, then the MSTRQ bit. User's Manual U16541EJ5V1UD 695 CHAPTER 18 IEBus CONTROLLER (d) Slave transmission enable flag (ENSLVTX)...Bit 4 <Set/clear conditions> Set: By software Clear: By software Cautions 1. The ENSLVTX bit must be set before the parity bit in the control field is received. 2. Clear the ENSLVTX bit (0) before setting the MSTRQ bit (1) when making a master request. This is to avoid transmission of the data of the DR register that tries master transmission if the controller loses in arbitration after master operation and if slave transmission is requested by the master. 3. When returning to an enabled state from a disabled state, transmission becomes valid from the next frame. 4. If control data (3H or 7H) for data/command writing is received when the ENSLVTX bit = 0, the NACK signal is returned by the acknowledge bit in the control field. 5. The status interrupt request signals (INTIE2, INTSTA) will be generated and communication continued when the control data of a slave status request is returned, even if the ENSLVTX bit = 0. (e) Slave reception enable flag (ENSLVRX)...Bit 3 <Set/clear conditions> Set: By software Clear: By software Cautions 1. The ENSLVRX bit must be set before the parity bit in the control field is received. 2. While the CPU is busy with other processing, slave reception can be prevented by clearing the ENSLVRX bit (0). During individual communication, the NACK signal is returned in the control field and communication is completed. During broadcast communication, communication cannot be completed because the acknowledge bit is ignored. However, the IEBus controller does not respond to the broadcast communication and does not generate an interrupt request signal. 3. When returning to an enabled state from a disabled state, transmission becomes valid from the next frame. 696 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (2) IEBus power save register (PSR) The PSR register is an 8-bit register that controls the internal clock and communication mode of the IEBus controller. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H PSR R/W Address: FFFFF361H <7> <6> 5 4 3 2 1 0 ENCLK IEMODE 0 0 0 0 0 0 ENCLK Internal clock operation enable flag 0 Stop internal clock of IEBus controller 1 Enable internal clock of IEBus controller IEMODE IEBus communication mode setting flag 0 Set communication mode 1 1 Set communication mode 2 Cautions 1. Do not set the PSR register while communication is enabled (BCR.ENIEBUS bit = 1). 2. Be sure to clear bits 5 to 0 to "0". User's Manual U16541EJ5V1UD 697 CHAPTER 18 IEBus CONTROLLER (3) IEBus slave status register (SSR) The SSR register is an 8-bit register that indicates the communication status of the slave unit. After receiving a slave status transmission request from the master, read this register by software, and write a slave status to the DR register to transmit the slave status. At this time, the telegraph length is automatically set to "01H", so setting of the DLR register is not required (because it is preset by hardware). Bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to "10" (mode 2). This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 81H. After reset: 81H SSR R Address: FFFFF362H 7 6 5 <4> 3 1 0 0 STATSLV 0 STATSLV <2> <1> STATLOCK STATRX Slave transmission status flag 0 Slave transmission stops 1 Slave transmission enabled STATLOCK Lock status flag 0 Unlock status 1 Lock status STATRX DR register receive status 0 Receive data not stored in DR register 1 Receive data stored in DR register STATTX DR register transmit status 0 Transmit data not stored in DR register 1 Transmit data stored in DR register (a) Slave transmission status flag (STATSLV)...Bit 4 Reflects the contents of the slave transmission enable flag (BCR.ENSLVTX bit). (b) Lock status flag (STATLOCK)...Bit 2 Reflects the contents of the lock flag (USR.LOCK bit). (c) DR register reception status (STATRX)...Bit 1 This flag indicates the DR register reception state. (d) DR register transmission status (STATTX)...Bit 0 This flag indicates the DR register transmission state. 698 User's Manual U16541EJ5V1UD <0> STATTX CHAPTER 18 IEBus CONTROLLER (4) IEBus unit status register (USR) The USR register is an 8-bit register that indicates the IEBus unit status. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H USR R Address: FFFFF363H 7 <6> <5> <4> <3> 2 1 0 0 SLVRQ ARBIT ALLTRNS ACK LOCK 0 0 Slave request flag SLVRQ 0 No request from master to slave 1 Request from master to slave Arbitration result flag ARBIT 0 Arbitration loss not occurred 1 Arbitration loss occurred Broadcast communication flag ALLTRNS 0 Individual communication status 1 Broadcast communication status Acknowledge transmission flag ACK 0 NACK signal transmitted 1 ACK signal transmitted Lock status flag LOCK 0 Unit unlocked 1 Unit locked User's Manual U16541EJ5V1UD 699 CHAPTER 18 IEBus CONTROLLER (a) Slave request flag (SLVRQ)...Bit 6 A flag indicating whether there has been a slave request from the master. <Set/clear conditions> Set: When the unit is requested as a slave (if the condition in Table 18-13 Slave Request Condition (SLVRQ Bit Setting Condition) is satisfied), this flag is set (1) by hardware when the acknowledge period of the slave address field starts. Clear: This flag is cleared (0) by hardware when the unit is not requested as a slave (if the condition in Table 18-13 Slave Request Condition (SLVRQ Bit Setting Condition) is not satisfied). The reset timing is the same as the set timing. If the unit is requested as a slave immediately after communication has been correctly received (when the SLVRQ bit = 1), and if a parity error occurs in the slave address field for that communication, the flag is not cleared. Table 18-13. Slave Request Condition (SLVRQ Bit Setting Condition) Status of Unit Received Master Communication Mode Received Slave Address Address Not locked don't care Individual UAR register matching Broadcast Group matching FFFH Locked Locked master matching Individual UAR register matching Broadcast Group matching FFFH Caution If a unit other than the locked master communicates with the unit while the unit is locked, the SLVRQ bit is not set but the ACK signal is returned to the slave address field. This is because communication must be continued, even if a unit other than the locked master returns the signal, if the control data is a slave status request. (b) Arbitration result flag (ARBIT)...Bit 5 A flag that indicates the result of arbitration. <Set/clear conditions> Set: This flag is set (1) when the data output by the IEBus unit during the arbitration period does not match the bus line data. Clear: This flag is cleared (0) by the start bit timing. Cautions 1. The timing at which the arbitration result flag (ARBIT bit) is cleared differs depending on whether the unit outputs a start bit. * If start bit is output: The flag is cleared at the output start timing. * If start bit is not output: The flag is cleared at the detection timing of the start bit (approx. 160 s (mode 1, at 6.29 MHz) after output) 2. The flag is cleared (0) at the detection timing of the start bit if the other unit outputs the start bit earlier and the unit does not output the start bit after the master request. 700 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (c) Broadcast communication flag (ALLTRNS)...Bit 4 Flag indicating whether the unit is performing broadcast communication. The contents of the flag are updated in the broadcast field of each frame. Except for initialization (reset) by system reset, the set/clear conditions vary depending on the receive data of the broadcast field bit. <Set/clear conditions> Set: When "broadcast" is received by the broadcast field Clear: When "individual" is received by the broadcast field, or upon the input of a system reset. Caution The broadcast flag is updated regardless of whether IEBus is the communication target or not. Figure 18-12. Example of Broadcast Communication Flag Operation IEBus sequence Start Broadcast M11 M10 Start Individual M11 M10 Broadcast communication flag Set Not cleared by start bit Clear (d) Acknowledge transmission flag (ACK)...Bit 3 A flag that indicates whether the ACK signal has been transmitted in the acknowledge bit period of the acknowledge bit field when IEBus is the receiving unit. The contents of the flag are updated in the acknowledge bit period of each frame. However, if the internal circuit is initialized by the occurrence of a parity error, etc., the contents are not updated in the acknowledge bit period of that field. (e) Lock status flag (LOCK)...Bit 2 A flag that indicates whether the unit is locked. <Set/clear conditions> Set: This flag is set (1) when the communication end flag (ISR.ENDTRNS bit) goes low and the frame end flag (ISR.ENDFRAM bit) goes high after receipt of a lock specification (3H, 6H, AH, BH) in the control field. Clear: When the communication enable flag (BCR.ENIEBUS bit) is cleared (0). When the communication end flag (ENDTRNS bit) is set (1) after receipt of a lock release (3H, 6H, AH, BH) in the control field. Caution Lock specification/release is not possible in broadcast communication. In the lock status, individual communication from a unit other than the one that requests locking is not acknowledged. However, even communication from a unit other than the one that requests locking is acknowledged as long as the communication is a slave status request. User's Manual U16541EJ5V1UD 701 CHAPTER 18 IEBus CONTROLLER (5) IEBus interrupt status register (ISR) The ISR register indicates the interrupt source when IEBus issues an interrupt request signal. This register is read to generate an interrupt request signal, after which the specified interrupt processing is carried out. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H ISR R/W Note 1 7 <6> 0 IEERR IEERR Address: FFFFF364H <5> <4> <3> <2> STARTF STATUSF ENDTRNS ENDFRAM 1 0 0 0 Communication error flag (during communication) 0 No communication error 1 Communication error STARTF Start interrupt flag 0 Start interrupt request signal did not occur 1 Start interrupt request signal occurred STATUSF Status transmission flag (slave) 0 No slave status/lock address (higher 4 bits, lower 8 bits) transmission request 1 Slave status/lock address (higher 4 bits, lower 8 bits) transmission request ENDTRNS Communication end flag 0 Communication does not end after the number of bytes set in the telegraph length field have been transferred 1 Communication ends after the number of bytes set in the telegraph length field have been transferred ENDFRAM Frame end flag 0 The frame (transfer of the maximum number of bytes) does not end 1 The frame (transfer of the maximum number of bytes) ends Notes 1. Only the IEERR bit can be written, and only to 0 (i.e., the IEERR bit can only be cleared). The IEERR bit is not set (1) even if 1 is written to it. 2. Mode 1: 32 bytes Mode 2: 128 bytes 702 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (a) Communication error flag (IEERR)...Bit 6 A flag that indicates a communication error has occurred. When a communication error occurs, the INTIE2 and INTERR interrupt request signals are generated. <Set/clear conditions> Set: The flag is set (1) if a timing error, parity error (except in the data field), NACK reception error (except in the data field), underrun error, overrun error (that occurs during broadcast communication reception), or write error occurs. Clear: By software (b) Start interrupt flag (STARTF)...Bit 5 A flag that indicates the start interrupt. When a start interrupt occurs, the INTIE2 and INTSTA interrupt request signals are generated. <Set/clear conditions> Set: This flag is set (1) in the slave address field, upon a master request. When IEBus is a slave unit, this flag is set (1) upon a request from the master (only if it was a slave request in the locked state from the unit requesting a lock). Clear: This flag is cleared (0) if the status transmission interrupt, communication end interrupt, frame end interrupt, or INTIE1 interrupt request signal is generated. (c) Status transmission flag (STATUSF)...Bit 4 A flag that indicates the master requested transmission of the slave status and lock address (higher 4 bits and lower 8 bits) when the controller was serving as a slave. <Set/clear conditions> Set: This flag is set (1) when 0H, 4H, 5H, or 6H is received in the control field from the master when the IEBus is a slave unit. Clear: This flag is cleared (0) if the start interrupt, communication end interrupt, frame end interrupt, or INTIE1 interrupt request signal is generated. (d) Communication end flag (ENDTRANS)...Bit 3 A flag that indicates whether communication ends after the number of bytes set in the telegraph length field have been transferred. When a communication error occurs, the INTIE2 and INTSTA interrupt request signals are generated. <Set/clear conditions> Set: This flag is set (1) when the count value of the SCR register is 00H. Clear: This flag is cleared (0) if the start interrupt, status transmission interrupt, frame end interrupt (if the communication end interrupt does not occur), or INTIE1 interrupt request signal is generated. User's Manual U16541EJ5V1UD 703 CHAPTER 18 IEBus CONTROLLER (e) Frame end flag (ENDFRAM)...Bit 2 A flag that indicates whether communication ends after the maximum number of bytes (mode 1: 32 bytes, mode 2: 128 bytes) have been transferred. <Set/clear conditions> Set: This flag is set (1) when the count value of the CCR register is 00H. Clear: This flag is cleared (0) if the start interrupt, status transmission interrupt, communication end interrupt (if the frame end interrupt does not occur), or INTIE1 interrupt request signal is generated Cautions 1. If both the CCR and SCR registers are cleared to 00H, the ENDTRNS and ENDFRAM bits are set (1) at the same time. 2. If the last data field is the NACK signal when the maximum number of transmitted bytes is reached as a result of retransmitting the data, the ENDFRAM bit and IEERR (NACK reception error) bit are set at the same time. 704 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (6) IEBus error status register (ESR) The ESR register indicates the source of the communication error interrupt request signal of IEBus. Each bit of this register is set (1) as soon as the communication error flag (ISR.IEERR bit) is set (1). The source of a communication error, if any, can be identified by checking the contents of this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H ESR R/W Address: FFFFF365H <7> <6> <5> <4> <3> <2> 1 <0> TERR PERR NERR UERR OERR WERR 0 DEFLAG TERR Timing error occurrence flag 0 Timing error did not occur 1 Timing error occurred PERR Parity error occurrence flag 0 Parity error did not occur 1 Parity error occurred NERR NACK reception error occurrence flag 0 NACK reception error does not occur 1 NACK reception error occurred UERR Underrun error occurrence flag 0 Underrun error did not occur 1 Underrun error occurred OERR Overrun error occurrence flag 0 Overrun error did not occur 1 Overrun error occurred WERR Write error occurrence flag 0 Write error did not occur 1 Write error occurred DEFLAG Third party error occurrence flag 0 Error occurred during communication with unit 1 Error occurred during communication with station other than unit Cautions 1. Each bit can only be cleared (0). It cannot be set (1) even if 1 is written to it. 2. The value of the ESR register is updated when an error occurs. If the ESR register is read at this time, however, an undefined value is read. It is recommended to read the ESR register in error interrupt servicing. 3. If a communication error occurs, the IEBus controller returns to the default status and makes preparation for communication. If communication is started without the error corrected, the error flag accumulates the error. Correct the error before the next communication is started. User's Manual U16541EJ5V1UD 705 CHAPTER 18 IEBus CONTROLLER (a) Timing error occurrence flag (TERR)...Bit 7 <Set/clear conditions> Set: This flag is set (1) if a timing error occurs. Clear: By software A timing error occurs if the high-/low-level width of the communication bit is not the defined value. The defined value of the high- and low-level width is set to the bit processing block and monitored by the internal timer. If a timing error occurs, the INTERR and INTIE2 interrupt request signals are generated. (b) Parity error occurrence flag (PERR)...Bit 6 <Set/clear conditions> Set: This flag is set (1) if a parity error occurs. Clear: By software A parity error occurs if the parity generated in each field does not match the received parity while the controller is serving as a receiver unit. If the parity does not match in the data field during individual communication, however, the NACK signal is returned and retransmission of data is requested. Therefore, the parity error does not occur. Table 18-14. Operation if Parity Does Not Match Field Communication Mode Operation if Parity Does Not Match Master address field Individual/broadcast Parity error occurs. Slave address field Individual/broadcast Parity error occurs. Control data field Individual/broadcast Parity error occurs. Telegraph length field Individual/broadcast Parity error occurs. Data field Individual Retransmission is requested by returning NACK signal. Broadcast Parity error occurs. (c) NACK reception error occurrence flag (NERR)...Bit 5 <Set/clear conditions> Set: This flag is set (1) if a NACK reception error occurs. Clear: By software A NACK reception error occurs if the NACK signal is received during the acknowledge bit period of the slave address field, control data field, or telegraph length field during individual communication, regardless of whether the controller is operating as the master or a slave. If the NACK signal is received during the acknowledge bit period of the data field, a NACK reception error does not occur because data is retransmitted. If the NACK signal is received during the acknowledge period of the last data field when the maximum number of transfer bytes is reached, the NACK reception error occurs. The NACK reception error does not occur during broadcast communication because the ACK/NACK signal is not identified. The NACK reception error does not occur during third-party communication because only the timing/parity error is detected as an error. 706 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (d) Underrun error occurrence flag (UERR) ... Bit 4 <Set/clear conditions> Set: This flag is set (1) if an underrun error occurs. Clear: By software An underrun error occurs if the next data is not transmitted to the DR register in time before the ACK signal is received. If the NACK signal is received during individual communication and during the acknowledge bit period, the underrun error does not occur because the data is retransmitted. Figure 18-13. Timing of Underrun Error Occurrence ... P A Data field P A Data field ... Request to write data to DR register INTIE1 Underrun error occurs if data is not written to DR register during this period. Remark P: Parity bit A: Acknowledge bit User's Manual U16541EJ5V1UD 707 CHAPTER 18 IEBus CONTROLLER (e) Overrun error occurrence flag (OERR) ... Bit 3 <Set/clear conditions> Set: This flag is set (1) if an overrun error occurs. Clear: By software If 1-byte data is stored in the DR register while the IEBus controller serves as a receiver unit, the data request interrupt request signal (INTIE1) is generated, and the DR register is read by means of DMA or by software. If this reading is delayed and the next data is received, an overrun error occurs. Cautions 1. If the DR register is not read and the number of retransmitted data reaches the maximum number of transmitted bytes (32 bytes) after the overrun error has occurred, the frame end interrupt request signal (INTSTA or INTIE2) occurs. The overrun status is maintained until the DR register is read, even after the frame has ended. 2. The overrun status is cleared only when the DR register is read and when the system is reset. Therefore, be sure to read the DR register in the communication error interrupt processing program. 3. The next data cannot be transmitted in the overrun status if it is 2 bytes or more. Because the data request interrupt request signal (INTIE1) does not occur, the transmit data cannot be set and an underrun error occurs. Therefore, be sure to execute transmission after clearing the overrun status. Remark During individual communication reception, the NACK signal is returned during the acknowledge bit period of the next data. In response, the transmitter unit retransmits data. Therefore, the CCR register is decremented but the SCR register is not decremented. During broadcast communication reception, the communication error interrupt request signal (INTIE2) is generated and reception is stopped. At this time, the DR register is not updated. The INTIE1 signal is not generated. The STATRX bit of the SSR register is held set (to 1). The overrun status is cleared when data is received after the DR register has been read. Figure 18-14. Timing of Overrun Error Occurrence ... P A Data field P A Request to write data to DR register INTIE1 Overrun error occurs if data is not written to DR register during this period. Remark P: Parity bit A: Acknowledge bit 708 User's Manual U16541EJ5V1UD Data field ... CHAPTER 18 IEBus CONTROLLER (f) Write error occurrence flag (WERR) ... Bit 2 <Set/clear conditions> Set: This flag is set (1) if a write error occurs. Clear: By software A write error occurs if the data written to the DR register is not transmitted in the data field during unit transmission. The timing of occurrence of a write error is illustrated below. Figure 18-15. Timing of Write Error Occurrence ... Acknowledge bit Data field ... INTIE1 Approx. 170 ns Write error occurs if data is not written to DR register during this period. Cautions 1. Even when the WERR bit is set (1), the INTIE1 interrupt request signal may be generated. 2. If the NACK signal is returned, the WERR bit is not set because data is retransmitted. (g) Third-party error occurrence flag (DEFLAG)...Bit 0 <Set/clear conditions> Set: This flag is set (1) if a timing error or parity error occurs during communication regardless of the unit (during communication between third parties). Clear: By software Caution If an error occurs before the third-party communication starts even when the slave address field does not match that of the unit (for example, if the NACK signal is received when the received address does not match that of the unit in the slave address field (if the NERR bit is set (1))), the DEFLAG bit is not set (1). Remark Communication between third parties may take place in the following two cases. <1> If the received address in the slave address field does not match that of the unit (during individual communication: Matching with UAR register, during broadcast communication: Matching with group or FFFH) and if communication continues after the ACK signal has been received, the unit monitors that communication. <2> If the unit cannot respond to the received control data in the control field during broadcast communication and if communication continues, the unit monitors that communication. For example, this happens when the unit receives control data FH from master during broadcast communication but the slave reception enable flag of the unit is disabled (BCR.ENSLVRX bit = 0) (the NACK signal is returned and communication ends during individual communication). User's Manual U16541EJ5V1UD 709 CHAPTER 18 IEBus CONTROLLER (7) IEBus unit address register (UAR) The UAR register sets the unit address of an IEBus unit. This register must always be set before starting communication. Sets the unit address (12 bits) to bits 11 to 0. This register can be read or written in 16-bit units. Reset sets this register to 0000H. 15 14 13 12 11 10 UAR Caution 0 0 0 9 8 7 6 5 4 3 2 1 0 0 Address FFFFF366H After reset R/W 0000H R/W Do not set the UAR register while communication is enabled (BCR.ENIEBUS bit = 1). (8) IEBus slave address register (SAR) During a master request, the value of this register is reflected in the value of the transmit data in the slave address field. The SAR register must always be set before starting communication. The SAR register sets the slave address (12 bits) to bits 11 to 0. This register can be read or written in 16-bit units. Reset sets this register to 0000H. 15 14 13 12 11 10 SAR Caution 0 0 0 9 8 7 6 5 4 3 2 1 0 0 Address FFFFF368H After reset R/W 0000H R/W Do not set the SAR register while communication is enabled (BCR.ENIEBUS bit = 1). (9) IEBus partner address register (PAR) The PAR register stores the master address value received in the master address field regardless of whether the unit is operating as the master or a slave. If a request "4H" to read the lock address (lower 8 bits) is received from the master, read the value of this register by software, and write the data of the lower 8 bits to the DR register. If a request "5H" to read the lock address (higher 4 bits) is received from the master, read the value of this register by software and write the data of bits 11 to 8 to the higher 4 bits of the DR register. The PAR register sets the partner address (12 bits) to bits 11 to 0. This register is read-only, in 16-bit units. Reset sets this register to 0000H. 15 14 13 12 11 10 PAR Caution 0 0 0 9 8 7 6 5 4 3 2 1 0 0 Address FFFFF36AH After reset R/W 0000H R The PAR register stores an address value if the parity is correct and the unit is not locked when the parity period of the master address field expires. If the PAR register is read at this time, an undefined value is read. 710 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (10) IEBus receive slave address register (RSA) The RSA register stores the slave address value received in the slave address field regardless of whether the unit is operating as the master or a slave. This register is read-only, in 16-bit units. Reset sets this register to 0000H. 15 14 13 12 11 10 RSA Caution 0 0 0 9 8 7 6 5 4 3 2 1 0 0 Address After reset R/W FFFFF36CH 0000H R The RSA register stores an address value if the parity is correct and the unit is not locked when the parity period of the slave address field expires. If the RSA register is read at this time, an undefined value is read. (11) IEBus control data register (CDR) The CDR register can be read or written in 8-bit units. Reset sets this register to 00H. Remark The CDR register consists of a write register and a read register and data written to the CDR register cannot be read as is. The data read from this register is the data received by IEBus communication. (a) When master unit The data of the lower 4 bits is reflected in the data transmitted in the control field. During a master request, the CDR register must be set in advance before starting communication. (b) When slave unit The data received in the control field is written to the lower 4 bits. When the status transmission flag (ISR.STATUSF bit) is set (1), an interrupt request signal (INTIE2) is issued, and each processing should be performed by software, according to the value of the lower 4 bits of the CDR register. User's Manual U16541EJ5V1UD 711 CHAPTER 18 IEBus CONTROLLER After reset: 00H CDR R/W Address: FFFFF36EH 7 6 5 4 3 2 1 0 0 0 0 0 MOD SELCL2 SELCL1 SELCL0 MOD SELCL2 SELCL1 SELCL0 0 0 0 0 Read slave status 0 0 0 1 Undefined 0 0 1 0 Undefined 0 0 1 1 Read data and lock 0 1 0 0 Read lock address (lower 8 bits) 0 1 0 1 Read lock address (lower 4 bits) 0 1 1 0 Read slave status and unlock 0 1 1 1 Read data 1 0 0 0 Undefined 1 0 0 1 Undefined 1 0 1 0 Write command and lock 1 0 1 1 Write data and lock 1 1 0 0 Undefined 1 1 0 1 Undefined 1 1 1 0 Write command 1 1 1 1 Write data Function Cautions 1. Because the slave unit must judge whether the received data is a "command" or "data", read the value of the CDR register after completing communication. 2. If the master unit sets an undefined value, the slave unit returns the NACK signal and communication is aborted. During broadcast communication, the master unit ignores the acknowledge bit and continues communication. Therefore, do not set an undefined value. 712 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (c) Slave status return operation When IEBus receives a request to transfer from master to slave status or a lock address request (control data: 0H, 6H), whether the ACK/NACK signal in the control field is returned or not depends on the status of the IEBus unit. (1) If 0H or 6H control data was received in the unlocked state ACK signal returned (2) If 4H or 5H control data was received in the unlocked state NACK signal returned (3) If 0H, 4H, 5H or 6H control data was received in the locked ACK signal returned state from the unit that sent the lock request (4) If 0H, 4H, or 5H control data was received in the locked state ACK signal returned from other than the unit that sent the lock request (5) If 6H control data was received in the locked state from other NACK signal returned than the unit that sent the lock request In all of the above cases, the acknowledgment of a slave status or lock request will cause the STATUSF bit to be set (1) and the status interrupt signal (INTIE2, INTSTA) to be generated. The generation timing is at the end of the control field parity bit (at the start of the acknowledge bit). However, if NACK is returned, a NACK receive error is generated after the acknowledge bit, and communication is terminated. Figure 18-16. Interrupt Request Signal Generation Timing (for (1), (3), and (4)) Control field IEBus sequence Control bits (4 bits) Parity bit (1 bit) Telegraph length field Acknowledge bit (1 bit) Telegraph length bits (8 bits) INTIE2, INTSTA signal Set by reception of 0H, 4H, 5H, 6H Cleared by software STATUSF bit Internal NACK flag 0 User's Manual U16541EJ5V1UD 713 CHAPTER 18 IEBus CONTROLLER Figure 18-17. Interrupt Request Signal Generation Timing (for (2) and (5)) Control field IEBus sequence Control bit (4 bits) Parity bit (1 bit) Acknowledge bit (1 bit) Terminated by communication error INTIE2 INTSTA INTERR Set by reception of 0H, 4H, 5H, 6H Cleared by software STATUSF bit Set by detection of NACK signal Internal NACK flag Because in (4) and (5) the communication was from other than the unit that sent the lock request while IEBus was in the locked state, the start or communication end interrupt request signals (INTIE2, INTSTA) are not generated, even if the IEBus unit is the communication target. The STATUSF bit is set (1) and the status interrupt request signals (INTIE2, INTSTA) are generated, however, if a slave status or lock address request is acknowledged. Note that even if the same control data is received while IEBus is in the locked state, the interrupt generation timing for INTIE2 and INTSTA differs depending on whether the master unit (3) or another unit (4) is requesting the locked state. Figure 18-18. Timing of INTIE2 and INTSTA Interrupt Request Signal Generation in Locked State (for (4) and (5)) Start IEBus sequence Broadcast Master address (12 + P) Slave address (12 + P + A) Telegraph Control DataNote lengthNote (4 + P + A) (8 + P + A) (8 + P + A) INTIE2, INTSTA Status interrupt Note The telegraph length and data modes are not set in the case of (5) because the NACK signal is returned. Remark 714 P: Parity bit, A: Acknowledge bit User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER Figure 18-19. Timing of INTIE2 and INTSTA Interrupt Request Signal Generation in Locked State (for (3)) IEBus sequence Start Broadcast Master address (12 + P) Slave address (12 + P + A) Control Telegraph length Data (4 + P + A) (8 + P + A) (8 + P + A) INTIE2, INTSTA Start interrupt Remark Status interrupt Communication end interrupt P: Parity bit, A: Acknowledge bit User's Manual U16541EJ5V1UD 715 CHAPTER 18 IEBus CONTROLLER (12) IEBus telegraph length register (DLR) The DLR register can be read or written in 8-bit units. Reset sets this register to 01H. (a) When transmission unit ... Master transmission, slave transmission The data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. The DLR register must be set in advance before transmission. (b) When reception unit ... Master reception, slave reception The receive data in the telegraph length field transmitted from the transmission unit is written to this register. Remark The DLR register consists of a write register and a read register. Consequently, data written to this register cannot be read as is. The data that can be read is the data received during IEBus communication. After reset: 01H R/W Address: FFFFF36FH 7 6 5 4 3 2 1 0 DLR Bit Setting Remaining number of communication data bytes 7 6 5 4 3 2 1 0 value 0 0 0 0 0 0 0 1 01H 1 byte 0 0 0 0 0 0 1 0 02H 2 bytes : : : : : : : : : 0 0 1 0 0 0 0 0 20H : : : : : : : : : 1 1 1 1 1 1 1 1 FFH 255 bytes 0 0 0 0 0 0 0 0 00H 256 bytes : 32 bytes : Cautions 1. When the master issues a request (0H, 4H, 5H, or 6H) for transmission of a slave status or a lock address (higher 4 bits and lower 8 bits), 01H is transmitted as the telegraph length regardless of the contents of the DLR register. It is therefore not necessary to set the DLR register by software. 2. When the IEBus controller serves as a receiver unit, the DLR register stores a telegraph length if the value of the parity bit of the telegraph length field is correct. If the DLR register is read at this time, an undefined value is read. 716 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (13) IEBus data register (DR) The DR register sets the communication data (8 bits) to bits 7 to 0. This register can be read or written in 8-bit units. Reset sets this register to 00H. Remark The DR register consists of a write register and a read register. Consequently, data written to this register cannot be read as is. The data that can be read is the data received during IEBus communication. (a) When transmission unit The data (1 byte) written to the DR register is stored in the transmit shift register of the IEBus interface block. It is then output from the most significant bit, and an interrupt request signal (INTIE1) is generated each time 1 byte has been transmitted. If the NACK signal is received after 1-byte data has been transferred during individual transfer, data is not transferred from the DR register to the transmit shift register, and the same data is retransmitted. At this time, INTIE1 signal is not generated. INTIE1 signal is generated when the transmit shift register stores the DR register value. However, when the last byte and 32nd byte (the last byte of 1 communication frame) is stored in the transmit shift register, the INTIE1 signal is not generated. (b) When reception unit One byte of the data received by the receive shift register of the IEBus interface block is stored in this register. Each time 1 byte has been correctly received, an interrupt request signal (INTIE1) is generated. When transmit/receive data is transferred to and from the DR register, using DMA can reduce the CPU processing load. After reset: 00H 7 R/W Address: FFFFF370H 6 5 4 3 2 1 0 DR Cautions 1. If the next data is not in time while the transmission unit is set, an underrun occurs, and a communication error interrupt request signal (INTIE2, INTERR) occurs, stopping transmission. 2. If data is not read in time before the next data is read when the IEBus controller functions as a receiver unit during individual communication reception, the NACK signal is returned by the acknowledge bit of the data field, requesting the master to retransmit the data. If the DR register is not read after the data has reached the maximum number of transmit bytes, however, the frame end interrupt request signal (INTIE2, INTSTA) and NACK reception error interrupt request signal (INTIE2, INTERR) are generated at the same time. 3. If data is not read in time before the next data is received when the IEBus controller functions as a receiver unit during broadcast communication reception, an overrun error occurs and the communication error interrupt request signal (INTIE2, INTERR) is generated. 4. When the IEBus controller serves as a receiver unit, the DR register stores receive data if the value of the parity bit of the data field is correct. If the DR register is read at this time, an undefined value is read. User's Manual U16541EJ5V1UD 717 CHAPTER 18 IEBus CONTROLLER (14) IEBus field status register (FSR) The FSR register stores the status of the field status of the IEBus controller if an interrupt request signal (INTIE1, INTIE2, INTSTA, or INTERR) is generated. This register is read-only, in 8-bit units. Reset sets this register to 00H. Cautions 1. If an interrupt request signal is generated during communication between third parties, the FSR register is cleared to 00H. However, because only an interrupt request signal that is generated if an error occurs is generated during communication between third parties, the error can be identified as that during communication between third parties, by reading third-party error flag (ESR.DEFLAG bit). 2. The FSR register updates the status information when an interrupt request signal is generated. If the FSR register is read at this time, however, an undefined value is read. 3. If another interrupt request signal is generated before the FSR register is read, the status information when the preceding interrupt occurred is updated by the status information when the new interrupt occurs. 4. Use the FSR register only for problem analysis; do not use it with the actual software. After reset: 00H FSR Remark R Address: FFFFF371H 7 6 5 4 3 2 0 0 0 0 0 0 1 0 FSTATE1 FSTATE0 For the explanation of the FSTATE1 and FSTATE0 bits, see Table 18-15 Field Status. Table 18-15. Field Status Field Status Explanation Master/Slave Slave transmission status FSR = 00H Slave operation Field Start field Transmission/Reception Reception Master address field Slave address field Control data field Telegraph length field Data field Slave transmission status FSR = 01H Slave operation Telegraph length field Master reception status FSR = 02H Master operation Master transmission status FSR = 03H Master operation Data field Telegraph length field Reception Data field Start field Master address field Slave address field Control data field Telegraph length field Data field 718 Transmission User's Manual U16541EJ5V1UD Transmission CHAPTER 18 IEBus CONTROLLER (15) IEBus success count register (SCR) The SCR register indicates the number of remaining communication bytes. The count value of the counter in which the value set by the DLR register is decremented by the ACK signal in the data field is read from this register. When the count value has reached "00H", the communication end flag (ISR.ENDTRNS bit) is set (1). This register is read-only, in 8-bit units. Reset sets this register to 00H. After reset: 01H R Address: FFFFF372H 7 6 5 4 3 2 1 0 SCR Bit Setting Remaining number of communication data bytes 7 6 5 4 3 2 1 0 value 0 0 0 0 0 0 0 1 01H 1 byte 0 0 0 0 0 0 1 0 02H 2 bytes : : : : : : : : : 0 0 1 0 0 0 0 0 20H : : : : : : : : : 1 1 1 1 1 1 1 1 FFH 0 0 0 0 0 0 0 0 00H : 32 bytes : 255 bytes 0 bytes (end of communication) or 256 Note bytes Note The actual counter consists of 9 bits. When "00H" is read, it cannot be judged whether the remaining number of communication data bytes is 0 (end of communication) or 256. Therefore, either the communication end flag (ENDTRNS bit) is used, or if "00H" is read when the first interrupt occurs at the beginning of communication, the remaining number of communication data bytes is judged to be 256. Caution The SCR register is updated when the parity period of the telegraph field expires and when the ACK signal of the data field is received. If the SCR register is read at this time, however, an undefined value is read. User's Manual U16541EJ5V1UD 719 CHAPTER 18 IEBus CONTROLLER (16) IEBus communication count register (CCR) The CCR register indicates the number of bytes remaining from the communication byte number specified by the communication mode. This register indicates the number of transfer bytes. The maximum number of transmitted bytes per frame defined in each mode (mode 1: 32 bytes, mode 2: 128 bytes) is preset to this register. The count value of the counter that is decremented during the acknowledge bit period of the data field regardless of the ACK/NACK signal is read from this register. Whereas the SCR register is decremented during normal communication (ACK signal), the CCR register is decremented when 1 byte has been communicated, regardless of whether the signal is ACK or NACK. When the count value has reached "00H", the frame end flag (ISR.ENDFRAM bit) is set (1). The preset value of the maximum number of transmitted bytes per frame is 20H (32 bytes) in mode 1 and 80H (128 bytes) in mode 2. This register is read-only, in 8-bit units. Reset input sets this register to 20H. After reset: 20H 7 R Address: FFFFF373H 6 5 4 3 2 1 0 CCR Caution The maximum number of transmit bytes is preset to the CCR register when the start bit is transmitted or received, and the register is decremented when the parity period of the data field expires. If the CCR register is read at this time, however, an undefined value is read. 720 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER (17) IEBus clock select register (OCKS2) The OCKS2 register selects the clock of IEBus. The main clock frequencies that can be used are shown below. No other main clock frequencies can be used. This register can be read or written in 8-bit units. Reset input clears this register to 00H. * 6.0 MHz/6.291456 MHz (6.29 MHz) * 12.0 MHz/12.582912 MHz (12.58 MHz) * 18.0 MHz/18.874368 MHz (18.87 MHz) * 24.0 MHz/25.165824 MHz (25.16 MHz)Note <R> <R> * 30.0 MHz/31.457280 MHz (31.45 MHz)Note <R> Note V850ES/SG2-H only After reset: 00H OCKS2 R/W Address: FFFFF348H 7 6 5 0 0 0 OCKSEN2 4 3 OCKSEN2 OCKSTH2 2 0 1 0 OCKS21 OCKS20 IEBus clock operation specification 0 IEBus clock operation stops 1 IEBus clock operation enabled OCKSTH2 OCKS21 OCKS20 IEBus clock selection 0 0 0 fXX/2 (when fXX = 12.0 MHz or fXX = 12.58 MHz) 0 0 1 fXX/3 (when fXX = 18.0 MHz or fXX = 18.87 MHz) <R> 0 1 0 fXX/4 (when fXX = 24.0 MHz or fXX = 25.16 MHz)Note <R> 0 1 1 fXX/5 (when fXX = 30.0 MHz or fXX = 31.45 MHz)Note 0 0 1 Other than above <R> fXX (when fXX = 6.0 MHz or fXX = 6.29 MHz) Setting prohibited Note V850ES/SG2-H only User's Manual U16541EJ5V1UD 721 CHAPTER 18 IEBus CONTROLLER 18.4 Interrupt Operations of IEBus Controller 18.4.1 Interrupt control block Interrupt request signal <1> Communication error IEERR (i) Timing error: TERR (ii) Parity error: PERR (iii) NACK receive error: NERR (iv) Underrun error: UERR (v) Overrun error: OERR (vi) Write error: WERR <2> Start interrupt STARTF <3> Status communication STATUSF <4> End of communication ENDTRNS <5> End of frame ENDFRAM <6> Transmit data write request STATTX <7> Receive data read request STATRX A communication error <1> occurs if any of the above error sources (i) to (vi) is generated. These error sources are assigned to the error status register (ESR) (see Table 18-18 Communication Error Source Processing List). The above interrupt signals <1> to <5> are assigned to the ISR register (see Table 18-17 Interrupt Source List). The configuration of the interrupt control block is illustrated below. 722 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER Figure 18-20. Configuration of Interrupt Control Block TERR PERR NERR UERR OERR WERR INTERR INTIE2 STARTF STATUSF ENDTRNS ENDFRAM INTSTA STATTX STATRX <R> INTIE1 IEBus controller Interrupt control block INTC of V850ES/SG2, V850ES/SG2-H Cautions 1. The logical sum (OR) output of the STATRX and STATTX signals is treated as an interrupt request signal (INTIE1). 2. The logical sum (OR) output of the TERR, PERR, NERR, UERR, OERR, and WERR signals is treated as a communication error (IEERR) or an interrupt request signal (INTERR). 3. The logical sum (OR) output of the STARTF, STATUSF, ENDTRNS, and ENDFRAM signals is treated as an interrupt request signal (INTSTA). 4. The logical sum (OR) output of the IEERR, STARTF, STATUSF, ENDTRNS, and ENDFRAM signals (logical sum (OR) output of INTSTA and INTERR signals) is treated as an interrupt request signal (INTIE2). User's Manual U16541EJ5V1UD 723 CHAPTER 18 IEBus CONTROLLER Table 18-16. Interrupt Request Signal Generation Source List Interrupt Source Symbol Interrupt Request Signal INTIE1 Communication error interrupt INTIE2 INTERR IEERR Timing error TERR Parity error PERR NACK reception error NERR Underrun error UERR Overrun error OERR Write error WERR INTSTA Start interrupt STARTF Status transmission STATUSF End of communication ENDTRNS End of frame ENDFRAM Transmit data write request STATTX Receive data write request STATRX 724 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER 18.4.2 Example of identifying interrupt The IEBus controller processes interrupts in the following two ways. * Using three interrupt request signals: INTIE1, INTERR, and INTSTA * Using two interrupt request signals: INTIE1 and INTIE2 Caution Mask the interrupt sources that are not used so that the interrupts do not occur. How an interrupt is identified in each of the above cases is explained below. (1) When INTIE1, INTERR, and INTSTA signals are used Figure 18-21. Example of Identifying INTIE1 Signal Interrupt (When INTIE1, INTERR, and INTSTA Signals Are Used) INTIE1 signal generated Master transmission or slave transmission No Yes Transmission write processing Reception read processing Figure 18-22. Example of Identifying INTERR Signal Interrupt (When INTIE1, INTERR, and INTSTA Signals Are Used) INTERR signal generated ESR register TEER bit PEER bit NEER bit UEER bit OEER bit WEER bit Error source identification User's Manual U16541EJ5V1UD 725 CHAPTER 18 IEBus CONTROLLER Figure 18-23. Example of Identifying INTSTA Signal Interrupt (When INTIE1, INTERR, and INTSTA Signals Are Used) INTSTA signal generated ISR register STARTF bit Start interrupt occurs SSR register Arbitration loss detection ARBIT bit Remaster processing SLVRQ bit STATUSF bit Slave request identification Status transmission identification Status transmission processing CDR register 00H, 06H Writing SSR register to DR register 04H Writing lower 8 bits of PAR register to DR register 05H Writing higher 4 bits of PAR register to DR register ENDTRNS bit Communication end identification ENDFRAM bit Frame end identification (2) When INTIE1 and INTIE2 signals are used Figure 18-24. Example of Identifying INTIE1 Signal Interrupt (When INTIE1 and INTIE2 Signals Are Used) INTIE1 signal generated Master transmission or slave transmission No Yes Transmission write processing 726 Reception read processing User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER Figure 18-25. Example of Identifying INTIE2 Signal Interrupt (When INTIE1 and INTIE2 Signals Are Used) INTIE2 signal generated ISR register IEERR bit Communication error identification Error source identification ESR register TEER bit PEER bit NEER bit UEER bit OEER bit WEER bit STARTF bit Start interrupt occurs SSR register Arbitration loss detection ARBIT bit SLVRQ bit STATUSF bit Remaster processing Slave request identification Status transmission identification Status transmission processing CDR register 00H, 06H Writing SSR register to DR register 04H Writing lower 8 bits of PAR register to DR register 05H Writing higher 4 bits of PAR register to DR register ENDTRNS bit Communication end identification ENDFRAM bit Frame end identification User's Manual U16541EJ5V1UD 727 CHAPTER 18 IEBus CONTROLLER 18.4.3 Interrupt source list The interrupt request signals of the internal IEBus controller in the V850ES/SG2 and V850ES/SG2-H can be classified into vector interrupts and DMA transfer interrupts. These interrupt request signals can be specified via software manipulation. The interrupt sources are listed below. Table 18-17. Interrupt Source List Interrupt Source Condition of Generation Unit Field Timing error Master/slave All fields Parity error Reception Other than data Remark Software Processing After Generation of Interrupt Request Signal Undo communication processing Communication error is logical sum (OR) output of timing error, parity error, NACK (individual) Communication error <R> reception error, underrun error, overrun error, and write error. All fields (broadcast) NACK reception Reception Other than data (Transmission) (individual) Underrun error Transmission Data Overrun error Reception Data (broadcast) Write error Start interrupt Transmission Data Master Slave/address Slave request judgment Interrupt always occurs if lost in Arbitration judgment arbitration during master request (If lost, remaster processing) Communication preparation processing Slave Status transmission Slave Slave/address Control Slave request judgment Generated only during slave Communication preparation processing request Refer to transmission processing Interrupt occurs regardless of example such as slave status. slave transmission enable flag Interrupt occurs if NACK is returned in the control field. End of communication Transmission Data DMA transfer end processing Reception Data DMA transfer end processing Set if SCR register is cleared to 00H Receive data processing End of frame Transmission Reception Data Data Retransmission preparation Set if CCR register is cleared to processing 00H Re-reception preparation processing Transmit data write Transmission Data Reading of transmit data Note Set after transfer transmission data to internal shift register This does not occur when the last data is transferred. Receive data read Reception Data Reading of received data Note If DMA transfer or software manipulation is not executed. 728 User's Manual U16541EJ5V1UD Note Set after normal data reception CHAPTER 18 IEBus CONTROLLER 18.4.4 Communication error source processing list The following table shows the occurrence conditions of the communication errors (timing error, NACK reception error, overrun error, underrun error, parity error, and write error), error processing by the IEBus controller, and examples of processing by software. Table 18-18. Communication Error Source Processing List (1/2) Timing Error Occurrence condition Broadcast communication Unit status Reception Transmission Occurrence condition If bit specification timing is not correct Location of occurrence Other than data field Hardware processing * Reception stops. * INTIE2 signal occurs * To start bit waiting status Data field Other than data field Data field * Transmission stops. * INTIE2 signal occurs * To start bit waiting status Remark Communication between other units does not end. Individual communication Software processing * Error processing (such as retransmission request) * Error processing (such as retransmission request) Hardware processing * * * * * Transmission stops. * INTIE2 signal occurs * To start bit waiting status Software processing * Error processing (such as retransmission request) Reception stops. INTIE2 signal occurs NACK signal is returned. To start bit waiting status * Error processing (such as retransmission request) NACK Reception Error Occurrence condition Broadcast communication Individual communication Unit status Reception Transmission Occurrence condition Unit NACK signal transmission Unit NACK signal transmission Location of occurrence Other than data field Other than data field Data field Data field NACK signal reception of data of 32nd byte Hardware processing - - - - - Software processing - - - - - Hardware processing * Reception stops. * INTIE2 signal occurs. * To start bit waiting status Software processing * Error processing (such as retransmission request) * INTIE2 signal * Reception does not occur. stops. * Data * INTIE2 signal retransmitted occurs. by other unit is * To start bit received. waiting status - * Error processing (such as retransmission request) User's Manual U16541EJ5V1UD * INTIE2 signal * INTIE2 signal does not occur. occurs. * Retrans* To start bit mission waiting status processing - * Error processing (such as retransmission request) 729 CHAPTER 18 IEBus CONTROLLER Table 18-18. Communication Error Source Processing List (2/2) Overrun Error Occurrence condition Broadcast communication Underrun Error/Write Error Unit status Reception Transmission Occurrence condition DR register cannot be read in time before the next data is received. DR register cannot be written in time before the next data is transmitted. Location of occurrence Other than Data field data field Other than Data field data field Hardware processing - * Reception stops. * INTIE2 signal occurs. * To start bit waiting status - * Transmission stops. * INTIE2 signal occurs. * To start bit waiting status - * Error processing (such as retransmission request) - * Transmission stops. * INTIE2 signal occurs. * To start bit waiting status - * Error processing (such as retransmission request) Remarks 1. Communication between other units does not end. 2. Data cannot be received until the overrun status is cleared. Software processing - * DR register is read and overrun status is cleared. * Error processing (such as retransmission request) Individual communication Hardware processing - * INTIE2 signal does not occur. * NACK signal is returned. * Data is retransmitted from other unit. Remark Data cannot be received until overrun status is cleared. Software processing - * DR register is read and overrun status is cleared. * Error processing (such as retransmission request) Parity Error Occurrence condition Broadcast communication Unit status Reception Occurrence condition Received data and received parity do not match. Transmission Location of occurrence Other than data field Hardware processing * Reception stops. * INTIE2 signal occurs. * To start bit waiting status Software processing Data field - Other than data field Data field - - * Error processing (such as retransmission request) - - Hardware processing * Reception stops. * INTIE2 signal occurs. * To start bit waiting status * Reception does not stop. * INTIE2 signal does not occur. * NACK signal is returned. * Data retransmitted by other unit is received. - - Software processing * Error processing (such as retransmission request) - - - Remark Communication between other units does not end. Individual communication 730 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER 18.5 Interrupt Request Signal Generation Timing and Main CPU Processing 18.5.1 Master transmission Initial preparation processing: Sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. Communication start processing: Set the BCR register (enable communication, master request, and slave reception). Figure 18-26. Master Transmission Approx. 624 s (mode 1, at 6.29 MHz) <1> Broadcast Start M address P S address P A Control P A Telegraph length P A Data 1 Data n P Approx. 390 s (mode 1, at 6.29 MHz) <2> Data 1 P A Data 2 P A Data n - 1 P A A <1> Interrupt request signal (INTIE2, INTSTA) occurrence Judgment of occurrence of errorNote Error processing Judgment of slave request Slave reception processing (See 18.5.1 (1) Slave reception processing) Judgment of arbitration result Remaster request processing <2> Interrupt request signal (INTIE2, INTSTA) occurrence Judgment of occurrence of errorNote Error processing Judgment of end of communication End of communication processing Judgment of end of frame Recommunication processing (See 18.5.1 (3) Recommunication processing) Note This processing is necessary only when the INTIE2 interrupt request signal is used as the start interrupt, and is not necessary when the INTSTA interrupt request signal is used (in this case, the error processing is performed by using the INTERR interrupt request signal). : Interrupt request signal (INTIE1) occurrence (See 18.5.1 (2) Interrupt request signal (INTIE1) occurrence) The transmit data of the second and subsequent bytes is written to the DR register by DMA transfer. At this time, the data transfer direction is RAM on-chip peripheral I/O : An interrupt request signal (INTIE1) does not occur. 2. 3. n = Final number of data bytes Remarks 1. User's Manual U16541EJ5V1UD 731 CHAPTER 18 IEBus CONTROLLER (1) Slave reception processing If a slave reception request is confirmed during vector interrupt servicing, the data transfer direction of the macro service must change from RAM on-chip peripheral I/O to on-chip peripheral I/O RAM until the first data is received. The maximum pending period of this data transfer direction changing processing is about 1,040 s in communication mode 1 (at 6.29 MHz). (2) Interrupt request signal (INTIE1) occurrence If the NACK signal is received from the slave in the data field, an interrupt request signal (INTIE1) is not issued to the interrupt controller (INTC), and the same data is retransmitted by hardware. If the transmit data is not written in time during the period of writing the next data, a communication error interrupt request signal (INTERR) occurs due to occurrence of underrun, and communication ends midway. (3) Recommunication processing In the vector interrupt servicing in <2> in Figure 18-26, it is judged whether the data has been correctly transmitted within one frame. If the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted. 732 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER 18.5.2 Master reception Before performing master reception, it is necessary to notify the unit that will be the slave of slave transmission. Therefore, more than two communication frames are necessary for master reception. The slave unit prepares the transmit data, sets (1) the slave transmission enable flag (BCR.ENSLVTX bit), and waits. Initial preparation processing: Set a unit address, slave address, and control data. Communication start processing: Set the BCR register (enable communication and master request). Figure 18-27. Master Reception Approx. 1,014 s (mode 1, at 6.29 MHz) <1> Broadcast Start M address P S address P A Control P A Telegraph length P A Data 1 Approx. 390 s (mode 1, at 6.29 MHz) <2> Data 1 P A Data 2 P A Data n - 1 P A Data n P A <1> Interrupt request signal (INTIE2, INTSTA) occurrence Judgment of occurrence of errorNote Error processing Slave processing Remaster request processing Judgment of slave request Judgment of arbitration result <2> Interrupt request signal (INTIE2, INTSTA) occurrence Note Judgment of occurrence of error Error processing End of communication processing Frame end processing (See 18.5.2 (2) Frame end processing) Judgment of end of communication Judgment of end of frame Note This processing is necessary only when the INTIE2 interrupt request signal is used as the start interrupt, and is not necessary when the INTSTA interrupt request signal is used (in this case, the error processing is performed by using the INTERR interrupt request signal). Remarks 1. : Interrupt request signal (INTIE1) occurrence (See 18.5.2 (1) Interrupt request signal (INTIE1) occurrence) The receive data stored in the DR register is read by DMA transfer. At this time, the data transfer direction is on-chip peripheral I/O RAM. 2. n = Final number of data bytes User's Manual U16541EJ5V1UD 733 CHAPTER 18 IEBus CONTROLLER (1) Interrupt request signal (INTIE1) occurrence If the NACK signal is transmitted (hardware processing) in the data field, an interrupt request signal (INTIE1) is not issued to the INTC, and the same data is retransmitted from the slave. If the receive data is not read by the time the next data is received, the hardware automatically transmits the NACK signal. (2) Frame end processing In the vector interrupt servicing in <2> in Figure 18-27, it is judged whether the data has been correctly received within one frame. If the data has not been correctly received (if the number of data to be received in one frame could not be received), a request to retransmit the data must be made to the slave in the next communication frame. 734 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER 18.5.3 Slave transmission Initial preparation processing: Set a unit address, telegraph length, and the first byte of the transmit data. Communication start processing: Set the BCR register (enable communication, slave transmission, and slave reception). Figure 18-28. Slave Transmission Approx. 624 s (mode 1, at 6.29 MHz) <1> Broadcast Start M address P S address P A Control P A Telegraph length P A Data 1 Approx. 390 s (mode 1, at 6.29 MHz) <2> Data 1 P A Data 2 P A Data n - 1 P A Data n P A <1> Interrupt request signal (INTIE2, INTSTA) occurrence Judgment of occurrence of errorNote Error processing Judgment of slave request <2> Interrupt request signal (INTIE2, INTSTA) occurrence Judgment of occurrence of errorNote Error processing End of communication processing Frame end processing (See 18.5.3 (2) Frame end processing) Judgment of end of communication Judgment of end of frame Note This processing is necessary only when the INTIE2 interrupt request signal is used as the start interrupt, and is not necessary when the INTSTA interrupt request signal is used (in this case, the error processing is performed by using the INTERR interrupt request signal). Remarks 1. : Interrupt request signal (INTIE1) occurrence (See 18.5.3 (1) Interrupt request signal (INTIE1) occurrence). The transmit data of the second and subsequent bytes is written to the DR register by DMA transfer. At this time, the data transfer direction is RAM on-chip peripheral I/O. 2. : An interrupt request signal (INTIE1) does not occur. 3. : Interrupt request signal (INTIE2) occurrence An interrupt request signal occurs only when 0H, 4H, 5H, or 6H is received in the control field in the slave status (for the slave status response operation during the locked status, see 18.3 (11) IEBus control data register (CDR)). 4. n = Final number of data bytes User's Manual U16541EJ5V1UD 735 CHAPTER 18 IEBus CONTROLLER (1) Interrupt request signal (INTIE1) occurrence If the NACK signal is received from the master in the data field, an interrupt request signal (INTIE1) is not issued to the INTC, and the same data is retransmitted by hardware. If the transmit data is not written in time during the period of writing the next data, a communication error interrupt request signal (INTERR) occurs due to occurrence of underrun, and communication is abnormally ended. (2) Frame end processing In the vector interrupt servicing in <2> in Figure 18-28, it is judged whether the data has been correctly transmitted within one frame. If the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remaining data must be transmitted. 736 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER 18.5.4 Slave reception Initial preparation processing: Set a unit address. Communication start processing: Set the BCR register (enable communication, disables slave transmission, and enables slave reception). Figure 18-29. Slave Reception Approx. 1,014 s (mode 1, at 6.29 MHz) <1> Broadcast Start M address P S address P A Control P A Telegraph length P A Data 1 Approx. 390 s (mode 1, at 6.29 MHz) <2> Data 1 P A Data 2 P A Data n - 1 P A Data n P A <1> Interrupt request signal (INTIE2, INTSTA) occurrence Judgment of occurrence of errorNote Error processing Slave processing Judgment of slave request <2> Interrupt request signal (INTIE2, INTSTA) occurrence Judgment of occurrence of errorNote Error processing End of communication processing Frame end processing (See 18.5.4 (2) Frame end processing). Judgment of end of communication Judgment of end of frame Note This processing is necessary only when the INTIE2 interrupt request signal is used as the start interrupt, and is not necessary when the INTSTA interrupt request signal is used (in this case, the error processing is performed by using the INTERR interrupt request signal). Remarks 1. : Interrupt request signal (INTIE1) occurrence (See 18.5.4 (1) Interrupt request signal (INTIE1) occurrence). The receive data stored in the DR register is read by DMA transfer. At this time, the data transfer direction is on-chip peripheral I/O RAM. 2. n = Final number of data bytes User's Manual U16541EJ5V1UD 737 CHAPTER 18 IEBus CONTROLLER (1) Interrupt request signal (INTIE1) occurrence If the NACK signal is transmitted in the data field, an interrupt request signal (INTIE1) is not issued to the INTC, and the same data is retransmitted from the master. If the receive data is not read by the time the next data is received, the NACK signal is automatically transmitted. (2) Frame end processing In the vector interrupt servicing in <2> in Figure 18-29, it is judged whether the data has been correctly received within one frame. 738 User's Manual U16541EJ5V1UD CHAPTER 18 IEBus CONTROLLER 18.5.5 Interval of occurrence of interrupt request signal for IEBus control Each control interrupt request signal must occur at each point of communication and perform the necessary processing until the next interrupt request signal occurs. Therefore, the IEBus control block is controlled by software, taking the shortest time of this interrupt request signal occurrence interval into consideration. The locations at which the following interrupt request signals may occur are indicated by in the field where it may occur. does not mean that the interrupt request signal occurs at each of the points indicated by . If an error interrupt request signal (timing error, parity error, or NACK receive error) occurs, the IEBus internal circuit is initialized. As a result, the following interrupt request signal does not occur in that communication frame. (1) Master transmission Figure 18-30. Master Transmission (Interval of Interrupt Request Signal Occurrence) BroadMaster address P cast Start bit t1 T Slave address T T T P A Control A t3 P A T Telegraph length A T t2 P A T Data A P A T U t4 t5 Communication starts Data T Communication start interrupt P A Data Data P A A T U t4 End of communication End of frame Remarks 1. T: Timing error A: NACK receive error U: Underrun error : Data set interrupt (INTIE1) 2. End of frame occurs at the end of 32-byte data. Values in parentheses indicate MIN. value (IEBus: mode 1, at 6.29 MHz). t1: Communication starts timing error (approx. 93 s) t2: Communication starts communication start interrupt (approx. 1,282 s) t3: Communication start interrupt timing error (approx. 15 s) t4: Communication start interrupt end of communication (approx. 1,012 s) t5: Transmission data request interrupt interval (approx. 375 s) User's Manual U16541EJ5V1UD 739 CHAPTER 18 IEBus CONTROLLER (2) Master reception Figure 18-31. Master Reception (Interval of Interrupt Request Signal Occurrence) Broadcast Master address Start bit t1 T T P Slave address P A T T Data P A T t5 A t3 P A T T t2 Communication starts A Control Telegraph length A T P A Data P A t4 Communication start interrupt Data Data T P A A t4 End of communication End of frame Remarks 1. T: Timing error P: Parity error A: NACK receive error : Data set interrupt request signal (INTIE1) 2. End of frame occurs at the end of 32-byte data. Values in parentheses indicate MIN. value (IEBus: mode 1, at 6.29 MHz). t1: Communication starts timing error (approx. 93 s) t2: Communication starts communication start interrupt (approx. 1,282 s) t3: Communication start interrupt timing error (approx. 15 s) t4: Communication start interrupt end of communication (approx. 1,012 s) t5: Receive data read interval (approx. 375 s) 740 User's Manual U16541EJ5V1UD T P CHAPTER 18 IEBus CONTROLLER (3) Slave transmission Figure 18-32. Slave Transmission (Interval of Interrupt Request Signal Occurrence) BroadMaster address cast Start bit t1 T T P Slave address P A P T T t3 P Control T t2 Communication starts Data P A T Data U Telegraph length T P A t6 t4 T Communication start interrupt Data P A P A T Data A T P A U t5 t7 Status request P A A T t7 End of communication End of frame Remarks 1. T: Timing error P: Parity error A: NACK receive error U: Underrun error : Data set interrupt (INTIE1) 2. End of frame occurs at the end of 32-byte data. Values in parentheses indicate MIN. value (IEBus: mode 1, at 6.29 MHz). t1: Communication starts timing error (approx. 196 s) t2: Communication starts communication start interrupt (approx. 1,192 s) t3: Communication start interrupt timing error (approx. 15 s) t4: Communication start interrupt status request (approx. 225 s) t5: Transmission data request interrupt interval (approx. 375 s) t6: Status request timing error (approx. 15 s) t7: Status request end of communication (approx. 787 s) User's Manual U16541EJ5V1UD 741 CHAPTER 18 IEBus CONTROLLER (4) Slave reception Figure 18-33. Slave Reception (Interval of Interrupt Request Signal Occurrence) Broadcast Master address Start bit t1 T T P Slave address P A T P T t2 Communication starts A Data P A O P T t5 Control A t3 PT T P A Telegraph length P A T P A Data P A t4 Communication start interrupt Data Data T P A O A P t4 End of communication End of frame Remarks 1. T: Timing error P: Parity error A: NACK receive error O: : Overrun error Data set interrupt (INTIE1) 2. End of frame occurs at the end of 32-byte data. Values in parentheses indicate MIN. value (IEBus: mode 1, at 6.29 MHz). t1: Communication starts timing error (approx. 196 s) t2: Communication starts communication start interrupt (approx. 1,192 s) t3: Communication start interrupt timing error (approx. 15 s) t4: Communication start interrupt end of communication (approx. 1,012 s) t5: Receive data read interval (approx. 375 s) 742 User's Manual U16541EJ5V1UD T P P CHAPTER 19 CAN CONTROLLER <R> Caution The CAN controller is allocated in the programmable peripheral I/O area. Before using the CAN controller, enable use of the programmable peripheral I/O area by using the BPC register. For details, refer to 3.4.7 Programmable peripheral I/O registers. 19.1 Overview <R> The V850ES/SG2 and V850ES/SG2-H feature an on-chip 1-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. <R> <R> The V850ES/SG2 and V850ES/SG2-H products with an on-chip CAN controller are as follows. * PD703280, 703280Y, 703281, 703281Y, 70F3281, 70F3281Y, 703282, 703282Y, 703283, 703283Y, 70F3283, 70F3283Y, 703282HY, 703283HY, 70F3283HY 19.1.1 Features * Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) * Standard frame and extended frame transmission/reception enabled * Transfer rate: 1 Mbps max. (CAN clock input 8 MHz) * 32 message buffers/channels * Receive/transmit history list function * Automatic block transmission function * Multi-buffer receive block function * Mask setting of four patterns is possible for each channel User's Manual U16541EJ5V1UD 743 CHAPTER 19 CAN CONTROLLER 19.1.2 Overview of functions Table 19-1 presents an overview of the CAN controller functions. Table 19-1. Overview of Functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Baud rate Maximum 1 Mbps (CAN clock input 8 MHz) Data storage Storing messages in the CAN RAM Number of messages * 32 message buffers/channels * Each message buffer can be set to be either a transmit message buffer or a receive message buffer. Message reception * Unique ID can be set to each message buffer. * Mask setting of four patterns is possible for each channel. * A reception completion interrupt is generated each time a message is received and stored in a message buffer. * Two or more receive message buffers can be used as a FIFO receive buffer (multi-buffer receive block function). * Receive history list function Message transmission * Unique ID can be set to each message buffer. * Transmit completion interrupt for each message buffer * Message buffer numbers 0 to 7 specified as transmit message buffers can be used for automatic block transfer. Message transmission interval is programmable (automatic block transmission function (hereafter referred to as "ABT")). * Transmission history list function <R> Remote frame processing Remote frame processing by transmit message buffer Time stamp function * The time stamp function can be set for a receive message when a 16-bit timer is used in combination. * The time stamp capture trigger can be selected (SOF or EOF in a CAN message frame can be detected). Diagnostic function * Readable error counters * "Valid protocol operation flag" for verification of bus connections * Receive-only mode * Single-shot mode * CAN protocol error type decoding * Self-test mode Release from bus-off state * Can be forcibly released from bus-off by software (timing restrictions are ignored). * Cannot be automatically released from bus-off (release request by software is required). Power save mode * CAN sleep mode (can be woken up by CAN bus) * CAN stop mode (cannot be woken up by CAN bus) 744 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.1.3 Configuration The CAN controller is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC Peripheral I/O Bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU. (2) MCM (Memory Control Module) This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module. (3) CAN protocol layer This functional block is involved in the operation of the CAN protocol and its related settings. (4) CAN RAM This is the CAN memory functional block, which is used to store message IDs, message data, etc. Figure 19-1. Block Diagram of CAN Module CPU Interrupt request NPB (NEC peripheral I/O bus) INTC0TRX INTC0REC INTC0ERR INTC0WUP CAN bus CAN module NPB interface MCM (Memory Control Module) CAN protocol layer CTXD CRXD CAN transceiver CAN_H0 CAN_L0 CAN RAM TSOUT C0MASK1 C0MASK2 C0MASK3 C0MASK4 ... Message buffer 0 Message buffer 1 Message buffer 2 Message buffer 3 Message buffer 31 User's Manual U16541EJ5V1UD 745 CHAPTER 19 CAN CONTROLLER 19.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link layer includes logical link and medium access control. The composition of these layers is illustrated below. Figure 19-2. Composition of Layers * Logical link control (LLC) Higher Data link layerNote Lower * Medium access control (MAC) Physical layer * Acceptance filtering * Overload report * Recovery management * Data capsuled/not capsuled * Frame coding (stuffing/no stuffing) * Medium access management * Error detection * Error report * Acknowledgment * Seriated/not seriated Prescription of signal level and bit description Note CAN controller specification 19.2.1 Frame format (1) Standard format frame * The standard format frame uses 11-bit identifiers, which means that it can handle up to 2,048 messages. (2) Extended format frame * The extended format frame uses 29-bit (11 bits + 18 bits) identifiers, which increases the number of messages that can be handled to 2,048 x 218 messages. * An extended format frame is set when "recessive level" (CMOS level of "1") is set for both the SRR and IDE bits in the arbitration field. 746 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 19-2. Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame Frame used to delay the next data frame or remote frame (1) Bus value The bus values are divided into dominant and recessive. * Dominant level is indicated by logical 0. * Recessive level is indicated by logical 1. * When a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 19.2.3 Data frame and remote frame (1) Data frame A data frame is composed of seven fields. Figure 19-3. Data Frame Data frame R D <1> <2> <3> <4> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Data field Control field Arbitration field Start of frame (SOF) Remark D: Dominant = 0 R: Recessive = 1 User's Manual U16541EJ5V1UD 747 CHAPTER 19 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. Figure 19-4. Remote Frame Remote frame R D <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1. The data field is not transferred even if the control field's data length code is not "0000B". 2. D: Dominant = 0 R: Recessive = 1 (3) Description of fields <1> Start of frame (SOF) The start of frame field is located at the start of a data frame or remote frame. Figure 19-5. Start of Frame (SOF) (Interframe space or bus idle) Start of frame (Arbitration field) R D 1 bit Remark D: Dominant = 0 R: Recessive = 1 * If a dominant level is detected in the bus idle state, a hardware synchronization is performed (the current TQ is assigned to be the SYNC segment). * If a dominant level is sampled at the sample point following such a hardware synchronization, the bit is assigned to be a SOF. If a recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a noise only. In this case an error frame is not generated. 748 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 19-6. Arbitration Field (in Standard Format Mode) Arbitration field (Control field) R D Identifier RTR IDE (r1) ID28 * * * * * * * * * * * * * * * * * * * * ID18 (11 bits) (1 bit) r0 (1 bit) Cautions 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first. Remark D: Dominant = 0 R: Recessive = 1 Figure 19-7. Arbitration Field (in Extended Format Mode) Arbitration field (Control field) R D Identifier SRR IDE Identifier RTR r1 r0 ID28 * * * * * * * * * * * * * * ID18 ID17 * * * * * * * * * * * * * * * * * ID0 (11 bits) (1 bit) (1 bit) (18 bits) (1 bit) Cautions 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first. Remark D: Dominant = 0 R: Recessive = 1 Table 19-3. RTR Frame Settings Frame Type RTR Bit Data frame 0 (D) Remote frame 1 (R) Table 19-4. Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits Frame Format SRR Bit IDE Bit Number of Bits Standard format mode None 0 (D) 11 bits Extended format mode 1 (R) 1 (R) 29 bits User's Manual U16541EJ5V1UD 749 CHAPTER 19 CAN CONTROLLER <3> Control field The control field sets "DLC" as the number of data bytes in the data field (DLC = 0 to 8). Figure 19-8. Control Field (Arbitration field) Control field (Data field) R D RTR Remark r1 (IDE) r0 DLC3 DLC2 DLC1 DLC0 D: Dominant = 0 R: Recessive = 1 In a standard format frame, the control field's IDE bit is the same as the r1 bit. Table 19-5. Data Length Setting Data Length Code Data Byte Count DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes Other than above 8 bytes regardless of the value of DLC3 to DLC0 Caution In the remote frame, there is no data field even if the data length code is not 0000B. 750 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 19-9. Data Field (Control field) Data field (CRC field) R D MSB Remark Data 0 (8 bits) MSB LSB Data 7 (8 bits) LSB D: Dominant = 0 R: Recessive = 1 <5> CRC field The CRC field is a 16-bit field that is used to check for errors in transmit data. Figure 19-10. CRC Field (Data field or control field) CRC field (ACK field) R D CRC sequence (15 bits) Remark CRC delimiter (1 bit) D: Dominant = 0 R: Recessive = 1 * The polynomial P(X) used to generate the 15-bit CRC sequence is expressed as follows. P(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1 * Transmitting node: Transmits the CRC sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field. * Receiving node: Compares the CRC sequence calculated using data bits that exclude the stuffing bits in the receive data with the CRC sequence in the CRC field. If the two CRC sequences do not match, the node issues an error frame. User's Manual U16541EJ5V1UD 751 CHAPTER 19 CAN CONTROLLER <6> ACK field The ACK field is used to acknowledge normal reception. Figure 19-11. ACK Field (CRC field) ACK field (End of frame) R D ACK slot (1 bit) Remark ACK delimiter (1 bit) D: Dominant = 0 R: Recessive = 1 * If no CRC error is detected, the receiving node sets the ACK slot to the dominant level. * The transmitting node outputs two recessive-level bits. <7> End of frame (EOF) The end of frame field indicates the end of data frame/remote frame. Figure 19-12. End of Frame (EOF) (ACK field) End of frame (Interframe space or overload frame) R D (7 bits) Remark D: Dominant = 0 R: Recessive = 1 752 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. * The bus state differs depending on the error status. (a) Error active node The interframe space consists of a 3-bit intermission field and a bus idle field. Figure 19-13. Interframe Space (Error Active Node) (Frame) Interframe space (Frame) R D Intermission (3 bits) Bus idle (0 to bits) Remarks 1. Bus idle: State in which the bus is not used by any node. 2. D: Dominant = 0 R: Recessive = 1 (b) Error passive node The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. Figure 19-14. Interframe Space (Error Passive Node) (Frame) R D (Frame) Interframe space Intermission (3 bits) Suspend transmission (8 bits) Remarks 1. Bus idle: Bus idle (0 to bits) State in which the bus is not used by any node. Suspend transmission: Sequence of 8 recessive-level bits transmitted from the node in the error passive status. 2. D: Dominant = 0 R: Recessive = 1 Usually, the intermission field is 3 bits. If the transmitting node detects a dominant level at the third bit of the intermission field, however, it executes transmission. * Operation in error status Table 19-6. Operation in Error Status Error Status Operation Error active A node in this status can transmit immediately after a 3-bit intermission. Error passive A node in this status can transmit 8 bits after the intermission. User's Manual U16541EJ5V1UD 753 CHAPTER 19 CAN CONTROLLER 19.2.4 Error frame An error frame is output by a node that has detected an error. Figure 19-15. Error Frame Error frame R D (<4>) <1> <2> <3> 6 bits 0 to 6 bits 8 bits (<5>) Interframe space or overload frame Error delimiter Error flag 2 Error flag 1 Error bit Remark D: Dominant = 0 R: Recessive = 1 Table 19-7. Definition of Error Frame Fields No. <1> Name Error flag 1 Bit Count Definition Error active node: 6 Outputs 6 dominant-level bits consecutively. Error passive node: Outputs 6 recessive-level bits consecutively. If another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> Error flag 2 0 to 6 Nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> Error delimiter 8 Outputs 8 recessive-level bits consecutively. If a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> Error bit - The bit at which the error was detected. The error flag is output from the bit next to the error bit. In the case of a CRC error, this bit is output following the ACK delimiter. <5> Interframe space/overload - An interframe space or overload frame starts from here. frame 754 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.2.5 Overload frame An overload frame is transmitted under the following conditions. * When the receiving node has not completed the reception operationNote * If a dominant level is detected at the first two bits during intermission * If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter Note In this CAN controller, all receive frames can be loaded without outputting an overload frame because of the enough high-speed internal processing. Figure 19-16. Overload Frame Overload frame R D (<4>) <1> <2> <3> 6 bits 0 to 6 bits 8 bits (<5>) Interframe space or overload frame Overload delimiter Overload flag (node n) Overload flag (node m) Frame Remark D: Dominant = 0 R: Recessive = 1 Node n node m Table 19-8. Definition of Overload Frame Fields No Name Bit Count Definition <1> Overload flag 6 Outputs 6 dominant-level bits consecutively. <2> Overload flag from other node 0 to 6 The node that received an overload flag in the interframe space <3> Overload delimiter 8 outputs an overload flag. Outputs 8 recessive-level bits consecutively. If a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> Frame - Output following an end of frame, error delimiter, or overload delimiter. <5> Interframe space/overload - An interframe space or overload frame starts from here. frame User's Manual U16541EJ5V1UD 755 CHAPTER 19 CAN CONTROLLER 19.3 Functions 19.3.1 Determining bus priority (1) When a node starts transmission: * During bus idle, the node that output data first transmits the data. (2) When more than one node starts transmission: * The node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value). * The transmitting node compares its output arbitration field and the data level on the bus. Table 19-9. Determining Bus Priority Level match Continuous transmission Level mismatch Continuous transmission (3) Priority of data frame and remote frame * When a data frame and a remote frame are on the bus, the data frame has priority because its RTR bit, the last bit in the arbitration field, carries a dominant level. Remark If the extended-format data frame and the standard-format remote frame conflict on the bus (if ID28 to ID18 of both of them are the same), the standard-format remote frame takes priority. 19.3.2 Bit stuffing Bit stuffing is used to establish synchronization by appending 1 bit of inverted-level data if the same level continues for 5 bits, in order to prevent a burst error. Table 19-10. Bit Stuffing Transmission During the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, 1 inverted-level bit of data is inserted before the following bit. Reception During the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, reception is continued after deleting the next bit. 19.3.3 Multi masters As the bus priority (a node which acquires transmission rights) is determined by the identifier, any node can be the bus master. 19.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. 756 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.3.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function puts the CAN controller in waiting mode to achieve low power consumption. The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop mode by bus operation (the CAN stop mode is controlled by CPU access). 19.3.6 Error control function (1) Error types Table 19-11. Error Types Type Description of Error Detection Method Comparison of the output level Bit error Detection State Detection Transmission/ Condition Reception Mismatch of levels and level on the bus Field/Frame Transmitting/ Bit that is outputting data on the bus receiving node at the start of frame to end of frame, Receiving node Start of frame to CRC sequence error frame and overload frame. Stuff error CRC error Check of the receive data at 6 consecutive bits of the stuff bit the same output level Comparison of the CRC Mismatch of CRC Receiving node CRC field Field/frame check of the fixed Detection of fixed Receiving node CRC delimiter format format violation sequence generated from the receive data and the received CRC sequence Form error ACK field End of frame Error frame Overload frame ACK error Check of the ACK slot by the Detection of recessive transmitting node level in ACK slot Transmitting node ACK slot (2) Output timing of error frame Table 19-12. Output Timing of Error Frame Type Bit error, stuff error, form Output Timing Error frame output is started at the timing of the bit following the detected error. error, ACK error CEC error Error frame output is started at the timing of the bit following the ACK delimiter. (3) Processing in case of error The transmission node re-transmits the data frame or remote frame after the error frame. (However, it does not re-transmit the frame in the single-shot mode.) User's Manual U16541EJ5V1UD 757 CHAPTER 19 CAN CONTROLLER (4) Error state (a) Types of error states The following three types of error states are defined by the CAN specification. * Error active * Error passive * Bus-off These types of error states are classified by the values of the C0ERC.TEC7 to C0ERC.TEC0 bits (transmission error counter bits) and the C0ERC.REC6 to C0ERC.REC0 bits (reception error counter bits) as shown in Table 19-13. The present error state is indicated by the C0INFO register. When each error counter value becomes equal to or greater than the error warning level (96), the C0INFO.TECS0 or C0INFO.RECS0 bit is set to 1. In this case, the bus state must be tested because it is considered that the bus has a serious fault. An error counter value of 128 or more indicates an error passive state and the TECS1 or RECS1 bit is set to 1. * If the value of the transmission error counter is greater than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the C0INFO.BOFF bit is set to 1. * If only one node is active on the bus at startup (i.e., when the bus is connected only to the local station), ACK is not returned even if data is transmitted. Consequently, re-transmission of the error frame and data is repeated. In the error passive state, however, the transmission error counter is not incremented and the bus-off state is not reached. Table 19-13. Types of Error States Type Error active Error passive Bus-off Note Operation Transmission Value of Error Counter 0 to 95 Indication of C0INFO Register Operation Specific to Error State TECS1, TECS0 = 00 * Outputs an active error flag (6 consecutive dominantlevel bits) on detection of the error. Reception 0 to 95 RECS1, RECS0 = 00 Transmission 96 to 127 TECS1, TECS0 = 01 Reception 96 to 127 RECS1, RECS0 = 01 Transmission 128 to 255 TECS1, TECS0 = 11 Reception 128 or more RECS1, RECS0 = 11 Transmission 256 or more Note (not indicated) BOFF = 1, TECS1, TECS0 = 11 * Outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. * Transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). * Communication is not possible. However, when the frame is received, no messages are stored and the following operations are performed. <1> TSOUT toggles. <2> REC is incremented/decremented. <3> VALID bit is set. * If the initialization mode is set, after request to transit to an operation mode other than the initialization mode, 11 consecutive recessive-level bits are generated 128 times, and then the error counter is reset to 0 and the error active state can be restored. The value of the transmit error counter (TEC) does not carry any meaning if BOFF has been set. If an error that increments the value of the transmission error counter by 8 while the counter value is in a range of 248 to 255 occurs, the counter is not incremented and the bus-off state is assumed. 758 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter counts up immediately after error detection. <R> Table 19-14. Error Counter State Receiving node detects an error (except bit error in the active error Transmission Error Counter Reception Error Counter (TEC7 to TEC0 Bits) (REC6 to REC0 Bits) No change +1 (REPS bit = 0) No change +8 (REPS bit = 0) +8 No change +8 No change No change +8 (REPS bit = 0) +8 (transmitting) +8 (receiving, REPS bit = 0) -1 No change No change * -1 (1 REC6 to REC0 flag or overload flag). Receiving node detects dominant level following error flag of error frame. Transmitting node transmits an error flag. [As exceptions, the error counter does not change in the following cases.] <1> ACK error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> A stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. Bit error detection while active error flag or overload flag is being output (error-active transmitting node) Bit error detection while active error flag or overload flag is being output (error-active receiving node) When the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant-level bits. When the node detects 8 consecutive dominant levels after a passive error flag When the transmitting node has completed transmission without error (0 if error counter = 0) When the receiving node has completed reception without error 127, REPS bit = 0) * 0 (REC6 to REC0 = 0, REPS bit = 0) * Any value of 119 to 127 is set (REPS bit = 1) (c) Occurrence of bit error in intermission An overload frame is generated. Caution If an error occurs, it is controlled according to the contents of the transmission error counter and reception error counter before the error occurred. The value of the error counter is incremented after the error flag has been output. User's Manual U16541EJ5V1UD 759 CHAPTER 19 CAN CONTROLLER (5) Recovery from bus-off state When the CAN module is in the bus-off state, the transmission pins (CTXD0) cut off from the CAN bus always output the recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence. <1> Request to enter the CAN initialization mode <2> Request to enter a CAN operation mode (a) Recovery operation through normal recovery sequence (b) Forced recovery operation that skips recovery sequence (a) Recovery from bus-off state through normal recovery sequence The CAN module first issues a request to enter the initialization mode (see timing <1> in Figure 19-17). This request will be immediately acknowledged, and the C0CTRL.OPMODE2 to OPMODE0 bits are cleared to 000B. Processing such as analyzing the fault that has caused the bus-off state, re-defining the CAN module and message buffer using application software, or stopping the operation of the CAN module can be performed by clearing the C0GMCTRL.GOM bit to 0. Next, the module requests to change the mode from the initialization mode to an operation mode (see timing <2> in Figure 19-17). This starts an operation to recover the CAN module from the bus-off state. The conditions under which the module can recover from the bus-off state are defined by the CAN protocol ISO 11898, and it is necessary to detect 11 consecutive recessive-level bits more than 128 times. At this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. When the recovery conditions are satisfied (see timing <3> in Figure 19-17), the CAN module can enter the operation mode it has requested. Until the CAN module enters this operation mode, it stays in the initialization mode. Whether the CAN module has completed transition to any other operation mode can be confirmed by reading OPMODE. Before transition to any other operation mode is completed, OPMODE2 to OPMODE0 bits = 000B is read. During the bus-off period and bus-off recovery sequence, the C0INFO.BOFF bit stays set (to 1). In the bus-off recovery sequence, the reception error counter (C0ERC.REC0 to C0ERC.REC6) counts the number of times 11 consecutive recessive-level bits have been detected on the bus. Therefore, the recovery state can be checked by reading the REC0 to REC6 bits. <R> Cautions 1. If a request to change the mode from the initialization mode to any operation mode to execute the bus-off recovery sequence again during a bus-off recovery sequence, the bus-off recovery sequence starts from the beginning and 11 contiguous recessive bits are counted 128 times again on the bus. 2. In the bus-off recovery sequence, the REC0 to REC6 bits counts up (+1) each time 11 consecutive recessive-level bits have been detected. Even during the bus-off period, the CAN module can enter the CAN sleep mode or CAN stop mode. To be released from the bus-off state, the module must enter the initialization mode once. If the module is in the CAN sleep mode or CAN stop mode, however, it cannot directly enter the initialization mode. In this case, the bus off recovery sequence is started at the same time as the CAN sleep mode is released even without shifting to the initialization mode. In addition to clearing the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits by software, the bus off recovery sequence is also started due to wakeup by dominant edge detection on the CAN bus (when the CAN clock is supplied, the PSMODE0 bit must be cleared by software after the dominant edge has been detected.) 760 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-17. Recovery from Bus-off State Through Normal Recovery Sequence TEC > FFH bus-off error-passive bus-off-recovery-sequence error-active BOFF bit in C0INFO register <1> OPMODE[2:0] in C0CTRL register (written by user) 00H <2> 00H 00H <3> OPMODE[2:0] in C0CTRL register (read by user) 00H TEC[7:0] in C0ERC 80H TEC[7:0] FFH register REC[7:0] in C0ERC register 00H 00H FFH < TEC [7:0] 00H REC[7:0] 80H 00H Undefined 00H TEC[7:0] < 80H 00H REC[7:0] < 80H (b) Forced recovery operation that skips bus-off recovery sequence The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. Here is the procedure. First, the CAN module requests to enter the initialization mode. For the operation and points to be noted at this time, see 19.3.6 (5) (a) Recovery from bus-off state through normal recovery sequence. Next, the module requests to enter an operation mode. At the same time, the C0CTRL.CCERC bit must be set to 1. As a result, the bus-off recovery sequence defined by the CAN protocol ISO 11898 is skipped, and the module immediately enters the operation mode. In this case, the module is connected to the CAN bus after it has monitored 11 consecutive recessive-level bits. For details, see the processing in Figure 19-54. Caution This function is not defined by the CAN protocol ISO 11898. When using this function, thoroughly evaluate its effect on the network system. (6) Initializing CAN module error counter register (C0ERC) in initialization mode If it is necessary to initialize the C0ERC and C0INFO registers for debugging or evaluating a program, they can be initialized to the default value by setting the C0CTRL.CCERC bit in the initialization mode. When initialization has been completed, the CCERC bit is automatically cleared to 0. Cautions 1. This function is enabled only in the initialization mode. Even if the CCERC bit is set to 1 in a CAN operation mode, the C0ERC and C0INFO registers are not initialized. 2. The CCERC bit can be set at the same time as the request to enter a CAN operation mode. User's Manual U16541EJ5V1UD 761 CHAPTER 19 CAN CONTROLLER 19.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (fCAN) supplied to CAN. This prescaler generates a CAN protocol layer base clock (fTQ) that is the CAN module system clock (fCANMOD) divided by 1 to 256 (see 19.6 (12) CAN0 module bit rate prescaler register (C0BRP)). (2) Data bit time (8 to 25 time quanta) One data bit time is defined as shown in Figure 19-18. 1 Time Quanta = 1/fTQ The CAN controller sets the data bit time by replacing it with the bit timing parameters such as time segment 1, time segment 2, and reSynchronization Jump Width (SJW), as shown in Figure 19-18. Time segment 1 is equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the CAN protocol specification. Time segment 2 is equivalent to phase segment 2. Figure 19-18. Segment Setting Data bit time (DBT) Sync segment Prop segment Phase segment 1 Time segment 1 (TSEG1) Phase segment 2 Time segment 2 Sample point (SPT) Segment name Settable range Time segment 1 (TSEG1) 2TQ to 16TQ Time segment 2 (TSEG2) 1TQ to 8TQ Notes on setting to conform to CAN specification - IPT of the CAN controller is 0TQ. To conform to the CAN <R> protocol specification, therefore, a length equal or less to phase segment 1 must be set here. This means that the length of time segment 1 minus 1TQ is the settable upper limit of time segment 2. reSynchronization Jump Width The length of time segment 1 minus 1TQ or 4TQ, 1TQ to 4TQ whichever smaller. (SJW) Remark IPT: Information Processing Time TQ: Time Quanta 762 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Remark The CAN protocol specification defines the segments constituting the data bit time as shown in Figure 19-19. Figure 19-19. Configuration of Data Bit Time Defined by CAN Specification Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 SJW Sample point (SPT) Segment name Sync segment Segment length Description This segment starts at the edge where the level changes 1 from recessive to dominant when hardware synchronization (Synchronization segment) is established. Prop segment Programmable to 1 to 8, This segment absorbs the delay of the output buffer, CAN (Propagation segment) or greater bus, and input buffer. Phase segment 1 Programmable to 1 to 8 The length of this segment is set so that ACK is returned before the start of phase segment 1. Time of prop segment (Delay of output buffer) + 2 x (Phase buffer segment 1) (Delay of CAN bus) + (Delay of input buffer) Phase segment 2 Phase segment 1 or IPT, This segment compensates for an error in the data bit time. (Phase buffer segment 2) whichever greater The longer this segment, the wider the permissible range but the slower the communication speed. SJW Programmable from 1TQ This width sets the upper limit of expansion or contraction (reSynchronization Jump to segment 1TQ to 4TQ, of the phase segment during resynchronization. Width) whichever is smaller Remark IPT: Information Processing Time TQ: Time Quanta User's Manual U16541EJ5V1UD 763 CHAPTER 19 CAN CONTROLLER (3) Synchronizing data bit * The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. * The transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) Hardware synchronization This synchronization is established when the receiving node detects the start of frame in the interframe space. * When a falling edge is detected on the bus, that TQ means the sync segment and the next segment is the prop segment. In this case, synchronization is established regardless of SJW. Figure 19-20. Hardware Synchronization to Detect Dominant Level During Bus Idle Interframe space Start of frame CAN bus Bit timing 764 Sync segment Prop segment Phase segment 1 User's Manual U16541EJ5V1UD Phase segment 2 CHAPTER 19 CAN CONTROLLER (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). * The phase error of the edge is given by the relative position of the detected edge and sync segment. <Sign of phase error> 0: If the edge is within the sync segment Positive: If the edge is before the sample point (phase error) Negative: If the edge is after the sample point (phase error) If phase error is positive: Phase segment 1 is longer by specified SJW. If phase error is negative: Phase segment 2 is shorter by specified SJW. * The sample point of the data of the receiving node moves relatively due to the "discrepancy" in the baud rate between the transmitting node and receiving node. Figure 19-21. Resynchronization If phase error is positive CAN bus Bit timing Sync segment Prop segment Phase segment 2 Phase segment 1 Sample point If phase error is negative CAN bus Bit timing Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point User's Manual U16541EJ5V1UD 765 CHAPTER 19 CAN CONTROLLER 19.4 Connection with Target System The microcontroller with on-chip CAN controller has to be connected to the CAN bus using an external transceiver. Figure 19-22. Connection to CAN Bus Microcontroller with on-chip CAN controller 766 CTxD0 CRxD0 CANL Transceiver User's Manual U16541EJ5V1UD CANH CHAPTER 19 CAN CONTROLLER 19.5 Internal Registers of CAN Controller 19.5.1 CAN controller configuration Table 19-15. List of CAN Controller Registers Item CAN global registers Register Name CAN0 global control register (C0GMCTRL) CAN0 global clock selection register (C0GMCS) CAN0 global automatic block transmission control register (C0GMABT) CAN0 global automatic block transmission delay setting register (C0GMABTD) CAN module registers CAN0 module mask 1 register (C0MASK1L, C0MASK1H) CAN0 module mask 2 register (C0MASK2L, C0MASK2H) CAN0 module mask 3 register (C0MASK3L, C0MASK3H) CAN0 module mask 4 registers (C0MASK4L, C0MASK4H) CAN0 module control register (C0CTRL) CAN0 module last error information register (C0LEC) CAN0 module information register (C0INFO) CAN0 module error counter register (C0ERC) CAN0 module interrupt enable register (C0IE) CAN0 module interrupt status register (C0INTS) CAN0 module bit rate prescaler register (C0BRP) CAN0 module bit rate register (C0BTR) CAN0 module last in-pointer register (C0LIPT) CAN0 module receive history list register (C0RGPT) CAN0 module last out-pointer register (C0LOPT) CAN0 module transmit history list register (C0TGPT) CAN0 module time stamp register (C0TS) Message buffer registers CAN0 message data byte 01 register m (C0MDATA01m) CAN0 message data byte 0 register m (C0MDATA0m) CAN0 message data byte 1 register m (C0MDATA1m) CAN0 message data byte 23 register m (C0MDATA23m) CAN0 message data byte 2 register m (C0MDATA2m) CAN0 message data byte 3 register m (C0MDATA3m) CAN0 message data byte 45 register m (C0MDATA45m) CAN0 message data byte 4 register m (C0MDATA4m) CAN0 message data byte 5 register m (C0MDATA5m) CAN0 message data byte 67 register m (C0MDATA67m) CAN0 message data byte 6 register m (C0MDATA6m) CAN0 message data byte 7 register m (C0MDATA7m) CAN0 message data length register m (C0MDLCm) CAN0 message configuration register m (C0MCONFm) CAN0 message ID register m (C0MIDLm, C0MIDHm) CAN0 message control register m (C0MCTRLm) Remarks 1. The CAN global register is defined as C0GM <register function>. The CAN module register is defined as C0 <register function>. The message buffer register is defined as C0M <register function>. 2. m = 00 to 31 User's Manual U16541EJ5V1UD 767 CHAPTER 19 CAN CONTROLLER 19.5.2 Register access type Table 19-16. Register Access Types (1/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC000H CAN0 global control register C0GMCTRL 03FEC002H CAN0 global clock selection register C0GMCS 03FEC006H CAN0 global automatic block transmission register C0GMABT 03FEC008H CAN0 global automatic block transmission delay register C0GMABTD 03FEC040H CAN0 module mask 1 register 03FEC042H 03FEC044H CAN0 module mask 2 register 03FEC046H 03FEC048H CAN0 module mask 3 register 03FEC04AH 03FEC04CH CAN0 module mask 4 register 03FEC04EH 16 Bits R/W 0000H 0FH 0000H 00H C0MASK1L Undefined C0MASK1H Undefined C0MASK2L Undefined C0MASK2H Undefined C0MASK3L Undefined C0MASK3H Undefined C0MASK4L Undefined C0MASK4H Undefined 03FEC050H CAN0 module control register C0CTRL 03FEC052H CAN0 module last error code register C0LEC 03FEC053H CAN0 module information register C0INFO 03FEC054H CAN0 module error counter register C0ERC 03FEC056H CAN0 module interrupt enable register C0IE 03FEC058H CAN0 module interrupt status register C0INTS 03FEC05AH CAN0 module bit-rate prescaler register C0BRP 03FEC05CH CAN0 module bit-rate register C0BTR 03FEC05EH CAN0 module last in-pointer register C0LIPT R 03FEC060H CAN0 module receive history list register C0RGPT R/W 03FEC062H CAN0 module last out-pointer register C0LOPT R 03FEC064H CAN0 module transmit history list register C0TGPT R/W 03FEC066H CAN0 module time stamp register C0TS 768 8 Bits After Reset User's Manual U16541EJ5V1UD R 0000H 00H 00H R/W 0000H 0000H 0000H FFH 370FH Undefined xx02H Undefined xx02H 0000H CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (2/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC100H After Reset 8 Bits 16 Bits CAN0 message data byte 01 register 00 C0MDATA0100 03FEC100H CAN0 message data byte 0 register 00 C0MDATA000 Undefined 03FEC101H CAN0 message data byte 1 register 00 C0MDATA100 Undefined CAN0 message data byte 23 register 00 C0MDATA2300 03FEC102H CAN0 message data byte 2 register 00 C0MDATA200 Undefined 03FEC103H CAN0 message data byte 3 register 00 C0MDATA300 Undefined CAN0 message data byte 45 register 00 C0MDATA4500 03FEC104H CAN0 message data byte 4 register 00 C0MDATA400 Undefined 03FEC105H CAN0 message data byte 5 register 00 C0MDATA500 Undefined CAN0 message data byte 67 register 00 C0MDATA6700 03FEC106H CAN0 message data byte 6 register 00 C0MDATA600 Undefined 03FEC107H CAN0 message data byte 7 register 00 C0MDATA700 Undefined 03FEC108H CAN0 message data length register 00 C0MDLC00 0000xxxxB 03FEC109H CAN0 message configuration register 00 C0MCONF00 Undefined 03FEC10AH CAN0 message identifier register 00 C0MIDL00 Undefined C0MIDH00 Undefined C0MCTRL00 00x00000 03FEC102H 03FEC104H 03FEC106H 03FEC10CH 03FEC10EH CAN0 message control register 00 R/W Undefined Undefined Undefined Undefined 000xx000B 03FEC120H CAN0 message data byte 01 register 01 C0MDATA0101 03FEC120H CAN0 message data byte 0 register 01 C0MDATA001 Undefined 03FEC121H CAN0 message data byte 1 register 01 C0MDATA101 Undefined CAN0 message data byte 23 register 01 C0MDATA2301 03FEC122H CAN0 message data byte 2 register 01 C0MDATA201 Undefined 03FEC123H CAN0 message data byte 3 register 01 C0MDATA301 Undefined CAN0 message data byte 45 register 01 C0MDATA4501 03FEC124H CAN0 message data byte 4 register 01 C0MDATA401 Undefined 03FEC125H CAN0 message data byte 5 register 01 C0MDATA501 Undefined CAN0 message data byte 67 register 01 C0MDATA6701 03FEC126H CAN0 message data byte 6 register 01 C0MDATA601 Undefined 03FEC127H CAN0 message data byte 7 register 01 C0MDATA701 Undefined 03FEC128H CAN0 message data length register 01 C0MDLC01 0000xxxxB 03FEC129H CAN0 message configuration register 01 C0MCONF01 Undefined 03FEC12AH CAN0 message identifier register 01 C0MIDL01 Undefined C0MIDH01 Undefined C0MCTRL01 00x00000 03FEC122H 03FEC124H 03FEC126H 03FEC12CH 03FEC12EH CAN0 message control register 01 Undefined Undefined Undefined Undefined 000xx000B User's Manual U16541EJ5V1UD 769 CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (3/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC140H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 02 C0MDATA0102 03FEC140H CAN0 message data byte 0 register 02 C0MDATA002 Undefined 03FEC141H CAN0 message data byte 1 register 02 C0MDATA102 Undefined CAN0 message data byte 23 register 02 C0MDATA2302 03FEC142H CAN0 message data byte 2 register 02 C0MDATA202 Undefined 03FEC143H CAN0 message data byte 3 register 02 C0MDATA302 Undefined CAN0 message data byte 45 register 02 C0MDATA4502 CAN0 message data byte 4 register 02 C0MDATA402 03FEC142H 03FEC144H 03FEC144H 03FEC145H Undefined Undefined Undefined Undefined CAN0 message data byte 5 register 02 C0MDATA502 CAN0 message data byte 67 register 02 C0MDATA6702 03FEC146H CAN0 message data byte 6 register 02 C0MDATA602 Undefined 03FEC147H CAN0 message data byte 7 register 02 C0MDATA702 Undefined 03FEC148H CAN0 message data length register 02 C0MDLC02 0000xxxxB 03FEC149H CAN0 message configuration register 02 C0MCONF02 Undefined 03FEC14AH CAN0 message identifier register 02 C0MIDL02 Undefined C0MIDH02 Undefined 00x00000 03FEC146H 03FEC14CH Undefined Undefined 03FEC14EH CAN0 message control register 02 C0MCTRL02 03FEC160H CAN0 message data byte 01 register 03 C0MDATA0103 03FEC160H CAN0 message data byte 0 register 03 C0MDATA003 Undefined 03FEC161H CAN0 message data byte 1 register 03 C0MDATA103 Undefined CAN0 message data byte 23 register 03 C0MDATA2303 03FEC162H CAN0 message data byte 2 register 03 C0MDATA203 Undefined 03FEC163H CAN0 message data byte 3 register 03 C0MDATA303 Undefined CAN0 message data byte 45 register 03 C0MDATA4503 03FEC164H CAN0 message data byte 4 register 03 C0MDATA403 Undefined 03FEC165H CAN0 message data byte 5 register 03 C0MDATA503 Undefined CAN0 message data byte 67 register 03 C0MDATA6703 03FEC166H CAN0 message data byte 6 register 03 C0MDATA603 Undefined 03FEC167H CAN0 message data byte 7 register 03 C0MDATA703 Undefined 03FEC168H CAN0 message data length register 03 C0MDLC03 0000xxxxB 03FEC169H CAN0 message configuration register 03 C0MCONF03 Undefined 03FEC16AH CAN0 message identifier register 03 C0MIDL03 C0MIDH03 Undefined CAN0 message control register 03 C0MCTRL03 00x00000 000xx000B 03FEC162H 03FEC164H 03FEC166H 03FEC16CH 03FEC16EH Undefined Undefined Undefined Undefined Undefined 000xx000B 770 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (4/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC180H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 04 C0MDATA0104 03FEC180H CAN0 message data byte 0 register 04 C0MDATA004 Undefined 03FEC181H CAN0 message data byte 1 register 04 C0MDATA104 Undefined CAN0 message data byte 23 register 04 C0MDATA2304 03FEC182H CAN0 message data byte 2 register 04 C0MDATA204 Undefined 03FEC183H CAN0 message data byte 3 register 04 C0MDATA304 Undefined CAN0 message data byte 45 register 04 C0MDATA4504 03FEC184H CAN0 message data byte 4 register 04 C0MDATA404 03FEC185H CAN0 message data byte 5 register 04 C0MDATA504 CAN0 message data byte 67 register 04 C0MDATA6704 03FEC186H CAN0 message data byte 6 register 04 C0MDATA604 Undefined 03FEC187H CAN0 message data byte 7 register 04 C0MDATA704 Undefined 03FEC188H CAN0 message data length register 04 C0MDLC04 0000xxxxB 03FEC189H CAN0 message configuration register 04 C0MCONF04 Undefined 03FEC18AH CAN0 message identifier register 04 C0MIDL04 Undefined C0MIDH04 Undefined 00x00000 03FEC182H 03FEC184H 03FEC186H 03FEC18CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC18EH CAN0 message control register 04 C0MCTRL04 03FEC1A0H CAN0 message data byte 01 register 05 C0MDATA0105 03FEC1A0H CAN0 message data byte 0 register 05 C0MDATA005 Undefined 03FEC1A1H CAN0 message data byte 1 register 05 C0MDATA105 Undefined CAN0 message data byte 23 register 05 C0MDATA2305 03FEC1A2H CAN0 message data byte 2 register 05 C0MDATA205 Undefined 03FEC1A3H CAN0 message data byte 3 register 05 C0MDATA305 Undefined CAN0 message data byte 45 register 05 C0MDATA4505 03FEC1A4H CAN0 message data byte 4 register 05 C0MDATA405 Undefined 03FEC1A5H CAN0 message data byte 5 register 05 C0MDATA505 Undefined CAN0 message data byte 67 register 05 C0MDATA6705 03FEC1A6H CAN0 message data byte 6 register 05 C0MDATA605 Undefined 03FEC1A7H CAN0 message data byte 7 register 05 C0MDATA705 Undefined 03FEC1A8H CAN0 message data length register 05 C0MDLC05 0000xxxxB 03FEC1A9H CAN0 message configuration register 05 C0MCONF05 Undefined 03FEC1AAH CAN0 message identifier register 05 C0MIDL05 C0MIDH05 Undefined CAN0 message control register 05 C0MCTRL05 00x00000 000xx000B 03FEC1A2H 03FEC1A4H 03FEC1A6H 03FEC1ACH 03FEC1AEH Undefined Undefined Undefined Undefined Undefined 000xx000B User's Manual U16541EJ5V1UD 771 CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (5/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC1C0H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 06 C0MDATA0106 03FEC1C0H CAN0 message data byte 0 register 06 C0MDATA006 Undefined 03FEC1C1H CAN0 message data byte 1 register 06 C0MDATA106 Undefined CAN0 message data byte 23 register 06 C0MDATA2306 03FEC1C2H CAN0 message data byte 2 register 06 C0MDATA206 Undefined 03FEC1C3H CAN0 message data byte 3 register 06 C0MDATA306 Undefined CAN0 message data byte 45 register 06 C0MDATA4506 03FEC1C4H CAN0 message data byte 4 register 06 C0MDATA406 03FEC1C5H CAN0 message data byte 5 register 06 C0MDATA506 CAN0 message data byte 67 register 06 C0MDATA6706 03FEC1C6H CAN0 message data byte 6 register 06 C0MDATA606 Undefined 03FEC1C7H CAN0 message data byte 7 register 06 C0MDATA706 Undefined 03FEC1C8H CAN0 message data length register 06 C0MDLC06 0000xxxxB 03FEC1C9H CAN0 message configuration register 06 C0MCONF06 Undefined 03FEC1CAH CAN0 message identifier register 06 C0MIDL06 Undefined C0MIDH06 Undefined 00x00000 03FEC1C2H 03FEC1C4H 03FEC1C6H 03FEC1CCH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC1CEH CAN0 message control register 06 C0MCTRL06 03FEC1E0H CAN0 message data byte 01 register 07 C0MDATA0107 03FEC1E0H CAN0 message data byte 0 register 07 C0MDATA007 Undefined 03FEC1E1H CAN0 message data byte 1 register 07 C0MDATA107 Undefined CAN0 message data byte 23 register 07 C0MDATA2307 03FEC1E2H CAN0 message data byte 2 register 07 C0MDATA207 Undefined 03FEC1E3H CAN0 message data byte 3 register 07 C0MDATA307 Undefined CAN0 message data byte 45 register 07 C0MDATA4507 000xx000B 03FEC1E2H 03FEC1E4H Undefined Undefined Undefined 03FEC1E4H CAN0 message data byte 4 register 07 C0MDATA407 Undefined 03FEC1E5H CAN0 message data byte 5 register 07 C0MDATA507 Undefined CAN0 message data byte 67 register 07 C0MDATA6707 03FEC1E6H CAN0 message data byte 6 register 07 C0MDATA607 Undefined 03FEC1E7H CAN0 message data byte 7 register 07 C0MDATA707 Undefined 03FEC1E8H CAN0 message data length register 07 C0MDLC07 0000xxxxB 03FEC1E9H CAN0 message configuration register 07 C0MCONF07 Undefined 03FEC1EAH CAN0 message identifier register 07 C0MIDL07 C0MIDH07 Undefined CAN0 message control register 07 C0MCTRL07 00x00000 03FEC1E6H 03FEC1ECH 03FEC1EEH Undefined Undefined 000xx000B 772 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (6/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC200H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 08 C0MDATA0108 03FEC200H CAN0 message data byte 0 register 08 C0MDATA008 Undefined 03FEC201H CAN0 message data byte 1 register 08 C0MDATA108 Undefined CAN0 message data byte 23 register 08 C0MDATA2308 03FEC202H CAN0 message data byte 2 register 08 C0MDATA208 Undefined 03FEC203H CAN0 message data byte 3 register 08 C0MDATA308 Undefined CAN0 message data byte 45 register 08 C0MDATA4508 03FEC204H CAN0 message data byte 4 register 08 C0MDATA408 03FEC205H CAN0 message data byte 5 register 08 C0MDATA508 CAN0 message data byte 67 register 08 C0MDATA6708 03FEC206H CAN0 message data byte 6 register 08 C0MDATA608 Undefined 03FEC207H CAN0 message data byte 7 register 08 C0MDATA708 Undefined 03FEC208H CAN0 message data length register 08 C0MDLC08 0000xxxxB 03FEC209H CAN0 message configuration register 08 C0MCONF08 Undefined 03FEC20AH CAN0 message identifier register 08 C0MIDL08 Undefined C0MIDH08 Undefined 00x00000 03FEC202H 03FEC204H 03FEC206H 03FEC20CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC20EH CAN0 message control register 08 C0MCTRL08 03FEC220H CAN0 message data byte 01 register 09 C0MDATA0109 03FEC220H CAN0 message data byte 0 register 09 C0MDATA009 Undefined 03FEC221H CAN0 message data byte 1 register 09 C0MDATA109 Undefined CAN0 message data byte 23 register 09 C0MDATA2309 03FEC222H CAN0 message data byte 2 register 09 C0MDATA209 Undefined 03FEC223H CAN0 message data byte 3 register 09 C0MDATA309 Undefined CAN0 message data byte 45 register 09 C0MDATA4509 03FEC224H CAN0 message data byte 4 register 09 C0MDATA409 Undefined 03FEC225H CAN0 message data byte 5 register 09 C0MDATA509 Undefined CAN0 message data byte 67 register 09 C0MDATA6709 03FEC226H CAN0 message data byte 6 register 09 C0MDATA609 Undefined 03FEC227H CAN0 message data byte 7 register 09 C0MDATA709 Undefined 03FEC228H CAN0 message data length register 09 C0MDLC09 0000xxxxB 03FEC229H CAN0 message configuration register 09 C0MCONF09 Undefined 03FEC22AH CAN0 message identifier register 09 C0MIDL09 C0MIDH09 Undefined CAN0 message control register 09 C0MCTRL09 00x00000 000xx000B 03FEC222H 03FEC224H 03FEC226H 03FEC22CH 03FEC22EH Undefined Undefined Undefined Undefined Undefined 000xx000B User's Manual U16541EJ5V1UD 773 CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (7/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC240H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 10 C0MDATA0110 03FEC240H CAN0 message data byte 0 register 10 C0MDATA010 Undefined 03FEC241H CAN0 message data byte 1 register 10 C0MDATA110 Undefined CAN0 message data byte 23 register 10 C0MDATA2310 03FEC242H CAN0 message data byte 2 register 10 C0MDATA210 Undefined 03FEC243H CAN0 message data byte 3 register 10 C0MDATA310 Undefined CAN0 message data byte 45 register 10 C0MDATA4510 03FEC244H CAN0 message data byte 4 register 10 C0MDATA410 03FEC245H CAN0 message data byte 5 register 10 C0MDATA510 CAN0 message data byte 67 register 10 C0MDATA6710 03FEC246H CAN0 message data byte 6 register 10 C0MDATA610 Undefined 03FEC247H CAN0 message data byte 7 register 10 C0MDATA710 Undefined 03FEC248H CAN0 message data length register 10 C0MDLC10 0000xxxxB 03FEC249H CAN0 message configuration register 10 C0MCONF10 Undefined 03FEC24AH CAN0 message identifier register 10 C0MIDL10 Undefined C0MIDH10 Undefined 00x00000 03FEC242H 03FEC244H 03FEC246H 03FEC24CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC24EH CAN0 message control register 10 C0MCTRL10 03FEC260H CAN0 message data byte 01 register 11 C0MDATA0111 03FEC260H CAN0 message data byte 0 register 11 C0MDATA011 Undefined 03FEC261H CAN0 message data byte 1 register 11 C0MDATA111 Undefined CAN0 message data byte 23 register 11 C0MDATA2311 03FEC262H CAN0 message data byte 2 register 11 C0MDATA211 Undefined 03FEC263H CAN0 message data byte 3 register 11 C0MDATA311 Undefined CAN0 message data byte 45 register 11 C0MDATA4511 000xx000B 03FEC262H 03FEC264H Undefined Undefined Undefined 03FEC264H CAN0 message data byte 4 register 11 C0MDATA411 Undefined 03FEC265H CAN0 message data byte 5 register 11 C0MDATA511 Undefined CAN0 message data byte 67 register 11 C0MDATA6711 03FEC266H CAN0 message data byte 6 register 11 C0MDATA611 Undefined 03FEC267H CAN0 message data byte 7 register 11 C0MDATA711 Undefined 03FEC268H CAN0 message data length register 11 C0MDLC11 0000xxxxB 03FEC269H CAN0 message configuration register 11 C0MCONF11 Undefined 03FEC26AH CAN0 message identifier register 11 C0MIDL11 C0MIDH11 Undefined CAN0 message control register 11 C0MCTRL11 00x00000 03FEC266H 03FEC26CH 03FEC26EH Undefined Undefined 000xx000B 774 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (8/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC280H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 12 C0MDATA0112 03FEC280H CAN0 message data byte 0 register 12 C0MDATA012 Undefined 03FEC281H CAN0 message data byte 1 register 12 C0MDATA112 Undefined CAN0 message data byte 23 register 12 C0MDATA2312 03FEC282H CAN0 message data byte 2 register 12 C0MDATA212 Undefined 03FEC283H CAN0 message data byte 3 register 12 C0MDATA312 Undefined CAN0 message data byte 45 register 12 C0MDATA4512 03FEC284H CAN0 message data byte 4 register 12 C0MDATA412 03FEC285H CAN0 message data byte 5 register 12 C0MDATA512 CAN0 message data byte 67 register 12 C0MDATA6712 03FEC286H CAN0 message data byte 6 register 12 C0MDATA612 Undefined 03FEC287H CAN0 message data byte 7 register 12 C0MDATA712 Undefined 03FEC288H CAN0 message data length register 12 C0MDLC12 0000xxxxB 03FEC289H CAN0 message configuration register 12 C0MCONF12 Undefined 03FEC28AH CAN0 message identifier register 12 C0MIDL12 Undefined C0MIDH12 Undefined 00x00000 03FEC282H 03FEC284H 03FEC286H 03FEC28CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC28EH CAN0 message control register 12 C0MCTRL12 03FEC2A0H CAN0 message data byte 01 register 13 C0MDATA0113 03FEC2A0H CAN0 message data byte 0 register 13 C0MDATA013 Undefined 03FEC2A1H CAN0 message data byte 1 register 13 C0MDATA113 Undefined CAN0 message data byte 23 register 13 C0MDATA2313 03FEC2A2H CAN0 message data byte 2 register 13 C0MDATA213 Undefined 03FEC2A3H CAN0 message data byte 3 register 13 C0MDATA313 Undefined CAN0 message data byte 45 register 13 C0MDATA4513 03FEC2A4H CAN0 message data byte 4 register 13 C0MDATA413 Undefined 03FEC2A5H CAN0 message data byte 5 register 13 C0MDATA513 Undefined CAN0 message data byte 67 register 13 C0MDATA6713 03FEC2A6H CAN0 message data byte 6 register 13 C0MDATA613 Undefined 03FEC2A7H CAN0 message data byte 7 register 13 C0MDATA713 Undefined 03FEC2A8H CAN0 message data length register 13 C0MDLC13 0000xxxxB 03FEC2A9H CAN0 message configuration register 13 C0MCONF13 Undefined 03FEC2AAH CAN0 message identifier register 13 C0MIDL13 C0MIDH13 Undefined CAN0 message control register 13 C0MCTRL13 00x00000 000xx000B 03FEC2A2H 03FEC2A4H 03FEC2A6H 03FEC2ACH 03FEC2AEH Undefined Undefined Undefined Undefined Undefined 000xx000B User's Manual U16541EJ5V1UD 775 CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (9/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC2C0H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 14 C0MDATA0114 03FEC2C0H CAN0 message data byte 0 register 14 C0MDATA014 Undefined 03FEC2C1H CAN0 message data byte 1 register 14 C0MDATA114 Undefined CAN0 message data byte 23 register 14 C0MDATA2314 03FEC2C2H CAN0 message data byte 2 register 14 C0MDATA214 Undefined 03FEC2C3H CAN0 message data byte 3 register 14 C0MDATA314 Undefined CAN0 message data byte 45 register 14 C0MDATA4514 03FEC2C4H CAN0 message data byte 4 register 14 C0MDATA414 03FEC2C5H CAN0 message data byte 5 register 14 C0MDATA514 CAN0 message data byte 67 register 14 C0MDATA6714 03FEC2C6H CAN0 message data byte 6 register 14 C0MDATA614 Undefined 03FEC2C7H CAN0 message data byte 7 register 14 C0MDATA714 Undefined 03FEC2C8H CAN0 message data length register 14 C0MDLC14 0000xxxxB 03FEC2C9H CAN0 message configuration register 14 C0MCONF14 Undefined 03FEC2CAH CAN0 message identifier register 14 C0MIDL14 Undefined C0MIDH14 Undefined 00x00000 03FEC2C2H 03FEC2C4H 03FEC2C6H 03FEC2CCH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC2CEH CAN0 message control register 14 C0MCTRL14 03FEC2E0H CAN0 message data byte 01 register 15 C0MDATA0115 03FEC2E0H CAN0 message data byte 0 register 15 C0MDATA015 Undefined 03FEC2E1H CAN0 message data byte 1 register 15 C0MDATA115 Undefined CAN0 message data byte 23 register 15 C0MDATA2315 03FEC2E2H CAN0 message data byte 2 register 15 C0MDATA215 Undefined 03FEC2E3H CAN0 message data byte 3 register 15 C0MDATA315 Undefined CAN0 message data byte 45 register 15 C0MDATA4515 000xx000B 03FEC2E2H 03FEC2E4H Undefined Undefined Undefined 03FEC2E4H CAN0 message data byte 4 register 15 C0MDATA415 Undefined 03FEC2E5H CAN0 message data byte 5 register 15 C0MDATA515 Undefined CAN0 message data byte 67 register 15 C0MDATA6715 03FEC2E6H CAN0 message data byte 6 register 15 C0MDATA615 Undefined 03FEC2E7H CAN0 message data byte 7 register 15 C0MDATA715 Undefined 03FEC2E8H CAN0 message data length register 15 C0MDLC15 0000xxxxB 03FEC2E9H CAN0 message configuration register 15 C0MCONF15 Undefined 03FEC2EAH CAN0 message identifier register 15 C0MIDL15 C0MIDH15 Undefined CAN0 message control register 15 C0MCTRL15 00x00000 03FEC2E6H 03FEC2ECH 03FEC2EEH Undefined Undefined 000xx000B 776 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (10/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC300H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 16 C0MDATA0116 03FEC300H CAN0 message data byte 0 register 16 C0MDATA016 Undefined 03FEC301H CAN0 message data byte 1 register 16 C0MDATA116 Undefined CAN0 message data byte 23 register 16 C0MDATA2316 03FEC302H CAN0 message data byte 2 register 16 C0MDATA216 Undefined 03FEC303H CAN0 message data byte 3 register 16 C0MDATA316 Undefined CAN0 message data byte 45 register 16 C0MDATA4516 03FEC304H CAN0 message data byte 4 register 16 C0MDATA416 03FEC305H CAN0 message data byte 5 register 16 C0MDATA516 CAN0 message data byte 67 register 16 C0MDATA6716 03FEC306H CAN0 message data byte 6 register 16 C0MDATA616 Undefined 03FEC307H CAN0 message data byte 7 register 16 C0MDATA716 Undefined 03FEC308H CAN0 message data length register 16 C0MDLC16 0000xxxxB 03FEC309H CAN0 message configuration register 16 C0MCONF16 Undefined 03FEC30AH CAN0 message identifier register 16 C0MIDL16 Undefined C0MIDH16 Undefined 00x00000 03FEC302H 03FEC304H 03FEC306H 03FEC30CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC30EH CAN0 message control register 16 C0MCTRL16 03FEC320H CAN0 message data byte 01 register 17 C0MDATA0117 03FEC320H CAN0 message data byte 0 register 17 C0MDATA017 Undefined 03FEC321H CAN0 message data byte 1 register 17 C0MDATA117 Undefined CAN0 message data byte 23 register 17 C0MDATA2317 03FEC322H CAN0 message data byte 2 register 17 C0MDATA217 Undefined 03FEC323H CAN0 message data byte 3 register 17 C0MDATA317 Undefined CAN0 message data byte 45 register 17 C0MDATA4517 03FEC324H CAN0 message data byte 4 register 17 C0MDATA417 Undefined 03FEC325H CAN0 message data byte 5 register 17 C0MDATA517 Undefined CAN0 message data byte 67 register 17 C0MDATA6717 03FEC326H CAN0 message data byte 6 register 17 C0MDATA617 Undefined 03FEC327H CAN0 message data byte 7 register 17 C0MDATA717 Undefined 03FEC328H CAN0 message data length register 17 C0MDLC17 0000xxxxB 03FEC329H CAN0 message configuration register 17 C0MCONF17 Undefined 03FEC32AH CAN0 message identifier register 17 C0MIDL17 C0MIDH17 Undefined CAN0 message control register 17 C0MCTRL17 00x00000 000xx000B 03FEC322H 03FEC324H 03FEC326H 03FEC32CH 03FEC32EH Undefined Undefined Undefined Undefined Undefined 000xx000B User's Manual U16541EJ5V1UD 777 CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (11/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC340H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 18 C0MDATA0118 03FEC340H CAN0 message data byte 0 register 18 C0MDATA018 Undefined 03FEC341H CAN0 message data byte 1 register 18 C0MDATA118 Undefined CAN0 message data byte 23 register 18 C0MDATA2318 03FEC342H CAN0 message data byte 2 register 18 C0MDATA218 Undefined 03FEC343H CAN0 message data byte 3 register 18 C0MDATA318 Undefined CAN0 message data byte 45 register 18 C0MDATA4518 03FEC344H CAN0 message data byte 4 register 18 C0MDATA418 03FEC345H CAN0 message data byte 5 register 18 C0MDATA518 CAN0 message data byte 67 register 18 C0MDATA6718 03FEC346H CAN0 message data byte 6 register 18 C0MDATA618 Undefined 03FEC347H CAN0 message data byte 7 register 18 C0MDATA718 Undefined 03FEC348H CAN0 message data length register 18 C0MDLC18 0000xxxxB 03FEC349H CAN0 message configuration register 18 C0MCONF18 Undefined 03FEC34AH CAN0 message identifier register 18 C0MIDL18 Undefined C0MIDH18 Undefined 00x00000 03FEC342H 03FEC344H 03FEC346H 03FEC34CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC34EH CAN0 message control register 18 C0MCTRL18 03FEC360H CAN0 message data byte 01 register 19 C0MDATA0119 03FEC360H CAN0 message data byte 0 register 19 C0MDATA019 Undefined 03FEC361H CAN0 message data byte 1 register 19 C0MDATA119 Undefined CAN0 message data byte 23 register 19 C0MDATA2319 03FEC362H CAN0 message data byte 2 register 19 C0MDATA219 Undefined 03FEC363H CAN0 message data byte 3 register 19 C0MDATA319 Undefined CAN0 message data byte 45 register 19 C0MDATA4519 000xx000B 03FEC362H 03FEC364H Undefined Undefined Undefined 03FEC364H CAN0 message data byte 4 register 19 C0MDATA419 Undefined 03FEC365H CAN0 message data byte 5 register 19 C0MDATA519 Undefined CAN0 message data byte 67 register 19 C0MDATA6719 03FEC366H CAN0 message data byte 6 register 19 C0MDATA619 Undefined 03FEC367H CAN0 message data byte 7 register 19 C0MDATA719 Undefined 03FEC368H CAN0 message data length register 19 C0MDLC19 0000xxxxB 03FEC369H CAN0 message configuration register 19 C0MCONF19 Undefined 03FEC36AH CAN0 message identifier register 19 C0MIDL19 C0MIDH19 Undefined CAN0 message control register 19 C0MCTRL19 00x00000 03FEC366H 03FEC36CH 03FEC36EH Undefined Undefined 000xx000B 778 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (12/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC380H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 20 C0MDATA0120 03FEC380H CAN0 message data byte 0 register 20 C0MDATA020 Undefined 03FEC381H CAN0 message data byte 1 register 20 C0MDATA120 Undefined CAN0 message data byte 23 register 20 C0MDATA2320 03FEC382H CAN0 message data byte 2 register 20 C0MDATA220 Undefined 03FEC383H CAN0 message data byte 3 register 20 C0MDATA320 Undefined CAN0 message data byte 45 register 20 C0MDATA4520 03FEC384H CAN0 message data byte 4 register 20 C0MDATA420 03FEC385H CAN0 message data byte 5 register 20 C0MDATA520 CAN0 message data byte 67 register 20 C0MDATA6720 03FEC386H CAN0 message data byte 6 register 20 C0MDATA620 Undefined 03FEC387H CAN0 message data byte 7 register 20 C0MDATA720 Undefined 03FEC388H CAN0 message data length register 20 C0MDLC20 0000xxxxB 03FEC389H CAN0 message configuration register 20 C0MCONF20 Undefined 03FEC38AH CAN0 message identifier register 20 C0MIDL20 Undefined C0MIDH20 Undefined 00x00000 03FEC382H 03FEC384H 03FEC386H 03FEC38CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC38EH CAN0 message control register 20 C0MCTRL20 03FEC3A0H CAN0 message data byte 01 register 21 C0MDATA0121 03FEC3A0H CAN0 message data byte 0 register 21 C0MDATA021 Undefined 03FEC3A1H CAN0 message data byte 1 register 21 C0MDATA121 Undefined CAN0 message data byte 23 register 21 C0MDATA2321 03FEC3A2H CAN0 message data byte 2 register 21 C0MDATA221 Undefined 03FEC3A3H CAN0 message data byte 3 register 21 C0MDATA321 Undefined CAN0 message data byte 45 register 21 C0MDATA4521 03FEC3A4H CAN0 message data byte 4 register 21 C0MDATA421 Undefined 03FEC3A5H CAN0 message data byte 5 register 21 C0MDATA521 Undefined CAN0 message data byte 67 register 21 C0MDATA6721 03FEC3A6H CAN0 message data byte 6 register 21 C0MDATA621 Undefined 03FEC3A7H CAN0 message data byte 7 register 21 C0MDATA721 Undefined 03FEC3A8H CAN0 message data length register 21 C0MDLC21 0000xxxxB 03FEC3A9H CAN0 message configuration register 21 C0MCONF21 Undefined 03FEC3AAH CAN0 message identifier register 21 C0MIDL21 C0MIDH21 Undefined CAN0 message control register 21 C0MCTRL21 00x00000 000xx000B 03FEC3A2H 03FEC3A4H 03FEC3A6H 03FEC3ACH 03FEC3AEH Undefined Undefined Undefined Undefined Undefined 000xx000B User's Manual U16541EJ5V1UD 779 CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (13/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC3C0H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 22 C0MDATA0122 03FEC3C0H CAN0 message data byte 0 register 22 C0MDATA022 Undefined 03FEC3C1H CAN0 message data byte 1 register 22 C0MDATA122 Undefined CAN0 message data byte 23 register 22 C0MDATA2322 03FEC3C2H CAN0 message data byte 2 register 22 C0MDATA222 Undefined 03FEC3C3H CAN0 message data byte 3 register 22 C0MDATA322 Undefined CAN0 message data byte 45 register 22 C0MDATA4522 03FEC3C4H CAN0 message data byte 4 register 22 C0MDATA422 03FEC3C5H CAN0 message data byte 5 register 22 C0MDATA522 CAN0 message data byte 67 register 22 C0MDATA6722 03FEC3C6H CAN0 message data byte 6 register 22 C0MDATA622 Undefined 03FEC3C7H CAN0 message data byte 7 register 22 C0MDATA722 Undefined 03FEC3C8H CAN0 message data length register 22 C0MDLC22 0000xxxxB 03FEC3C9H CAN0 message configuration register 22 C0MCONF22 Undefined 03FEC3CAH CAN0 message identifier register 22 C0MIDL22 Undefined C0MIDH22 Undefined 00x00000 03FEC3C2H 03FEC3C4H 03FEC3C6H 03FEC3CCH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC3CEH CAN0 message control register 22 C0MCTRL22 03FEC3E0H CAN0 message data byte 01 register 23 C0MDATA0123 03FEC3E0H CAN0 message data byte 0 register 23 C0MDATA023 Undefined 03FEC3E1H CAN0 message data byte 1 register 23 C0MDATA123 Undefined CAN0 message data byte 23 register 23 C0MDATA2323 03FEC3E2H CAN0 message data byte 2 register 23 C0MDATA223 Undefined 03FEC3E3H CAN0 message data byte 3 register 23 C0MDATA323 Undefined CAN0 message data byte 45 register 23 C0MDATA4523 000xx000B 03FEC3E2H 03FEC3E4H Undefined Undefined Undefined 03FEC3E4H CAN0 message data byte 4 register 23 C0MDATA423 Undefined 03FEC3E5H CAN0 message data byte 5 register 23 C0MDATA523 Undefined CAN0 message data byte 67 register 23 C0MDATA6723 03FEC3E6H CAN0 message data byte 6 register 23 C0MDATA623 Undefined 03FEC3E7H CAN0 message data byte 7 register 23 C0MDATA723 Undefined 03FEC3E8H CAN0 message data length register 23 C0MDLC23 0000xxxxB 03FEC3E9H CAN0 message configuration register 23 C0MCONF23 Undefined 03FEC3EAH CAN0 message identifier register 23 C0MIDL23 C0MIDH23 Undefined CAN0 message control register 23 C0MCTRL23 00x00000 03FEC3E6H 03FEC3ECH 03FEC3EEH Undefined Undefined 000xx000B 780 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (14/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC400H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 24 C0MDATA0124 03FEC400H CAN0 message data byte 0 register 24 C0MDATA024 Undefined 03FEC401H CAN0 message data byte 1 register 24 C0MDATA124 Undefined CAN0 message data byte 23 register 24 C0MDATA2324 03FEC402H CAN0 message data byte 2 register 24 C0MDATA224 Undefined 03FEC403H CAN0 message data byte 3 register 24 C0MDATA324 Undefined CAN0 message data byte 45 register 24 C0MDATA4524 03FEC404H CAN0 message data byte 4 register 24 C0MDATA424 03FEC405H CAN0 message data byte 5 register 24 C0MDATA524 CAN0 message data byte 67 register 24 C0MDATA6724 03FEC406H CAN0 message data byte 6 register 24 C0MDATA624 Undefined 03FEC407H CAN0 message data byte 7 register 24 C0MDATA724 Undefined 03FEC408H CAN0 message data length register 24 C0MDLC24 0000xxxxB 03FEC409H CAN0 message configuration register 24 C0MCONF24 Undefined 03FEC40AH CAN0 message identifier register 24 C0MIDL24 Undefined C0MIDH24 Undefined 00x00000 03FEC402H 03FEC404H 03FEC406H 03FEC40CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC40EH CAN0 message control register 24 C0MCTRL24 03FEC420H CAN0 message data byte 01 register 25 C0MDATA0125 03FEC420H CAN0 message data byte 0 register 25 C0MDATA025 Undefined 03FEC421H CAN0 message data byte 1 register 25 C0MDATA125 Undefined CAN0 message data byte 23 register 25 C0MDATA2325 03FEC422H CAN0 message data byte 2 register 25 C0MDATA225 Undefined 03FEC423H CAN0 message data byte 3 register 25 C0MDATA325 Undefined CAN0 message data byte 45 register 25 C0MDATA4525 03FEC424H CAN0 message data byte 4 register 25 C0MDATA425 Undefined 03FEC425H CAN0 message data byte 5 register 25 C0MDATA525 Undefined CAN0 message data byte 67 register 25 C0MDATA6725 03FEC426H CAN0 message data byte 6 register 25 C0MDATA625 Undefined 03FEC427H CAN0 message data byte 7 register 25 C0MDATA725 Undefined 03FEC428H CAN0 message data length register 25 C0MDLC25 0000xxxxB 03FEC429H CAN0 message configuration register 25 C0MCONF25 Undefined 03FEC42AH CAN0 message identifier register 25 C0MIDL25 C0MIDH25 Undefined CAN0 message control register 25 C0MCTRL25 00x00000 000xx000B 03FEC422H 03FEC424H 03FEC426H 03FEC42CH 03FEC42EH Undefined Undefined Undefined Undefined Undefined 000xx000B User's Manual U16541EJ5V1UD 781 CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (15/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC440H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 26 C0MDATA0126 03FEC440H CAN0 message data byte 0 register 26 C0MDATA026 Undefined 03FEC441H CAN0 message data byte 1 register 26 C0MDATA126 Undefined CAN0 message data byte 23 register 26 C0MDATA2326 03FEC442H CAN0 message data byte 2 register 26 C0MDATA226 Undefined 03FEC443H CAN0 message data byte 3 register 26 C0MDATA326 Undefined CAN0 message data byte 45 register 26 C0MDATA4526 03FEC444H CAN0 message data byte 4 register 26 C0MDATA426 03FEC445H CAN0 message data byte 5 register 26 C0MDATA526 CAN0 message data byte 67 register 26 C0MDATA6726 03FEC446H CAN0 message data byte 6 register 26 C0MDATA626 Undefined 03FEC447H CAN0 message data byte 7 register 26 C0MDATA726 Undefined 03FEC448H CAN0 message data length register 26 C0MDLC26 0000xxxxB 03FEC449H CAN0 message configuration register 26 C0MCONF26 Undefined 03FEC44AH CAN0 message identifier register 26 C0MIDL26 Undefined C0MIDH26 Undefined 00x00000 03FEC442H 03FEC444H 03FEC446H 03FEC44CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC44EH CAN0 message control register 26 C0MCTRL26 03FEC460H CAN0 message data byte 01 register 27 C0MDATA0127 03FEC460H CAN0 message data byte 0 register 27 C0MDATA027 Undefined 03FEC461H CAN0 message data byte 1 register 27 C0MDATA127 Undefined CAN0 message data byte 23 register 27 C0MDATA2327 03FEC462H CAN0 message data byte 2 register 27 C0MDATA227 Undefined 03FEC463H CAN0 message data byte 3 register 27 C0MDATA327 Undefined CAN0 message data byte 45 register 27 C0MDATA4527 000xx000B 03FEC462H 03FEC464H Undefined Undefined Undefined 03FEC464H CAN0 message data byte 4 register 27 C0MDATA427 Undefined 03FEC465H CAN0 message data byte 5 register 27 C0MDATA527 Undefined CAN0 message data byte 67 register 27 C0MDATA6727 03FEC466H CAN0 message data byte 6 register 27 C0MDATA627 Undefined 03FEC467H CAN0 message data byte 7 register 27 C0MDATA727 Undefined 03FEC468H CAN0 message data length register 27 C0MDLC27 0000xxxxB 03FEC469H CAN0 message configuration register 27 C0MCONF27 Undefined 03FEC46AH CAN0 message identifier register 27 C0MIDL27 C0MIDH27 Undefined CAN0 message control register 27 C0MCTRL27 00x00000 03FEC466H 03FEC46CH 03FEC46EH Undefined Undefined 000xx000B 782 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (16/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC480H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 28 C0MDATA0128 03FEC480H CAN0 message data byte 0 register 28 C0MDATA028 Undefined 03FEC481H CAN0 message data byte 1 register 28 C0MDATA128 Undefined CAN0 message data byte 23 register 28 C0MDATA2328 03FEC482H CAN0 message data byte 2 register 28 C0MDATA228 Undefined 03FEC483H CAN0 message data byte 3 register 28 C0MDATA328 Undefined CAN0 message data byte 45 register 28 C0MDATA4528 03FEC484H CAN0 message data byte 4 register 28 C0MDATA428 03FEC485H CAN0 message data byte 5 register 28 C0MDATA528 CAN0 message data byte 67 register 28 C0MDATA6728 03FEC486H CAN0 message data byte 6 register 28 C0MDATA628 Undefined 03FEC487H CAN0 message data byte 7 register 28 C0MDATA728 Undefined 03FEC488H CAN0 message data length register 28 C0MDLC28 0000xxxxB 03FEC489H CAN0 message configuration register 28 C0MCONF28 Undefined 03FEC48AH CAN0 message identifier register 28 C0MIDL28 Undefined C0MIDH28 Undefined 00x00000 03FEC482H 03FEC484H 03FEC486H 03FEC48CH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC48EH CAN0 message control register 28 C0MCTRL28 03FEC4A0H CAN0 message data byte 01 register 29 C0MDATA0129 03FEC4A0H CAN0 message data byte 0 register 29 C0MDATA029 Undefined 03FEC4A1H CAN0 message data byte 1 register 29 C0MDATA129 Undefined CAN0 message data byte 23 register 29 C0MDATA2329 03FEC4A2H CAN0 message data byte 2 register 29 C0MDATA229 Undefined 03FEC4A3H CAN0 message data byte 3 register 29 C0MDATA329 Undefined CAN0 message data byte 45 register 29 C0MDATA4529 03FEC4A4H CAN0 message data byte 4 register 29 C0MDATA429 Undefined 03FEC4A5H CAN0 message data byte 5 register 29 C0MDATA529 Undefined CAN0 message data byte 67 register 29 C0MDATA6729 03FEC4A6H CAN0 message data byte 6 register 29 C0MDATA629 Undefined 03FEC4A7H CAN0 message data byte 7 register 29 C0MDATA729 Undefined 03FEC4A8H CAN0 message data length register 29 C0MDLC29 0000xxxxB 03FEC4A9H CAN0 message configuration register 29 C0MCONF29 Undefined 03FEC4AAH CAN0 message identifier register 29 C0MIDL29 C0MIDH29 Undefined CAN0 message control register 29 C0MCTRL29 00x00000 000xx000B 03FEC4A2H 03FEC4A4H 03FEC4A6H 03FEC4ACH 03FEC4AEH Undefined Undefined Undefined Undefined Undefined 000xx000B User's Manual U16541EJ5V1UD 783 CHAPTER 19 CAN CONTROLLER Table 19-16. Register Access Types (17/17) Address Register Name Symbol R/W Bit Manipulation Units 1 Bit 03FEC4C0H After Reset 8 Bits 16 Bits R/W CAN0 message data byte 01 register 30 C0MDATA0130 03FEC4C0H CAN0 message data byte 0 register 30 C0MDATA030 Undefined 03FEC4C1H CAN0 message data byte 1 register 30 C0MDATA130 Undefined CAN0 message data byte 23 register 30 C0MDATA2330 03FEC4C2H CAN0 message data byte 2 register 30 C0MDATA230 Undefined 03FEC4C3H CAN0 message data byte 3 register 30 C0MDATA330 Undefined CAN0 message data byte 45 register 30 C0MDATA4530 03FEC4C4H CAN0 message data byte 4 register 30 C0MDATA430 03FEC4C5H CAN0 message data byte 5 register 30 C0MDATA530 CAN0 message data byte 67 register 30 C0MDATA6730 03FEC4C6H CAN0 message data byte 6 register 30 C0MDATA630 Undefined 03FEC4C7H CAN0 message data byte 7 register 30 C0MDATA730 Undefined 03FEC4C8H CAN0 message data length register 30 C0MDLC30 0000xxxxB 03FEC4C9H CAN0 message configuration register 30 C0MCONF30 Undefined 03FEC4CAH CAN0 message identifier register 30 C0MIDL30 Undefined C0MIDH30 Undefined 00x00000 03FEC4C2H 03FEC4C4H 03FEC4C6H 03FEC4CCH Undefined Undefined Undefined Undefined Undefined Undefined 03FEC4CEH CAN0 message control register 30 C0MCTRL30 03FEC4E0H CAN0 message data byte 01 register 31 C0MDATA0131 03FEC4E0H CAN0 message data byte 0 register 31 C0MDATA031 Undefined 03FEC4E1H CAN0 message data byte 1 register 31 C0MDATA131 Undefined CAN0 message data byte 23 register 31 C0MDATA2331 03FEC4E2H CAN0 message data byte 2 register 31 C0MDATA231 Undefined 03FEC4E3H CAN0 message data byte 3 register 31 C0MDATA331 Undefined CAN0 message data byte 45 register 31 C0MDATA4531 000xx000B 03FEC4E2H 03FEC4E4H Undefined Undefined Undefined 03FEC4E4H CAN0 message data byte 4 register 31 C0MDATA431 Undefined 03FEC4E5H CAN0 message data byte 5 register 31 C0MDATA531 Undefined CAN0 message data byte 67 register 31 C0MDATA6731 03FEC4E6H CAN0 message data byte 6 register 31 C0MDATA631 Undefined 03FEC4E7H CAN0 message data byte 7 register 31 C0MDATA731 Undefined 03FEC4E8H CAN0 message data length register 31 C0MDLC31 0000xxxxB 03FEC4E9H CAN0 message configuration register 31 C0MCONF31 Undefined 03FEC4EAH CAN0 message identifier register 31 C0MIDL31 C0MIDH31 Undefined CAN0 message control register 31 C0MCTRL31 00x00000 03FEC4E6H 03FEC4ECH 03FEC4EEH Undefined Undefined 000xx000B 784 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.5.3 Register bit configuration Table 19-17. CAN Global Register Bit Configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 03FEC000H C0GMCTRL (W) 0 0 0 0 0 0 0 Clear GOM 0 0 0 0 0 0 Set EFSD Set GOM 0 0 0 0 0 0 EFSD GOM MBON 0 0 0 0 0 0 0 03FEC001H 03FEC000H C0GMCTRL (R) 03FEC001H 03FEC002H C0GMCS 0 0 0 0 CCP3 CCP2 CCP1 CCP0 03FEC006H C0GMABT (W) 0 0 0 0 0 0 0 Clear ABTTRG 0 0 0 0 0 0 Set ABTCLR Set ABTTRG C0GMABT (R) 0 0 0 0 0 0 ABTCLR ABTTRG 0 0 0 0 0 0 0 0 C0GMABTD 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 03FEC007H 03FEC006H 03FEC007H 03FEC008H User's Manual U16541EJ5V1UD 785 CHAPTER 19 CAN CONTROLLER Table 19-18. CAN Module Register Bit Configuration (1/2) Address 03FEC040H Symbol Bit 7/15 Bit 6/14 Bit 5/13 CMID7 to CMID0 C0MASK1H CMID23 to CMID16 0 0 0 0 0 0 CMID7 to CMID0 C0MASK3H CMID23 to CMID16 CMID15 to CMID8 0 0 0 CMID15 to CMID8 C0CTRL (W) 03FEC051H 03FEC050H CMID23 to CMID16 C0MASK4H 03FEC04FH 03FEC050H CMID28 to CMID24 CMID7 to CMID0 C0MASK4L 03FEC04DH 03FEC04EH CMID28 to CMID24 C0MASK3L 03FEC04BH 03FEC04CH CMID28 to CMID24 CMID23 to CMID16 C0MASK2H 03FEC049H 03FEC04AH Bit 0/8 CMID15 to CMID8 03FEC047H 03FEC048H Bit 1/9 CMID7 to CMID0 C0MASK2L 03FEC045H 03FEC046H Bit 2/10 CMID15 to CMID8 03FEC043H 03FEC044H Bit 3/11 C0MASK1L 03FEC041H 03FEC042H Bit 4/12 C0CTRL (R) 03FEC051H 0 0 0 CMID28 to CMID24 0 Clear AL Clear VALID Clear Clear Clear Clear Clear PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0 Set CCERC Set AL 0 Set Set Set Set Set PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0 CCERC AL VALID PS MODE1 PS MODE0 OP MODE2 OP MODE1 OP MODE0 0 0 0 0 0 0 RSTAT TSTAT 0 0 0 0 0 0 0 0 03FEC052H C0LEC (W) 03FEC052H C0LEC (R) 0 0 0 0 0 LEC2 LEC1 LEC0 03FEC053H C0INFO 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 03FEC054H C0ERC TEC7 to TEC0 03FEC055H 03FEC056H REC7 to REC0 C0IE (W) 03FEC057H 03FEC056H C0IE (R) 03FEC057H 03FEC058H C0INTS (W) 03FEC059H 03FEC058H 03FEC059H 786 C0INTS (R) 0 0 Clear CIE5 Clear CIE4 Clear CIE3 Clear CIE2 Clear CIE1 Clear CIE0 0 0 Set CIE5 Set CIE4 Set CIE3 Set CIE2 Set CIE1 Set CIE0 0 0 CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 0 0 0 0 0 0 0 0 0 0 Clear CINTS5 Clear CINTS4 Clear CINTS3 Clear CINTS2 Clear CINTS1 Clear CINTS0 0 0 0 0 0 0 0 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 0 0 0 0 0 0 0 0 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-18. CAN Module Register Bit Configuration (2/2) Address Symbol 03FEC05AH C0BRP 03FEC05CH C0BTR 03FEC05DH 03FEC05EH C0LIPT 03FEC060H C0RGPT (W) 03FEC061H 03FEC060H C0RGPT (R) Bit 7/15 Bit 6/14 Bit 5/13 C0LOPT 03FEC064H C0TGPT (W) 03FEC065H 0 0 0 0 0 SJW1, SJW0 C0TGPT (R) Bit 0/8 0 TSEG13 to TSEG10 0 TSEG22 to TSEG20 0 0 0 0 0 0 0 Clear ROVF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHPM ROVF LOPT7 to LOPT0 0 0 0 0 0 0 0 Clear TOVF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THPM TOVF TGPT7 to TGPT0 C0TS (W) 03FEC067H C0TS (R) 03FEC067H 03FEC068H to 03FEC0FFH Bit 1/9 LIPT7 to LIPT0 03FEC065H 03FEC066H Bit 2/10 RGPT7 to RGPT0 03FEC062H 03FEC066H Bit 3/11 TQPRS7 to TQPRS0 03FEC061H 03FEC064H Bit 4/12 - 0 0 0 0 0 Clear TSLOCK Clear TSSEL Clear TSEN 0 0 0 0 0 Set TSLOCK Set TSSEL Set TSEN 0 0 0 0 0 TSLOCK TSSEL TSEN 0 0 0 0 0 0 0 0 Access prohibited (reserved for future use) User's Manual U16541EJ5V1UD 787 CHAPTER 19 CAN CONTROLLER Table 19-19. Message Buffer Register Bit Configuration Address Symbol 03FECxx0H Bit 7/15 Bit 6/14 Bit 5/13 C0MDATA01m Message data (byte 0) 03FECxx0H C0MDATA0m Message data (byte 0) 03FECxx1H C0MDATA1m Message data (byte 1) 03FECxx2H C0MDATA23m 03FECxx1H 03FECxx3H C0MDATA3m Message data (byte 3) 03FECxx4H C0MDATA45m Message data (byte 4) 03FECxx4H C0MDATA4m Message data (byte 4) 03FECxx5H C0MDATA5m Message data (byte 5) 03FECxx6H C0MDATA67m 03FECxx5H C0MDATA6m Message data (byte 6) 03FECxx7H C0MDATA7m Message data (byte 7) 03FECxx8H C0MDLCm 03FECxx9H C0MCONFm 03FECxxAH C0MIDLm 03FECxxBH C0MIDHm 03FECxxDH C0MCTRLm (W) 03FECxxFH C0MCTRLm (R) 03FECxxFH Remark MDLC3 MDLC2 MDLC1 MDLC0 Message data (byte 6) Message data (byte 7) 03FECxx6H 03FECxx0 to 03FECxxFH Bit 0/8 Message data (byte 5) 03FECxx7H 03FECxxEH Bit 1/9 Message data (byte 2) Message data (byte 2) 03FECxxEH Bit 2/10 Message data (byte 3) C0MDATA2m 03FECxxCH Bit 3/11 Message data (byte 1) 03FECxx3H 03FECxx2H Bit 4/12 0 OWS RTR MT2 MT1 MT0 0 0 MA0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 IDE 0 0 ID28 ID27 ID26 ID25 ID24 0 0 0 Clear MOW Clear IE Clear DN 0 0 0 0 Set IE 0 Set TRQ Set RDY 0 0 0 MOW IE DN TRQ RDY 0 0 MUC 0 0 0 0 0 - Clear TRQ Clear RDY Access prohibited (reserved for future use) m = 00 to 31 xx = 10, 12, 14, 16, 18, 1A, 1C, 1E, 20, 22, 24, 26, 28, 2A, 2C, 2E, 30, 32, 34, 36, 38, 3A, 3C, 3E, 40, 42, 44, 46, 48, 4A, 4C, 4E 788 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.6 Registers Caution Accessing the CAN controller registers is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock Remark m = 00 to 31 (1) CAN0 global control register (C0GMCTRL) The C0GMCTRL register is used to control the operation of the CAN module. (1/2) After reset: 0000H R/W Address: 03FEC000H (a) Read C0GMCTRL 15 14 13 12 11 10 9 8 MBON 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 EFSD GOM 15 14 13 12 11 10 9 8 0 0 0 0 0 0 (b) Write C0GMCTRL Set Set EFSD GOM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Clear GOM (a) Read MBON Bit enabling access to message buffer register, transmit/receive history registers 0 Write access and read access to the message buffer register and the transmit/receive history list registers is disabled. 1 Write access and read access to the message buffer register and the transmit/receive history list registers is enabled. Cautions 1. While the MBON bit is cleared (to 0), software access to the message buffers (C0MDATA0m, C0MDATA1m, C0MDATA01m, C0MDATA2m, C0MDATA3m, C0MDATA23m, C0MDATA4m, C0MDATA5m, C0MDATA45m, C0MDATA6m, C0MDATA7m, C0MDATA67m, C0MDLCm, C0MCONFm, C0MIDLm, C0MIDHm, and C0MCTRLm), or registers related to transmit history or receive history (C0LOPT, C0TGPT, C0LIPT, and C0RGPT) is disabled. 2. This bit is read-only. Even if 1 is written to the MBON bit while it is 0, the value of the MBON bit does not change, and access to the message buffer registers, or registers related to transmit history or receive history remains disabled. Remark When the CAN sleep mode/CAN stop mode is entered, or when the GOM bit is cleared to 0, the MBON bit is cleared to 0. When the CAN sleep mode/CAN stop mode is released, or when the GOM bit is set to 1, the MBON bit is set to 1. User's Manual U16541EJ5V1UD 789 CHAPTER 19 CAN CONTROLLER (2/2) EFSD Bit enabling forced shut down 0 Forced shut down by GOM bit = 0 disabled. 1 Forced shut down by GOM bit = 0 enabled. Caution To request forced shut down, clear the GOM bit to 0 immediately after the EFSD bit has been set to 1. If access to another register (including reading the C0GMCTRL register) is executed without clearing the GOM bit immediately after the EFSD bit has been set to 1, the EFSD bit is forcibly cleared to 0, and the forced shut down request is invalid. GOM Global operation mode bit 0 CAN module is disabled from operating. 1 CAN module is enabled to operate. Caution The GOM bit is cleared to 0 only in the initialization mode or immediately after the EFSD bit is set to 1. (b) Write Set EFSD EFSD bit setting 0 No change in EFSD bit. 1 EFSD bit set to 1. Set GOM Clear GOM 0 1 GOM bit cleared to 0. 1 0 GOM bit set to 1. Other than above GOM bit setting No change in GOM bit. Caution Be sure to set the GOM bit and EFSD bit separately. <R> 790 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (2) CAN0 global clock selection register (C0GMCS) The C0GMCS register is used to select the CAN module system clock. After reset: 0FH R/W C0GMCS Address: 03FEC002H 7 6 5 4 3 2 1 0 0 0 0 0 CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 0 0 0 0 fCAN/1 0 0 0 1 fCAN/2 0 0 1 0 fCAN/3 0 0 1 1 fCAN/4 0 1 0 0 fCAN/5 0 1 0 1 fCAN/6 0 1 1 0 fCAN/7 0 1 1 1 fCAN/8 1 0 0 0 fCAN/9 1 0 0 1 fCAN/10 1 0 1 0 fCAN/11 1 0 1 1 fCAN/12 1 1 0 0 fCAN/13 1 1 0 1 fCAN/14 1 1 1 0 fCAN/15 1 1 1 1 fCAN/16 (default value) Remark CAN module system clock (fCANMOD) fCAN = Clock supplied to CAN = fXX User's Manual U16541EJ5V1UD 791 CHAPTER 19 CAN CONTROLLER (3) CAN0 global automatic block transmission control register (C0GMABT) The C0GMABT register is used to control the automatic block transmission (ABT) operation. (1/2) After reset: 0000H R/W Address: 03FEC006H (a) Read C0GMABT 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ABTCLR ABTTRG 15 14 13 12 11 10 9 8 0 0 0 0 0 0 (a) Write C0GMABT Set Set ABTCLR ABTTRG 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Clear ABTTRG Caution Before changing the normal operation mode with ABT to the initialization mode, be sure to set the C0GMABT register to the default value (0000H). After setting, confirm that the C0GMABT register is initialized to 0000H. (a) Read ABTCLR Automatic block transmission engine clear status bit 0 Clearing the automatic transmission engine is completed. 1 The automatic transmission engine is being cleared. Remarks 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. The operation is not guaranteed if the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1. 2. When the automatic block transmission engine is cleared by setting the ABTCLR bit to 1, the ABTCLR bit is automatically cleared to 0 as soon as the requested clearing processing is complete. ABTTRG Automatic block transmission status bit 0 Automatic block transmission is stopped. 1 Automatic block transmission is under execution. Cautions 1. Do not set the ABTTRG bit to 1 in the initialization mode. If the ABTTRG bit is set to 1 in the initialization mode, the operation is not guaranteed after the CAN module has entered the normal operation mode with ABT. 2. Do not set the ABTTRG bit to 1 while the C0CTRL.TSTAT bit is set to 1. Directly confirm that the TSTAT bit = 0 before setting the ABTTRG bit to 1. 792 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set ABTCLR Automatic block transmission engine clear request bit 0 The automatic block transmission engine is in idle status or under operation. 1 Request to clear the automatic block transmission engine. After the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1. Set ABTTRG Clear ABTTRG 0 1 Request to stop automatic block transmission. 1 0 Request to start automatic block transmission. Other than above <R> Automatic block transmission start bit No change in ABTTRG bit. Caution Even if the ABTTRG bit is set (1), transmission is not immediately executed, depending on the situation such as when a message is received from another node or when a message other than the ABT message (message buffers 8 to 31) is transmitted. Even if the ABTTRG bit is cleared (0), transmission is not terminated midway. If transmission is under execution, it is continued until completed (regardless of whether transmission is successful or fails). User's Manual U16541EJ5V1UD 793 CHAPTER 19 CAN CONTROLLER (4) CAN0 global automatic block transmission delay register (C0GMABTD) The C0GMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT. After reset: 00H C0GMABTD R/W Address: 03FEC008H 7 6 5 4 3 2 1 0 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 Data frame interval during automatic block transmission ABTD3 ABTD2 ABTD1 ABTD0 0 0 0 0 0 DBT (default value) 0 0 0 1 2 DBT 0 0 1 0 2 DBT 0 0 1 1 2 DBT 0 1 0 0 2 DBT 0 1 0 1 2 DBT 0 1 1 0 2 DBT 0 1 1 1 2 DBT 1 0 0 0 2 DBT Other than above (Unit: Data bit time (DBT)) 5 6 7 8 9 10 11 12 Setting prohibited Cautions 1. Do not change the contents of the C0GMABTD register while the ABTTRG bit is set to 1. 2. The timing at which the ABT message is actually transmitted onto the CAN bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an ABT message (message buffers 8 to 31) is made. 794 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (5) CAN0 module mask control register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) The C0MASKaL and C0MASKaH registers are used to extend the number of receivable messages in the same message buffer by masking part of the identifier (ID) of a message and invalidating the ID comparison of the masked part. (1/2) * CAN0 module mask 1 register (C0MASK1L, C0MASK1H) After reset: Undefined C0MASK1L C0MASK1H R/W Address: C0MASK1L 03FEC040H, C0MASK1H 03FEC042H 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 * CAN0 module mask 2 register (C0MASK2L, C0MASK2H) After reset: Undefined C0MASK2L C0MASK2H R/W Address: C0MASK2L 03FEC044H, C0MASK2H 03FEC046H 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 User's Manual U16541EJ5V1UD 795 CHAPTER 19 CAN CONTROLLER (2/2) * CAN0 module mask 3 register (C0MASK3L, C0MASK3H) After reset: Undefined C0MASK3L R/W Address: C0MASK3L 03FEC048H, C0MASK3H 03FEC04AH 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 C0MASK3H * CAN0 module mask 4 register (C0MASK4L, C0MASK4H) After reset: Undefined C0MASK4L Address: C0MASK4L 03FEC04CH, C0MASK4H 03FEC04EH 15 14 13 12 11 10 9 8 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 C0MASK4H CMID28 to CMID0 0 R/W Mask pattern setting of ID bit The ID bits of the message buffer set by the CMID28 to CMID0 bits are compared with the ID bits of the received message frame. 1 The ID bits of the message buffer set by the CMID28 to CMID0 bits are not compared with the ID bits of the received message frame (they are masked). Remark Masking is always defined by an ID length of 29 bits. If a mask is assigned to a message with a standard ID, the CMID17 to CMID0 bits are ignored. Therefore, only the CMID28 to CMID18 bits of the received ID are masked. The same mask can be used for both the standard and extended IDs. 796 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (6) CAN0 module control register (C0CTRL) The C0CTRL register is used to control the operation mode of the CAN module. (1/4) After reset: 0000H R/W Address: 03FEC050H (a) Read C0CTRL 15 14 13 12 11 10 9 8 0 0 0 0 0 0 RSTAT TSTAT 7 6 5 4 3 2 1 0 CCERC AL VALID PSMODE PSMODE OPMODE OPMODE OPMODE 1 0 2 1 0 12 11 10 9 8 (a) Write C0CTRL 15 14 13 Set Set 0 CCERC AL Set Set Set Set Set PSMODE PSMODE OPMODE OPMODE OPMODE 1 0 2 1 0 4 3 2 1 0 7 6 5 0 Clear Clear Clear Clear Clear Clear Clear AL VALID PSMODE PSMODE OPMODE OPMODE OPMODE 1 0 2 1 0 (a) Read RSTAT Reception status bit 0 Reception is stopped. 1 Reception is in progress. Remark The RSTAT bit is set to 1 under the following conditions (timing) * The SOF bit of a receive frame is detected * On occurrence of arbitration loss during a transmit frame The RSTAT bit is cleared to 0 under the following conditions (timing) * When a recessive level is detected at the second bit of the interframe space * On transition to the initialization mode at the first bit of the interframe space TSTAT <R> Transmission status bit 0 Transmission is stopped. 1 Transmission is in progress. Remark The TSTAT bit is set to 1 under the following conditions (timing) * The SOF bit of a transmit frame is detected The TSTAT bit is cleared to 0 under the following conditions (timing) * During transition to bus-off status * On occurrence of arbitration loss in transmit frame * On detection of recessive level at the second bit of the interframe space * On transition to the initialization mode at the first bit of the interframe space User's Manual U16541EJ5V1UD 797 CHAPTER 19 CAN CONTROLLER (2/4) CCERC Error counter clear bit 0 The C0ERC and C0INFO registers are not cleared in the initialization mode. 1 The C0ERC and C0INFO registers are cleared in the initialization mode. Remarks 1. The CCERC bit is used to clear the C0ERC and C0INFO registers for re-initialization or forced recovery from the bus-off status. This bit can be set to 1 only in the initialization mode. 2. When the C0ERC and C0INFO registers have been cleared, the CCERC bit is also cleared to 0 automatically. 3. The CCERC bit can be set to 1 at the same time as a request to change the initialization mode to an operation mode is made. 4. If the CCERC bit is set to 1 immediately after the INIT mode is entered in the self test mode, the receive data may be corrupted. AL Bit to set operation in case of arbitration loss 0 Re-transmission is not executed in case of an arbitration loss in the single-shot mode. 1 Re-transmission is executed in case of an arbitration loss in the single-shot mode. Remark The AL bit is valid only in the single-shot mode. VALID Valid receive message frame detection bit 0 A valid message frame has not been received since the VALID bit was last cleared to 0. 1 A valid message frame has been received since the VALID bit was last cleared to 0. Remarks 1. Detection of a valid receive message frame is not dependent upon the existance or nonexistance of the storage in the receive message buffer (data frame) or transmit message buffer (remote frame). 2. Clear the VALID bit (0) before changing the initialization mode to an operation mode. 3. If only two CAN nodes are connected to the CAN bus with one transmitting a message frame <R> in the normal mode and the other in the receive-only mode, since no ACK is generated in the receive-only mode, the VALID bit is not set to 1 before the transmitting node enters the error passive status. 4. To clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the VALID bit is cleared. If it is not cleared, perform clearing processing again. 798 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (3/4) PSMODE1 PSMODE0 Power save mode 0 0 No power save mode is selected. 0 1 CAN sleep mode 1 0 Setting prohibited 1 1 CAN stop mode Cautions 1. Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored. <R> 2. After releasing the power save mode, the C0GMCTRL.MBON flag must be checked before accessing the message buffer again. <R> 3. A request for transition to the CAN sleep mode is held pending until it is canceled by software or until the CAN bus enters the bus idle state. The software can check transition to the CAN sleep mode by reading the PSMODE0 and PSMODE1 bits. OPMODE2 OPMODE1 OPMODE0 Operation mode 0 0 0 No operation mode is selected (CAN module is in the initialization mode). 0 0 1 Normal operation mode 0 1 0 Normal operation mode with automatic block transmission function (normal operation mode with ABT) 0 1 1 Receive-only mode 1 0 0 Single-shot mode 1 0 1 Self-test mode Other than above <R> Setting prohibited Caution It may take time to change the mode to the initialization mode or power save mode. Therefore, be sure to check if the mode has been successfully changed, by reading the register value before executing the processing. Remark The OPMODE0 to OPMODE2 bits are read-only in the CAN sleep mode or CAN stop mode. (b) Write Set CCERC 1 Setting of CCERC bit CCERC bit is set to 1. Other than above CCERC bit is not changed. Set AL Clear AL 0 1 AL bit is cleared to 0. 1 0 AL bit is set to 1. Other than above Setting of AL bit AL bit is not changed. Clear VALID Setting of VALID bit 0 VALID bit is not changed. 1 VALID bit is cleared to 0. User's Manual U16541EJ5V1UD 799 CHAPTER 19 CAN CONTROLLER (4/4) Set PSMODE0 Clear PSMODE0 0 1 1 0 Other than above PSMODE0 bit is cleared to 0. PSMODE bit is set to 1. PSMODE0 bit is not changed. Set PSMODE1 Clear PSMODE1 0 1 PSMODE1 bit is cleared to 0. 1 0 PSMODE1 bit is set to 1. Other than above Set OPMODE0 Clear OPMODE0 0 1 1 0 Other than above Setting of PSMODE1 bit PSMODE1 bit is not changed. Setting of OPMODE0 bit OPMODE0 bit is cleared to 0. OPMODE0 bit is set to 1. OPMODE0 bit is not changed. Set OPMODE1 Clear OPMODE1 0 1 OPMODE1 bit is cleared to 0. 1 0 OPMODE1 bit is set to 1. Other than above Set OPMODE2 Clear OPMODE2 0 1 1 0 Other than above 800 Setting of PSMODE0 bit Setting of OPMODE1 bit OPMODE1 bit is not changed. Setting of OPMODE2 bit OPMODE2 bit is cleared to 0. OPMODE2 bit is set to 1. OPMODE2 bit is not changed. User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (7) CAN0 module last error information register (C0LEC) The C0LEC register provides the error information of the CAN protocol. After reset: 00H C0LEC R/W Address: 03FEC052H 7 6 5 4 3 2 1 0 0 0 0 0 0 LEC2 LEC1 LEC0 Remarks 1. The contents of the C0LEC register are not cleared when the CAN module changes from an operation mode to the initialization mode. 2. If an attempt is made to write a value other than 00H to the C0LEC register by software, the access is ignored. LEC2 LEC1 LEC0 Last CAN protocol error information 0 0 0 No error 0 0 1 Stuff error 0 1 0 Form error 0 1 1 ACK error 1 0 0 Bit error. (The CAN module tried to transmit a recessive-level bit as part of a transmit message (except the arbitration field), but the value on the CAN bus is a dominant-level bit.) Bit error. (The CAN module tried to transmit a dominant-level bit as part of a 1 0 1 transmit message, ACK bit, error frame, or overload frame, but the value on the CAN bus is a recessive-level bit.) 1 1 0 CRC error 1 1 1 Undefined User's Manual U16541EJ5V1UD 801 CHAPTER 19 CAN CONTROLLER (8) CAN0 module information register (C0INFO) The C0INFO register indicates the status of the CAN module. After reset: 00H C0INFO R Address: 03FEC053H 7 6 5 4 3 2 1 0 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 BOFF Bus-off status bit 0 Not bus-off status (transmit error counter 255). (The value of the transmit counter is less than 256.) 1 Bus-off status (transmit error counter > 255). (The value of the transmit error counter is 256 or more.) TECS1 TECS0 Transmission error counter status bit 0 0 The value of the transmission error counter is less than that of the warning level (< 96). 0 1 The value of the transmission error counter is in the range of the warning level (96 to 127). 1 0 Undefined 1 1 The value of the transmission error counter is in the range of the error passive or bus-off status ( 128). 802 RECS1 RECS0 Reception error counter status bit 0 0 The value of the reception error counter is less than that of the warning level (< 96). 0 1 The value of the reception error counter is in the range of the warning level (96 to 127). 1 0 Undefined 1 1 The value of the reception error counter is in the error passive range ( 128). User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (9) CAN0 module error counter register (C0ERC) The C0ERC register indicates the count value of the transmission/reception error counter. After reset: 0000H C0ERC R Address: 03FEC054H 15 14 13 12 11 10 9 8 REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REPS Reception error passive status bit 0 The value of the reception error counter is not error passive (< 128) 1 The value of the reception error counter is in the error passive range ( 128) REC6 to REC0 0 to 127 Reception error counter bit Number of reception errors. These bits reflect the status of the reception error counter. The number of errors is defined by the CAN protocol. Remark The REC6 to REC0 bits of the reception error counter are invalid in the reception error passive status (C0INFO.RECS1, C0INFO.RECS0 bit = 11B). TEC7 to TEC0 0 to 255 Transmission error counter bit Number of transmission errors. These bits reflect the status of the transmission error counter. The number of errors is defined by the CAN protocol. Remark The TEC7 to TEC0 bits of the transmission error counter are invalid in the bus-off status (C0INFO.BOFF bit = 1). User's Manual U16541EJ5V1UD 803 CHAPTER 19 CAN CONTROLLER (10) CAN0 module interrupt enable register (C0IE) The C0IE register is used to enable or disable the interrupts of the CAN module. (1/2) After reset: 0000H R/W Address: 03FEC056H (a) Read C0IE 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 15 14 13 12 11 10 9 8 0 0 (b) Write C0IE Set Set Set Set Set Set CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 7 6 5 4 3 2 1 0 0 0 Clear Clear Clear Clear Clear Clear CIE5 CIE4 CIE3 CIE2 CIE1 CIE0 (a) Read CIE5 to CIE0 804 CAN module interrupt enable bit 0 Output of the interrupt corresponding to interrupt status register CINTSx is disabled. 1 Output of the interrupt corresponding to interrupt status register CINTSx is enabled. User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set CIE5 Clear CIE5 0 1 CIE5 bit is cleared to 0. 1 0 CIE5 bit is set to 1. Other than above Setting of CIE5 bit CIE5 bit is not changed. Set CIE4 Clear CIE4 0 1 CIE4 bit is cleared to 0. 1 0 CIE4 bit is set to 1. Other than above Setting of CIE4 bit CIE4 bit is not changed. Set CIE3 Clear CIE3 0 1 CIE3 bit is cleared to 0. 1 0 CIE3 bit is set to 1. Other than above Setting of CIE3 bit CIE3 bit is not changed. Set CIE2 Clear CIE2 0 1 CIE2 bit is cleared to 0. 1 0 CIE2 bit is set to 1. Other than above Setting of CIE2 bit CIE2 bit is not changed. Set CIE1 Clear CIE1 0 1 CIE1 bit is cleared to 0. 1 0 CIE1 bit is set to 1. Other than above Setting of CIE1 bit CIE1 bit is not changed. Set CIE0 Clear CIE0 0 1 CIE0 bit is cleared to 0. 1 0 CIE0 bit is set to 1. Other than above Setting of CIE0 bit CIE0 bit is not changed. User's Manual U16541EJ5V1UD 805 CHAPTER 19 CAN CONTROLLER (11) CAN0 module interrupt status register (C0INTS) The C0INTS register indicates the interrupt status of the CAN module. After reset: 0000H R/W Address: 03FEC058H (a) Read C0INTS 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 (b) Write C0INTS Clear Clear Clear Clear Clear Clear CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 (a) Read CINTS5 to CINTS0 CAN interrupt status bit 0 No related interrupt source event is generated. 1 A related interrupt source event is generated. Interrupt status bit Note Related interrupt source event Note CINTS5 Wakeup interrupt from CAN sleep mode CINTS4 Arbitration loss interrupt CINTS3 CAN protocol error interrupt CINTS2 CAN error status interrupt CINTS1 Interrupt on completion of reception of valid message frame to message buffer m CINTS0 Interrupt on normal completion of transmission of message frame from message buffer m The CINTS5 bit is set (1) only when the CAN module is woken up from the CAN sleep mode by a CAN bus operation. The CINTS5 bit is not set (1) when the CAN sleep mode has been released by software. (b) Write Clear Setting of CINTS5 to CINTS0 bits CINTS5 to CINTS0 <R> 0 CINTS5 to CINTS0 bits are not changed. 1 CINTS5 to CINTS0 bits are cleared to 0. Caution The status bit of this register is not automatically cleared. Clear it (0) by software if each status must be checked in the interrupt servicing. 806 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (12) CAN0 module bit rate prescaler register (C0BRP) The C0BRP register is used to select the CAN protocol layer base clock (fTQ). The communication baud rate is set to the C0BTR register. After reset: FFH C0BRP R/W Address: 03FEC05AH 7 6 5 4 3 2 1 0 TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 TQPRS7 to TQPRS0 CAN protocol layer base system clock (fTQ) 0 fCANMOD/1 1 fCANMOD/2 n fCANMOD/(n+1) : 255 : fCANMOD/256 (default value) Figure 19-23. CAN Module Clock CAN0 global clock selection register (C0GMCS) 0 fCAN 0 0 0 CCP3 CCP2 CCP1 CCP0 fCANMOD Prescaler Baud rate generator fTQ CAN0 bit-rate register (C0BTR) TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 CAN0 module bit-rate prescaler register (C0BRP) Remark fCAN: Clock supplied to CAN = fXX fCANMOD: CAN module system clock fTQ: CAN protocol layer basic system clock Caution The C0BRP register can be write-accessed only in the initialization mode. User's Manual U16541EJ5V1UD 807 CHAPTER 19 CAN CONTROLLER (13) CAN0 module bit rate register (C0BTR) The C0BTR register is used to control the data bit time of the communication baud rate. Figure 19-24. Data Bit Time Data bit time (DBT) Sync segment Prop segment Phase segment 1 Time segment 1 (TSEG1) 808 Phase segment 2 Time segment 2 (TSEG2) Sample point (SPT) User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER After reset: 370FH C0BTR R/W Address: 03FEC05CH 15 14 13 12 11 10 9 8 0 0 SJW1 SJW0 0 TSEG22 TSEG21 TSEG20 7 6 5 4 3 2 1 0 0 0 0 0 TSEG13 TSEG12 TSEG11 TSEG10 SJW1 SJW0 0 0 1TQ 0 1 2TQ 1 0 3TQ 1 1 4TQ (default value) TSEG22 TSEG21 TSEG20 0 0 0 1TQ 0 0 1 2TQ 0 1 0 3TQ 0 1 1 4TQ 1 0 0 5TQ 1 0 1 6TQ 1 1 0 7TQ 1 1 1 8TQ (default value) TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 Setting prohibited 0 0 0 1 2TQ 0 0 1 0 3TQ 0 0 1 1 4TQ 0 1 0 0 5TQ 0 1 0 1 6TQ 0 1 1 0 7TQ 0 1 1 1 8TQ 1 0 0 0 9TQ 1 0 0 1 10TQ 1 0 1 0 11TQ 1 0 1 1 12TQ 1 1 0 0 13TQ 1 1 0 1 14TQ 1 1 1 0 15TQ 1 1 1 1 16TQ (default value) Note Length of synchronization jump width Length of time segment 2 Length of time segment 1 Note Note This setting must not be made when the C0BRP register = 00H. Remark TQ = 1/fTQ (fTQ: CAN protocol layer basic system clock) User's Manual U16541EJ5V1UD 809 CHAPTER 19 CAN CONTROLLER (14) CAN0 module last in-pointer register (C0LIPT) The C0LIPT register indicates the number of the message buffer in which a data frame or a remote frame was last stored. After reset: Undefined C0LIPT R Address: 03FEC05EH 7 6 5 4 3 2 1 0 LIPT7 LIPT6 LIPT5 LIPT4 LIPT3 LIPT2 LIPT1 LIPT0 LIPT7 to LIPT0 0 to 31 Last in-pointer register (C0LIPT) When the C0LIPT register is read, the contents of the element indexed by the last in-pointer (LIPT) of the receive history list are read. These contents indicate the number of the message buffer in which a data frame or a remote frame was last stored. Remark The read value of the C0LIPT register is undefined if a data frame or a remote frame has never been stored in the message buffer. If the C0RGPT.RHPM bit is set to 1 after the CAN module has changed from the initialization mode to an operation mode, therefore, the read value of the C0LIPT register is undefined. 810 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (15) CAN0 module receive history list register (C0RGPT) The C0RGPT register is used to read the receive history list. After reset: xx02H R/W Address: 03FEC060H (a) Read C0RGPT 15 14 13 12 11 10 9 8 RGPT7 RGPT6 RGPT5 RGPT4 RGPT3 RGPT2 RGPT1 RGPT0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RHPM ROVF 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 (b) Write C0RGPT Clear ROVF (a) Read RGPT7 to RGPT0 Receive history list read pointer 0 to 31 When the C0RGPT register is read, the contents of the element indexed by the receive history list get pointer (RGPT) of the receive history list are read. These contents indicate the number of the message buffer in which a data frame or a remote frame has been stored. RHPM <R> Note 1 Receive history list pointer match 0 The receive history list has at least one message buffer number that has not been read. 1 The receive history list has no message buffer numbers that have not been read. ROVF Note 2 Receive history list overflow bit All the message buffer numbers that have not been read are preserved. All the numbers of the 0 message buffers in which a new data frame or remote frame has been received and stored are recorded to the receive history list (the receive history list has a vacant element). At least 23 entries have been stored since the host processor serviced the RHL last time (i.e. read 1 C0RGPT). The first 22 entries are sequentially stored whereas the last entry might have been overwritten by newly received messages a number of times because all buffer numbers are stored at position LIPT-1 when the ROVF bit is set to 1. As a consequence receptions cannot be completely recovered in the order that they were received. Notes 1. The read value of the RGPT0 to RGPT7 bits is invalid when the RHPM bit = 1. 2. If all the receive history is read by the C0RGPT register while the ROVF bit is set (1), the RHPM <R> bit is not cleared (0) but kept set (1) even if newly received data is stored. (b) Write Clear ROVF Setting of ROVF bit 0 ROVF bit is not changed. 1 ROVF bit is cleared to 0. User's Manual U16541EJ5V1UD 811 CHAPTER 19 CAN CONTROLLER (16) CAN0 module last out-pointer register (C0LOPT) The C0LOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. After reset: Undefined C0LOPT LOPT7 to LOPT0 0 to 31 R Address: 03FEC062H 7 6 5 4 3 2 1 0 LOPT7 LOPT6 LOPT5 LOPT4 LOPT3 LOPT2 LOPT1 LOPT0 Last out-pointer of transmit history list (LOPT) When the C0LOPT register is read, the contents of the element indexed by the last out-pointer (LOPT) of the receive history list are read. These contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. Remark The value read from the C0LOPT register is undefined if a data frame or remote frame has never been transmitted from a message buffer. If the C0TGPT.THPM bit is set to 1 after the CAN module has changed from the initialization mode to an operation mode, therefore, the read value of the C0LOPT register is undefined. 812 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (17) CAN0 module transmit history list register (C0TGPT) The C0TGPT register is used to read the transmit history list. After reset: xx02H R/W Address: 03FEC064H (a) Read C0TGPT 15 14 13 12 11 10 9 8 TGPT7 TGPT6 TGPT5 TGPT4 TGPT3 TGPT2 TGPT1 TGPT0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 THPM TOVF 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 (b) Write C0TGPT Clear TOVF (a) Read TGPT7 to TGPT0 0 to 31 Transmit history list read pointer When the C0TGPT register is read, the contents of the element indexed by the read pointer (TGPT) of the transmit history list are read. These contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. Note 1 THPM <R> Transmit history pointer match 0 The transmit history list has at least one message buffer number that has not been read. 1 The transmit history list has no message buffer numbers that have not been read. Note 2 TOVF Transmit history list overflow bit All the message buffer numbers that have not been read are preserved. All the numbers of the 0 message buffers to which a new data frame or remote frame has been transmitted are recorded to the transmit history list (the transmit history list has a vacant element). At least 7 entries have been stored since the host processor serviced the THL last time (i.e. read 1 C0TGPT). The first 6 entries are sequentially stored whereas the last entry might have been overwritten by newly transmitted messages a number of times because all buffer numbers are stored at position LOPT-1 when TOVF bit is set to 1. As a consequence receptions cannot be completely recovered in the order that they were received. Notes 1. The read value of the TGPT0 to TGPT7 bits is invalid when the THPM bit = 1. <R> 2. If all the transmit history is read by the C0TGPT register while the TOVF bit is set (1), the THPM bit is not cleared (0) but kept set (1), even if transmission of new data has been completed. Remark Transmission from message buffers 0 to 7 is not recorded to the transmit history list in the normal operation mode with ABT. (b) Write Clear TOVF Setting of TOVF bit 0 TOVF bit is not changed. 1 TOVF bit is cleared to 0. User's Manual U16541EJ5V1UD 813 CHAPTER 19 CAN CONTROLLER (18) CAN0 module time stamp register (C0TS) The C0TS register is used to control the time stamp function. (1/2) After reset: 0000H R/W Address: 03FEC066H (a) Read 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 TSLOCK TSSEL TSEN 15 14 13 12 11 10 9 8 0 0 0 0 0 C0TS (b) Write C0TS Remark 7 6 5 4 3 0 0 0 0 0 Set Set Set TSLOCK TSSEL TSEN 2 1 0 Clear Clear Clear TSLOCK TSSEL TSEN The lock function of the time stamp functions must not be used when the CAN module is in the normal operation mode with ABT. (a) Read TSLOCK Time stamp lock function enable bit Time stamp lock function stopped. 0 The TSOUT signal toggles each time the selected time stamp capture event occurs. Time stamp lock function enabled. The TSOUT signal toggles each time the selected time stamp capture event occurred. However, the 1 TSOUT output signal is locked when a data frame has been correctly received to message buffer 0 Note Note . The TSEN bit is automatically cleared to 0. TSSEL Time stamp capture event selection bit 0 The time stamp capture event is SOF. 1 The time stamp capture event is the last bit of EOF. TSEN TSOUT operation setting bit 0 TSOUT toggle operation is disabled. 1 TSOUT toggle operation is enabled. Remark The TSOUT signal is output from the CAN controller to a timer. For details, refer to CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP). 814 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (2/2) (b) Write Set TSLOCK Clear TSLOCK 0 1 TSLOCK bit is cleared to 0. 1 0 TSLOCK bit is set to 1. Other than above Setting of TSLOCK bit TSLOCK bit is not changed. Set TSSEL Clear TSSEL 0 1 TSSEL bit is cleared to 0. 1 0 TSSEL bit is set to 1. Other than above Setting of TSSEL bit TSSEL bit is not changed. Set TSEN Clear TSEN 0 1 TSEN bit is cleared to 0. 1 0 TSEN bit is set to 1. Other than above Setting of TSEN bit TSEN bit is not changed. User's Manual U16541EJ5V1UD 815 CHAPTER 19 CAN CONTROLLER (19) CAN0 message data byte register (C0MDATAxm, C0MDATAym) (x = 0 to 7, y = 01, 23, 45, 67) The C0MDATAxm register is used to store the data of a transmit/receive message, and can be accessed in 8-bit unit. The C0MDATAxm register can be accessed in 16-bit units by the C0MDATAym register. (1/2) After reset: Undefined C0MDATA01m C0MDATA0m C0MDATA1m C0MDATA23m C0MDATA2m C0MDATA3m 816 R/W Address: See Table 19-16. 15 14 13 12 11 10 9 8 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 MDATA0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 MDATA1 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA2 MDATA2 MDATA2 MDATA2 MDATA2 MDATA2 MDATA2 MDATA2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA3 MDATA3 MDATA3 MDATA3 MDATA3 MDATA3 MDATA3 MDATA3 7 6 5 4 3 2 1 0 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (2/2) C0MDATA45m C0MDATA4m C0MDATA5m C0MDATA67m C0MDATA6m C0MDATA7m 15 14 13 12 11 10 9 8 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 MDATA4 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 MDATA5 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA6 MDATA6 MDATA6 MDATA6 MDATA6 MDATA6 MDATA6 MDATA6 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MDATA7 MDATA7 MDATA7 MDATA7 MDATA7 MDATA7 MDATA7 MDATA7 7 6 5 4 3 2 1 0 User's Manual U16541EJ5V1UD 817 CHAPTER 19 CAN CONTROLLER (20) CAN0 message data length register m (C0MDLCm) The C0MDLCm register is used to set the number of bytes of the data field of a message buffer. After reset: 0000xxxxB C0MDLCm R/W Address: See Table 19-16. 7 6 5 4 3 2 1 0 0 0 0 0 MDLC3 MDLC2 MDLC1 MDLC0 MDLC3 MDLC2 MDLC1 MDLC0 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes 1 0 0 1 Setting prohibited 1 0 1 0 (If these bits are set during transmission, 8-byte data is transmitted 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Note Data length of transmit/receive message regardless of the set DLC value when a data frame is transmitted. However, the DLC actually transmitted to the CAN bus is the DLC Note value set to this register.) The data and DLC value actually transmitted to CAN bus are as follows. Type of transmit frame Data frame Length of transmit data Number of bytes specified by DLC DLC transmitted MDLC3 to MDLC0 bits (However, 8 bytes if DLC 8) Remote frame 0 bytes Cautions 1. Be sure to set bits 7 to 4 to 0000B. 2. Receive data is stored in as many C0MDATAxm register as the number of bytes (however, the upper limit is 8) corresponding to DLC of receive frame. C0MDATAxm register in which no data is stored is undefined. 818 User's Manual U16541EJ5V1UD The CHAPTER 19 CAN CONTROLLER (21) CAN0 message configuration register m (C0MCONFm) The C0MCONFm register is used to specify the type of the message buffer and to set a mask. (1/2) After reset: Undefined C0MCONFm R/W Address: See Table 19-16. 7 6 5 4 3 2 1 0 OWS RTR MT2 MT1 MT0 0 0 MA0 OWS Overwrite control bit Note The message buffer 0 that has already received a data frame is not overwritten by a newly received data frame. The newly received data frame is discarded. The message buffer that has already received a data frame is overwritten by a newly received data 1 frame. Note The "message buffer that has already received a data frame" is a receive message buffer whose the C0MCTRLm.DN bit has been set to 1. Remark A remote frame is received and stored, regardless of the setting of the OWS and DN bits. A remote frame that satisfies the other conditions (ID matches, the RTR bit = 0, the C0MCTRLm.TRQ bit = 0) is always received and stored in the corresponding message buffer (interrupt generated, DN flag set, the C0MDLCm.MDLC0 to C0MDLCm.MDLC3 bits updated, and recorded to the receive history list). RTR Remote frame request bit 0 Transmit a data frame. 1 Transmit a remote frame. Note Note The RTR bit specifies the type of message frame that is transmitted from a message buffer defined as a transmit message buffer. Even if a valid remote frame has been received, the RTR bit of the transmit message buffer that has received the frame remains cleared to 0. Even if a remote frame whose ID matches has been received from the CAN bus with the RTR bit of the transmit message buffer set to 1 to transmit a remote frame, that remote frame is not received or stored (interrupt generated, DN flag set, the MDLC0 to MDLC3 bits updated, and recorded to the receive history list). MT2 MT1 MT0 0 0 0 Message buffer type setting bit Transmit message buffer 0 0 1 Receive message buffer (no mask setting) 0 1 0 Receive message buffer (mask 1 set) 0 1 1 Receive message buffer (mask 2 set) 1 0 0 Receive message buffer (mask 3 set) 1 0 1 Receive message buffer (mask 4 set) Other than above Setting prohibited User's Manual U16541EJ5V1UD 819 CHAPTER 19 CAN CONTROLLER (2/2) MA0 Message buffer assignment bit 0 Message buffer not used. 1 Message buffer used. Caution Be sure to write 0 to bits 2 and 1. (22) CAN0 message ID register m (C0MIDLm, C0MIDHm) The C0MIDLm and C0MIDHm registers are used to set an identifier (ID). After reset: Undefined C0MIDLm C0MIDHm R/W Address: See Table 19-16. 15 14 13 12 11 10 9 8 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 15 14 13 12 11 10 9 8 IDE 0 0 ID28 ID27 ID26 ID25 ID24 7 6 5 4 3 2 1 0 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 IDE Format mode specification bit 0 Standard format mode (ID28 to ID18: 11 bits) 1 Extended format mode (ID28 to ID0: 29 bits) Note The ID17 to ID0 bits are not used. ID28 to ID0 Message ID ID28 to ID18 Standard ID value of 11 bits (when IDE = 0) ID28 to ID0 Extended ID value of 29 bits (when IDE = 1) Cautions 1 <R> Note Be sure to write 0 to bits 14 and 13 of the C0MIDHm register. 2. Be sure to arrange the ID values to be registered in accordance with the bit positions of this register. For the standard ID, shift the bit positions of ID28 to ID18 of the ID value. 820 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (23) CAN0 message control register m (C0MCTRLm) The C0MCTRLm register is used to control the operation of the message buffer. (1/3) After reset: 00x000000 R/W Address: See Table 19-16. 000xx000B (a) Read C0MCTRLm 15 14 13 12 11 10 9 8 0 0 MUC 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 MOW IE DN TRQ RDY 15 14 13 12 11 10 9 8 0 0 0 0 Set 0 (b) Write C0MCTRLm IE 7 6 5 0 0 0 Set Set TRQ RDY 4 3 2 1 0 Clear Clear Clear Clear Clear MOW IE DN TRQ RDY (a) Read Note MUC Bit indicating that message buffer data is being updated 0 The CAN module is not updating the message buffer (reception and storage). 1 The CAN module is updating the message buffer (reception and storage). Note The MUC bit is undefined until the first reception and storage is performed. MOW Message buffer overwrite status bit 0 The message buffer is not overwritten by a newly received data frame. 1 The message buffer is overwritten by a newly received data frame. Remark The MOW bit is not set to 1 even if a remote frame is received and stored in the transmit message buffer with the DN bit = 1. IE 0 Message buffer interrupt request enable bit Receive message buffer: Valid message reception completion interrupt disabled. Transmit message buffer: Normal message transmission completion interrupt disabled. 1 Receive message buffer: Valid message reception completion interrupt enabled. Transmit message buffer: Normal message transmission completion interrupt enabled. DN Message buffer data update bit 0 A data frame or remote frame is not stored in the message buffer. 1 A data frame or remote frame is stored in the message buffer. User's Manual U16541EJ5V1UD 821 CHAPTER 19 CAN CONTROLLER (2/3) TRQ Message buffer transmission request bit 0 No message frame transmitting request that is pending or being transmitted is in the message buffer. 1 The message buffer is holding transmission of a message frame pending or is transmitting a message frame. Caution Do not set the TRQ bit and RDY bit to 1 at the same time. Be sure to set the RDY bit to 1 before setting the TRQ bit to 1. RDY Message buffer ready bit 0 The message buffer can be written by software. The CAN module cannot write to the message buffer. 1 Writing the message buffer by software is ignored (except a write access to the RDY, TRQ, DN, and MOW bits). The CAN module can write to the message buffer. Cautions 1. Do not clear (0) the RDY bit during message transmission. Follow transmission abort procedures in order to clear the RDY bit for redefinition. <R> 2. If the RDY bit is not cleared (0) even when the processing to clear it is executed, <R> 3. Confirm, by reading the RDY bit again, that the RDY bit has been cleared (0) before execute the clearing processing again. writing data to the message buffer. However, it is unnecessary to confirm that the TRQ or RDY bit has been set (1) or that the DN or MOW bit has been cleared (0). (b) Write Clear MOW Setting of MOW bit 0 MOW bit is not changed. 1 MOW bit is cleared to 0. Set IE Clear IE 0 1 IE bit is cleared to 0. 1 0 IE bit is set to 1. Other than above Setting of IE bit IE bit is not changed. Caution Be sure to set the IE and RDY bits separately. <R> Clear DN Setting of DN bit 1 DN bit is cleared to 0. 0 DN bit is not changed. Caution Do not set the DN bit to 1 by software. Be sure to write 0 to bit 10. 822 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (3/3) Set TRQ Clear TRQ 0 1 1 0 Other than above <R> Setting of TRQ bit TRQ bit is cleared to 0. TRQ bit is set to 1. TRQ bit is not changed. Caution Even if the TRQ bit is set (1), transmission may not be immediately executed depending on the situation such as when a message is received from another node or when a message is transmitted from the message buffer. Transmission under execution is not terminated midway even if the TRQ bit is cleared. Transmission is continued until it is completed (regardless of whether it is executed successfully or fails). Set RDY Clear RDY 0 1 1 0 Other than above <R> Setting of RDY bit RDY bit is cleared to 0. RDY bit is set to 1. RDY bit is not changed. Caution Be sure to set the TRQ and RDY bits separately. User's Manual U16541EJ5V1UD 823 CHAPTER 19 CAN CONTROLLER 19.7 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values. * CAN0 global control register (C0GMCTRL) * CAN0 global automatic block transmission control register (C0GMABT) * CAN0 module control register (C0CTRL) * CAN0 module interrupt enable register (C0IE) * CAN0 module interrupt status register (C0INTS) * CAN0 module receive history list register (C0RGPT) * CAN0 module transmit history list register (C0TGPT) * CAN0 module time stamp register (C0TS) * CAN0 message control register (C0MCTRLm) Remark m = 00 to 31 All the 16 bits in the above registers can be read via the usual method. Use the procedure described in Figure 1925 below to set or clear the lower 8 bits in these registers. Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (see the bit status after set/clear operation is specified in Figure 19-26). Figure 19-25 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. Figure 19-25. Example of Bit Setting/Clearing Operations 1 1 0 1 0 0 0 1 Write value 0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 set 0 0 0 0 1 0 1 1 clear 1 1 0 1 1 0 0 0 Register's value after write operation 824 0 0 0 0 0 0 0 Set 0 Set 0 No change 0 No change 0 Clear 0 No change 0 Clear 0 Clear 0 Bit status Register's current value 0 0 0 0 0 0 0 1 1 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-26. Bit Status After Bit Setting/Clearing Operations Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Clear 7 Clear 6 Clear 5 Clear 4 Clear 3 Clear 2 Clear 1 Clear 0 Remark Set n Clear n Status of bit n after bit set/clear operation 0 0 No change 0 1 0 1 0 1 1 1 No change n = 0 to 7 User's Manual U16541EJ5V1UD 825 CHAPTER 19 CAN CONTROLLER 19.8 CAN Controller Initialization 19.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the C0GMCS.CCP0 to C0GMCS.CCP3 bits by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled. The CAN module is enabled by setting the C0GMCTRL.GOM bit. For the procedure of initializing the CAN module, see 19.16 Operation of CAN Controller. 19.8.2 Initialization of message buffer After the CAN module is enabled, the message buffers contain undefined values. A minimum initialization for all the message buffers, even for those not used in the application, is necessary before switching the CAN module from the initialization mode to one of the operation modes. * Clear the C0MCTRLm.RDY, C0MCTRLm.TRQ, and C0MCTRLm.DN bits to 0. * Clear the C0MCONFm.MA0 bit to 0. Remark m = 00 to 31 19.8.3 Redefinition of message buffer Redefining a message buffer means changing the ID and control information of the message buffer while a message is being received or transmitted, without affecting other transmission/reception operations. (1) To redefine message buffer in initialization mode Place the CAN module in the initialization mode once and then change the ID and control information of the message buffer in the initialization mode. After changing the ID and control information, set the CAN module to an operation mode. (2) To redefine message buffer during reception Perform redefinition as shown in Figure 19-39. 826 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (3) To redefine message buffer during transmission To rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (see 19.10.4 (1) Transmission abort process other than in normal operation mode with automatic block transmission (ABT), 19.10.4 (2) Transmission abort process except for ABT transmission in normal operation mode with automatic block transmission (ABT). Confirm that transmission has been aborted or completed, and then redefine the message buffer. After redefining the transmit message buffer, set a transmission request using the procedure described below. When setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. Figure 19-27. Setting Transmission Request (TRQ) to Transmit Message Buffer After Redefinition Redefinition completed Execute transmission? No Yes Wait for a period of 1 CAN data bit. Set TRQ bit Set TRQ bit = 1 Clear TRQ bit = 0 END Cautions 1. When a message is received, reception filtering is performed in accordance with the ID and mask set to each receive message buffer. If the procedure in Figure 19-39 is not observed, the contents of the message buffer after it has been redefined may contradict the result of reception (result of reception filtering). If this happens, check that the ID and IDE received first and stored in the message buffer following redefinition are those stored after the message buffer has been redefined. If no ID and IDE are stored after redefinition, redefine the message buffer again. 2. When a message is transmitted, the transmission priority is checked in accordance with the ID, IDE, and RTR bits set to each transmit message buffer to which a transmission request was set. The transmit message buffer having the highest priority is selected for transmission. If the procedure in Figure 19-27 is not observed, a message with an ID not having the highest priority may be transmitted after redefinition. User's Manual U16541EJ5V1UD 827 CHAPTER 19 CAN CONTROLLER 19.8.4 Transition from initialization mode to operation mode The CAN module can be switched to the following operation modes. * Normal operation mode * Normal operation mode with ABT * Receive-only mode * Single-shot mode * Self-test mode Figure 19-28. Transition to Operation Modes OPMODE[2:0] = 00H and CAN bus is busy. [Receive-only mode] OPMODE[2:0]=03H OPMODE[2:0] = 00H and CAN bus is busy. OPMODE[2:0] = 00H and CAN bus is busy. [Normal operation mode with ABT] OPMODE[2:0]=02H OPMODE[2:0] = 03H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 04H OPMODE[2:0] = 02H OPMODE[2:0] = 00H and CAN bus is busy. [Normal operation mode] OPMODE[2:0]=01H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 01H [Single-shot mode] OPMODE[2:0]=04H OPMODE[2:0] = 00H and interframe space INIT mode OPMODE[2:0] = 00H OPMODE[2:0] = 05H OPMODE[2:0] = 00H and interframe space OPMODE[2:0] = 00H and CAN bus is busy. [Self-test mode] OPMODE[2:0]=05H GOM = 1 All CAN modules are in INIT mode and GOM = 0 EFSD = 1 and GOM = 0 CAN module channel invalid RESET released RESET The transition from the initialization mode to an operation mode is controlled by the C0CTRL.OPMODE2 to C0CTRL.OPMODE0 bits. Changing from one operation mode into another requires shifting to the initialization mode in between. Do not change one operation mode to another directly; otherwise the operation will not be guaranteed. Requests for transition from an operation mode to the initialization mode are held pending when the CAN bus is not in the interframe space (i.e., frame reception or transmission is in progress), and the CAN module enters the initialization mode at the first bit in the interframe space (the values of the OPMODE2 to OPMODE0 bits are changed to 000B). After issuing a request to change the mode to the initialization mode, read the OPMODE2 to OPMODE0 bits until their values become 000B to confirm that the module has entered the initialization mode (see Figure 19-37). 19.8.5 Resetting error counter C0ERC of CAN module If it is necessary to reset the C0ERC and C0INFO registers when re-initialization or forced recovery from the busoff status is made, set the C0CTRL.CCERC bit to 1 in the initialization mode. When this bit is set to 1, the C0ERC and C0INFO registers are cleared to their default values. 828 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.9 Message Reception 19.9.1 Message reception All buffers satisfying the following conditions are searched in all the message buffer areas in all the operation modes in order to store newly receive messages. * Used as a message buffer (C0MCONFm.MA0 bit is set to 1.) * Set as a receive message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits are set to 001B, 010B, 011B, 100B, or 101B.) * Ready for reception (C0MCTRLm.RDY bit is set to 1.) Remark m = 00 to 31 When two or more message buffers of the CAN module receive a message, the message is stored according to the priority explained below. The message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. For example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same ID, the received message is not stored in the message buffer linked to mask 1 that has not received a message, even if a message has already been received in the unmasked receive message buffer. In other words, when a condition has been set to store a message in two or more message buffers with different priorities, the message buffer with the highest priority always stores the message; the message is not stored in message buffers with a lower priority. This also applies when the message buffer with the highest priority is unable to receive and store a message (i.e., when the DN bit = 1 indicating that a message has already been received, but rewriting is disabled because the OWS bit = 0). In this case, the message is not actually received and stored in the candidate message buffer with the highest priority, but neither is it stored in a message buffer with a lower priority. Priority 1 (high) Storing Condition If Same ID Is Set Unmasked message buffer DN bit = 0 DN bit = 1 and OWS bit = 1 2 Message buffer linked to mask 1 DN bit = 0 DN bit = 1 and OWS bit = 1 3 Message buffer linked to mask 2 DN bit = 0 4 Message buffer linked to mask 3 DN bit = 0 DN bit = 1 and OWS bit = 1 DN bit = 1 and OWS bit = 1 5 (low) Message buffer linked to mask 4 DN bit = 0 DN bit = 1 and OWS bit = 1 User's Manual U16541EJ5V1UD 829 CHAPTER 19 CAN CONTROLLER <R> 19.9.2 Reading reception data If it is necessary to consistently read data from the CAN message buffer by software, follow the recommended procedures shown in Figures 19-49 and 19-50. While receiving a message, the CAN module sets the C0MCTRLm.DN bit two times, at the beginning of the processing to store data in the message buffer and at the end of this storing processing. During this storing processing, the C0MCTRLm.MUC bit of the message buffer is set (1) (refer to Figure 19-29). Before the data is completely stored, the receive history list is written. During this data storing period (MUC bit = 1), the CPU is prohibited from rewriting the C0MCTRLm.RDY bit of the message buffer in which the data is to be stored. Completion of this data storing processing may be delayed by a CPU's access to any message buffer. Remark m = 0 to 31 Figure 19-29. DN and MUC Bit Setting Period (in Standard ID Format) (11) R0 (1) IDE ID RTR SOF CAN standard ID format (1) (1) (1) Recessive DLC DATA0-DATA7 CRC (4) (0-64) (16) ACK EOF (2) IFS Dominant (7) Message stored DATA, DLC, ID Message buffer DN bit MUC bit C0INTS.CINTS1 bit INTC0REC signal The DN and MUC bits are set (1) at the same time. Operation of CAN controller 830 User's Manual U16541EJ5V1UD The DN bit is set (1) and the MUC bit is cleared (0) at the same time. CHAPTER 19 CAN CONTROLLER 19.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding C0LIPT register and the receive history list get pointer (RGPT) with the corresponding C0RGPT register. The RHL is undefined immediately after the transition of the CAN module from the initialization mode to one of the operation modes. The C0LIPT register holds the contents of the RHL element indicated by the value of the LIPT pointer minus 1. By reading the C0LIPT register, therefore, the number of the message buffer that received and stored a data frame or remote frame first can be checked. The LIPT pointer is utilized as a write pointer that indicates to what part of the RHL a message buffer number is recorded. Any time a data frame or remote frame is received and stored, the corresponding message buffer number is recorded to the RHL element indicated by the LIPT pointer. Each time recording to the RHL has been completed, the LIPT pointer is automatically incremented. In this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. The RGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the RHL. This pointer indicates the first RHL element that the CPU has not read yet. By reading the C0RGPT register by software, the number of a message buffer that has received and stored a data frame or remote frame can be read. Each time a message buffer number is read from the C0RGPT register, the RGPT pointer is automatically incremented. If the value of the RGPT pointer matches the value of the LIPT pointer, the C0RGPT.RHPM bit (receive history list pointer match) is set to 1. This indicates that no message buffer number that has not been read remains in the RHL. If a new message buffer number is recorded, the LIPT pointer is incremented and because its value no longer matches the value of the RGPT pointer, the RHPM bit is cleared. In other words, the numbers of the unread message buffers exist in the RHL. If the LIPT pointer is incremented and matches the value of the RGPT pointer minus 1, the C0RGPT.ROVF bit (receive history list overflow) is set to 1. This indicates that the RHL is full of numbers of message buffers that have not been read. When further message reception and storing occur, the last recorded message buffer number is overwritten by the number of the message buffer that received and stored the new message. After the ROVF bit has been set to 1, the recorded message buffer numbers in the RHL do not completely reflect chronological order. However the messages themselves are not lost and can be located by a CPU search in the message buffer memory with the help of the DN bit. <R> Caution Even if the receive history list overflows (C0RGPT.ROVF bit = 1), the receive history can be read until no more history is left unread and the C0RGPT.RHPM bit is set (1). However, the ROVF bit is kept set (1) (= overflow occurs) until cleared (0) by software. In this status, the RHPM bit is not cleared (0), unless the ROVF bit is cleared (0), even if a new receive history is stored and written to the list. If ROVF bit = 1 and RHPM bit = 1 and the receive history list overflows, therefore, the RHPM bit indicates that no more history is left unread even if new history is received and stored. Remark m = 00 to 31 User's Manual U16541EJ5V1UD 831 CHAPTER 19 CAN CONTROLLER As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without the RHL being read by the host processor, a complete sequence of receptions can not be recovered. Figure 19-30. Receive History List Receive history list (RHL) Receive history list (RHL) 23 22 : : : Last inmassage pointer (LIPT) 7 6 5 4 3 2 1 0 23 22 Event: - Message buffer 6, 9, 2, and 7 are read by host processor. - Newly received messages are stored in message buffer 3, 4, and 8. Message buffer 7 Message buffer 2 Message buffer 9 Message buffer 6 Receive history list get pointer (RGPT) : : : Last inmassage pointer (LIPT) 7 6 5 4 3 2 1 0 Message buffer1 Message buffer9 : : : Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 6 Message buffer 11 Message buffer 10 Message buffer 8 Message buffer 4 Message buffer 3 Receive history list get pointer (RGPT) Event: - 20 other massages are received. Message buffer 6 carries last received message. - Upon reception in message buffer 6, RHL is full. - ROVF bit is set to 1. Receive history list (RHL) 23 22 7 6 5 4 3 2 1 0 Last inmassage pointer (LIPT) Receive history list (RHL) 23 22 Event: - Reception in message buffer13, 14, and 15 occurs. - Overflow situation occurs. Receive history list get pointer (RGPT) Last inmassage pointer (LIPT) ROVF bit = 1 LIPT is blocked 7 6 5 4 3 2 1 0 Message buffer 1 Message buffer 9 : : : Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 15 Message buffer 11 Message buffer 10 Receive history list get pointer (RGPT) ROVF bit = 1 LIPT is blocked ROVF bit = 1 denotes that LIPT equals RGPT - 1 while message buffer number stored to element indicated by LIPT - 1. 832 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.9.4 Mask function For some message buffers that are used for reception, whether one of four global reception masks is applied can be selected. Load resulting from comparing message identifiers is reduced by masking some bits, and, as a result, some different identifiers can be received in a buffer. By using the mask function, the identifier of a message received from the CAN bus can be compared with the identifier set to a message buffer in advance. Regardless of whether the masked ID is set to 0 or 1, the received message can be stored in the defined message buffer. While the mask function is in effect, an identifier bit that is defined to be 1 by a mask in the received message is not compared with the corresponding identifier bit in the message buffer. However, this comparison is performed for any bit whose value is defined as 0 by the mask. For example, let us assume that all messages that have a standard-format ID, in which bits ID27 to ID25 are 0 and bits ID24 and ID22 are 1, are to be stored in message buffer 14. The procedure for this example is shown below. <1> Identifier to be stored in message buffer ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 x 0 0 0 1 x 1 x x x x Remark x = don't care <2> Identifier to be configured in message buffer 14 (example) (Using C0MIDL14 and C0MIDH14 registers) ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 x 0 0 0 1 x 1 x x x x ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 x x x x x x x x x x x ID6 ID5 ID4 ID3 ID2 ID1 ID0 x x x x x x x ID with the ID27 to ID25 bits cleared to 0 and the ID24 and ID22 bits set to 1 is registered (initialized) to message buffer 14. Remark x = don't care Remark Message buffer 14 is set as a standard format identifier that is linked to mask 1 (C0MCONF14.MT2 to C0MCONF14.MT0 bits are set to 010B). User's Manual U16541EJ5V1UD 833 CHAPTER 19 CAN CONTROLLER <3> Mask setting for CAN module 0 (mask 0) (example) (Using CAN0 module mask 1 registers L and H (C0MASK1L and C0MASK1H)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 1 0 0 0 0 1 0 1 1 1 1 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 1 1 1 1 1 1 1 1 1 1 1 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 1 1 1 1 1 1 1 1: Not compared (masked) 0: Compared The CMID27 to CMID24 and CMID22 bits are cleared to 0, and the CMID28, CMID23, and CMID21 to CMID0 bits are set to 1. 834 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type. These message buffers can be allocated in any area in the message buffer memory, and they are not necessarily to be allocated adjacent to each other. Suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and the same ID is set to each message buffer. If the first message whose ID matches an ID of the message buffers is received, it is stored in message buffer 10. At this point, the DN bit of message buffer 10 is set, prohibiting overwriting the message buffer. When the next message with a matching ID is received, it is received and stored in message buffer 11. Each time a message with a matching ID is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and so on. Even when a data block consisting of multiple messages is received, the messages can be stored and received without overwriting the previously received matching-ID data. Whether a data block has been received and stored can be checked by setting the C0MCTRLm.IE bit of each message buffer. For example, if a data block consists of k messages, k message buffers are initialized for reception of the data block. The IE bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the IE bit in message buffer k-1 is set to 1 (interrupts enabled). In this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating that MBRB has become full. Alternatively, by clearing the IE bit of message buffers 0 to (k-3) and setting the IE bit of message buffer k-2, a warning that MBRB is about to overflow can be issued. The basic conditions of storing receive data in each message buffer for the MBRB are the same as the conditions of storing data in a single message buffer. Cautions 1. MBRB can be configured for each of the same message buffer types. Therefore, even if a message buffer of another MBRB whose ID matches but whose message buffer type is different has a vacancy, the received message is not stored in that message buffer, but instead discarded. 2. MBRB does not have a ring buffer structure. Therefore, after a message is stored in the message buffer having the highest number in the MBRB configuration, a newly received message will no longer be stored in the message buffer in the order from the lowest message buffer number. 3. MBRB operates based on the reception and storage conditions; there are no settings dedicated to MBRB, such as function enable bits. By setting the same message buffer type and ID to two or more message buffers, MBRB is automatically configured. 4. With MBRB, "matching ID" means "matching ID after mask". Even if the ID set to each message buffer is not the same, if the ID that is masked by the mask register matches, it is considered a matching ID and the buffer that has this ID is treated as the storage destination of a message. 5. Priority among each MBRB conforms to the priority shown in 19.9.1 Message reception. Remark m = 00 to 31 User's Manual U16541EJ5V1UD 835 CHAPTER 19 CAN CONTROLLER 19.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. * Used as a message buffer (C0MCONFm.MA0 bit set to 1.) * Set as a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits set to 000B) * Ready for reception (C0MCTRLm.RDY bit set to 1.) * Set to transmit message (C0MCONFm.RTR bit is cleared to 0.) * Transmission request is not set. (C0MCTRLm.TRQ bit is cleared to 0.) Upon acceptance of a remote frame, the following actions are executed if the ID of the received remote frame matches the ID of a message buffer that satisfies the above conditions. * The C0MDLCm.DLC3 to C0MDLCm.DLC0 bits store the received DLC value. * The C0MDATA0m to C0MDATA7m registers in the data area are not updated (data before reception is saved). * The C0MCTRLm.DN bit is set to 1. * The C0INTS.CINTS1 bit is set to 1 (if the C0MCTRLm.IE bit of the message buffer that receives and stores the frame is set to 1). * The reception completion interrupt (INTC0REC) is output (if the IE bit of the message buffer that receives and stores the frame is set to 1 and if the C0IE.CIE1 bit is set to 1). * The message buffer number is recorded in the receive history list. Caution When a message buffer is searched for receiving and storing a remote frame, overwrite control by the C0MCONFm.OWS bit of the message buffer and the DN bit are not affected. The setting of the OWS bit is ignored and the DN bit is set to 1 in every case. If more than one transmit message buffer has the same ID and the ID of the received remote frame matches that ID, the remote frame is stored in the transmit message buffer with the lowest message buffer number. Remark 836 m = 00 to 31 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.10 Message Transmission 19.10.1 Message transmission In all the operation modes, if the C0MCTRLm.TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched. * Used as a message buffer (C0MCONFm.MA0 bit set to 1.) * Set as a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits set to 000B.) * Ready for transmission (C0MCTRLm.RDY bit is set to 1.) Remark m = 00 to 31 The CAN system is a multi-master communication system. In a system like this, the priority of message transmission is determined based on message identifiers (IDs). To facilitate transmission processing by software when there are several messages awaiting transmission, the CAN module uses hardware to check the ID of the message with the highest priority and automatically identifies that message. This eliminates the need for softwarebased priority control. Transmission priority is controlled by the identifier (ID). Figure 19-31. Message Processing Example Message No. Message waiting to be transmitted 0 1 ID = 120H 2 ID = 229H 3 4 5 ID = 223H 6 ID = 023H The CAN module transmits messages in the following sequence. 1. Message 6 2. Message 1 3. Message 8 4. Message 5 5. Message 2 7 8 ID = 123H 9 After the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the TRQ bit set to 1 in advance) is transmitted. If a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. If the new transmission request has a higher priority, it is transmitted, unless transmission of a message with a low priority has already started. To solve this reversal of priorities, software can request that transmission of a message of low priority be stopped. The highest priority is determined according to the following rules. User's Manual U16541EJ5V1UD 837 CHAPTER 19 CAN CONTROLLER Priority 1 (high) Conditions Value of first 11 bits of ID [ID28 to ID18]: Description The message frame with the lowest value represented by the first 11 bits of the ID is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11-bit standard ID has a higher priority than a message frame with a 29-bit extended ID. 2 Frame type A data frame with an 11-bit standard ID (C0MCONFm.RTR bit is cleared to 0) has a higher priority than a remote frame with a standard ID and a message frame with an extended ID. 3 ID type A message frame with a standard ID (C0MIDHm.IDE bit is cleared to 0) has a higher priority than a message frame with an extended ID. 4 Value of lower 18 bits of ID If one or more transmission-pending extended ID message frame has equal [ID17 to ID0]: values in the first 11 bits of the ID and the same frame type (equal RTR bit values), the message frame with the lowest value in the lower 18 bits of its extended ID is transmitted first. 5 (low) Message buffer number If two or more message buffers request transmission of message frames with the same ID, the message from the message buffer with the lowest message buffer number is transmitted first. Remarks 1. If the automatic block transmission request bit C0GMABT.ABTTRG bit is set to 1 in the normal operation mode with ABT, the TRQ bit is set to 1 only for one message buffer in the ABT message buffer group. If the ABT mode was triggered by the ABTTRG bit (1), one TRQ bit is set to 1 in the ABT area (buffers 0 to 7). In addition to this TRQ bit, the application can request transmissions (set TRQ bit to 1) for other TX-message buffers that do not belong to the ABT area. In that case an internal arbitration process (TX-search) evaluates all of the TX-message buffers with the TRQ bit set to 1 and chooses the message buffer that contains the highest prioritized identifier for the next transmission. If there are 2 or more identifiers that have the highest priority (i.e. identical identifiers), the message located at the lowest message buffer number is transmitted first. Upon successful transmission of a message frame, the following operations are performed. * The TRQ bit of the corresponding transmit message buffer is automatically cleared to 0. * The transmission completion status bit CINTS0 of the C0INTS register is set to 1 (if the interrupt enable bit (IE) of the corresponding transmit message buffer is set to 1). * An interrupt request signal INTC0TRX is output (if the C0IE.CIE0 bit is set to 1 and if the interrupt enable bit (IE) of the corresponding transmit message buffer is set to 1). <R> 2. Before changing the contents of the transmit message buffer, the RDY flag of this buffer must be cleared. Since the RDY flag may be temporarily locked while the internal processing is changed, it is necessary to check the status of the RDY flag after changing the buffer contents. 838 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer in which each data frame or remote frame was received and stored. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding C0LOPT register, and the transmit history list get pointer (TGPT) with the corresponding C0TGPT register. The THL is undefined immediately after the transition of the CAN module from the initialization mode to one of the operation modes. The C0LOPT register holds the contents of the THL element indicated by the value of the LOPT pointer minus 1. By reading the C0LOPT register, therefore, the number of the message buffer that transmitted a data frame or remote frame first can be checked. The LOPT pointer is utilized as a write pointer that indicates to what part of the THL a message buffer number is recorded. Any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the THL element indicated by the LOPT pointer. Each time recording to the THL has been completed, the LOPT pointer is automatically incremented. In this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. The TGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the THL. This pointer indicates the first THL element that the CPU has not yet read. By reading the C0TGPT register by software, the number of a message buffer that has completed transmission can be read. Each time a message buffer number is read from the C0TGPT register, the TGPT pointer is automatically incremented. If the value of the TGPT pointer matches the value of the LOPT pointer, the C0TGPT.THPM bit (transmit history list pointer match) is set to 1. This indicates that no message buffer numbers that have not been read remain in the THL. If a new message buffer number is recorded, the LOPT pointer is incremented and because its value no longer matches the value of the TGPT pointer, the THPM bit is cleared. In other words, the numbers of the unread message buffers exist in the THL. If the LOPT pointer is incremented and matches the value of the TGPT pointer minus 1, the TOVF bit (transmit history list overflow) of the C0TGPT register is set to 1. This indicates that the THL is full of message buffer numbers that have not been read. If a new message is received and stored, the message buffer number recorded last is overwritten by the number of the message buffer that received and stored the new message. After the TOVF bit has been set (1), therefore, the recorded message buffer numbers in the THL do not completely reflect chronological order. However the transmitted messages can be found by a CPU search applied to all transmit message buffers unless the CPU has not overwritten a transmit object in one of these buffers beforehand. In total up to six transmission completions can occur without overflowing the THL. <R> Caution Even if the transmit history list overflows (C0TGPT.TOVF bit = 1), the transmit history can be read until no more history is left unread and the C0TGPT.THPM bit is set (1). However, the TOVF bit is kept set (1) (= overflow occurs) until cleared (0) by software. In this status, the THPM bit is not cleared (0), unless the TOVF bit is cleared (0), even if a new transmit history is stored and written to the list. If the TOVF bit = 1 and the THPM bit = 1 and the receive history list overflows, therefore, the THPM bit indicates that no more history is left unread even if new history is received and stored. User's Manual U16541EJ5V1UD 839 CHAPTER 19 CAN CONTROLLER Figure 19-32. Transmit History List Transmit history list (THL) Transmit history list (THL) Last outmessage pointer (LOPT) 7 6 5 4 3 2 1 0 Event: Message buffer 7 Message buffer 2 Message buffer 9 Message buffer 6 - CPU confirms Tx completion of message buffer 6, 9, and 2. Last out- Tx completion of message message buffer 3, and 4. pointer (LOPT) Transmit history list get pointer (TGPT) 7 6 5 4 3 2 1 0 Message buffer 4 Message buffer 3 Message buffer 7 Transmit history list get pointer (TGPT) Event: - Message buffer 8, 5, 6, and 10 completes transmission. - THL is full. - TOVF bit is set to 1. Transmit history list (THL) Last outmessage pointer (LOPT) 7 6 5 4 3 2 1 0 Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 7 Message buffer 10 Message buffer 6 TOVF bit = 1 LOPT is blocked Transmit history list (THL) Event: - Message buffer11, 13, and 14 completes transmission. - Overflow situation occurs. Transmit history list get pointer (TGPT) 7 6 5 4 3 2 1 0 Message buffer 5 Message buffer 8 Message buffer 4 Message buffer 3 Message buffer 7 Last outMessage buffer 14 message Message buffer 6 pointer (LOPT) TOVF bit = 1 LOPT is blocked Transmit history list get pointer (TGPT) TOVF bit = 1 denotes that LOPT equals TGPT - 1 while message buffer number stored to element indicated by LOPT - 1. 840 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7). By setting the C0CTRL.OPMODE2 to C0CTRL.OPMODE0 bits to 010B, "normal operation mode with automatic block transmission function" (hereafter referred to as ABT mode) can be selected. To issue an ABT transmission request, define the message buffers by software first. Set the C0MCONFm.MA0 bit (1) in all the message buffers used for ABT, and define all the buffers as transmit message buffers by setting the C0MCONFm.MA2 to C0MCONFm.MA0 bits to 000B. Be sure to set the ID used in the message buffer for ABT for each message buffer, even when that ID is being used for all the message buffers. To use two or more IDs, set the ID of each message buffer by using the C0MIDLm and C0MIDHm registers. Set the C0MDLCm and C0MDATA0m to C0MDATA7m registers before issuing a transmission request for the ABT function. After initialization of message buffers for ABT is finished, the C0MCTRLm.RDY bit needs to be set (1). In the ABT mode, the C0MCTRLm.TRQ bit does not have to be manipulated by software. After the data for the ABT message buffers has been prepared, set the C0GMABT.ABTTRG bit to 1. Automatic block transmission is then started. When ABT is started, the TRQ bit in the first message buffer (message buffer 0) is automatically set to 1. After transmission of the data of message buffer 0 is finished, the TRQ bit of the next message buffer, message buffer 1, is set automatically. In this way, transmission is executed successively. A delay time can be inserted by program in the interval in which the transmission request (TRQ bit) is automatically set while successive transmission is being executed. The delay time to be inserted is defined by the C0GMABTD register. The unit of the delay time is DBT (data bit time). DBT depends on the setting of the C0BRP and C0BTR registers. During ABT, the priority of the transmission ID is not searched in the ABT transmit message buffer. The data of message buffers 0 to 7 is sequentially transmitted. When transmission of the data frame from message buffer 7 has been completed, the ABTTRG bit is automatically cleared to 0 and the ABT operation is finished. If the RDY bit of an ABT message buffer is cleared during ABT, no data frame is transmitted from that buffer, ABT is stopped, and the ABTTRG bit is cleared. After that, transmission can be resumed from the message buffer where ABT stopped, by setting the RDY and ABTTRG bits to 1 by software. To not resume transmission from the message buffer where ABT stopped, the internal ABT engine can be reset by setting the C0GMABT.ABTCLR bit to 1 while ABT mode is stopped and the ABTTRG bit is cleared to 0. In this case, transmission is started from message buffer 0 if the ABTCLR bit is cleared to 0 and then the ABTTRG bit is set to 1. An interrupt can be used to check if data frames have been transmitted from all the message buffers for ABT. To do so, the C0MCTRLm.IE bit of each message buffer except the last message buffer needs to be cleared (0). If a transmit message buffer other than those used by the ABT function (message buffers 8 to 31) is assigned to a transmit message buffer, the priority of the message to be transmitted is determined by the priority of the transmission ID of the ABT message buffer whose transmission is currently held pending and the transmission message buffer of the message buffers other than those used by the ABT function. Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list (THL). User's Manual U16541EJ5V1UD 841 CHAPTER 19 CAN CONTROLLER Cautions 1. To resume the normal operation mode with ABT from the message buffer 0, set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed. 2. Whether the automatic block transmission engine is cleared by setting the ABTCLR bit to 1 can be confirmed if the ABTCLR bit is automatically cleared immediately after the processing of the clearing request is completed. 3. Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in the initialization mode, the proper operation is not guaranteed after the mode is changed from the initialization mode to the ABT mode. 4. Do not set the TRQ bit of the ABT message buffers to 1 by software in the normal operation mode with ABT. Otherwise, the operation is not guaranteed. 5. The C0GMABTD register is used to set the delay time that is inserted in the period from completion of the preceding ABT message to setting of the TRQ bit for the next ABT message when the transmission requests are set in the order of message numbers for each message for ABT that is successively transmitted in the ABT mode. The timing at which the messages are actually transmitted onto the CAN bus varies depending on the status of transmission from other stations and the status of the setting of the transmission request for messages other than the ABT messages (message buffers 8 to 31). 6. If a transmission request is made for a message other than an ABT message and if no delay time is inserted in the interval in which transmission requests for ABT are automatically set (C0GMABTD register = 00H), messages other than ABT messages may be transmitted regardless of their priority in regards to the ABT message. 7. Do not clear the RDY bit to 0 when the ABTTRG bit = 1. 8. If a message is received from another node in the normal operation mode with ABT, the message may be transmitted after the time of one frame has elapsed even when C0GMABTD register = 00H. Remark m = 00 to 31 19.10.4 Transmission abort process Remark m = 00 to 31 (1) Transmission abort process other than in normal operation mode with automatic block transmission (ABT) The user can clear the C0MCTRLm.TRQ bit to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked using the C0CTRL.TSTAT bit and the C0TGPT register, which indicate the transmission status on the CAN bus (for details, see the processing in Figure 19-46). (2) Transmission abort process except for ABT transmission in normal operation mode with automatic block transmission (ABT) The user can clear the C0GMABT.ABTTRG bit to 0 to abort a transmission request. After checking the ABTTRG bit of the C0GMABT register = 0, clear the C0MCTRLm.TRQ bit to 0. The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or not can be checked by using the C0CTRL.TSTAT bit and the C0TGPT register, which indicate the transmission status on the CAN bus (for details, see the process in Figure 19-47). 842 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (3) Transmission abort in normal operation mode with automatic block transmission (ABT) To abort ABT that is already started, clear the C0GMABT.ABTTRG bit to 0. In this case, the ABTTRG bit remains 1 if an ABT message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. This aborts ABT. If the last transmission (before ABT) was successful, the normal operation mode with ABT is left with the internal ABT pointer pointing to the next message buffer to be transmitted. In the case of an erroneous transmission, the position of the internal ABT pointer depends on the status of the TRQ bit in the last transmitted message buffer. If the TRQ bit is set to 1 when clearing the ABTTRG bit is requested, the internal ABT pointer points to the last transmitted message buffer (for details, see the process in Figure 19-48 (a)). If the TRQ bit is cleared to 0 when clearing the ABTTRG bit is requested, the internal ABT pointer is increased in increments of 1 and indicates the next message buffer in the ABT area (for details, see the process in Figure 19-48 (b)). Caution Be sure to abort ABT by clearing the ABTTRG bit to 0. The operation is not guaranteed if aborting transmission is requested by clearing RDY. When the normal operation mode with ABT is resumed after ABT has been aborted and the ABTTRG bit is set to 1, the next ABT message buffer to be transmitted can be determined from the following table. Status of TRQ of ABT Message Buffer Set (1) Cleared (0) Note Abort After Successful Transmission Abort After Erroneous Transmission Next message buffer in the ABT area Note Same message buffer in the ABT area Next message buffer in the ABT area Note Next message buffer in the ABT area Note The above resumption operation can be performed only if a message buffer ready for ABT exists in the ABT area. For example, an abort request that is issued while ABT of message buffer 7 is in progress is regarded as completion of ABT, rather than abort, if transmission of message buffer 7 has been successfully completed, even if the ABTTRG bit is cleared to 0. If the C0MCTRLm.RDY bit in the next message buffer in the ABT area is cleared to 0, the internal ABT pointer is retained, but the resumption operation is not performed even if the ABTTRG bit is set to 1, and ABT ends immediately. Remark m = 00 to 31 19.10.5 Remote frame transmission Remote frames can be transmitted only from transmit message buffers. Set whether a data frame or remote frame is transmitted via the C0MCONFm.RTR bit. Setting (1) the RTR bit sets remote frame transmission. Remark m = 00 to 31 User's Manual U16541EJ5V1UD 843 CHAPTER 19 CAN CONTROLLER 19.11 Power Saving Modes 19.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered. In the CAN sleep mode, the CAN module does not transmit messages, even when transmission requests are issued or pending. (1) Entering CAN sleep mode The CPU issues a CAN sleep mode transition request by writing 01B to the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits. This transition request is only acknowledged only under the following conditions. (i) The CAN module is already in one of the following operation modes * Normal operation mode * Normal operation mode with ABT * Receive-only mode * Single-shot mode * Self-test mode * CAN stop mode in all the above operation modes (ii) The CAN bus state is bus idle (the 4th bit in the interframe space is recessive)Note Note If the CAN bus is fixed to dominant, the request for transition to the CAN sleep mode is held pending. Also the transition from CAN stop mode to CAN sleep mode is independent of the CAN bus state. (iii) No transmission request is pending If any one of the conditions mentioned above is not met, the CAN module will operate as follows. * If the CAN sleep mode is requested from the initialization mode, the CAN sleep mode transition request is ignored and the CAN module remains in the initialization mode. * If the CAN bus state is not bus idle (i.e., the CAN bus state is either transmitting or receiving) when the CAN sleep mode is requested in one of the operation modes, immediate transition to the CAN sleep mode is not possible. In this case, the CAN sleep mode transition request has to be held pending until the CAN bus state becomes bus idle (the 4th bit in the interframe space is recessive). In the time from the CAN sleep mode request to successful transition, the PSMODE1 and PSMODE0 bits remain 00B. When the module has entered the CAN sleep mode, the PSMODE1 and PSMODE0 bits are set to 01B. * If a request for transition to the initialization mode and a request for transition to the CAN sleep mode are made at the same time while the CAN module is in one of the operation modes, the request for the initialization mode is enabled. The CAN module enters the initialization mode at a predetermined timing. At this time, the CAN sleep mode request is not held pending and is ignored. * Even when the initialization mode and sleep mode are not requested simultaneously (i.e the first request was not granted when a second request was made), the request for initialization has priority over the CAN sleep mode request. The CAN sleep mode request is cancelled when the initialization mode is requested. When a pending request for the initialization mode is present, a subsequent request for the CAN sleep mode request is cancelled right at the point in time when it was submitted. 844 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER (2) Status in CAN sleep mode The CAN module is in one of the following states after it enters the CAN sleep mode. * The internal operating clock is stopped and the power consumption is minimized. * The function to detect the falling edge of the CAN reception pin (CRXD0) remains in effect to wake up the CAN module from the CAN bus. * To wake up the CAN module from the CPU, data can be written to the PSMODE1 and PSMODE0 bits, but nothing can be written to other CAN0 module registers or bits. * The CAN0 module registers can be read, except for the C0LIPT, C0RGPT, C0LOPT, and C0TGPT registers. * The CAN0 message buffer registers cannot be written or read. <R> * C0GMCTRL.MBON bit is cleared to 0. * A request for transition to the initialization mode is not acknowledged and is ignored. (3) Releasing CAN sleep mode The CAN sleep mode is released by the following events. * When the CPU writes 00B to the PSMODE1 and PSMODE0 bits * A falling edge at the CAN reception pin (CRXD0) (i.e. the CAN bus level shifts from recessive to dominant) Cautions 1. Even if the falling edge belongs to the SOF of a receive message, this message will not be received and stored. If the CPU has turned off the clock to the CAN while the CAN was in sleep mode, later on the CAN sleep mode will not be released and PSMODE1 and PSMODE0 bits will continue to be 01B unless the clock for the CAN is provided again. In addition to this, the receive message will not be received afterwards. <R> 2. If the falling edge is detected on the CAN reception pin (CRXD0) while the CAN clock is supplied, the PSMODE0 bit must be cleared by software (for details, refer to the processing in Figure 19-53). After releasing the sleep mode, the CAN module returns to the operation mode from which the CAN sleep mode was requested and the PSMODE1 and PSMODE0 bits are reset to 00B. If the CAN sleep mode is released by a change in the CAN bus state, the C0INTS.CINTS5 bit is set to 1, regardless of the C0IE.CIE bit. After the CAN module is released from the CAN sleep mode, it participates in the CAN bus again by <R> automatically detecting 11 consecutive recessive-level bits on the CAN bus. After releasing the sleep mode and before accessing the message buffer by application again, confirm that C0GMCTRL.MBON bit = 1. When a request for transition to the initialization mode is made while the CAN module is in the CAN sleep mode, that request is ignored; the CPU has to be released from sleep mode by software first before entering the initialization mode. <R> Caution When the CAN sleep mode is released by an event of the CAN bus, a wakeup interrupt occurs even if the event of the CAN bus occurs immediately after the mode has been changed to the sleep mode. Note that the interrupt can occur at any time. User's Manual U16541EJ5V1UD 845 CHAPTER 19 CAN CONTROLLER 19.11.2 CAN stop mode The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode. The CAN stop mode can only be released (shifting to CAN sleep mode) by writing 01B to the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits and not by a change in the CAN bus state. No message is transmitted even when transmission requests are issued or pending. (1) Entering CAN stop mode A CAN stop mode transition request is issued by writing 11B to the PSMODE1 and PSMODE0 bits. A CAN stop mode request is only acknowledged when the CAN module is in the CAN sleep mode. In all other modes, the request is ignored. Caution To set the CAN module to the CAN stop mode, the module must be in the CAN sleep mode. To confirm that the module is in the sleep mode, check that the PSMODE1 and PSMODE0 bits = 01B, and then request the CAN stop mode. If a bus change occurs at the CAN reception pin (CRXD0) while this process is being performed, the CAN sleep mode is automatically released. <R> In this case, the CAN stop mode transition request cannot be acknowledged (when the CAN clock is supplied, however, the PSMODE0 bit must be cleared by software after a bus change occurs at the CAN reception pin (CRXD0)). (2) Status in CAN stop mode The CAN module is in one of the following states after it enters the CAN stop mode. * The internal operating clock is stopped and the power consumption is minimized. * To wake up the CAN module from the CPU, data can be written to the PSMODE1 and PSMODE0 bits, but nothing can be written to other CAN0 module registers or bits. * The CAN0 module registers can be read, except for the C0LIPT, C0RGPT, C0LOPT, and C0TGPT registers. * The CAN0 message buffer registers cannot be written or read. <R> * The C0GMCTRL.MBON bit is cleared to 0. * An initialization mode transition request is not acknowledged and is ignored. (3) Releasing CAN stop mode The CAN stop mode can only be released by writing 01B to the PSMODE1 and PSMODE0 bits. After releasing the CAN stop mode, the CAN module enters the CAN sleep mode. When the initialization mode is requested while the CAN module is in the CAN stop mode, that request is ignored; the CPU has to release the stop mode and subsequently the CAN sleep mode before entering into initialization mode. It is impossible to enter another operation mode directly from the CAN stop mode without entering the CAN sleep mode, the request will be ignored. 846 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus. Here is an example of using the power saving modes. First, put the CAN module in the CAN sleep mode (PSMODE1, PSMODE0 bits = 01B). Next, put the CPU in the power saving mode. If an edge transition from recessive to dominant is detected at the CRXD0 signal in this status, the CINTS5 bit in the CAN module is set to 1. If the C0CTRL.CIE5 bit is set to 1, a wakeup interrupt (INTC0WUP) is generated. The CAN module is automatically released from the CAN sleep mode (PSMODE1, PSMODE0 bits = 00B) <R> and returns to normal operation mode (when the CAN clock is supplied, however, the PSMODE0 bit must be cleared by software after a bus change occurs at the CAN reception pin (CRXD0)). The CPU, in response to INTC0WUP, can release its own power saving mode and return to normal operation mode. To further reduce the power consumption of the CPU, the internal clocks, including that of the CAN module, may be tuned off. In this case, the operating clock supplied to the CAN module is turned off after the CAN module is put in the CAN sleep mode. Then the CPU enters a power saving mode in which the clock supplied to the CPU is turned off. If an edge transition from recessive to dominant is detected at the CRXD0 signal in this status, the CAN module can set the CINTS5 bit to 1 and generate a wakeup interrupt (INTC0WUP) even if it is not supplied with a clock. The other functions, however, do not operate because the clock supply to the CAN module is shut off, and the module remains in the CAN sleep mode. The CPU, in response to INTC0WUP, releases its power saving mode, resumes supply of the internal clocks, including the clock to the CAN module, after oscillation stabilization time has elapsed, and starts instruction execution. The CAN module is immediately released from the CAN sleep mode when the clock supply is resumed, and returns to normal operation mode (PSMODE1, PSMODE0 bits = 00B). User's Manual U16541EJ5V1UD 847 CHAPTER 19 CAN CONTROLLER 19.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. After an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software. Table 19-20. List of CAN Module Interrupt Sources No. Interrupt Status Bit Name Register Interrupt Enable Bit Name Note 1 C0INTS CIE0 Note 1 C0INTS Register Interrupt Interrupt Source Description Request Signal Note 1 C0IE INTC0TRX CIE1 Note 1 C0IE INTC0REC Valid message frame reception in message buffer m INTC0ERR CAN module error state interrupt Message frame successfully transmitted from 1 CINTS0 2 CINTS1 3 CINTS2 C0INTS CIE2 C0IE 4 CINTS3 C0INTS CIE3 C0IE CAN module protocol error interrupt 5 CINTS4 C0INTS CIE4 C0IE CAN module arbitration loss interrupt 6 CINTS5 C0INTS CIE5 C0IE message buffer m INTC0WUP Note 2 Note 3 CAN module wakeup interrupt from CAN sleep mode Note 4 Notes 1. The C0MCTRL.IE bit (message buffer interrupt enable bit) of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process. 2. This interrupt is generated when the transmission/reception error counter is at the warning level, or in the error passive or bus-off state. 3. This interrupt is generated when a stuff error, form error, ACK error, bit error, or CRC error occurs. 4. This interrupt is generated when the CAN module is woken up from the CAN sleep mode because a falling edge is detected at the CAN reception pin (CAN bus transition from recessive to dominant). Remark 848 m = 00 to 31 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 19.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes. For example, this mode can be used for automatic baud-rate detection. The baud rate in the CAN module is changed until "valid reception" is detected, so that the baud rates in the module match ("valid reception" means a message frame has been received in the CAN protocol layer without occurrence of an error and with an appropriate ACK between nodes connected to the CAN bus). A valid reception does not require message frames to be stored in a receive message buffer (data frames) or transmit message buffer (remote frames). The event of valid reception is indicated by setting the C0CTRL.VALID bit (1). Figure 19-33. CAN Module Terminal Connection in Receive-Only Mode CAN macro Tx Fixed to the recessive level CTXD0 Rx CRXD0 In the receive-only mode, no message frames can be transmitted from the CAN module to the CAN bus. Transmit requests issued for message buffers defined as transmit message buffers are held pending. In the receive-only mode, the CAN transmission pin (CTXD0) in the CAN module is fixed to the recessive level. Therefore, no active error flag can be transmitted from the CAN module to the CAN bus even when a CAN bus error is detected while receiving a message frame. Since no transmission can be issued from the CAN module, the transmission error counter the C0ERC.TEC7 to C0ERC.TEC0 bits are never updated. Therefore, a CAN module in the receive-only mode does not enter the bus-off state. Furthermore, ACK is not returned to the CAN bus in this mode upon the valid reception of a message frame. Internally, the local node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN bus. User's Manual U16541EJ5V1UD 849 CHAPTER 19 CAN CONTROLLER Caution If only two CAN nodes are connected to the CAN bus and one of them is operating in the receiveonly mode, there is no ACK on the CAN bus. Due to the missing ACK, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. The transmitting node becomes error passive after transmitting the message frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred). When the message frame is transmitted for the 17th time, the transmitting node generates a passive error flag. The receiving node in the receive-only mode detects the first valid message frame at this point, and the VALID bit is set to 1 for the first time. 19.13.2 Single-shot mode In the single-shot mode, automatic re-transmission as defined in the CAN protocol is switched off. (According to the CAN protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has to be repeated without control by software.) All other behavior of single shot mode is identical to normal operation mode. Features of single shot mode can not be used in combination with normal mode with ABT. The single-shot mode disables the re-transmission of an aborted message frame transmission according to the setting of the C0CTRL.AL bit. When the AL bit is cleared to 0, re-transmission upon arbitration loss and upon error occurrence is disabled. If the AL bit is set to 1, re-transmission upon error occurrence is disabled, but re-transmission upon arbitration loss is enabled. As a consequence, the C0MCTRLm.TRQ bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events. * Successful transmission of the message frame * Arbitration loss while sending the message frame (AL bit = 0) * Error occurrence while sending the message frame The events arbitration loss and error occurrence can be distinguished by checking the C0INTS.CINTS4 and C0INTS.CINTS3 bits, and the type of the error can be identified by reading the C0LEC.LEC2 to C0LEC.LEC0 bits of the register. Upon successful transmission of the message frame, the transmit completion interrupt the CINTS0 bit of the C0INTS register is set to 1. If the C0IE.CIE0 bit is set to 1 at this time, an interrupt request signal is output. The single-shot mode can be used when emulating time-triggered communication methods (e.g., TTCAN level 1). Caution The AL bit is only valid in single-shot mode. It does not affect the operation of re-transmission upon arbitration loss in other operation modes. 850 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back. The CAN transmission pin (CTXD0) is fixed to the recessive level. If the falling edge on the CAN reception pin (CRXD0) is detected after the CAN module has entered the CAN sleep mode from the self-test mode, however, the module is released from the CAN sleep mode in the same manner as the <R> other operation modes (when the CAN clock is supplied, however, the PSMODE0 bit must be cleared by software after a bus change occurs at the CAN reception pin (CRXD0)). To keep the module in the CAN sleep mode, use the CAN reception pin (CRXD0) as a port pin. Figure 19-34. CAN Module Terminal Connection in Self-Test Mode CAN macro Tx Fixed to the recessive level CTXD0 Rx CRXD0 User's Manual U16541EJ5V1UD 851 CHAPTER 19 CAN CONTROLLER <R> 19.13.4 Transmission/reception operation in each operation mode Table 19-21 shows the transmission/reception operation in each operation mode. Table 19-21. Overview of Transmission/Reception Operation in Each Operation Mode Operation Mode Retransmission Automatic Block Setting of VALID Storing Data in Data Frame/ ACK Error Frame/ Remote Frame Transmission Overload Frame Transmission Transmission (ABT) Transmission Bit Message Buffer Initialization Mode - - - - - - - Normal operation mode - Normal operation mode Receive-only mode - - - - - Single-shot mode with ABT Self test mode Note 2 Note 2 Note 2 - - - Note 1 Note 2 Note 2 Notes 1. If arbitration is lost, retransmission can be selected by the C0CTRL.AL bit. 2. Each signal is not output to the external circuit but is internally generated by the CAN module. 852 User's Manual U16541EJ5V1UD Note 2 CHAPTER 19 CAN CONTROLLER 19.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may even have different frequencies). In some applications, however, a common time base over the network (= global time base) is needed. In order to build up a global time base, a time stamp function is used. The essential mechanism of a time stamp function is the capture of timer values triggered by signals on the CAN bus. 19.14.1 Time stamp function The CAN controller supports the capturing of timer values triggered by a specific frame. An on-chip 16-bit capture timer unit in a microcontroller system is used in addition to the CAN controller. The 16-bit capture timer unit captures the timer value according to a trigger signal (TSOUT) for capturing that is output when a data frame is received from the CAN controller. The CPU can retrieve the time of occurrence of the capture event, i.e., the time stamp of the message received from the CAN bus, by reading the captured value. The TSOUT signal can be selected from the following two event sources and is specified by the C0TS.TSSEL bit. * SOF event (start of frame) (TSSEL bit = 0) * EOF event (last bit of end of frame) (TSSEL bit = 1) The TSOUT signal is enabled by setting the C0TS.TSEN bit to 1. Figure 19-35. Timing Diagram of Capture Signal TSOUT SOF SOF SOF SOF TSOUT t The TSOUT signal toggles its level upon occurrence of the selected event during data frame reception (in Figure 19-34, the SOF is used as the trigger event source). To capture a timer value by using the TSOUT signal, the capture timer unit must detect the capture signal at both the rising edge and falling edge. This time stamp function is controlled by the C0TS.TSLOCK bit. When the TSLOCK bit is cleared to 0, the TSOUT signal toggles upon occurrence of the selected event. If the TSLOCK bit is set to 1, the TSOUT signal toggles upon occurrence of the selected event, but the toggle is stopped as the TSEN bit is automatically cleared to 0 when a data frame starts to be received and stored in message buffer 0. This suppresses the subsequent toggle occurrence by the TSOUT signal, so that the time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data frame was received in message buffer 0. User's Manual U16541EJ5V1UD 853 CHAPTER 19 CAN CONTROLLER Caution The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of the TSOUT signal cannot be stopped by reception of a remote frame. Toggle of the TSOUT signal does not stop when a data frame is received in a message buffer other than message buffer 0. For these reasons, a data frame cannot be received in message buffer 0 when the CAN module is in the normal operation mode with ABT, because message buffer 0 must be set as a transmit message buffer. In this operation mode, therefore, the function to stop toggle of the TSOUT signal by the TSLOCK bit cannot be used. 854 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.15 Baud Rate Settings 19.15.1 Bit rate setting conditions Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as follows. (a) 5TQ SPT (sampling point) 17 TQ <R> SPT = TSEG1 + 1TQ (b) 8 TQ DBT (data bit time) 25 TQ DBT = TSEG1 + TSEG2 + 1TQ = TSEG2 + SPT (c) 1 TQ SJW (synchronization jump width) 4TQ SJW DBT - SPT <R> <R> (d) 4TQ TSEG1 16TQ [3 Setting value of TSEG1[3:0] 15] (e) 1TQ TSEG2 8TQ [0 Setting value of TSEG2[2:0] 7] Remark TQ = 1/fTQ (fTQ: CAN protocol layer basic system clock) TSEG1[3:0] (C0BTR.TSEG13 to C0BTR.TSEG10 bits) TSEG2[2:0] (C0BTR.TSEG22 to C0BTR.TSEG20 bits) Table 19-22 shows the combinations of bit rates that satisfy the above conditions. User's Manual U16541EJ5V1UD 855 CHAPTER 19 CAN CONTROLLER Table 19-22. Settable Bit Rate Combinations (1/3) Valid Bit Rate Setting Sampling Point (Unit %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.9 22 1 5 8 8 1100 111 63.6 22 1 7 7 7 1101 110 68.2 22 1 9 6 6 1110 101 72.7 22 1 11 5 5 1111 100 77.3 21 1 4 8 8 1011 111 61.9 21 1 6 7 7 1100 110 66.7 21 1 8 6 6 1101 101 71.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 20 1 3 8 8 1010 111 60.0 20 1 5 7 7 1011 110 65.0 20 1 7 6 6 1100 101 70.0 20 1 9 5 5 1101 100 75.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 19 1 2 8 8 1001 111 57.9 19 1 4 7 7 1010 110 63.2 19 1 6 6 6 1011 101 68.4 19 1 8 5 5 1100 100 73.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 18 1 1 8 8 1000 111 55.6 18 1 3 7 7 1001 110 61.1 18 1 5 6 6 1010 101 66.7 18 1 7 5 5 1011 100 72.2 18 1 9 4 4 1100 011 77.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 DBT Length 856 C0BTR Register Setting Value User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-22. Settable Bit Rate Combinations (2/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 17 1 2 7 7 1000 110 58.8 17 1 4 6 6 1001 101 64.7 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 16 1 1 7 7 0111 110 56.3 16 1 3 6 6 1000 101 62.5 16 1 5 5 5 1001 100 68.8 16 1 7 4 4 1010 011 75.0 16 1 9 3 3 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 15 1 2 6 6 0111 101 60.0 15 1 4 5 5 1000 100 66.7 15 1 6 4 4 1001 011 73.3 15 1 8 3 3 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 14 1 1 6 6 0110 101 57.1 14 1 3 5 5 0111 100 64.3 14 1 5 4 4 1000 011 71.4 14 1 7 3 3 1001 010 78.6 14 1 9 2 2 1010 001 85.7 14 1 11 1 1 1011 000 92.9 13 1 2 5 5 0110 100 61.5 13 1 4 4 4 0111 011 69.2 13 1 6 3 3 1000 010 76.9 13 1 8 2 2 1001 001 84.6 13 1 10 1 1 1010 000 92.3 12 1 1 5 5 0101 100 58.3 12 1 3 4 4 0110 011 66.7 12 1 5 3 3 0111 010 75.0 12 1 7 2 2 1000 001 83.3 12 1 9 1 1 1001 000 91.7 DBT Length User's Manual U16541EJ5V1UD 857 CHAPTER 19 CAN CONTROLLER Table 19-22. Settable Bit Rate Combinations (3/3) Valid Bit Rate Setting C0BTR Register Setting Value Sampling Point (Unit %) SYNC PROP PHASE PHASE TSEG13 to TSEG22 to SEGMENT SEGMENT SEGMENT1 SEGMENT2 TSEG10 TSEG20 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.0 10 1 5 2 2 0110 001 80.0 10 1 7 1 1 0111 000 90.0 9 1 2 3 3 0100 010 66.7 9 1 4 2 2 0101 001 77.8 9 1 6 1 1 0110 000 88.9 8 1 1 3 3 0011 010 62.5 8 1 3 2 2 0100 001 75.0 8 1 5 1 1 0101 000 87.5 7 Note 1 2 2 2 0011 001 71.4 7 Note 1 4 1 1 0100 000 85.7 6 Note 1 1 2 2 0010 001 66.7 6 Note 1 3 1 1 0011 000 83.3 5 Note 1 2 1 1 0010 000 80.0 4 Note 1 1 1 1 0001 000 75.0 DBT Length Note Setting with a DBT value of 7 or less is valid only when the value of the C0BRP register is other than 00H. Caution The values in Table 19-22 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. 858 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.15.2 Representative examples of baud rate settings Tables 19-23 and 19-24 show representative examples of baud rate settings. Table 19-23. Representative Examples of Baud Rate Settings (fCANMOD = 8 MHz) (1/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Value Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 1000 1 00000000 8 1 1 3 3 0011 010 62.5 1000 1 00000000 8 1 3 2 2 0100 001 75.0 1000 1 00000000 8 1 5 1 1 0101 000 87.5 500 1 00000000 16 1 1 7 7 0111 110 56.3 500 1 00000000 16 1 3 6 6 1000 101 62.5 500 1 00000000 16 1 5 5 5 1001 100 68.8 500 1 00000000 16 1 7 4 4 1010 011 75.0 500 1 00000000 16 1 9 3 3 1011 010 81.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 500 2 00000001 8 1 1 3 3 0011 010 62.5 500 2 00000001 8 1 3 2 2 0100 001 75.0 500 2 00000001 8 1 5 1 1 0101 000 87.5 250 2 00000001 16 1 1 7 7 0111 110 56.3 250 2 00000001 16 1 3 6 6 1000 101 62.5 250 2 00000001 16 1 5 5 5 1001 100 68.8 250 2 00000001 16 1 7 4 4 1010 011 75.0 250 2 00000001 16 1 9 3 3 1011 010 81.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 250 4 00000011 8 1 3 2 2 0100 001 75.0 250 4 00000011 8 1 5 1 1 0101 000 87.5 125 4 00000011 16 1 1 7 7 0111 110 56.3 125 4 00000011 16 1 3 6 6 1000 101 62.5 125 4 00000011 16 1 5 5 5 1001 100 68.8 125 4 00000011 16 1 7 4 4 1010 011 75.0 125 4 00000011 16 1 9 3 3 1011 010 81.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 125 8 00000111 8 1 3 2 2 0100 001 75.0 125 8 00000111 8 1 5 1 1 0101 000 87.5 Caution The values in Table 19-23 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. User's Manual U16541EJ5V1UD 859 CHAPTER 19 CAN CONTROLLER Table 19-23. Representative Examples of Baud Rate Settings (fCANMOD = 8 MHz) (2/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Value Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 100 4 00000011 20 1 7 6 6 1100 101 70.0 100 4 00000011 20 1 9 5 5 1101 100 75.0 100 5 00000100 16 1 7 4 4 1010 011 75.0 100 5 00000100 16 1 9 3 3 1011 010 81.3 100 8 00000111 10 1 3 3 3 0101 010 70.0 100 8 00000111 10 1 5 2 2 0110 001 80.0 100 10 00001001 8 1 3 2 2 0100 001 75.0 100 10 00001001 8 1 5 1 1 0101 000 87.5 83.3 4 00000011 24 1 7 8 8 1110 111 66.7 83.3 4 00000011 24 1 9 7 7 1111 110 70.8 83.3 6 00000101 16 1 5 5 5 1001 100 68.8 83.3 6 00000101 16 1 7 4 4 1010 011 75.0 83.3 6 00000101 16 1 9 3 3 1011 010 81.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3 8 00000111 12 1 5 3 3 0111 010 75.0 83.3 8 00000111 12 1 7 2 2 1000 001 83.3 83.3 12 00001011 8 1 3 2 2 0100 001 75.0 83.3 12 00001011 8 1 5 1 1 0101 000 87.5 33.3 10 00001001 24 1 7 8 8 1110 111 66.7 33.3 10 00001001 24 1 9 7 7 1111 110 70.8 33.3 12 00001011 20 1 7 6 6 1100 101 70.0 33.3 12 00001011 20 1 9 5 5 1101 100 75.0 33.3 15 00001110 16 1 7 4 4 1010 011 75.0 33.3 15 00001110 16 1 9 3 3 1011 010 81.3 33.3 16 00001111 15 1 6 4 4 1001 011 73.3 33.3 16 00001111 15 1 8 3 3 1010 010 80.0 33.3 20 00010011 12 1 5 3 3 0111 010 75.0 33.3 20 00010011 12 1 7 2 2 1000 001 83.3 33.3 24 00010111 10 1 3 3 3 0101 010 70.0 33.3 24 00010111 10 1 5 2 2 0110 001 80.0 33.3 30 00011101 8 1 3 2 2 0100 001 75.0 33.3 30 00011101 8 1 5 1 1 0101 000 87.5 Caution The values in Table 19-23 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. 860 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Table 19-24. Representative Examples of Baud Rate Settings (fCANMOD = 16 MHz) (1/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Value Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 1000 1 00000000 16 1 1 7 7 0111 110 56.3 1000 1 00000000 16 1 3 6 6 1000 101 62.5 1000 1 00000000 16 1 5 5 5 1001 100 68.8 1000 1 00000000 16 1 7 4 4 1010 011 75.0 1000 1 00000000 16 1 9 3 3 1011 010 81.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 1000 2 00000001 8 1 3 2 2 0100 001 75.0 1000 2 00000001 8 1 5 1 1 0101 000 87.5 500 2 00000001 16 1 1 7 7 0111 110 56.3 500 2 00000001 16 1 3 6 6 1000 101 62.5 500 2 00000001 16 1 5 5 5 1001 100 68.8 500 2 00000001 16 1 7 4 4 1010 011 75.0 500 2 00000001 16 1 9 3 3 1011 010 81.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 500 4 00000011 8 1 3 2 2 0100 001 75.0 500 4 00000011 8 1 5 1 1 0101 000 87.5 250 4 00000011 16 1 3 6 6 1000 101 62.5 250 4 00000011 16 1 5 5 5 1001 100 68.8 250 4 00000011 16 1 7 4 4 1010 011 75.0 250 4 00000011 16 1 9 3 3 1011 010 81.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 250 8 00000111 8 1 3 2 2 0100 001 75.0 250 8 00000111 8 1 5 1 1 0101 000 87.5 125 8 00000111 16 1 3 6 6 1000 101 62.5 125 8 00000111 16 1 7 4 4 1010 011 75.0 125 8 00000111 16 1 9 3 3 1011 010 81.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125 16 00001111 8 1 3 2 2 0100 001 75.0 125 16 00001111 8 1 5 1 1 0101 000 87.5 Caution The values in Table 19-24 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. User's Manual U16541EJ5V1UD 861 CHAPTER 19 CAN CONTROLLER Table 19-24. Representative Examples of Baud Rate Settings (fCANMOD = 16 MHz) (2/2) Set Baud Division C0BRP Rate Value Ratio of Register Set (Unit: kbps) C0BRP Value Register Valid Bit Rate Setting (Unit: kbps) C0BTR Register Setting Value Length of SYNC DBT SEGMENT PROP PHASE PHASE SEGMENT SEGMENT1 SEGMENT2 Sampling Point TSEG13 to TSEG22 to TSEG10 TSEG20 (Unit: %) 100 8 00000111 20 1 9 5 5 1101 100 75.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 100 10 00001001 16 1 7 4 4 1010 011 75.0 100 10 00001001 16 1 9 3 3 1011 010 81.3 100 16 00001111 10 1 3 3 3 0101 010 70.0 100 16 00001111 10 1 5 2 2 0110 001 80.0 100 20 00010011 8 1 3 2 2 0100 001 75.0 83.3 8 00000111 24 1 7 8 8 1110 111 66.7 83.3 8 00000111 24 1 9 7 7 1111 110 70.8 83.3 12 00001011 16 1 7 4 4 1010 011 75.0 83.3 12 00001011 16 1 9 3 3 1011 010 81.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.3 16 00001111 12 1 5 3 3 0111 010 75.0 83.3 16 00001111 12 1 7 2 2 1000 001 83.3 83.3 24 00010111 8 1 3 2 2 0100 001 75.0 83.3 24 00010111 8 1 5 1 1 0101 000 87.5 33.3 30 00011101 24 1 7 8 8 1110 111 66.7 33.3 30 00011101 24 1 9 7 7 1111 110 70.8 33.3 24 00010111 20 1 9 5 5 1101 100 75.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.3 30 00011101 16 1 7 4 4 1010 011 75.0 33.3 30 00011101 16 1 9 3 3 1011 010 81.3 33.3 32 00011111 15 1 8 3 3 1010 010 80.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.3 37 00100100 13 1 6 3 3 1000 010 76.9 33.3 37 00100100 13 1 8 2 2 1001 001 84.6 33.3 40 00100111 12 1 5 3 3 0111 010 75.0 33.3 40 00100111 12 1 7 2 2 1000 001 83.3 33.3 48 00101111 10 1 3 3 3 0101 010 70.0 33.3 48 00101111 10 1 5 2 2 0110 001 80.0 33.3 60 00111011 8 1 3 2 2 0100 001 75.0 33.3 60 00111011 8 1 5 1 1 0101 000 87.5 Caution The values in Table 19-24 do not guarantee the operation of the network system. Thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the CAN bus and CAN transceiver. 862 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER 19.16 Operation of CAN Controller The processing procedure shown below is recommended to operate the CAN controller. Develop your program by referring to this recommended processing procedure. Remark m = 00 to 31 Figure 19-36. Initialization START Set C0GMCS register. Set C0GMCTRL register. (Set GOM bit = 1) Set C0BRP register, C0BTR register. Set C0IE register. Set C0MASK register. Initialize message buffers. Set C0CTRL register. (Set OPMODE bit.) END Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, singleshot mode, self-test mode User's Manual U16541EJ5V1UD 863 CHAPTER 19 CAN CONTROLLER Figure 19-37. Re-initialization START Clear OPMODE. INIT mode? No Yes Set C0BRP register, C0BTR register. Initialize message buffers. Set C0IE register. C0ERC and C0INFO register clear? No Yes Set C0MASK register. Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register. (Set OPMODE bit.) END Caution After setting the CAN module to the initialization mode, avoid setting the module to another operation mode immediately after. If it is necessary to immediately set the module to another operation mode, be sure to access registers other than the C0CTRL and C0GMCTRL registers (e.g., set a message buffer). Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, singleshot mode, self-test mode 864 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-38. Message Buffer Initialization START No RDY bit = 1? Yes Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Yes Set C0MCONFm register. Set C0MIDHm register, C0MIDLm register. Transmit message buffer? No Yes Set C0MDLCm register. Clear C0MDATAm register. Set C0MCTRLm register. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 END Cautions 1. Before a message buffer is initialized, the RDY bit must be cleared. 2. Make the following settings for message buffers not used by the application. * Clear the C0MCTRLm.RDY, C0MCTRLm.TRQ, and C0MCTRLm.DN bits to 0. * Clear the C0MCONFm.MA0 bit to 0. User's Manual U16541EJ5V1UD 865 CHAPTER 19 CAN CONTROLLER Figure 19-39 shows the processing for a receive message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 001B to 101B). Figure 19-39. Message Buffer Redefinition START Clear VALID bit. No RDY = 1? Yes Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY = 0? No Yes RSTAT = 0 or 1 Note VALID = 1?Note <R> No Yes Wait for a period of 4 CAN data Note 2 bits. <R> Set message buffers. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 END Notes 1. If redefinition is performed during a message reception, confirm that a message is being received because the RDY bit must be set after a message is completely received. <R> 2. 866 This 4-bit period may redefine the message buffer while a message is received and stored. User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-40 shows the processing for a transmit message buffer during transmission (MT2 to MT0 bits of C0MCONFm register = 000B). Figure 19-40. Message Buffer Redefinition During Transmission START Transmit abort process Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 =0 RDY bit = 0? No Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Transmit? No Yes Wait for a period of 1 CAN data bit. Set TRQ bit. Set TRQ bit = 1 = 1 Clear TRQ bit = 0 END User's Manual U16541EJ5V1UD 867 CHAPTER 19 CAN CONTROLLER Figure 19-41 shows the processing for a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 000B). Figure 19-41. Message Transmit Processing START No TRQ bit = 0? Yes Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0? No Yes Data frame Data frame or remote frame? Remote frame Set RTR bit of C0MDLCm register and C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Set TRQ bit. Set TRQ bit = 1 Clear TRQ bit = 0 END Cautions 1. The RDY bit should be set before the TRQ bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. 868 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-42 shows the processing for a transmit message buffer (C0MCONFm.MT2 to C0MCONFm.MT0 bits = 000B). Figure 19-42. ABT Message Transmit Processing START ABTTRG bit = 0? No Yes Clear RDY bit Set RDY bit = 0 = 0 Clear RDY bit = 1 RDY bit = 0? No Yes Set C0MDATAxm register. Set C0MDLCm register. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Set all ABT transmit messages? No Yes TSTAT bit = 0? No Yes Set ABTTRG bit. Set ABTTRG bit = 1 Clear ABTTRG bit = 0 END Caution The ABTTRG bit should be set to 1 after the TSTAT bit is cleared to 0. The checking of the TSTAT bit and the setting for the ABTTRG bit to 1 must be continuous. Remark This processing (message transmit processing with ABS) can only be applied to message buffers 0 to 7. For message buffers other than the ABT message buffers, see Figure 19-41. User's Manual U16541EJ5V1UD 869 CHAPTER 19 CAN CONTROLLER Figure 19-43. Transmission via Interrupt (Using C0LOPT register) Start Transmit completion interrupt servicing Read C0LOPT register. Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Set TRQ bit. Set TRQ bit = 1 Clear TRQ bit = 0 END Cautions 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. <R> Remark Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and transmit history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore recommended to cancel the CAN sleep mode transition request before executing transmission interrupt servicing. 870 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-44. Transmission via Interrupt (Using C0TGPT Register) START Transmit completion interrupt servicing Read C0TGPT register. No TOVF bit = 1? Yes Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 No RDY bit = 0? Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Yes Data frame Data frame or remote frame? Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set TRQ bit. Set RDY bit = 1 Clear RDY bit = 0 Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. THPM bit = 1? No Yes END Cautions 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. <R> Remarks 1. Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and transmit history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore recommended to cancel the CAN sleep mode transition request before executing transmission interrupt servicing. <R> 2. If the TOVF bit is set (1) again, the transmit history list contradicts. Therefore, scan all the transmit message buffers that have completed transmission. User's Manual U16541EJ5V1UD 871 CHAPTER 19 CAN CONTROLLER Figure 19-45. Transmission via Software Polling START No CINTS0 bit = 1? Yes Clear CINTS0 bit. Clear CINTS0 bit = 1 Read C0TGPT register. No TOVF bit = 1? Yes Clear TOVF bit. Clear TOVF bit = 1 Clear RDY bit. Set RDY bit = 0 Clear RDY bit = 1 RDY bit = 0? No Set RDY bit. Set RDY bit = 1 Clear RDY bit = 0 Yes Data frame Set C0MDATAxm, C0MDLCm registers. Clear RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Data frame or remote frame? Remote frame Set C0MDLCm register. Set RTR bit of C0MCONFm register. Set C0MIDLm and C0MIDHm registers. Set TRQ bit. Set TRQ bit = 1 Clear TRQ bit = 0 THPM bit = 1? No Yes END Cautions 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time. <R> Remarks 1. Check the MBON bit at the start and end of the polling routine to see if the message buffer and transmit history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. <R> 2. If the TOVF bit is set (1) again, the transmit history list contradicts. Therefore, scan all the transmit message buffers that have completed transmission. 872 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-46. Transmission Abort Processing (Other Than in Normal Operation Mode with ABT) START Clear TRQ bit. Set TRQ bit = 0 Clear TRQ bit = 1 Wait for a period of 11 CAN data bitsNote. <R> TSTAT bit = 0? No Yes Read C0LOPT register. Message buffer to be aborted matches C0LOPT register? No Yes Transmission successful Transmit abort processing successful. END <R> Note During a period of a total of 11 bits, 3 bits of interframe space and 8 bits of suspend transmission, the transmission request may have already been acknowledged by the protocol layer. Consequently, transmission may not be aborted but started even if the TRQ bit is cleared. Cautions 1. Execute transmission abort processing by clearing the TRQ bit, not the RDY bit. 2. Before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. The TSTAT bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. Do not execute a new transmission request that includes other message buffers while transmission abort processing is in progress. <R> 5. If data of the same message buffer are successively transmitted or if only one message buffer is used, judgments whether transmission has been successfully executed or failed may contradict. In such a case, make a judgment by using the history information of the C0TGPT register. User's Manual U16541EJ5V1UD 873 CHAPTER 19 CAN CONTROLLER Figure 19-47. Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) START Clear ABTTRG bit. Set ABTTRG bit = 0 = 0 Clear ABTTRG bit = 1 ABTTRG bit = 0? No Yes Clear TRQ bit. Set TRQ bit = 0 Clear TRQ bit = 1 Wait for a period of 11 CAN data Note bits . <R> TSTAT bit = 0? No Yes Read C0LOPT register. Message buffer to be aborted matches C0LOPT register? Yes Transmission successful No Transmit abort processing successful. END <R> <R> Note During a period of a total of 11 bits, 3 bits of interframe space and 8 bits of suspend transmission, the transmission request may have already been acknowledged by the protocol layer. Consequently, transmission may not be aborted but started even if the TRQ bit is cleared. Cautions 1. Execute transmission request abort processing by clearing the TRQ bit, not the RDY bit. 2. Before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. The TSTAT bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. Do not execute the new transmission request including in the other message buffers while transmission abort processing is in progress. 5. If data of the same message buffer are successively transmitted or if only one message buffer is used, judgments whether transmission has been successfully executed or failed may contradict. In such a case, make a judgment by using the history information of the C0TGPT register. 874 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-48 (a) shows processing that does not skip resuming the transmission of a message that was interrupted when the transmission of an ABT message buffer was aborted. Figure 19-48 (a). ABT Transmission Abort Processing (Normal Operation Mode with ABT) START No TSTAT bit = 0? Yes Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 No ABTTRG bit = 0? Yes Clear TRQ bit of message buffer whose transmission was aborted. Transmit abort Transmission start pointer clear? No Yes Set ABTCLR bit. Set ABTCLR bit = 1. END Cautions 1. Do not set any transmission requests while ABT transmission abort processing is in progress. 2. Make a CAN sleep mode/CAN stop mode transition request after the ABTTRG bit is cleared (after ABT mode is stopped) following the procedure shown in Figure 19-48 (a) or (b). When clearing a transmission request in an area other than the ABT area, follow the procedure shown in Figure 19-46. User's Manual U16541EJ5V1UD 875 CHAPTER 19 CAN CONTROLLER Figure 19-48 (b) shows the processing that does not skip resuming the transmission of a message that was interrupted when the transmission of an ABT message buffer was aborted. Figure 19-48 (b). ABT Transmission Request Abort Processing (Normal Operation Mode with ABT) START Clear TRQ bit of message buffer undergoing transmission. Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 No ABTTRG bit = 0? Yes Transmit abort Transmission start pointer clear? No Yes Set ABTCLR bit. Set ABTCLR bit = 1 END Cautions 1. Do not set any transmission requests while ABT transmission abort processing is in progress. 2. Make a CAN sleep mode/CAN stop mode request after the ABTTRG bit is cleared (after ABT mode is stopped) following the procedure shown in Figure 19-48 (a) or (b). When clearing a transmission request in an area other than the ABT area, follow the procedure shown in Figure 19-46. 876 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-49. Reception via Interrupt (Using C0LIPT Register) START Transmit abort Read C0LIPT register. Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 and MUC bit = 0Note No Yes Clear CINTS1 bit. Clear CINTS1 bit = 1 END Note Check the MUC and DN bits using one read access. <R> Remark Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and receive history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore recommended to cancel the CAN sleep mode transition request before executing reception interrupt servicing. User's Manual U16541EJ5V1UD 877 CHAPTER 19 CAN CONTROLLER <R> Figure 19-50. Reception via Interrupt (Using C0RGPT Register) START Receive completion interrupt Read C0RGPT register. No ROVF bit = 1? Yes Clear ROVF bit. Clear ROVF bit = 1 Yes RHPM bit = 1? No Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 AND MUC bit = 0Note No Yes Read illegal data. Read normal data. END Note Check the MUC and DN bits using one read access. Remarks 1. Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and receive history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is therefore recommended to cancel the CAN sleep mode transition request before executing reception interrupt servicing. 2. If the ROVF bit has been once set (1), the receive history list contradicts. Therefore, scan all the receive message buffers that have completed reception. 878 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER <R> Figure 19-51. Reception via Software Polling START No CINTS1 bit = 1? Yes Clear CINTS1 bit. Clear CINTS1 bit = 1 Read C0RGPT register No ROVF bit = 1? Yes Clear ROVF bit. Clear ROVF bit = 1 Yes RHPM bit = 1? No Clear DN bit. Clear DN bit = 1 Read C0MDATAxm, C0MDLCm, C0MIDLm, and C0MIDHm registers. DN bit = 0 AND MUC bit = 0Note No Yes Read illegal data. Read normal data. END Note Check the MUC and DN bits using one read access. Remarks 1. Check the MBON bit at the start and end of the polling routine to see if the message buffer and receive history register can be accessed, because a CAN sleep mode transition request which has been held pending may be under execution. If the MBON bit is cleared (0), stop the processing under execution. Re-execute the processing after the MBON bit is set (1) again. 2. If the ROVF bit has been once set (1), the receive history list contradicts. Therefore, scan all the receive message buffers that have completed reception. User's Manual U16541EJ5V1UD 879 CHAPTER 19 CAN CONTROLLER <R> Figure 19-52. Setting CAN Sleep Mode/Stop Mode START (when PSMODE[1:0] = 00B) Set PSMODE0 bit Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 PSMODE0 = 1? No Yes CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 PSMODE1 = 1? No No Request CAN sleep mode again? Yes CAN stop mode Yes Clear OPMODE. END No INIT mode? Yes Access to registers other than the C0CTRL and C0GMCTRL registers. Set C0CTRL register. (Set OPMODE.) Clear CINTS5 bit. Clear CINTS5 bit = 1 Caution To abort transmission before making a request for the CAN sleep mode, perform processing according to Figures 19-46 to 19-48. 880 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER <R> Figure 19-53. Clear CAN Sleep/Stop Mode START CAN stop mode Clear PSMODE1 bit. Set PSMODE1 bit = 0 Clear PSMODE1 bit = 1 CAN sleep mode (CAN bus clock not supplied) Releasing CAN sleep mode by CAN bus active After detect dominant edge PSMODE0 bit = 0 CINTS5 bit = 1 Releasing CAN sleep mode by user (CAN bus clock suppliedNote) Releasing CAN sleep mode by CAN bus active After detect dominant edge PSMODE0 bit = 0/1 CINTS5 bit = 1 Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 Clear CINTS5 bit. Clear CINTS5 bit = 1 Clear CINTS5 bit. Clear CINTS5 bit = 1 END Note "When the CAN clock is supplied" means a status in which the CAN sleep mode is set without the CPU standby mode set. * In STOP mode * In IDLE1, IDLE2 modes * When the main clock is stopped in the subclock operation mode or sub-IDLE mode User's Manual U16541EJ5V1UD 881 CHAPTER 19 CAN CONTROLLER Figure 19-54. Bus-off Recovery (Other Than in Normal Operation Mode with ABT) START No BOFF bit = 1? Yes Clear all TRQ bitsNote. <R> Set C0CTRL register. (Clear OPMODE bit.) Access to register other than C0CTRL and C0GMCTRL registers. Forced recovery from bus off? No Yes Set CCERC bit. Set CCERC bit = 1 Set C0CTRL register. (Set OPMODE bit.) Set C0CTRL register. (Set OPMODE bit.) Wait for recovery from bus off. END <R> Note To initialize the message buffer by clearing the RDY bit before starting the bus-off recovery sequence, clear all the TRQ bits. <R> Caution If a request to change the mode from the initialization mode to any operation mode is made to execute the bus-off recovery sequence again during a bus-off recovery sequence, the receive error counter (C0ERC.REC0 to REC6 bits) is cleared. It is therefore necessary to detect 11 contiguous recessive bits 128 times on the bus again. Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, singleshot mode, self-test mode 882 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-55. Bus-off Recovery (Normal Operation Mode with ABT) <R> START No BOFF bit = 1? Yes Clear ABTTRG bit. Set ABTTRG bit = 0 Clear ABTTRG bit = 1 Clear all TRQ bitNote Set C0CTRL register. (Clear OPMODE bit.) Access to register other than C0CTRL and C0GMCTRL registers. Forced recovery from bus off? No Yes Set CCERC register. Set CCERC bit = 1 Set C0CTRL register. (Set OPMODE.) Set C0CTRL register. (Set OPMODE bit.) Wait for recovery from bus off. END Note To initialize the message buffer by clearing the RDY bit before starting the bus-off recovery sequence, clear all the TRQ bits. Caution If a request to change the mode from the initialization mode to any operation mode is made to execute the bus-off recovery sequence again during a bus-off recovery sequence, the receive error counter (C0ERC.REC0 to REC6 bits) is cleared. It is therefore necessary to detect 11 contiguous recessive bits 128 times on the bus again. Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, singleshot mode, self-test mode User's Manual U16541EJ5V1UD 883 CHAPTER 19 CAN CONTROLLER <R> Figure 19-56. Normal Shutdown Process START INIT mode Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 Shutdown successful GOM bit = 0, EFSD bit = 0 END 884 User's Manual U16541EJ5V1UD CHAPTER 19 CAN CONTROLLER Figure 19-57. Forced Shutdown Process START Set EFSD bit. Set EFSD bit = 1 Must be a continuous write. Clear GOM bit. Set GOM bit = 0 Clear GOM bit = 1 No GOM bit = 0? Yes Shutdown successful GOM bit = 0, EFSD bit = 0 End Caution Do not read- or write-access any registers by software between setting the EFSD bit and clearing the GOM bit. User's Manual U16541EJ5V1UD 885 CHAPTER 19 CAN CONTROLLER Figure 19-58. Error Handling START Error interrupt No CINTS2 bit = 1? Yes Check CAN module state. (read C0INFO register) Clear CINTS2 bit. Clear CINTS2 bit = 1 CINTS3 bit = 1? No CINTS4 bit = 1? Yes Yes Check CAN protocol error state. (read C0LEC register) Clear CINTS4 bit. Clear CINTS4 bit = 1 Clear CINTS3 bit. Clear CINTS3 bit = 1 END 886 User's Manual U16541EJ5V1UD No CHAPTER 19 CAN CONTROLLER <R> Figure 19-59. Setting CPU Standby (from CAN Sleep Mode) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 No PSMODE0 bit = 1? Yes CAN sleep mode No MBON bit = 0? Yes CINTS5 bit 1? No Yes Set CPU standby mode. Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 END Clear CINTS5 bit. Clear CINTS5 bit = 1 Note Check if the CPU is in the CAN sleep mode before setting it to the standby mode. The CAN sleep mode may be released by wakeup after it is checked if the CPU is in the CAN sleep mode and before the CPU is set in the standby mode. User's Manual U16541EJ5V1UD 887 CHAPTER 19 CAN CONTROLLER <R> Figure 19-60. Setting CPU Standby (from CAN Stop Mode) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? No Yes CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 No Clear PSMODE0 bit. Set PSMODE0 bit = 0 Clear PSMODE0 bit = 1 PSMODE1 bit = 1? Yes CAN stop mode Clear CINTS5 bitNote Clear CINTS5 bit = 1 MBON bit = 1? No Yes Set CPU standby mode. END Note During wakeup interrupts Caution The CAN stop mode can only be released by writing 01 to the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits. It cannot be released by changing the CAN bus. 888 User's Manual U16541EJ5V1UD CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) <R> The V850ES/SG2 and V850ES/SG2-H include a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM or external memory). 20.1 Features * 4 independent DMA channels * Transfer unit: 8/16 bits * Maximum transfer count: 65,536 (216) * Transfer type: Two-cycle transfer * Transfer mode: Single transfer mode * Transfer requests * Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) or interrupts from external input pin * Requests by software trigger * Transfer targets * Internal RAM Peripheral I/O * Peripheral I/O Peripheral I/O * Internal RAM External memory * External memory Peripheral I/O * External memory External memory User's Manual U16541EJ5V1UD 889 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.2 Configuration On-chip peripheral I/O Internal RAM Internal bus On-chip peripheral I/O bus CPU Data control Address control DMA source address register n (DSAnH/DSAnL) DMA destination address register n (DDAnH/DDAnL) Count control DMA transfer count register n (DBCn) DMA channel control register n (DCHCn) DMA addressing control register n (DADCn) Channel control DMA trigger factor register n (DTFRn) DMAC Bus interface <R> External bus External I/O Remark 890 External RAM External ROM n = 0 to 3 User's Manual U16541EJ5V1UD V850ES/SG2, V850ES/SG2-H CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DSA0H FFFFF082H, DSA1H FFFFF08AH, DSA2H FFFFF092H, DSA3H FFFFF09AH, DSA0L FFFFF080H, DSA1L FFFFF088H, DSA2L FFFFF090H, DSA3L FFFFF098H DSAnH (n = 0 to 3) DSAnL (n = 0 to 3) IR 0 0 0 0 0 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 IR Specification of DMA transfer source 0 External memory or on-chip peripheral I/O 1 Internal RAM SA25 to SA16 Set the address (A25 to A16) of the DMA transfer source (default value is undefined). During DMA transfer, the next DMA transfer source address is held. When DMA transfer is completed, the DMA address set first is held. SA15 to SA0 Set the address (A15 to A0) of the DMA transfer source (default value is undefined). During DMA transfer, the next DMA transfer source address is held. When DMA transfer is completed, the DMA address set first is held. Cautions 1. Be sure to clear bits 14 to 10 of the DSAnH register to 0. 2. Set the DSAnH and DSAnL registers at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. When the value of the DSAn register is read, two 16-bit registers, DSAnH and DSAnL, are read. If reading and updating conflict, the value being updated may be read (see 20.13 Cautions). 4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. User's Manual U16541EJ5V1UD 891 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DDAnH and DDAnL. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DDA0H FFFFF086H, DDA1H FFFFF08EH, DA2H FFFFF096H, DDA3H FFFFF09EH, DDA0L FFFFF084H, DDA1L FFFFF08CH, DDA2L FFFFF094H, DDA3L FFFFF09CH DDAnH (n = 0 to 3) DDAnL (n = 0 to 3) IR 0 0 0 0 0 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 IR Specification of DMA transfer destination 0 External memory or on-chip peripheral I/O 1 Internal RAM DA25 to DA16 Set an address (A25 to A16) of DMA transfer destination (default value is undefined). During DMA transfer, the next DMA transfer destination address is held. When DMA transfer is completed, the DMA transfer source address set first is held. DA15 to DA0 Set an address (A15 to A0) of DMA transfer destination (default value is undefined). During DMA transfer, the next DMA transfer destination address is held. When DMA transfer is completed, the DMA transfer source address set first is held. Cautions 1. Be sure to clear bits 14 to 10 of the DDAnH register to 0. 2. Set the DDAnH and DDAnL registers at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. When the value of the DDAn register is read, two 16-bit registers, DDAnH and DDAnL, are read. If reading and updating conflict, a value being updated may be read (see 20.13 Cautions). 4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. 892 User's Manual U16541EJ5V1UD CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (3) DMA byte count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3). These registers hold the remaining transfer count during DMA transfer. These registers are decremented by 1 per one transfer regardless of the transfer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. These registers can be read or written in 16-bit units. After reset: Undefined R/W Address: DBC0 FFFFF0C0H, DBC1 FFFFF0C2H, DBC2 FFFFF0C4H, DBC3 FFFFF0C6H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBCn BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 (n = 0 to 3) Byte transfer count setting or remaining byte transfer count during DMA transfer BC15 to BC0 0000H Byte transfer count 1 or remaining byte transfer count 0001H Byte transfer count 2 or remaining byte transfer count : FFFFH : Byte transfer count 65,536 (216) or remaining byte transfer count The number of transfer data set first is held when DMA transfer is complete. Cautions 1. Set the DBCn register at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 2. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before starting DMA transfer. If these registers are not set, the operation when DMA transfer is started is not guaranteed. User's Manual U16541EJ5V1UD 893 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers can be read or written in 16-bit units. Reset sets these registers to 0000H. After reset: 0000H R/W Address: DADC0 FFFFF0D0H, DADC1 FFFFF0D2H, DADC2 FFFFF0D4H, DADC3 FFFFF0D6H DADCn 15 14 13 12 11 10 9 8 0 DS0 0 0 0 0 0 0 (n = 0 to 3) 7 6 5 4 3 2 1 0 SAD1 SAD0 DAD1 DAD0 0 0 0 0 Setting of transfer data size DS0 0 8 bits 1 16 bits SAD1 SAD0 Setting of count direction of the transfer source address 0 0 Increment 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited DAD1 DAD0 0 0 Increment 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited Setting of count direction of the destination address Cautions 1. Be sure to clear bits 15, 13 to 8, and 3 to 0 of the DADCn register to 0. 2. Set the DADCn register at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer 3. The DS0 bit specifies the size of the transfer data, and does not control bus sizing. If 8-bit data (DS0 bit = 0) is set, therefore, the lower data bus is not always used. 4. If the transfer data size is set to 16 bits (DS0 bit = 1), transfer cannot be started from an odd address. Transfer is always started from an address with the first bit of the lower address aligned to 0. 5. If DMA transfer is executed on an on-chip peripheral I/O register (as the transfer source or destination), be sure to specify the same transfer size as the register size. For example, to execute DMA transfer on an 8-bit register, be sure to specify 8-bit transfer. 894 User's Manual U16541EJ5V1UD CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n. These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are write-only. If bit 1 or 2 is read, the read value is always 0) Reset sets these registers to 00H. After reset: 00H R/W Address: DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H, DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H <7> DCHCn TCn Note 1 6 0 5 0 4 0 3 0 <2> INITn Note 2 <1> STGn Note 2 <0> Enn (n = 0 to 3) TCnNote 1 Status flag indicates whether DMA transfer through DMA channel n has completed or not 0 DMA transfer had not completed. 1 DMA transfer had completed. It is set to 1 on the last DMA transfer and cleared to 0 when it is read. INITnNote 2 If the INITn bit is set to 1 with DMA transfer disabled (Enn bit = 0), the DMA transfer status can be initialized. When re-setting the DMA transfer status (re-setting the DDAnH, DDAnL, DSAnH, DSAnL, DBCn, and DADCn registers) before DMA transfer is completed (before the TCn bit is set to 1), be sure to initialize the DMA channel. When initializing the DMA controller, however, be sure to observe the procedure described in 20.13 Cautions. STGnNote 2 This is a software startup trigger of DMA transfer. If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn bit = 1), DMA transfer is started. Enn Setting of whether DMA transfer through DMA channel n is to be enabled or disabled 0 DMA transfer disabled 1 DMA transfer enabled DMA transfer is enabled when the Enn bit is set to 1. When DMA transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. To abort DMA transfer, clear the Enn bit to 0 by software. To resume, set the Enn bit to 1 again. When aborting or resuming DMA transfer, however, be sure to observe the procedure described in 20.13 Cautions. Notes 1. The TCn bit is read-only. 2. The INITn and STGn bits are write-only. Cautions 1. Be sure to clear bits 6 to 3 of the DCHCn register to 0. 2. When DMA transfer is completed (when a terminal count is generated), the Enn bit is cleared to 0 and then the TCn bit is set to 1. If the DCHCn register is read while its bits are being updated, a value indicating "transfer not completed and transfer is disabled" (TCn bit = 0 and Enn bit = 0) may be read. User's Manual U16541EJ5V1UD 895 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O. The interrupt request signals set by these registers serve as DMA transfer start factors. These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units. Reset sets these registers to 00H. (1/2) After reset: 00H R/W Address: DTFR0 FFFFF810H, DTFR1 FFFFF812H, DTFR2 FFFFF814H, DTFR3 FFFFF816H DTFRn <7> 6 5 4 3 2 1 0 DFn 0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 (n = 0 to 3) DFnNote <R> DMA transfer request status flag 0 No DMA transfer request 1 DMA transfer request Note Do not set the DFn bit to "1" by software. Write 0 to this bit to clear a DMA transfer request if an interrupt that is specified as the cause of starting DMA transfer occurs while DMA transfer is disabled. Caution Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled (DCHCn.Enn bit = 0). * Period from after reset to start of first DMA transfer * Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer * Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next DMA transfer Remark 896 For the IFCn5 to IFCn0 bits, see Table 20-1 DMA Start Factors. User's Manual U16541EJ5V1UD CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (2/2) <R> Cautions 2. Be sure to follow the steps below when changing the DTFRn register settings. [V850ES/SG2] * When the values to be set to bits IFCn5 to IFCn0 are not set to bits IFCm5 to IFCm0 of another channel (n = 0 to 3, m = 0 to 3, n m) <1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0). <2> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the settings in the 8-bit manipulation.) <3> Confirm that DFn bit = 0. (Stop the interrupt generation source operation beforehand.) <4> Enable the DMAn operation (Enn bit = 1). * When the values to be set to bits IFCn5 to IFCn0 are set to bits IFCm5 to IFCm0 of another channel (n = 0 to 3, m = 0 to 3, n m) <1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0). <2> Stop the DMAm operation of the channel where the same values are set to bits IFCm5 to IFCm0 as the values to be used to rewrite bits IFCn5 to IFCn0 (DCHCm.Emm bit = 0). <3> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the settings in the 8-bit manipulation.) <4> Confirm that bits DFn and DFm = 0. (Stop the interrupt generation source operation beforehand.) <5> Enable the DMAn operation (bits Enn and Emm = 1). [V850ES/SG2-H] * To change the setting of the DTFRn register, be sure to stop DMAm of the channel with a priority lower than that of DMAn of the channel to be rewritten. <1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0). <2> Stop DMAm of the channel with a priority lower than that of DMAn of the channel to be rewritten. <3> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the settings in the 8-bit manipulation.) <4> Confirm that bits DFn and DFm = 0. (Stop the interrupt generation source operation beforehand.) <5> Enable the DMAn operation (bits Enn and Emm = 1). 3. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or sub-IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1). 4. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA transfer is enabled or disabled. If DMA is enabled in this status, DMA transfer is immediately started. Remark For the IFCn5 to IFCn0 bits, see Table 20-1 DMA Start Factors. User's Manual U16541EJ5V1UD 897 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) Table 20-1. DMA Start Factors (1/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 0 0 0 0 0 0 DMA request by interrupt disabled 0 0 0 0 0 1 INTP0 0 0 0 0 1 0 INTP1 0 0 0 0 1 1 INTP2 0 0 0 1 0 0 INTP3 0 0 0 1 0 1 INTP4 0 0 0 1 1 0 INTP5 0 0 0 1 1 1 INTP6 0 0 1 0 0 0 INTP7 0 0 1 0 0 1 INTTQ0OV 0 0 1 0 1 0 INTTQ0CC0 0 0 1 0 1 1 INTTQ0CC1 0 0 1 1 0 0 INTTQ0CC2 0 0 1 1 0 1 INTTQ0CC3 0 0 1 1 1 0 INTTP0OV 0 0 1 1 1 1 INTTP0CC0 0 1 0 0 0 0 INTTP0CC1 0 1 0 0 0 1 INTTP1OV 0 1 0 0 1 0 INTTP1CC0 0 1 0 0 1 1 INTTP1CC1 0 1 0 1 0 0 INTTP2OV 0 1 0 1 0 1 INTTP2CC0 0 1 0 1 1 0 INTTP2CC1 0 1 0 1 1 1 INTTP3CC0 0 1 1 0 0 0 INTTP3CC1 0 1 1 0 0 1 INTTP4CC0 0 1 1 0 1 0 INTTP4CC1 0 1 1 0 1 1 INTTP5CC0 0 1 1 1 0 0 INTTP5CC1 0 1 1 1 0 1 INTTM0EQ0 0 1 1 1 1 0 INTCB0R/INTIIC1 0 1 1 1 1 1 INTCB0T 1 0 0 0 0 0 INTCB1R 1 0 0 0 0 1 INTCB1T 1 0 0 0 1 0 INTCB2R 1 0 0 0 1 1 INTCB2T 1 0 0 1 0 0 INTCB3R Note 1 0 0 1 0 1 INTCB3T 1 0 0 1 1 0 INTUA0R/INTCB4R 1 0 0 1 1 1 INTUA0T/INTCB4T 1 0 1 0 0 0 INTUA1R/INTIIC2 1 0 1 0 0 1 INTUA1T 1 0 1 0 1 0 INTUA2R/INTIIC0 Note I2C bus version (Y products) only Remark 898 Interrupt Source n = 0 to 3 User's Manual U16541EJ5V1UD Note Note CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) Table 20-1. DMA Start Factors (2/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 1 0 1 0 1 1 INTUA2T Interrupt Source 1 0 1 1 0 0 INTAD 1 0 1 1 0 1 INTKR 1 0 1 1 1 0 INTERR Note 1 0 1 1 1 1 INTSTA 1 1 0 0 0 0 INTIE1 Other than above Note Note Setting prohibited Note IEBus controller version only Remark n = 0 to 3 20.4 Transfer Targets Table 20-2 shows the relationship between the transfer targets (: Transfer enabled, x: Transfer disabled). Table 20-2. Relationship Between Transfer Targets Transfer Destination Internal ROM On-Chip Internal RAM External Memory Source Peripheral I/O Caution On-chip peripheral I/O x Internal RAM x x External memory x Internal ROM x x x x The operation is not guaranteed for combinations of transfer destination and source marked with "x" in Table 20-2. 20.5 Transfer Modes Single transfer is supported as the transfer mode. In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence. If a new transfer request of the same channel and a transfer request of another channel with a lower priority are generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released to the CPU (the new transfer request of the same channel is ignored in the transfer cycle). User's Manual U16541EJ5V1UD 899 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.6 Transfer Types As a transfer type, the 2-cycle transfer is supported. In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In the write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination. An idle cycle of one clock is always inserted between a read cycle and a write cycle. If the data bus width differs between the transfer source and destination for DMA transfer of two cycles, the operation is performed as follows. <16-bit data transfer> <1> Transfer from 32-bit bus 16-bit bus A read cycle (the higher 16 bits are in a high-impedance state) is generated, followed by generation of a write cycle (16 bits). <2> Transfer from 16-/32-bit bus to 8-bit bus A 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice. <3> Transfer from 8-bit bus to 16-/32-bit bus An 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> Transfer between 16-bit bus and 32-bit bus A 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once. For DMA transfer executed to an on-chip peripheral I/O register (transfer source/destination), be sure to specify the same transfer size as the register size. For example, for DMA transfer to an 8-bit register, be sure to specify byte (8bit) transfer. Remark The bus width of each transfer target (transfer source/destination) is as follows. * On-chip peripheral I/O: 16-bit bus width 900 * Internal RAM: 32-bit bus width * External memory: 8-bit or 16-bit bus width User's Manual U16541EJ5V1UD CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 The priorities are checked for every transfer cycle. 20.8 Time Related to DMA Transfer The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are shown below. Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1Note 1 + Transfer destination memory access (<2>) DMA Cycle Minimum Number of Execution Clocks Note 2 <1> DMA request response time 4 clocks (MIN.) + Noise elimination time <2> Memory access External memory access Depends on connected memory. Internal RAM access 2 clocks Peripheral I/O register access 3 clocks + Number of wait cycles specified by VSWC register Note 3 Note 4 Notes 1. One clock is always inserted between a read cycle and a write cycle in DMA transfer. 2. If an external interrupt (INTPn) is specified as the trigger to start DMA transfer, noise elimination time is added (n = 0 to 7). 3. Two clocks are required for a DMA cycle. 4. More wait cycles are necessary for accessing a specific peripheral I/O register (for details, see 3.4.9 (2)). User's Manual U16541EJ5V1UD 901 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the STGn bit is set to 1 while the DCHCn.TCn bit = 0 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started. To request the next DMA transfer cycle immediately after that, confirm, by using the DBCn register, that the preceding DMA transfer cycle has been completed, and set the STGn bit to 1 again (n = 0 to 3). TCn bit = 0, Enn bit = 1 STGn bit = 1 ... Starts the first DMA transfer. Confirm that the contents of the DBCn register have been updated. STGn bit = 1 ... Starts the second DMA transfer. : Generation of terminal count ... Enn bit = 0, TCn bit = 1, and INTDMAn signal is generated. (2) Request by on-chip peripheral I/O If an interrupt request is generated from the on-chip peripheral I/O set by the DTFRn register when the DCHCn.TCn bit = 0 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started. Cautions 1. Two start factors (software trigger and hardware trigger) cannot be used for one DMA channel. If two start factors are simultaneously generated for one DMA channel, only one of them is valid. The start factor that is valid cannot be identified. 2. A new transfer request that is generated after the preceding DMA transfer request was generated or in the preceding DMA transfer cycle is ignored (cleared). 3. The transfer request interval of the same DMA channel varies depending on the setting of bus wait in the DMA transfer cycle, the start status of the other channels, or the external bus hold request. In particular, as described in Caution 2, a new transfer request that is generated for the same channel before the DMA transfer cycle or during the DMA transfer cycle is ignored. Therefore, the transfer request intervals for the same DMA channel must be sufficiently separated by the system. When the software trigger is used, completion of the DMA transfer cycle that was generated before can be checked by updating the DBCn register. 902 User's Manual U16541EJ5V1UD CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.10 DMA Abort Factors DMA transfer is aborted if a bus hold occurs. The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal memory/on-chip peripheral I/O. When the bus hold is cleared, DMA transfer is resumed. 20.11 End of DMA Transfer When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn bit is cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the interrupt controller (INTC) (n = 0 to 3). <R> The V850ES/SG2 and V850ES/SG2-H do not output a terminal count signal to an external device. Therefore, confirm completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit. 20.12 Operation Timing Figures 20-1 to 20-4 show DMA operation timing. User's Manual U16541EJ5V1UD 903 904 Figure 20-1. Priority of DMA (1) System clock DMA0 transfer request DMA1 transfer request DF0 bit User's Manual U16541EJ5V1UD DF1 bit DF2 bit DMA transfer Preparation for transfer Read Write End processing Preparation for transfer Read Idle Mode of processing CPU processing DMA0 processing Write End processing Preparation for transfer Read Idle CPU processing Remarks 1. Transfer in the order of DMA0 DMA1 DMA2 2. In the case of transfer between external memory spaces (multiplexed bus, no wait) DMA1 processing CPU processing DMA2 processing CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) DMA2 transfer request Figure 20-2. Priority of DMA (2) System clock DMA0 transfer request DMA1 transfer request DF0 bit User's Manual U16541EJ5V1UD DF1 bit DF2 bit DMA transfer Preparation for transfer Read Write End processing Preparation for transfer Idle Mode of processing CPU processing DMA0 processing Read Write End processing Preparation for transfer Read Idle CPU processing Remarks 1. Transfer in the order of DMA0 DMA1 DMA0 (DMA2 is held pending.) 2. In the case of transfer between external memory spaces (multiplexed bus, no wait) DMA1 processing CPU processing DMA0 processing CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) DMA2 transfer request 905 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) Figure 20-3. Period in Which DMA Transfer Request Is Ignored (1) System clock DMAn transfer requestNote 1 DFn bit Mode of processing DMA transfer Note 2 CPU processing Preparation for transfer Note 2 Note 2 DMA0 processing Read cycle Write cycle CPU processing End processing Idle Transfer request generated after this can be acknowledged Notes 1. Interrupt from on-chip peripheral I/O, or software trigger (STGn bit) 2. New DMA request of the same channel is ignored between when the first request is generated and the end processing is complete. Remark 906 In the case of transfer between external memory spaces (multiplexed bus, no wait) User's Manual U16541EJ5V1UD Figure 20-4. Period in Which DMA Transfer Request Is Ignored (2) System clock DMA0 transfer request DMA1 transfer request DF0 bit User's Manual U16541EJ5V1UD DF1 bit DF2 bit Preparation for transfer DMA transfer Write Read End processing Preparation for transfer Idle Mode of processing CPU processing <1> DMA0 processing <2> Read Write End processing Preparation for transfer Read Idle CPU processing <3> DMA1 processing CPU processing <4> <1> DMA0 transfer request <2> New DMA0 transfer request is generated during DMA0 transfer. A DMA transfer request of the same channel is ignored during DMA transfer. <3> Requests for DMA0 and DMA1 are generated at the same time. DMA0 request is ignored (a DMA transfer request of the same channel during transfer is ignored). DMA1 request is acknowledged. <4> Requests for DMA0, DMA1, and DMA2 are generated at the same time. DMA1 request is ignored (a DMA transfer request of the same channel during transfer is ignored). DMA0 request is acknowledged according to priority. DMA2 request is held pending (transfer of DMA2 occurs next). DMA0 processing CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) DMA2 transfer request 907 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) 20.13 Cautions (1) Caution for VSWC register When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the VSWC register. When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register, the operation is not correctly performed (for details of the VSWC register, see 3.4.9 (1) (a) System wait control register (VSWC)). (2) Caution for DMA transfer executed on internal RAM When executing the following instructions located in the internal RAM, do not execute a DMA transfer that transfers data to/from the internal RAM (transfer source/destination), because the CPU may not operate correctly afterward. * Bit manipulation instruction located in internal RAM (SET1, CLR1, or NOT1) * Data access instruction to misaligned address located in internal RAM Conversely, when executing a DMA transfer to transfer data to/from the internal RAM (transfer source/destination), do not execute the above two instructions. (3) Caution for reading DCHCn.TCn bit (n = 0 to 3) The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific timing. To accurately clear the TCn bit, add the following processing. (a) When waiting for completion of DMA transfer by polling TCn bit Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then read the TCn bit three more times. (b) When reading TCn bit in interrupt servicing routine Execute reading the TCn bit three times. 908 User's Manual U16541EJ5V1UD CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not be initialized. To accurately initialize the channel, execute either of the following two procedures. (a) Temporarily stop transfer of all DMA channels Initialize the channel executing DMA transfer using the procedure in <1> to <7> below. Note, however, that TCn bit is cleared to 0 when step <5> is executed. Make sure that the other processing programs do not expect that the TCn bit is 1. <1> Disable interrupts (DI). <2> Read the DCHCn.Enn bit of DMA channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> Clear the Enn bit of the DMA channels used (including the channel to be forcibly terminated) to 0. To clear the Enn bit of the last DMA channel, execute the clear instruction twice. If the target of DMA transfer (transfer source/destination) is the internal RAM, execute the instruction three times. Example: Execute instructions in the following order if channels 0, 1, and 2 are used (if the target of transfer is not the internal RAM). * Clear DCHC0.E00 bit to 0. * Clear DCHC1.E11 bit to 0. * Clear DCHC2.E22 bit to 0. * Clear DCHC2.E22 bit to 0 again. <4> Set the INITn bit of the channel to be forcibly terminated to 1. <5> Read the TCn bit of each channel not to be forcibly terminated. If both the TCn bit and the Enn bit read in <2> are 1 (logical product (AND) is 1), clear the saved Enn bit to 0. <6> After the operation in <5>, write the Enn bit value to the DCHCn register. <7> Enable interrupts (EI). Caution Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the channels whose DMA transfer has been normally completed between <2> and <3>. User's Manual U16541EJ5V1UD 909 CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) (b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly <1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral I/O). <2> Check that the DMA transfer request of the channel to be forcibly terminated is not held pending, by using the DTFRn.DFn bit. If a DMA transfer request is held pending, wait until execution of the pending request is completed. <3> When it has been confirmed that the DMA request of the channel to be forcibly terminated is not held pending, clear the Enn bit to 0. <4> Again, clear the Enn bit of the channel to be forcibly terminated. If the target of transfer for the channel to be forcibly terminated (transfer source/destination) is the internal RAM, execute this operation once more. <5> Copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose register. <6> Set the INITn bit of the channel to be forcibly terminated to 1. <7> Read the value of the DBCn register of the channel to be forcibly terminated, and compare it with the value copied in <5>. If the two values do not match, repeat operations <6> and <7>. Remarks 1. When the value of the DBCn register is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. If not, the remaining number of transfers is read. 2. Note that method (b) may take a long time if the application frequently uses DMA transfer for a channel other than the DMA channel to be forcibly terminated. (5) Procedure of temporarily stopping DMA transfer (clearing Enn bit) Stop and resume the DMA transfer under execution using the following procedure. <1> Suppress a transfer request from the DMA request source (stop the operation of the on-chip peripheral I/O). <2> Check the DMA transfer request is not held pending, by using the DFn bit (check if the DFn bit = 0). If a request is pending, wait until execution of the pending DMA transfer request is completed. <3> If it has been confirmed that no DMA transfer request is held pending, clear the Enn bit to 0 (this operation stops DMA transfer). <4> Set the Enn bit to 1 to resume DMA transfer. <5> Resume the operation of the DMA request source that has been stopped (start the operation of the onchip peripheral I/O). (6) Memory boundary The operation is not guaranteed if the address of the transfer source or destination exceeds the area of the DMA target (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer. (7) Transferring misaligned data DMA transfer of misaligned data with a 16-bit bus width is not supported. If an odd address is specified as the transfer source or destination, the least significant bit of the address is forcibly assumed to be 0. 910 User's Manual U16541EJ5V1UD CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) <R> (8) Bus arbitration for CPU Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU. However, the CPU can access the internal ROM and internal RAM for which DMA transfer is not being executed. * The CPU can access the internal ROM and internal RAM when DMA transfer is being executed between the external memory and on-chip peripheral I/O. * The CPU can access the internal ROM when DMA transfer is being executed between the on-chip peripheral I/O and internal RAM. (9) Registers/bits that must not be rewritten during DMA operation Set the following registers at the following timing when a DMA operation is not under execution. [Registers] * DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers * DTFRn.IFCn5 to DTFRn.IFCn0 bits [Timing of setting] * Period from after reset to start of the first DMA transfer * Time after channel initialization to start of DMA transfer * Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer (10) Be sure to set the following register bits to 0. * Bits 14 to 10 of DSAnH register * Bits 14 to 10 of DDAnH register * Bits 15, 13 to 8, and 3 to 0 of DADCn register * Bits 6 to 3 of DCHCn register <R> (11) DMA start factor Care must be exercised when setting the same start trigger for multiple DMA channels. If DMA transfers via such DMA channels are activated, the DMA channel with a lower priority may be acknowledged prior to the DMA channel with a higher priority. (12) Read values of DSAn and DDAn registers Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3). For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00), the value of the DSAn register differs as follows, depending on whether DMA transfer is executed immediately after the DSAnH register is read. (a) If DMA transfer does not occur while DSAn register is read <1> Read value of DSAnH register: DSAnH = 0000H <2> Read value of DSAnL register: DSAnL = FFFFH (b) If DMA transfer occurs while DSAn register is read <1> Read value of DSAnH register: DSAnH = 0000H <2> Occurrence of DMA transfer <3> Incrementing DSAn register: DSAn = 00100000H <4> Read value of DSAnL register: DSAnL = 0000H User's Manual U16541EJ5V1UD 911 CHAPTER 21 CRC FUNCTION 21.1 Functions * CRC operation circuit for detection of data block errors * Generation of 16-bit CRC code using a CRC-CCITT (X16 + X12 + X5 + 1) generation polynomial for blocks of data of any length in 8-bit units * CRC code is set to the CRC data register each time 1-byte data is transferred to the CRCIN register, after the initial value is set to the CRCD register. 21.2 Configuration The CRC function includes the following hardware. Table 21-1. CRC Configuration Item Configuration Control registers CRC input register (CRCIN) CRC data register (CRCD) Figure 21-1. Block Diagram of CRC Register Internal bus CRC input register (CRCIN) (8 bits) CRC code generator CRC data register (CRCD) (16 bits) Internal bus 912 User's Manual U16541EJ5V1UD CHAPTER 21 CRC FUNCTION 21.3 Registers (1) CRC input register (CRCIN) The CRCIN register is an 8-bit register for setting data. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H R/W Address: FFFFF310H 6 7 5 4 3 2 1 0 CRCIN (2) CRC data register (CRCD) The CRCD register is a 16-bit register that stores the CRC-CCITT operation results. This register can be read or written in 16-bit units. Reset sets this register to 0000H. Caution Accessing the CRCD register is prohibited in the following statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. * When the CPU operates with the subclock and the main clock oscillation is stopped * When the CPU operates with the internal oscillation clock After reset: 0000H 15 14 R/W 13 12 Address: FFFFF312H 11 10 9 8 7 6 5 4 3 2 1 0 CRCD User's Manual U16541EJ5V1UD 913 CHAPTER 21 CRC FUNCTION 21.4 Operation An example of the CRC operation circuit is shown below. Figure 21-2. CRC Operation Circuit Operation Example (LSB First) b7 b0 (1) Setting of CRCIN = 01H b15 b0 (2) CRCD register read 1189H CRC code is stored 16 12 The code when 01H is sent LSB first is (1000 0000). Therefore, the CRC code from generation polynomial X + X + X5 + 1 becomes the remainder when (1000 0000) X16 is divided by (1 0001 0000 0010 0001) using the modulo-2 operation formula. The modulo-2 operation is performed based on the following formula. 0+0=0 0+1=1 1+0=1 1+1=0 -1=1 LSB 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 0000 0000 0000 0001 0001 1000 0000 1 1000 0000 1000 1000 0000 MSB 0 1 1000 LSB MSB 9 8 1 1 Therefore, the CRC code becomes 1001 0001 1000 1000 . Since LSB first is used, this corresponds to 1189H in hexadecimal notation. 914 User's Manual U16541EJ5V1UD CHAPTER 21 CRC FUNCTION 21.5 Usage How to use the CRC logic circuit is described below. Figure 21-3. CRC Operation Flow Start Write of 0000H to CRCD register Yes Input data exists? No CRCD register read CRCIN register write End [Basic usage method] <1> Write 0000H to the CRCD register. <2> Write the required quantity of data to the CRCIN register. <3> Read the CRCD register. User's Manual U16541EJ5V1UD 915 CHAPTER 21 CRC FUNCTION Communication errors can easily be detected if the CRC code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. The following is an illustration using the transmission of 12345678H (0001 0010 0011 0100 0101 0110 0111 1000B) LSB-first as an example. Figure 21-4. CRC Transmission Example 78 56 34 12 Transmit/receive data (12345678H) F6 08 CRC code (08F6H) Setting procedure on transmitting side <1> Write the initial value 0000H to the CRCD register. <2> Write the 1 byte of data to be transmitted first to the transmit buffer register. (At this time, also write the same data to the CRCIN register.) <3> When transmitting several bytes of data, write the same data to the CRCIN register each time transmit data is written to the transmit buffer register. <4> After all the data has been transmitted, write the contents of the CRCD register (CRC code) to the transmit buffer register and transmit them. (Since this is LSB first, transmit the data starting from the lower bytes, then the higher bytes.) Setting procedure on receiving side <1> Write the initial value 0000H to the CRCD register. <2> When reception of the first 1 byte of data is complete, write that receive data to the CRCIN register. <3> If receiving several bytes of data, write the receive data to the CRCIN register upon every reception completion. (In the case of normal reception, when all the receive data has been written to the CRCIN register, the contents of the CRCD register on the receiving side and the contents of the CRCD register on the transmitting side are the same.) <4> Next, the CRC code is transmitted from the transmitting side, so write this data to the CRCIN register similarly to receive data. <5> When reception of all the data, including the CRC code, has been completed, reception was normal if the contents of the CRCD register are 0000H. If the contents of the CRCD register are other than 0000H, this indicates a communication error, so transmit a resend request to the transmitting side. 916 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION <R> The V850ES/SG2 and V850ES/SG2-H are provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 56 to 61 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. <R> The V850ES/SG2 and V850ES/SG2-H can process interrupt request signals from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 22.1 Features Interrupts * Non-maskable interrupts: 2 sources <R> * Maskable interrupts: External: 8, Internal: 46/47/50/51 sources (see Table 1-1) * 8 levels of programmable priorities (maskable interrupts) * Multiple interrupt control according to priority * Masks can be specified for each maskable interrupt request. * Noise elimination, edge detection, and valid edge specification for external interrupt request signals. Exceptions * Software exceptions: 32 sources * Exception trap: 2 sources (illegal opcode exception, debug trap) Interrupt/exception sources are listed in Table 22-1. Table 22-1. Interrupt Source List (1/4) Type Classification Default Name Trigger Generating Exception Handler Restored Unit Code Address PC Priority Interrupt Control Register Reset Interrupt - RESET RESET pin input RESET 0000H 00000000H Undefined - 0010H 00000010H nextPC - Reset input by internal source Non- Interrupt maskable Software Exception - NMI NMI pin valid edge input Pin - INTWDT2 WDT2 overflow WDT2 - TRAP0nNote 2 TRAP instruction 0020H 00000020H Note 1 - - 004nHNote 2 00000040H nextPC - Note 2 exception - TRAP1n TRAP instruction - 005nH 00000050H nextPC - Exception Exception - ILGOP/ Illegal opcode/ - 0060H 00000060H nextPC - DBG0 DBTRAP instruction trap Note 2 Notes 1. For the restoring in the case of INTWDT2, see 22.2.2 (2) INTWDT2 signal. 2. n = 0 to FH User's Manual U16541EJ5V1UD 917 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-1. Interrupt Source List (2/4) Type Classification Default Name Trigger Generating Exception Handler Restored Unit Code Address PC Priority Interrupt Control Register <R> Maskable Interrupt 0 INTLVINote Low voltage detection POCLVI 0080H 00000080H nextPC LVIIC 1 INTP0 External interrupt pin input Pin 0090H 00000090H nextPC PIC0 Pin 00A0H 000000A0H nextPC PIC1 Pin 00B0H 000000B0H nextPC PIC2 Pin 00C0H 000000C0H nextPC PIC3 Pin 00D0H 000000D0H nextPC PIC4 Pin 00E0H 000000E0H nextPC PIC5 Pin 00F0H 000000F0H nextPC PIC6 Pin 0100H 00000100H nextPC PIC7 edge detection (INTP0) 2 INTP1 External interrupt pin input edge detection (INTP1) 3 INTP2 External interrupt pin input edge detection (INTP2) 4 INTP3 External interrupt pin input edge detection (INTP3) 5 INTP4 External interrupt pin input edge detection (INTP4) 6 INTP5 External interrupt pin input edge detection (INTP5) 7 INTP6 External interrupt pin input edge detection (INTP6) 8 INTP7 External interrupt pin input edge detection (INTP7) 9 INTTQ0OV 10 INTTQ0CC0 TMQ0 capture 0/ TMQ0 overflow TMQ0 0110H 00000110H nextPC TQ0OVIC TMQ0 0120H 00000120H nextPC TQ0CCIC0 TMQ0 0130H 00000130H nextPC TQ0CCIC1 TMQ0 0140H 00000140H nextPC TQ0CCIC2 TMQ0 0150H 00000150H nextPC TQ0CCIC3 TMP0 0160H 00000160H nextPC TP0OVIC TMP0 0170H 00000170H nextPC TP0CCIC0 TMP0 0180H 00000180H nextPC TP0CCIC1 TMP1 0190H 00000190H nextPC TP1OVIC TMP1 01A0H 000001A0H nextPC TP1CCIC0 TMP1 01B0H 000001B0H nextPC TP1CCIC1 compare 0 match 11 INTTQ0CC1 TMQ0 capture 1/ compare 1 match 12 INTTQ0CC2 TMQ0 capture 2/ compare 2 match 13 INTTQ0CC3 TMQ0 capture 3/ compare 3 match 14 INTTP0OV TMP0 overflow 15 INTTP0CC0 TMP0 capture 0/ compare 0 match 16 INTTP0CC1 TMP0 capture 1/ compare 1 match 17 INTTP1OV TMP1 overflow 18 INTTP1CC0 TMP1 capture 0/ compare 0 match 19 INTTP1CC1 TMP1 capture 1/ compare 1 match 20 INTTP2OV 21 INTTP2CC0 TMP2 capture 0/ TMP2 overflow TMP2 01C0H 000001C0H nextPC TP2OVIC TMP2 01D0H 000001D0H nextPC TP2CCIC0 TMP2 01E0H 000001E0H nextPC TP2CCIC1 TMP3 01F0H 000001F0H nextPC TP3OVIC TMP3 0200H 00000200H nextPC TP3CCIC0 TMP3 0210H 00000210H nextPC TP3CCIC1 compare 0 match 22 INTTP2CC1 TMP2 capture 1/ compare 1 match 23 INTTP3OV TMP3 overflow 24 INTTP3CC0 TMP3 capture 0/ compare 0 match 25 INTTP3CC1 TMP3 capture 1/ compare 1 match <R> Note V850ES/SG2 only 918 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-1. Interrupt Source List (3/4) Type Classification Default Name Trigger Priority Generating Exception Handler Restored Unit Code Address PC Interrupt Control Register Maskable Interrupt 26 INTTP4OV TMP4 overflow 27 INTTP4CC0 TMP4 capture 0/ TMP4 0220H 00000220H nextPC TP4OVIC TMP4 0230H 00000230H nextPC TP4CCIC0 TMP4 0240H 00000240H nextPC TP4CCIC1 TMP5 0250H 00000250H nextPC TP5OVIC TMP5 0260H 00000260H nextPC TP5CCIC0 TMP5 0270H 00000270H nextPC TP5CCIC1 compare 0 match 28 INTTP4CC1 TMP4 capture 1/ compare 1 match 29 INTTP5OV TMP5 overflow 30 INTTP5CC0 TMP5 capture 0/ compare 0 match 31 INTTP5CC1 TMP5 capture 1/ compare 1 match 32 INTTM0EQ0 TMM0 compare match 33 INTCB0R/ CSIB0 reception completion/ CSIB0/ TMM0 INTIIC1Note CSIB0 reception error/ 0280H 00000280H nextPC TM0EQIC0 0290H 00000290H nextPC CB0RIC/ IIC1 IICIC1 IIC1 transfer completion 34 INTCB0T CSIB0 consecutive CSIB0 02A0H 000002A0H nextPC CB0TIC CSIB1 reception completion/ CSIB1 02B0H 000002B0H nextPC CB1RIC CSIB1 02C0H 000002C0H nextPC CB1TIC CSIB2 reception completion/ CSIB2 02D0H 000002D0H nextPC CB2RIC CSIB2 02E0H 000002E0H nextPC CB2TIC CSIB3 reception completion/ CSIB3 02F0H 000002F0H nextPC CB3RIC CSIB3 0300H 00000300H nextPC CB3TIC 0310H 00000310H nextPC transmission write enable 35 INTCB1R CSIB1 reception error 36 INTCB1T CSIB1 consecutive transmission write enable 37 INTCB2R CSIB2 reception error 38 INTCB2T CSIB2 consecutive transmission write enable 39 INTCB3R CSIB3 reception error 40 INTCB3T CSIB3 consecutive transmission write enable 41 INTUA0R/ UARTA0 reception UARTA0/ INTCB4R completion/ CSIB4 UA0RIC/C B4RIC CSIB4 reception completion/ CSIB4 reception error 42 INTUA0T/ UARTA0 consecutive UARTA0/ INTCB4T transmission enable/ CSIB4 0320H 00000320H nextPC UA0TIC/ CB4TIC CSIB4 consecutive transmission write enable 43 INTUA1R/ UARTA1 reception UARTA1/ INTIIC2Note completion/ IIC2 0330H 00000330H nextPC UA1RIC/ IICIC2 UARTA1 reception error/ IIC2 transfer completion 44 INTUA1T UARTA1 consecutive UARTA1 0340H 00000340H nextPC UA1TIC 0350H 00000350H nextPC UA2RIC/ transmission enable 45 INTUA2R/ UARTA2 reception UARTA/ INTIIC0Note completion/ IIC0 IICIC0 IIC0 transfer completion 46 INTUA2T UARTA2 consecutive UARTA2 0360H 00000360H nextPC UA2TIC transmission enable <R> Note I2C bus versions (Y products) only User's Manual U16541EJ5V1UD 919 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-1. Interrupt Source List (4/4) Type Classification Default Name Trigger Generating Exception Handler Restored Unit Code Address PC Priority Interrupt Control Register Maskable Interrupt 47 INTAD A/D conversion completion A/D 0370H 00000370H nextPC ADIC 48 INTDMA0 DMA0 transfer completion DMA 0380H 00000380H nextPC DMAIC0 49 INTDMA1 DMA1 transfer completion DMA 0390H 00000390H nextPC DMAIC1 50 INTDMA2 DMA2 transfer completion DMA 03A0H 000003A0H nextPC DMAIC2 51 INTDMA3 DMA3 transfer completion DMA 03B0H 000003B0H nextPC DMAIC3 52 INTKR Key return interrupt KR 03C0H 000003C0H nextPC KRIC 53 INTWTI Watch timer interval WT 03D0H 000003D0H nextPC WTIIC 54 INTWT Watch timer reference time WT 03E0H 000003E0H nextPC WTIC 55 INTC0ERRNote 1/ AFCAN0 error/IEBus error AFCAN0/ 03F0H 000003F0H nextPC INTERRNote 2 IEBus 56 INTC0WUPNote 1/ AFCAN0 wakeup/ IEBus status INTSTANote 2 57 Note 1 INTC0REC INTIE1 58 Note 2 / AFCAN0 reception/ IEBus data interrupt INTC0TRXNote 1/ AFCAN0 transmission/ INTIE2Note 2 IEBus error/IEBus status AFCAN0/ 0400H 00000400H nextPC IEBus AFCAN0/ WUPIC0/ STSAIC 0410H 00000410H nextPC IEBus AFCAN0/ ERRIC0/ ERRIC RECIC0/ IEIC1 0420H 00000420H IEBus nextPC TRXIC0/ IEIC2 Notes 1. CAN controller version only 2. IEBus controller version only Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The priority order of non-maskable interrupt is INTWDT2 > NMI. Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt servicing is started. Note, however, that the restored PC when a nonmaskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextPC (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Division instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only if an interrupt is generated before the stack pointer is updated) nextPC: The PC value that starts the processing following interrupt/exception processing. 2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (Restored PC - 4). 920 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals. This product has the following two non-maskable interrupt request signals. * NMI pin input (NMI) * Non-maskable interrupt request signal generated by overflow of watchdog timer (INTWDT2) The valid edge of the NMI pin can be selected from four types: "rising edge", "falling edge", "both edges", and "no edge detection". The non-maskable interrupt request signal generated by overflow of the watchdog timer 2 (INTWDT2) functions when the WDTM2.WDM21 and WDTM2.WDM20 bits are set to "01". If two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt request signal with the lower priority is ignored). INTWDT2 > NMI If a new NMI or INTWDT2 request signal is issued while a NMI is being serviced, it is serviced as follows. (1) If new NMI request signal is issued while NMI is being serviced The new NMI request signal is held pending, regardless of the value of the PSW.NP bit. The pending NMI request signal is acknowledged after the NMI currently under execution has been serviced (after the RETI instruction has been executed). (2) If INTWDT2 request signal is issued while NMI is being serviced The INTWDT2 request signal is held pending if the NP bit remains set (1) while the NMI is being serviced. The pending INTWDT2 request signal is acknowledged after the NMI currently under execution has been serviced (after the RETI instruction has been executed). If the NP bit is cleared (0) while the NMI is being serviced, the newly generated INTWDT2 request signal is executed (the NMI servicing is stopped). Caution For the non-maskable interrupt servicing executed by the non-maskable interrupt request signal (INTWDT2), see 22.2.2 (2) INTWDT2 signal. Figure 22-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (1/2) (a) NMI and INTWDT2 request signals generated at the same time Main routine INTWDT2 servicing NMI and INTWDT2 requests (generated simultaneously) System reset User's Manual U16541EJ5V1UD 921 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (2/2) (b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing Non-maskable interrupt being serviced NMI Non-maskable interrupt request signal generated during non-maskable interrupt servicing NMI INTWDT2 * NMI request generated during NMI servicing * INTWDT2 request generated during NMI servicing (NP bit = 1 retained before INTWDT2 request) Main routine NMI servicing Main routine NMI servicing NMI request NMI (Held pending) request Servicing of pending NMI INTWDT2 request NMI request (Held pending) INTWDT2 servicing System reset * INTWDT2 request generated during NMI servicing (NP bit = 0 set before INTWDT2 request) Main routine NMI servicing INTWDT2 servicing NP = 0 NMI request INTWDT2 request System reset * INTWDT2 request generated during NMI servicing (NP = 0 set after INTWDT2 request) Main routine NMI request INTWDT2 request NP = 0 NMI INTWDT2 servicing servicing (Held pending) System reset INTWDT2 * NMI request generated during INTWDT2 servicing * INTWDT2 request generated during INTWDT2 servicing Main routine Main routine INTWDT2 servicing INTWDT2 request NMI request (Invalid) INTWDT2 servicing INTWDT2 request System reset 922 User's Manual U16541EJ5V1UD INTWDT2 request (Invalid) System reset CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR. <4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0. <5> Sets the handler address (00000010H, 00000020H) corresponding to the non-maskable interrupt to the PC, and transfers control. The servicing configuration of a non-maskable interrupt is shown in Figure 22-2. Figure 22-2. Servicing Configuration of Non-Maskable Interrupt NMI input INTC acknowledged Non-maskable interrupt request CPU processing PSW.NP 1 0 FEPC FEPSW ECR.FECC PSW.NP PSW.EP PSW.ID PC Restored PC PSW 0010H, 0020H 1 0 1 00000010H, 00000020H Interrupt request held pending Interrupt servicing User's Manual U16541EJ5V1UD 923 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.2.2 Restore (1) From NMI pin input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit is 0 and the PSW.NP bit is 1. <2> Transfers control back to the address of the restored PC and PSW. Figure 22-3 illustrates how the RETI instruction is processed. Figure 22-3. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 1 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the EP and NP bits are changed by the LDSR instruction during non-maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 1 using the LDSR instruction immediately before the RETI instruction. Remark 924 The solid line shows the CPU processing flow. User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) From INTWDT2 signal Restoring from non-maskable interrupt servicing executed by the non-maskable interrupt request (INTWDT2) by using the RETI instruction is disabled. Execute the following software reset processing. Figure 22-4. Software Reset Processing INTWDT2 occurs. FEPC Software reset processing address FEPSW Value that sets NP bit = 1, EP bit = 0 INTWDT2 servicing routine RETI RETI 10 times (FEPC and FEPSWNote must be set.) PSW PSW default value setting Software reset processing routine Initialization processing Note FEPSW Value that sets NP bit = 1, EP bit = 0 22.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution. This flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. After reset: 00000020H PSW 0 NP NP EP ID SAT CY OV S Z Non-maskable interrupt servicing status 0 No non-maskable interrupt servicing 1 Non-maskable interrupt currently being serviced User's Manual U16541EJ5V1UD 925 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/SG2, V850ES/SG2<R> H has 54 to 59 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (DI) status is set. When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. To enable multiple interrupts, however, save EIPC and EIPSW to memory or general-purpose registers before executing the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of EIPC and EIPSW. 22.3.1 Operation If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower halfword of ECR (EICC). <4> Sets the PSW. ID bit to 1 and clears the PSW. EP bit to 0. <5> Sets the handler address corresponding to each interrupt to the PC, and transfers control. The maskable interrupt request signal masked by INTC and the maskable interrupt request signal generated while another interrupt is being serviced (while the PSW.NP bit = 1 or the PSW.ID bit = 1) are held pending inside INTC. In this case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or the NP and ID bits are cleared to 0 by using the RETI or LDSR instruction. How maskable interrupts are serviced is illustrated below. 926 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-5. Maskable Interrupt Servicing INT input INTC acknowledged xxIF = 1 No Interrupt requested? Yes xxMK = 0 Yes Priority higher than that of interrupt currently being serviced? No Is the interrupt mask released? No Yes Priority higher than that of other interrupt request? No Yes Highest default priority of interrupt requests with the same priority? No Yes Maskable interrupt request Interrupt request held pending CPU processing PSW.NP 1 0 PSW.ID 1 0 EIPC EIPSW ECR.EICC PSW.EP PSW.ID Corresponding bit of ISPRNote PC Restored PC PSW Exception code 0 1 1 Interrupt request held pending Handler address Interrupt servicing Note For the ISPR register, see 22.3.6 In-service priority register (ISPR). User's Manual U16541EJ5V1UD 927 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the PSW.NP bit is 0. <2> Transfers control to the address of the restored PC and PSW. Figure 22-6 illustrates the processing of the RETI instruction. Figure 22-6. RETI Instruction Processing RETI instruction 1 PSW.EP 0 1 PSW.NP 0 PC PSW Corresponding bit of ISPRNote EIPC EIPSW 0 PC PSW FEPC FEPSW Restores original processing Note For the ISPR register, see 22.3.6 In-service priority register (ISPR). Caution When the EP and NP bits are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 0 using the LDSR instruction immediately before the RETI instruction. Remark 928 The solid line shows the CPU processing flow. User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. For more information, see Table 22-1 Interrupt/Exception Source List. The programmable priority control customizes interrupt request signals into eight levels by setting the priority level specification flag. Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set to 1. Therefore, when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the interrupt service program) to set the interrupt enable mode. Remark xx: Identification name of each peripheral unit (see Table 22-2 Interrupt Control Register (xxICn)) n: Peripheral unit number (see Table 22-2 Interrupt Control Register (xxICn)). User's Manual U16541EJ5V1UD 929 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a EI Interrupt request a (level 3) Servicing of b EI Interrupt request b (level 2) Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of c Interrupt request c (level 3) Interrupt request d (level 2) Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. Servicing of d Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of f Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. Servicing of h Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. 930 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i EI Interrupt request i (level 2) Servicing of k EI Interrupt request j (level 3) Interrupt request k (level 1) Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. Servicing of j Servicing of l Interrupt request l (level 2) Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. Servicing of m Interrupt request o (level 3) Interrupt request p (level 2) Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request q Interrupt (level 1) request r (level 0) If levels 3 to 0 are acknowledged Servicing of s Interrupt request s (level 1) Interrupt request t (level 2) Interrupt request u (level 2) Note 1 Note 2 Pending interrupt requests t and u are acknowledged after servicing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Servicing of u Servicing of t Caution Notes 1. Lower default priority 2. Higher default priority To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. User's Manual U16541EJ5V1UD 931 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-8. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request c (level 1) Default priority a>b>c Servicing of interrupt request b Servicing of interrupt request c . . Interrupt request b and c are acknowledged first according to their priorities. Because the priorities of b and c are the same, b is acknowledged first according to the default priority. Servicing of interrupt request a Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be saved before executing the EI instruction. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. 932 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.4 Interrupt control register (xxICn) The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 47H. Cautions 1. Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit. If the xxIFn bit is read while interrupts are enabled (EI) or while the interrupt is unmasked, the correct value may not be read when acknowledging an interrupt and reading the bit conflict. <R> 2. In the V850ES/SG2-H, if generation of an interrupt source and a bit manipulation instruction (SET1, NOT1, or CLR1 (except TST1)) that manipulates the xxMKn or xxPRn2 to xxPRn0 bits of the interrupt source that has been generated conflict, the interrupt request signal may not be generated. This can be avoided in the following two ways. * When a bit manipulation instruction is not used to the xxICn register <1> Change from writing the xxMKn bit to a bit manipulation instruction that manipulates the IMRm register. <2> Change from writing the xxPRn2 to xxPRn0 bits to a byte access to the xxICn register. * When a bit manipulation instruction is used to the xxICn register Execute a bit manipulation instruction that manipulates the xxICn register after executing a dummy write (byte access) with the unused xxICn.xxIFn bit cleared to 0 in the interrupt disabled (DI) status. <R> 3. When manipulating the xxICn.xxMKn bit with the state where an interrupt request can be generated (including an interrupt disable (DI) state), be sure to manipulate with a bit manipulation instruction or by using the IMRm.xxMKn bit (m = 0 to 3). In the V850ES/SG2-H, however, when using the bit manipulation instruction, also note with caution the above caution 2. User's Manual U16541EJ5V1UD 933 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: 47H xxICn R/W <7> <6> xxIFn xxMKn Address: FFFFF110H to FFFFF184H 0 0 0 xxPRn2 xxPRn1 xxPRn0 Interrupt request flagNote xxIFn 0 Interrupt request not issued 1 Interrupt request issued xxMKn Interrupt mask flag 0 Interrupt servicing enabled 1 Interrupt servicing disabled (pending) xxPRn2 xxPRn1 xxPRn0 Interrupt priority specification bit 0 0 0 Specifies level 0 (highest). 0 0 1 Specifies level 1. 0 1 0 Specifies level 2. 0 1 1 Specifies level 3. 1 0 0 Specifies level 4. 1 0 1 Specifies level 5. 1 1 0 Specifies level 6. 1 1 1 Specifies level 7 (lowest). Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged. Remark xx: Identification name of each peripheral unit (see Table 22-2 Interrupt Control Register (xxICn)) n: Peripheral unit number (see Table 22-2 Interrupt Control Register (xxICn)). The addresses and bits of the interrupt control registers are as follows. 934 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-2. Interrupt Control Register (xxICn) (1/2) Address Register Bit <7> <R> 5 4 3 2 1 0 FFFFF110H LVIICNote 1 LVIIF LVIMF 0 0 0 LVIPR2 LVIPR1 LVIPR0 FFFFF112H PIC0 PIF0 PMK0 0 0 0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 0 0 0 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 0 0 0 PPR22 PPR21 PPR20 FFFFF118H PIC3 PIF3 PMK3 0 0 0 PPR32 PPR31 PPR30 FFFFF11AH PIC4 PIF4 PMK4 0 0 0 PPR42 PPR41 PPR40 FFFFF11CH PIC5 PIF5 PMK5 0 0 0 PPR52 PPR51 PPR50 FFFFF11EH PIC6 PIF6 PMK6 0 0 0 PPR62 PPR61 PPR60 FFFFF120H PIC7 PIF7 PMK7 0 0 0 PPR72 PPR71 PPR70 FFFFF122H TQ0OVIC TQ0OVIF TQ0OVMK 0 0 0 TQ0OVPR2 TQ0OVPR1 TQ0OVPR0 FFFFF124H TQ0CCIC0 TQ0CCIF0 TQ0CCMK0 0 0 0 TQ0CCPR02 TQ0CCPR01 TQ0CCPR00 FFFFF126H TQ0CCIC1 TQ0CCIF1 TQ0CCMK1 0 0 0 TQ0CCPR12 TQ0CCPR11 TQ0CCPR10 FFFFF128H TQ0CCIC2 TQ0CCIF2 TQ0CCMK2 0 0 0 TQ0CCPR22 TQ0CCPR21 TQ0CCPR20 FFFFF12AH TQ0CCIC3 TQ0CCIF3 TQ0CCMK3 0 0 0 TQ0CCPR32 TQ0CCPR31 TQ0CCPR30 FFFFF12CH TP0OVIC TP0OVIF TP0OVMK 0 0 0 TP0OVPR2 FFFFF12EH TP0CCIC0 TP0CCIF0 TP0CCMK0 0 0 0 TP0CCPR02 TP0CCPR01 TP0CCPR00 FFFFF130H TP0CCIC1 TP0CCIF1 TP0CCMK1 0 0 0 TP0CCPR12 TP0CCPR11 TP0CCPR10 TP0OVPR1 TP1OVPR1 TP0OVPR0 FFFFF132H TP1OVIC TP1OVIF TP1OVMK 0 0 0 TP1OVPR2 FFFFF134H TP1CCIC0 TP1CCIF0 TP1CCMK0 0 0 0 TP1CCPR02 TP1CCPR01 TP1CCPR00 FFFFF136H TP1CCIC1 TP1CCIF1 TP1CCMK1 0 0 0 TP1CCPR12 TP1CCPR11 TP1CCPR10 FFFFF138H TP2OVIC TP2OVIF TP2OVMK 0 0 0 TP2OVPR2 FFFFF13AH TP2CCIC0 TP2CCIF0 TP2CCMK0 0 0 0 TP2CCPR02 TP2CCPR01 TP2CCPR00 FFFFF13CH TP2CCIC1 TP2CCIF1 TP2CCMK1 0 0 0 TP2CCPR12 TP2CCPR11 TP2CCPR10 TP2OVPR1 TP3OVPR1 TP1OVPR0 TP2OVPR0 FFFFF13EH TP3OVIC TP3OVIF TP3OVMK 0 0 0 TP3OVPR2 FFFFF140H TP3CCIC0 TP3CCIF0 TP3CCMK0 0 0 0 TP3CCPR02 TP3CCPR01 TP3CCPR00 FFFFF142H TP3CCIC1 TP3CCIF1 TP3CCMK1 0 0 0 TP3CCPR12 TP3CCPR11 TP3CCPR10 TP4OVPR1 TP3OVPR0 FFFFF144H TP4OVIC TP4OVIF TP4OVMK 0 0 0 TP4OVPR2 FFFFF146H TP4CCIC0 TP4CCIF0 TP4CCMK0 0 0 0 TP4CCPR02 TP4CCPR01 TP4CCPR00 FFFFF148H TP4CCIC1 TP4CCIF1 TP4CCMK1 0 0 0 TP4CCPR12 TP4CCPR11 TP4CCPR10 FFFFF14AH TP5OVIC TP5OVIF TP5OVMK 0 0 0 TP5OVPR2 TP5CCPR02 TP5CCPR01 TP5CCPR00 TP5OVPR1 TP4OVPR0 TP5OVPR0 FFFFF14CH TP5CCIC0 TP5CCIF0 TP5CCMK0 0 0 0 FFFFF14EH TP5CCIC1 TP5CCIF1 TP5CCMK1 0 0 0 TP5CCPR12 TP5CCPR11 TP5CCPR10 FFFFF150H TM0EQIC0 TM0EQIF0 TM0EQMK0 0 0 0 TM0EQPR02 TM0EQPR01 TM0EQPR00 0 0 0 CB0RPR2/ CB0RPR1/ CB0RPR0/ IICPR12 IICPR11 IICPR10 FFFFF152H <R> <6> CB0RIC/ CB0RIF/ CB0RMK/ IICIC1Note 2 IICIF1 IICMK1 FFFFF154H CB0TIC CB0TIF CB0TMK 0 0 0 CB0TPR2 CB0TPR1 CB0TPR0 FFFFF156H CB1RIC CB1RIF CB1RMK 0 0 0 CB1RPR2 CB1RPR1 CB1RPR0 FFFFF158H CB1TIC CB1TIF CB1TMK 0 0 0 CB1TPR2 CB1TPR1 CB1TPR0 FFFFF15AH CB2RIC CB2RIF CB2RMK 0 0 0 CB2RPR2 CB2RPR1 CB2RPR0 FFFFF15CH CB2TIC CB2TIF CB2TMK 0 0 0 CB2TPR2 CB2TPR1 CB2TPR0 FFFFF15EH CB3RIC CB3RIF CB3RMK 0 0 0 CB3RPR2 CB3RPR1 CB3RPR0 FFFFF160H CB3TIC CB3TIF CB3TMK 0 0 0 CB3TPR2 CB3TPR1 CB3TPR0 Notes 1. V850ES/SG2 only 2. I2C bus versions (Y products) only User's Manual U16541EJ5V1UD 935 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 22-2. Interrupt Control Register (xxICn) (2/2) Address Register Bit <7> FFFFF162H FFFFF164H FFFFF166H <6> UA0RIC/ UA0RIF/ UA0RMK/ CB4RIC CB4RIF CB4RMK UA0TIC/ UA0TIF/ UA0TMK/ CB4TIC CB4TIF CB4TMK UA1RIC/ UA1RIF/ UA1RMK/ IICIC2Note 1 IICIF2 IICMK2 5 4 3 0 0 0 0 0 0 0 0 0 2 1 0 UA0RPR2/ UA0RPR1/ UA0RPR0/ CB4RPR2 CB4RPR1 CB4RPR0 UA0TPR2/ UA0TPR1/ UA0TPR0/ CB4TPR2 CB4TPR1 CB4TPR0 UA1RPR2/ UA1RPR1/ UA1RPR0/ IICPR22 IICPR21 IICPR20 FFFFF168H UA1TIC UA1TIF UA1TMK 0 0 0 UA1TPR2 UA1TPR1 UA1TPR0 FFFFF16AH UA2RIC/ UA2RIF/ UA2RMK/ 0 0 0 UA2RPR2/ UA2RPR1/ UA2RPR0/ IICIC0Note 1 IICIF0 IICMK0 IICPR02 IICPR01 IICPR00 FFFFF16CH UA2TIC UA2TIF UA2TMK 0 0 0 UA2TPR2 UA2TPR1 UA2TPR0 FFFFF16EH ADIC ADIF ADMK 0 0 0 ADPR2 ADPR1 ADPR0 FFFFF170H DMAIC0 DMAIF0 DMAMK0 0 0 0 DMAPR02 DMAPR01 DMAPR00 FFFFF172H DMAIC1 DMAIF1 DMAMK1 0 0 0 DMAPR12 DMAPR11 DMAPR10 FFFFF174H DMAIC2 DMAIF2 DMAMK2 0 0 0 DMAPR22 DMAPR21 DMAPR20 FFFFF176H DMAIC3 DMAIF3 DMAMK3 0 0 0 DMAPR32 DMAPR31 DMAPR30 FFFFF178H KRIC KRIF KRMK 0 0 0 KRPR2 KRPR1 KRPR0 FFFFF17AH WTIIC WTIIF WTIMK 0 0 0 WTIPR2 WTIPR1 WTIPR0 FFFFF17CH WTIC WTIF WTMK 0 0 0 WTPR2 WTPR1 WTPR0 FFFFF17EH ERRIC0Note 2/ ERRIF0/ ERRMK0/ 0 0 0 ERRPR02/ ERRPR01/ ERRPR00/ ERRICNote 3 ERRMK ERRPR2 ERRPR1 ERRPR0 WUPPR02/ WUPPR01/ WUPPR00/ STAPR2 STAPR1 STAPR0 RECPR02/ RECPR01/ RECPR00/ IEPR12 IEPR11 IEPR10 TRXPR02/ TRXPR01/ TRXPR00/ IEPR22 IEPR21 IEPR20 FFFFF180H FFFFF182H FFFFF184H ERRIF Note 2 WUPIC0 / WUPIF0/ STAICNote 3 STAIF RECIC0 Note 2 / RECIF0/ WUPMK0/ 0 0 0 STAMK RECMK0/ IEIC1Note 3 IEIF1 IEMK1 TRXIC0Note 2/ TRXIF0/ TRXMK0/ IEIC2Note 3 IEIF2 IEMK2 0 0 0 0 0 0 Notes 1. I2C bus versions (Y products) only 2. CAN controller versions only 3. IEBus controller versions only 22.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) The IMR0 to IMR3 registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxICn.xxMKn bit. The IMRm register can be read or written in 16-bit units (m = 0 to 3). If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 3). Reset sets these registers to FFFFH. Caution The device file defines the xxICn.xxMKn bit as a reserved word. If a bit is manipulated using the name of xxMKn, the contents of the xxICn register, instead of the IMRm register, are rewritten (as a result, the contents of the IMRm register are also rewritten). 936 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: FFFFH 15 Note 1 IMR3 (IMR3H 14 13 12 11 10 9 8 RECMK0/ IEMK1 WUPMK0/ STAMK 1 0 1 1 1 1 1 7 6 5 4 3 2 ERRMK0/ ERRMK WTMK WTIMK KRMK After reset: FFFFH R/W DMAMK3 DMAMK2 DMAMK1 DMAMK0 Address: IMR2 FFFFF104H, IMR2L FFFFF104H, IMR2H FFFFF105H 14 13 12 11 10 9 8 ADMK UA2TMK UA2RMK/ IICMK0 UA1TMK UA1RMK/ IIC2MK UA0TMK/ CB4TMK UA0RMK/ CB4RMK CB3TMK 7 6 5 4 3 2 1 0 CB0RMK/ IICMK1 TM0EQMK0 15 IMR2 (IMR2HNote 1) Address: IMR3 FFFFF106H, IMR3L FFFFF106H, IMR3H FFFFF107H TRXMK0/ IEMK2 ) IMR3L R/W IMR2L CB3RMK CB2TMK CB2RMK CB1TMK CB1RMK CB0TMK After reset: FFFFH 15 IMR1 (IMR1H Note 1 R/W 14 IMR1L TP3OVMK 6 15 IMR0 (IMR0H <R> ) TP0CCMK0 IMR0L 12 TP5OVMK 5 R/W 14 TP4CCMK1 TP4CCMK0 TP2OVMK 10 11 4 TP2CCMK1 TP2CCMK0 After reset: FFFFH Note 1 13 ) TP5CCMK1 TP5CCMK0 7 Address: IMR1 FFFFF102H, IMR1L FFFFF102H, IMR1H FFFFF103H 9 TP4OVMK 3 2 TP1CCMK1 TP1CCMK0 8 TP3CCMK1 TP3CCMK0 1 0 TP1OVMK TP0CCMK1 Address: IMR0 FFFFF100H, IMR0L FFFFF100H, IMR0H FFFFF101H 13 12 10 11 9 TP0OVMK TQ0CCMK3 TQ0CCMK2 TQ0CCMK1 TQ0CCMK0 TQ0OVMK 8 PMK7 7 6 5 4 3 2 1 0 PMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMKNote 2 Setting of interrupt mask flag xxMKn 0 Interrupt servicing enabled 1 Interrupt servicing disabled Notes 1. To read bits 8 to 15 of the IMR0 to IMR3 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of IMR0H to IMR3H registers. <R> 2. These bits are valid only in the V850ES/SG2. Be sure to set these bits to 1 in the V850ES/SG2-H. <R> Caution Set bits 11 to 15 of the IMR3 register to 1. If the setting of these bits is changed, the operation is not guaranteed. Remark xx: Identification name of each peripheral unit (see Table 22-2 Interrupt Control Register (xxICn)). n: Peripheral unit number (see Table 22-2 Interrupt Control Register (xxICn)) User's Manual U16541EJ5V1UD 937 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest priority is automatically cleared to 0 by hardware. However, it is not cleared to 0 when execution is returned from nonmaskable interrupt servicing or exception processing. This register is read-only, in 8-bit or 1-bit units. Reset sets this register to 00H. Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI). After reset: 00H ISPR R Address: FFFFF1FAH <7> <6> <5> <4> <3> <2> <1> <0> ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 ISPRn Remark 938 Priority of interrupt currently acknowledged 0 Interrupt request signal with priority n not acknowledged 1 Interrupt request signal with priority n acknowledged n = 0 to 7 (priority level) User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.3.7 ID flag This flag controls the maskable interrupt's operating state, and stores control information regarding enabling or disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW. Reset sets this flag to 00000020H. After reset: 00000020H PSW 0 NP EP ID SAT CY OV S Z Specification of maskable interrupt servicingNote ID 0 Maskable interrupt request signal acknowledgment enabled 1 Maskable interrupt request signal acknowledgment disabled (pending) Note Interrupt disable flag (ID) function This bit is set to 1 by the DI instruction and cleared to 0 by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When a maskable interrupt request signal is acknowledged, the ID flag is automatically set to 1 by hardware. The interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) is acknowledged when the xxICn.xxIFn bit is set to 1, and the ID flag is cleared to 0. 22.3.8 Watchdog timer mode register 2 (WDTM2) This register can be read or written in 8-bit units (for details, see CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2). Reset sets this register to 67H. After reset: 67H WDTM2 R/W Address: FFFFF6D0H 0 WDM21 WDM20 0 0 0 WDM21 WDM20 0 0 Stops operation 0 1 Non-maskable interrupt request mode 1 x Reset mode (initial-value) 0 0 Selection of watchdog timer operation mode User's Manual U16541EJ5V1UD 939 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 22.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). <4> Sets the PSW.EP and PSW.ID bits to 1. <5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC, and transfers control. Figure 22-9 illustrates the processing of a software exception. Figure 22-9. Software Exception Processing TRAP instructionNote CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restored PC PSW Exception code 1 1 Handler address Exception processing Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.) The handler address is determined by the TRAP instruction's operand (vector). If the vector is 00H to 0FH, it becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H. 940 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC's address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2> Transfers control to the address of the restored PC and PSW. Figure 22-10 illustrates the processing of the RETI instruction. Figure 22-10. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 1 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the EP and NP bits are changed by the LDSR instruction during the software exception processing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set the EP bit back to 1 and the NP bit back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. User's Manual U16541EJ5V1UD 941 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.4.3 EP flag The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H PSW 0 EP 942 NP EP Exception processing status 0 Exception processing not in progress. 1 Exception processing in progress. User's Manual U16541EJ5V1UD ID SAT CY OV S Z CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the <R> V850ES/SG2 and V850ES/SG2-H, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 22.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal instruction is executed. 15 11 10 5 4 0 31 27 26 23 22 16 0 1 1 1 to x x x x x 1 1 1 1 1 1 x x x x x x x x x x x x x x x x 0 1 1 1 1 x: Arbitrary Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control. Figure 22-11 illustrates the processing of the exception trap. User's Manual U16541EJ5V1UD 943 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 22-11. Exception Trap Processing Exception trap (ILGOP) occurs DBPC DBPSW PSW.NP PSW.EP PSW.ID PC CPU processing Restored PC PSW 1 1 1 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the address indicated by the restored PC and PSW. Caution <R> DBPC and DBPSW can be accessed only during the interval between the execution of the illegal opcode and DBRET instruction. Figure 22-12 illustrates the restore processing from an exception trap. Figure 22-12. Restore Processing from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC 944 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. (1) Operation Upon occurrence of a debug trap, the CPU performs the following processing. <1> Saves restored PC to DBPC. <2> Saves current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets handler address (00000060H) for debug trap to PC and transfers control. Figure 22-13 shows the debug trap processing format. Figure 22-13. Debug Trap Processing Format DBTRAP instruction CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Debug monitor routine processing User's Manual U16541EJ5V1UD 945 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2> Control is transferred to the fetched address of the restored PC and PSW. Caution DBPC and DBPSW can be accessed after the DBTRAP instruction is executed and before the DBRET instruction is executed. Table 22-14 shows the processing format for restoration from a debug trap. Figure 22-14. Processing Format of Restoration from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC 946 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) 22.6.1 Noise elimination (1) Eliminating noise on NMI pin The NMI pin has an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is detected after specific time. The NMI pin can be used to release the STOP mode. In the STOP mode, noise is not eliminated by using the system clock because the internal system clock is stopped. (2) Eliminating noise on INTP0 to INTP7 pins The INTP0 to INTP7 pins have an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is detected after specific time. 22.6.2 Edge detection The valid edge of each of the NMI and INTP0 to INTP7 pins can be selected from the following four. * Rising edge * Falling edge * Both rising and falling edges * No edge detected The edge of the NMI pin is not detected after reset. Therefore, the interrupt request signal is not acknowledged unless a valid edge is enabled by using the INTF0 and INTR0 register (the NMI pin functions as a normal port pin). User's Manual U16541EJ5V1UD 947 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0) The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI pin via bit 2 and the external interrupt pins (INTP0 to INTP3) via bits 3 to 6. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 00, and then set the port mode. After reset: 00H INTF0 INTR0 Remark 0 0 R/W Address: INTF0 FFFFFC00H, INTR0 FFFFFC20H INTF06 INTF05 INTF04 INTF03 INTF02 INTP3 INTP2 INTP1 INTP0 NMI INTR06 INTR05 INTR04 INTR03 INTR02 INTP3 INTP2 INTP1 INTP0 NMI 0 0 0 0 For how to specify a valid edge, see Table 22-3. Table 22-3. Valid Edge Specification INTF0n INTR0n 0 0 No edge detected 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges Caution Valid Edge Specification (n = 2 to 6) Be sure to clear the INTF0n and INTR0n bits to 00 when these registers are not used as the NMI or INTP0 to INTP3 pins. Remark n = 2: Control of NMI pin n = 3 to 6: Control of INTP0 to INTP3 pins 948 User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt falling, rising edge specification register 3 (INTF3, INTR3) The INTF3 and INTR3 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP7). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Cautions 1. When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, clear the INTF31 and INTR31 bits to 00, and then set the port mode. 2. The INTP7 pin and RXDA0 pin are alternate-function pins. When using the pin as the RXDA0 pin, disable edge detection for the INTP7 alternate-function pin (clear the INTF3.INTF31 bit and the INRT3.INTR31 bit to 0). When using the pin as the INTP7 pin, stop UARTA0 reception (clear the UA0CTL0.UA0RXE bit to 0). After reset: 00H INTF3 0 R/W 0 Address: INTF3 FFFFFC06H, INTR3 FFFFFC26H 0 0 0 0 INTF31 0 INTP7 INTR3 0 0 0 0 0 0 INTR31 0 INTP7 Remark For how to specify a valid edge, see Table 22-4. Table 22-4. Valid Edge Specification INTF31 INTR31 0 0 No edge detected 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges Caution Valid Edge Specification Be sure to clear the INTF31 and INTR31 bits to 00 when these registers are not used as INTP7 pin. User's Manual U16541EJ5V1UD 949 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt falling, rising edge specification register 9H (INTF9H, INTR9H) The INTF9H and INTR9H registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (INTP4 to INTP6). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. Therefore, clear the INTF9n and INTR9n bits to 0, and then set the port mode. After reset: 00H 15 INTF9H INTR9H 14 Address: INTF9H FFFFFC13H, INTR9H FFFFFC33H 13 INTF915 INTF914 INTF913 INTP6 INTP5 INTP4 15 14 13 INTR915 INTR914 INTR913 INTP6 Remark R/W INTP5 12 11 10 9 8 0 0 0 0 0 12 11 10 9 8 0 0 0 0 0 INTP4 For how to specify a valid edge, see Table 22-5. Table 22-5. Valid Edge Specification INTF9n INTR9n 0 0 No edge detected 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges Caution Valid Edge Specification (n = 13 to 15) Be sure to clear the INTF9n and INTR9n bits to 00 when these registers are not used as INTP4 to INTP6 pins. Remark 950 n = 13 to 15: Control of INTP4 to INTP6 pins User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) Noise elimination control register (NFC) Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using the NFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, and fXT. Sampling is performed 3 times. <R> When digital noise elimination is selected, if the clock that performs sampling in the standby mode is stopped, then the INTP3 interrupt request signal cannot be used for releasing the standby mode. When fXT is used as the sampling clock, the INTP3 interrupt request signal can be used for releasing either the subclock operating mode or the IDLE1/IDLE2/STOP/sub-IDLE mode. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution After the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital noise eliminator. Therefore, if an INTP3 valid edge is input within these 3 sampling clocks after the sampling clock has been changed, an interrupt request signal may be generated. Therefore, be careful about the following points when using the interrupt and DMA functions. * When using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (PIC3.PIF3 bit) has been cleared. * When using the DMA function (started by INTP3), enable DMA after 3 sampling clocks have elapsed. After reset: 00H NFC NFEN R/W Address: FFFFF318H 0 0 NFEN 0 0 NFC2 NFC1 NFC0 Settings of INTP3 pin noise elimination 0 Analog noise elimination (60 ns (TYP.)) 1 Digital noise elimination NFC2 NFC1 NFC0 0 0 0 fXX/64 0 0 1 fXX/128 0 1 0 fXX/256 0 1 1 fXX/512 1 0 0 fXX/1,024 1 0 1 fXT (subclock) Other than above Digital sampling clock Setting prohibited Remarks 1. Since sampling is performed 3 times, the reliably eliminated noise width is 2 sampling clocks. 2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. User's Manual U16541EJ5V1UD 951 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.7 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt. * In IDLE1/IDLE2/STOP mode * When the external bus is accessed * When interrupt request non-sampling instructions are successively executed (see 22.8 Interrupts Are Not Acknowledged by CPU.) * When the interrupt control register is accessed <R> * When an on-chip peripheral I/O register is accessed <R> * When a programmable peripheral I/O register is accessed 952 User's Manual U16541EJ5V1UD Periods in Which CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION <R> Figure 22-15. Pipeline Operation at Interrupt Request Signal Acknowledgment of V850ES/SG2 (Outline) (1) Minimum interrupt response time Internal system clock Interrupt acknowledgment Instruction 1 IF ID EX DF WB IFX IDX INT1 INT2 INT3 INT4 Instruction 2 Interrupt acknowledgment operation IF First instruction of interrupt servicing routine ID EX 4 system clocks (2) Maximum interrupt response time Internal system clock Interrupt acknowledgment Instruction 1 IF ID EX MEM MEM MEM WB IFX IDX INT1 INT2 INT3 INT3 INT3 INT4 Instruction 2 Interrupt acknowledgment operation IF First instruction of interrupt servicing routine ID EX 6 system clocks Remarks 1. INT1 to INT4: Interrupt acknowledgment processing IFX: Invalid instruction fetch IDX: Invalid instruction decode 2. If the same interrupt request signal is generated while an interrupt of four cycles is being acknowledged, the new interrupt request signal is discarded. The next interrupt request signal from the same source is registered four cycles later. Interrupt response time (internal system clock) Internal interrupt External interrupt Minimum 4 4+ Analog delay time Maximum 6 6+ Analog delay time Condition The following cases are exceptions. * In IDLE1/IDLE2/STOP mode * External bus access * Two or more interrupt request non-sample instructions are executed in succession * Access to interrupt control register * Access to on-chip peripheral I/O register * Access to programmable peripheral I/O register User's Manual U16541EJ5V1UD 953 CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION <R> Figure 22-16. Pipeline Operation at Interrupt Request Signal Acknowledgment of V850ES/SG2-H (Outline) (1) Minimum interrupt response time Internal system clock Interrupt acknowledgment Instruction 1 IF Instruction 2 IF IFX Interrupt acknowledgment operation ID EX DF WB IFX IDX INT1 INT2 INT3 INT4 IF First instruction of interrupt servicing routine 4 system clocks IF ID EX Interleave access (2) Maximum interrupt response time Internal system clock Interrupt acknowledgment Instruction 1 IF Instruction 2 IF IFX Interrupt acknowledgment operation ID EX MEM MEM MEM MEM WB IFX IDX INT1 INT2 INT3 INT3 INT3 INT3 INT4 IF First instruction of interrupt servicing routine 7 system clocks IF Interleave access Remarks 1. INT1 to INT4: Interrupt acknowledgment processing IFX: Invalid instruction fetch IDX: Invalid instruction decode 2. If the same interrupt request signal is generated while an interrupt of four cycles is being acknowledged, the new interrupt request signal is discarded. The next interrupt request signal from the same source is registered four cycles later. Interrupt response time (internal system clock) 954 Internal interrupt External interrupt Minimum 4 4+ Analog delay time Maximum 7 7+ Analog delay time Condition The following cases are exceptions. * In IDLE1/IDLE2/STOP mode * External bus access * Two or more interrupt request non-sample instructions are executed in succession * Access to interrupt control register * Access to on-chip peripheral I/O register * Access to programmable peripheral I/O register User's Manual U16541EJ5V1UD CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION 22.8 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows. * EI instruction * DI instruction * LDSR reg2, 0x5 instruction (for PSW) * The store instruction for the PRCMD register * The store, SET1, NOT1, or CLR1 instructions for the following registers. * Interrupt-related registers: Interrupt control register (xxICn), interrupt mask registers 0 to 3 (IMR0 to IMR3) * Power save control register (PSC) * On-chip debug mode register (OCDM) Remark xx: Identification name of each peripheral unit (see Table 22-2 Interrupt Control Register (xxICn)) n: Peripheral unit number (see Table 22-2 Interrupt Control Register (xxICn)). 22.9 Cautions (1) NMI pin The NMI pin and P02 pin are an alternate-function pin, and function as a normal port pin after being reset. To enable the NMI pin, validate the NMI pin with the PMC0 register. The initial setting of the NMI pin is "No edge detected". Select the NMI pin valid edge using the INTF0 and INTR0 registers. <R> (2) Interrupt control register (xxICn) of V850ES/SG2-H In the V850ES/SG2-H, if generation of an interrupt source and a bit manipulation instruction (SET1, NOT1, or CLR1 (except TST1)) that manipulates the xxMKn or xxPRn2 to xxPRn0 bits of the interrupt source that has been generated conflict, the interrupt request signal may not be generated. This can be avoided in the following two ways. * When a bit manipulation instruction is not used to the xxICn register <1> Change from writing the xxMKn bit to a bit manipulation instruction that manipulates the IMRm register. <2> Change from writing the xxPRn2 to xxPRn0 bits to a byte access to the xxICn register. * When a bit manipulation instruction is used to the xxICn register Execute a bit manipulation instruction that manipulates the xxICn register after executing a dummy write (byte access) with the unused xxICn.xxIFn bit cleared to 0 in the interrupt disabled (DI) status. <R> (3) Interrupt control register (xxICn) of V850ES/SG2 and V850ES/SG2-H When manipulating the xxICn.xxMKn bit with the state where an interrupt request can be generated (including an interrupt disable (DI) state), be sure to manipulate with a bit manipulation instruction or by using the IMRm.xxMKn bit (m = 0 to 3). In the V850ES/SG2-H, however, when using the bit manipulation instruction, also note with caution the above (2). <R> (4) In-service priority register (ISPR) If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI). User's Manual U16541EJ5V1UD 955 CHAPTER 23 KEY INTERRUPT FUNCTION 23.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Table 23-1. Assignment of Key Return Detection Pins Flag Pin Description KRM0 Controls KR0 signal in 1-bit units KRM1 Controls KR1 signal in 1-bit units KRM2 Controls KR2 signal in 1-bit units KRM3 Controls KR3 signal in 1-bit units KRM4 Controls KR4 signal in 1-bit units KRM5 Controls KR5 signal in 1-bit units KRM6 Controls KR6 signal in 1-bit units KRM7 Controls KR7 signal in 1-bit units Figure 23-1. Key Return Block Diagram KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) 956 User's Manual U16541EJ5V1UD CHAPTER 23 KEY INTERRUPT FUNCTION 23.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H KRM KRM7 R/W KRM6 KRMn Address: FFFFF300H KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Control of key return mode 0 Does not detect key return signal 1 Detects key return signal Caution Rewrite the KRM register after once clearing the KRM register to 00H. Remark For the alternate-function pin settings, see Table 4-15 Using Port Pin as Alternate Function Pin. 23.3 Cautions (1) If a low level is input to any of the KR0 to KR7 pins, the INTKR signal is not generated even if the falling edge of another pin is input. (2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin. To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear PFCE91 bit to 0). (3) If the KRM register is changed, an interrupt request signal (INTKR) may be generated. To prevent this, change the KRM register after disabling interrupts (DI) or masking, then clear the interrupt request flag (KRIC.KRIF bit) to 0, and enable interrupts (EI) or clear the mask. (4) To use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation with the KRM register. To switch from the key return pin to the port pin, disable the operation with the KRM register and then set the port pin. User's Manual U16541EJ5V1UD 957 CHAPTER 24 STANDBY FUNCTION 24.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 24-1. Table 24-1. Standby Modes Mode Functional Outline HALT mode Mode in which only the operating clock of the CPU is stopped IDLE1 mode Mode in which all the operations of the internal circuits except the oscillator, PLL memory are stopped IDLE2 mode Mode in which all the operations of the internal circuits except the oscillator are stopped STOP mode Mode in which all the operations of the internal circuits except the subclock oscillator are stopped Subclock operation mode Mode in which the subclock is used as the internal system clock Sub-IDLE mode Mode in which all the operations of the internal circuits except the oscillator are stopped, in the subclock operation mode Note The PLL holds the previous operating status. 958 User's Manual U16541EJ5V1UD Note , and flash CHAPTER 24 STANDBY FUNCTION Figure 24-1. Status Transition Reset Internal oscillation clock operation Sub-IDLE mode (fx operates, PLL operates) WDT overflow Oscillation stabilization wait Normal operation mode Subclock operation mode (fx operates, PLL operates) Clock through mode (PLL operates) PLL lockup time wait HALT mode (fx operates, PLL operates) PLL mode (PLL operates) Oscillation stabilization waitNote Clock through mode (PLL stops) IDLE1 mode (fx operates, PLL operates) Subclock operation mode (fx stops, PLL stops) Sub-IDLE mode (fx stops, PLL stops) HALT mode (fx operates, PLL stops) Oscillation stabilization waitNote IDLE2 mode (fx operates, PLL stops) Oscillation stabilization waitNote IDLE1 mode (fx operates, PLL stops) STOP mode (fx stops, PLL stops) Note If a WDT overflow occurs during an oscillation stabilization time, the CPU operates on the internal oscillation clock. Remark fX: Main clock oscillation frequency User's Manual U16541EJ5V1UD 959 CHAPTER 24 STANDBY FUNCTION 24.2 Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the STOP mode. This register is a special register that can be written only by the special sequence combinations (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H PSC R/W Address: FFFFF1FEH 7 <6> <5> <4> 3 2 <1> 0 0 NMI1M NMI0M INTM 0 0 STP 0 NMI1M Standby mode release control upon occurrence of INTWDT2 signal 0 Standby mode release by INTWDT2 signal enabled 1 Standby mode release by INTWDT2 signal disabled NMI0M Standby mode release control by NMI pin input 0 Standby mode release by NMI pin input enabled 1 Standby mode release by NMI pin input disabled INTM Standby mode release control via maskable interrupt request signal 0 Standby mode release by maskable interrupt request signal enabled 1 Standby mode release by maskable interrupt request signal disabled Standby modeNote setting STP 0 Normal mode 1 Standby mode Note Standby mode set by STP bit: IDLE1, IDLE2, STOP, or sub-IDLE mode Cautions 1. Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1 and PSMR.PSM0 bits and then set the STP bit. 2. Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is released. <R> 3. If the NMI1M, NMI0M, or INTM bit is set to 1 at the same time the STP bit is set to 1, the setting of NMI1M, NMI0M, or INTM bit becomes invalid. If there is an unmasked interrupt request signal being held pending when the IDLE1/IDLE2/STOP mode is set, set the bit corresponding to the interrupt request signal (NMI1M, NMI0M, or INTM) to 1, and then set the STP bit to 1. 960 User's Manual U16541EJ5V1UD CHAPTER 24 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H PSMR 0 R/W 0 Address: FFFFF820H 0 0 PSM1 PSM0 0 0 IDLE1, sub-IDLE modes 0 1 STOP mode 1 0 IDLE2, sub-IDLE modes 1 1 STOP mode 0 0 < > < > PSM1 PSM0 Specification of operation in software standby mode Cautions 1. Be sure to clear bits 2 to 7 to "0". 2. The PSM0 and PSM1 bits are valid only when the PSC.STP bit is 1. Remark IDLE1: In this mode, all operations except the oscillator operation and some other circuits (flash memory and PLL) are stopped. After the IDLE1 mode is released, the normal operation mode is restored without needing to secure the oscillation stabilization time, like the HALT mode. IDLE2: In this mode, all operations except the oscillator operation are stopped. After the IDLE2 mode is released, the normal operation mode is restored following the lapse of the setup time specified by the OSTS register (flash memory and PLL). STOP: In this mode, all operations except the subclock oscillator operation are stopped. After the STOP mode is released, the normal operation mode is restored following the lapse of the oscillation stabilization time specified by the OSTS register. Sub-IDLE: In this mode, all other operations are halted except for the oscillator. After the IDLE mode has been released by the interrupt request signal, the subclock operation mode will be restored after 12 cycles of the subclock have been secured. User's Manual U16541EJ5V1UD 961 CHAPTER 24 STANDBY FUNCTION (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register. The OSTS register can be read or written 8-bit units. Reset sets this register to 06H. After reset: 06H OSTS R/W 0 0 OSTS2 OSTS1 Address: FFFFF6C0H 0 0 0 OSTS2 OSTS1 OSTS0 OSTS0 Selection of oscillation stabilization time/setup timeNote fX 0 0 0 0 0 1 4 MHz 5 MHz 10 0.256 ms 0.205 ms 11 0.512 ms 0.410 ms 12 2 /fX 2 /fX 0 1 0 2 /fX 1.024 ms 0.819 ms 0 1 1 213/fX 2.048 ms 1.638 ms 14 4.096 ms 3.277 ms 15 8.192 ms 6.554 ms 16 16.38 ms 13.107 ms 1 1 0 0 0 1 2 /fX 2 /fX 1 1 0 2 /fX 1 1 1 Setting prohibited Note The oscillation stabilization time and setup time are required when the STOP mode and IDLE2 mode are released, respectively. Cautions 1. The wait time following release of the STOP mode does not include the time until the clock oscillation starts ("a" in the figure below) following release of the STOP mode, regardless of whether the STOP mode is released by reset input or the occurrence of an interrupt request signal. STOP mode release Voltage waveform of X1 pin a VSS 2. Be sure to clear bits 3 to 7 to "0". 3. The oscillation stabilization time following reset release is 216/fX (because the initial value of the OSTS register = 06H). Remark 962 fX: Main clock oscillation frequency User's Manual U16541EJ5V1UD CHAPTER 24 STANDBY FUNCTION 24.3 HALT Mode 24.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating. Table 24-3 shows the operating status in the HALT mode. The average current consumption of the system can be reduced by using the HALT mode in combination with the normal operation mode for intermittent operation. Cautions 1. Insert five or more NOP instructions after the HALT instruction. 2. If the HALT instruction is executed while an unmasked interrupt request signal is being held pending, the status shifts to HALT mode, but the HALT mode is then released immediately by the pending interrupt request. 24.3.2 Releasing HALT mode The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal <R> from a peripheral function operable in the HALT mode, or reset signal (RESET pin input, reset signal (WDT2RES) Note generation by overflow of watchdog timer, reset signal (LVIRES) generation by low voltage detector (LVI) , or reset signal (CLMRES) generation by clock monitor (CLM)). After the HALT mode has been released, the normal operation mode is restored. <R> Note V850ES/SG2 only (1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the HALT mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the HALT mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt request signal is acknowledged. Table 24-2. Operation After Releasing HALT Mode by Interrupt Request Signal Release Source Non-maskable interrupt request Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed. User's Manual U16541EJ5V1UD The next instruction is executed. 963 CHAPTER 24 STANDBY FUNCTION (2) Releasing HALT mode by reset The same operation as the normal reset operation is performed. Table 24-3. Operating Status in HALT Mode Setting of HALT Mode Item Operating Status When Subclock Is Not Used Main clock oscillator When Subclock Is Used Oscillation enabled - Subclock oscillator Internal oscillator Oscillation enabled PLL Operable CPU Stops operation DMA Operable Interrupt controller Operable ROM correction Stops operation Timer P (TMP0 to TMP5) Operable Timer Q (TMQ0) Operable Timer M (TMM0) Operable when a clock other than fXT is Oscillation enabled Operable selected as the count clock Watch timer Operable when fX (divided BRG) is Operable selected as the count clock Watchdog timer 2 Operable when a clock other than fXT is Operable selected as the count clock Serial interface CSIB0 to CSIB4 2 2 Operable I C00 to I C02 Operable UARTA0 to UARTA2 Operable CAN controller Operable IEBus controller Operable A/D converter Operable D/A converter Operable Real-time output function (RTO) Operable Key interrupt function (KR) Operable CRC arithmetic circuit Operable (in the status in which data is not input to CRCIN to stop the CPU) External bus interface See 2.2 Pin States. Port function Retains status before HALT mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the HALT mode was set. 964 User's Manual U16541EJ5V1UD CHAPTER 24 STANDBY FUNCTION 24.4 IDLE1 Mode 24.4.1 Setting and operation status The IDLE1 mode is set by clearing the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE1 mode was set are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 24-5 shows the operating status in the IDLE1 mode. The IDLE1 mode can reduce the power consumption more than the HALT mode because it stops the operation of the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization time after the IDLE1 mode has been released, in the same manner as when the HALT mode is released. Cautions 1, Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE1 mode. 2. If the IDLE1 mode is set while an unmasked interrupt request signal is being held pending, the IDLE1 mode is released immediately by the pending interrupt request. User's Manual U16541EJ5V1UD 965 CHAPTER 24 STANDBY FUNCTION 24.4.2 Releasing IDLE1 mode The IDLE1 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from a peripheral function operable in the IDLE1 mode, or reset signal (RESET pin input, reset signal (WDT2RES) Note <R> generation by overflow of watchdog timer, reset signal (LVIRES) generation by low voltage detector (LVI) , or reset signal (CLMRES) generation by clock monitor (CLM)). After the IDLE1 mode has been released, the normal operation mode is restored. <R> Note V850ES/SG2 only (1) Releasing IDLE1 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The IDLE1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the IDLE1 mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the IDLE1 mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the IDLE1 mode is released and that interrupt request signal is acknowledged. Caution An interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE1 mode is not released. Table 24-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal Release Source Non-maskable interrupt request Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed. 966 User's Manual U16541EJ5V1UD The next instruction is executed. CHAPTER 24 STANDBY FUNCTION (2) Releasing IDLE1 mode by reset The same operation as the normal reset operation is performed. Table 24-5. Operating Status in IDLE1 Mode Setting of IDLE1 Mode Item Operating Status When Subclock Is Not Used Main clock oscillator When Subclock Is Used Oscillation enabled - Subclock oscillator Oscillation enabled Internal oscillator Oscillation enabled PLL Operable CPU Stops operation DMA Stops operation Interrupt controller Stops operation (but standby mode release enabled) ROM correction Stops operation Timer P (TMP0 to TMP5) Stops operation Timer Q (TMQ0) Stops operation Timer M (TMM0) Operable when fR/8 is selected as the count clock Operable when fR/8 or fXT is selected as the count clock Watch timer Operable when fX (divided BRG) is selected as the count clock Operable Watchdog timer 2 Operable when fR is selected as the count clock Operable when fR or fXT is selected as the count clock Serial interface CSIB0 to CSIB4 2 2 Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4) I C00 to I C02 Stops operation UARTA0 to UARTA2 Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) CAN controller Stops operation IEBus controller Stops operation A/D converter Holds operation (conversion result held) D/A converter Holds operation (output held Real-time output function (RTO) Stops operation (output held) Key interrupt function (KR) Operable CRC arithmetic circuit Stops operation Note Note ) External bus interface See 2.2 Pin States. Port function Retains status before IDLE1 mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE1 mode was set. Note To realize low power consumption, stop the A/D converter and D/A converter before shifting to the IDLE1 mode. User's Manual U16541EJ5V1UD 967 CHAPTER 24 STANDBY FUNCTION 24.5 IDLE2 Mode 24.5.1 Setting and operation status The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are retained. The CPU, PLL, and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 24-7 shows the operating status in the IDLE2 mode. The IDLE2 mode can reduce the power consumption more than the IDLE1 mode because it stops the operations of the on-chip peripheral functions, PLL, and flash memory. However, because the PLL and flash memory are stopped, a setup time for the PLL and flash memory is required when IDLE2 mode is released. Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE2 mode. 2. If the IDLE2 mode is set while an unmasked interrupt request signal is being held pending, the IDLE2 mode is released immediately by the pending interrupt request. 24.5.2 Releasing IDLE2 mode The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the IDLE2 mode, or reset signal (RESET pin input, reset signal (WDT2RES) Note <R> generation by overflow of watchdog timer, reset signal (LVIRES) generation by low voltage detector (LVI) , or reset signal (CLMRES) generation by clock monitor (CLM)). After the IDLE2 mode has been released, the normal operation mode is restored. <R> Note V850ES/SG2 only (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the IDLE2 mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the IDLE2 mode is released and that interrupt request signal is acknowledged. Caution The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released. 968 User's Manual U16541EJ5V1UD CHAPTER 24 STANDBY FUNCTION Table 24-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request signal Execution branches to the handler address after securing the prescribed setup time. Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed after securing the prescribed setup time. The next instruction is executed after securing the prescribed setup time. (2) Releasing IDLE2 mode by reset The same operation as the normal reset operation is performed. Table 24-7. Operating Status in IDLE2 Mode Setting of IDLE2 Mode Item Operating Status When Subclock Is Not Used Main clock oscillator Oscillation enabled - Subclock oscillator <R> When Subclock Is Used Oscillation enabled Internal oscillator Oscillation enabled PLL Stops operation CPU Stops operation DMA Stops operation Interrupt controller Stops operation (but standby mode can be released) ROM correction Stops operation Timer P (TMP0 to TMP5) Stops operation Timer Q (TMP0) Stops operation Timer M (TMM0) Operable when fR/8 is selected as the count clock Operable when fR/8 or fXT is selected as the count clock Watch timer Operable when fX (divided BRG) is selected as the count clock Operable Watchdog timer 2 Operable when fR is selected as the count clock Operable when fR or fXT is selected as the count clock Serial interface CSIB0 to CSIB4 2 2 Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4) I C00 to I C02 Stops operation UARTA0 to UARTA2 Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) CAN controller Stops operation IEBus controller Stops operation A/D converter Holds operation (conversion result held) D/A converter Holds operation (output held Note Note ) Real-time output function (RTO) Stops operation (output held) Key interrupt function (KR) Operable CRC arithmetic circuit Stops operation External bus interface See 2.2 Pin States. Port function Retains status before IDLE2 mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE2 mode was set. Note To realize low power consumption, stop the A/D converter and D/A converter before shifting to the IDLE2 mode. User's Manual U16541EJ5V1UD 969 CHAPTER 24 STANDBY FUNCTION 24.5.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the ROM (flash memory) after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after the IDLE2 mode is set. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the specified setup time by setting the OSTS register. When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS register setting. When it overflows, the normal operation mode is restored. Oscillated waveform Main clock IDLE mode status Interrupt request ROM circuit stopped Setup time count (2) Release by reset (RESET pin input, WDT2RES generation) This operation is the same as that of a normal reset. The oscillation stabilization time is the initial value of the OSTS register, 216/fX. 970 User's Manual U16541EJ5V1UD CHAPTER 24 STANDBY FUNCTION 24.6 STOP Mode 24.6.1 Setting and operation status The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped. As a result, program execution stops, and the contents of the internal RAM before the STOP mode was set are retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. Table 24-9 shows the operating status in the STOP mode. Because the STOP mode stops operation of the main clock oscillator, it reduces the power consumption to a level lower than the IDLE2 mode. If the subclock oscillator, internal oscillator, and external clock are not used, the power consumption can be minimized with only leakage current flowing. Cautions 1, Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the STOP mode. 2. If the STOP mode is set while an unmasked interrupt request signal is being held pending, the STOP mode is released immediately by the pending interrupt request. 24.6.2 Releasing STOP mode The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the STOP mode, or reset signal (RESET pin input, reset signal (WDT2RES) <R> Note generation by overflow of watchdog timer, or reset signal (LVIRES) generation by low voltage detector (LVI) ). After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. <R> Note V850ES/SG2 only (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the STOP mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the STOP mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the STOP mode is released and that interrupt request signal is acknowledged. Caution The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and STOP mode is not released. User's Manual U16541EJ5V1UD 971 CHAPTER 24 STANDBY FUNCTION Table 24-8. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request signal Execution branches to the handler address after securing the oscillation stabilization time. Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed after securing the oscillation stabilization time. 972 User's Manual U16541EJ5V1UD The next instruction is executed after securing the oscillation stabilization time. CHAPTER 24 STANDBY FUNCTION (2) Releasing STOP mode by reset The same operation as the normal reset operation is performed. Table 24-9. Operating Status in STOP Mode Setting of STOP Mode Item Operating Status When Subclock Is Not Used Main clock oscillator - Subclock oscillator <R> When Subclock Is Used Stops oscillation Internal oscillator Oscillation enabled PLL Stops operation Oscillation enabled CPU Stops operation DMA Stops operation Interrupt controller Stops operation (but standby mode can be released) ROM correction Stops operation Timer P (TMP0 to TMP5) Stops operation Timer Q (TMP0) Stops operation Timer M (TMM0) Operable when fR/8 is selected as the count clock Operable when fR/8 or fXT is selected as the count clock Watch timer Stops operation Operable when fXT is selected as the count clock Watchdog timer 2 Operable when fR is selected as the count clock Operable when fR or fXT is selected as the count clock Serial interface CSIB0 to CSIB4 2 2 Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4) I C00 to I C02 Stops operation UARTA0 to UARTA2 Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) CAN controller Stops operation IEBus controller Stops operation A/D converter Stops operation (conversion result undefined) D/A converter Stops operation Real-time output function (RTO) Stops operation (output held) Key interrupt function (KR) Operable CRC arithmetic circuit Stops operation Notes 3, 4 Notes 1, 2 (high impedance is output) External bus interface See 2.2 Pin States. Port function Retains status before STOP mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the STOP mode was set. Notes 1. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically stopped and starts operating again after the STOP mode is released. However, in that case, the A/D conversion results after the STOP mode is released are invalid. All the A/D conversion results before the STOP mode is set are invalid. 2. Even if the STOP mode is set while the A/D converter is operating, the power consumption is reduced equivalently to when the A/D converter is stopped before the STOP mode is set. 3. If the STOP mode is set while the D/A converter is operating, the D/A converter is automatically stopped and the pin status becomes high impedance. After the STOP mode is released, D/A conversion resumes, the setting time elapses, and the status returns to the output level before the STOP mode was set. 4. Even if the STOP mode is set while the D/A converter is operating, the power consumption is reduced equivalently to when the D/A converter is stopped before the STOP mode is set. User's Manual U16541EJ5V1UD 973 CHAPTER 24 STANDBY FUNCTION 24.6.3 Securing oscillation stabilization time when releasing STOP mode Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the operation of the main clock oscillator stops after STOP mode is set. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the oscillation stabilization time by setting the OSTS register. When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS register setting. When it overflows, the normal operation mode is restored. Oscillated waveform Main clock STOP status Interrupt request ROM circuit stopped Setup time count (2) Release by reset This operation is the same as that of a normal reset. The oscillation stabilization time is the initial value of the OSTS register, 216/fX. 974 User's Manual U16541EJ5V1UD CHAPTER 24 STANDBY FUNCTION 24.7 Subclock Operation Mode 24.7.1 Setting and operation status The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. Check whether the clock has been switched by using the PCC.CLS bit. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system operates only on the subclock. In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. In addition, the power consumption can be further reduced to the level of the STOP mode by stopping the operation of the main clock oscillator. Table 24-10 shows the operating status in subclock operation mode. Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details of the PCC register, see 6.3 (1) Processor clock control register (PCC). 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied and set the subclock operation mode. Internal system clock (fCLK) > Subclock (fXT = 32.768 kHz) x 4 <R> Remark Internal system clock (fCLK): Clock generated from the main clock (fXX) by setting the CK2 to CK0 bits 24.7.2 Releasing subclock operation mode The subclock operation mode is released by a reset signal (RESET pin input, reset signal (WDT2RES) generation <R> Note by overflow of watchdog timer, reset signal (LVIRES) generation by low voltage detector (LVI) , or reset signal (CLMRES) generation by clock monitor (CLM)) when the CK3 bit is cleared to 0. If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main clock by software, and clear the CK3 bit to 0. The normal operation mode is restored when the subclock operation mode is released. <R> Note V850ES/SG2 only Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details of the PCC register, see 6.3 (1) Processor clock control register (PCC). User's Manual U16541EJ5V1UD 975 CHAPTER 24 STANDBY FUNCTION Table 24-10. Operating Status in Subclock Operation Mode Setting of Subclock Operation Mode Item Operating Status When Main Clock Is Oscillating Subclock oscillator Oscillation enabled Internal oscillator Oscillation enabled PLL Operable CPU Operable DMA Operable Interrupt controller Operable ROM correction Operable <R> Timer P (TMP0 to TMP5) <R> <R> When Main Clock Is Stopped Stops operation Note Operable Stops operation Note Timer Q (TMP0) Operable Stops operation Note Timer M (TMM0) Operable Operable when fR/8 or fXT is selected as the count clock Watch timer Operable Operable when fXT is selected as the count clock Watchdog timer 2 Operable Operable when fR or fXT is selected as the count clock Serial interface CSIB0 to CSIB4 Operable Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4) 2 <R> 2 Note I C00 to I C02 Operable Stops operation UARTA0 to UARTA2 Operable Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) <R> CAN controller Operable Stops operation Note <R> IEBus controller Operable Stops operation Note <R> A/D converter Operable Stops operation Note D/A converter Operable Real-time output function (RTO) Operable Key interrupt function (KR) Operable CRC arithmetic circuit Operable External bus interface Operable Port function Settable Internal data Settable <R> <R> <R> Note Stops operation (output held) Note To stop the main clock, be sure to stop PLL (PLLCTL.PLLON bit = 0). Also stop the internal peripheral functions that are operating on the main clock. Caution When the CPU is operating on the subclock and main clock oscillation is stopped, accessing a register in which a wait occurs is disabled. If a wait is generated, it can be released only by reset (see 3.4.9 (2)). 976 User's Manual U16541EJ5V1UD CHAPTER 24 STANDBY FUNCTION 24.8 Sub-IDLE Mode 24.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 in the subclock operation mode. In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other onchip peripheral functions is stopped. As a result, program execution stops and the contents of the internal RAM before the sub-IDLE mode was set are retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Because the sub-IDLE mode stops operation of the CPU, flash memory, and other on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock has been stopped, the current consumption can be reduced to a level as low as that in the STOP mode. Table 24-12 shows the operating status in the sub-IDLE mode. Cautions 1. Following the store instruction to the PSC register for setting the sub-IDLE mode, insert the five or more NOP instructions. 2. If the sub-IDLE mode is set while an unmasked interrupt request signal is being held pending, the sub-IDLE mode is then released immediately by the pending interrupt request. User's Manual U16541EJ5V1UD 977 CHAPTER 24 STANDBY FUNCTION 24.8.2 Releasing sub-IDLE mode The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-IDLE mode, or reset signal (RESET pin input, reset signal (WDT2RES) generation by overflow of watchdog timer, reset signal (LVIRES) generation by low voltage detector Note <R> (LVI) or reset signal (CLMRES) generation by clock monitor (CLM)). The PLL returns to the operating status it was in before the sub-IDLE mode was set. When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set. <R> Note V850ES/SG2 only (1) Releasing sub-IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The sub-IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. If the sub-IDLE mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the sub-IDLE mode is released, but that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-IDLE mode is released and that interrupt request signal is acknowledged. Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not released. 2. When the sub-IDLE mode is released, 12 cycles of the subclock (about 366 s) elapse from when the interrupt request signal that releases the sub-IDLE mode is generated to when the mode is released. Table 24-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal Release Source Non-maskable interrupt request Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address or the next instruction is executed. 978 User's Manual U16541EJ5V1UD The next instruction is executed. CHAPTER 24 STANDBY FUNCTION (2) Releasing sub-IDLE mode by reset The same operation as the normal reset operation is performed. Table 24-12. Operating Status in Sub-IDLE Mode Setting of Sub-IDLE Mode Item <R> Operating Status When Main Clock Is Oscillating When Main Clock Is Stopped Subclock oscillator Oscillation enabled Internal oscillator Oscillation enabled PLL Operable CPU Stops operation DMA Stops operation Interrupt controller Stops operation (but standby mode can be released) ROM correction Stops operation Timer P (TMP0 to TMP5) Stops operation Timer Q (TMP0) Stops operation Timer M (TMM0) Operable when fR/8 or fXT is selected as the count clock Watch timer Stops operation Watchdog timer 2 Operable when fR or fXT is selected as the count clock Serial interface CSIB0 to CSIB4 2 2 Stops operation Note 1 Operable when fXT is selected as the count clock Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4) I C00 to I C02 Stops operation UARTA0 to UARTA2 Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected) CAN controller Stops operation IEBus controller Stops operation A/D converter Holds operation (conversion result held) D/A converter Holds operation (output held Real-time output function (RTO) Stops operation (output held) Key interrupt function (KR) Operable CRC arithmetic circuit Stops operation External bus interface See 2.2 Pin States (same operation status as IDLE1, IDLE2 mode). Port function Retains status before sub-IDLE mode was set Internal data The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the sub-IDLE mode was set. Note 2 Note 2 ) Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock. 2. To realize low power consumption, stop the A/D and D/A converters before shifting to the sub-IDLE mode. User's Manual U16541EJ5V1UD 979 CHAPTER 25 RESET FUNCTIONS 25.1 Overview The following reset functions are available. (1) Reset sources * External reset input via the RESET pin * Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES) * System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage Note <R> (LVIRES) * System reset via the detecting clock monitor (CLM) oscillation stop (CLMRES) <R> Note V850ES/SG2 After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF). 980 User's Manual U16541EJ5V1UD CHAPTER 25 RESET FUNCTIONS (2) Emergency operation mode <R> If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset release or STOP mode release, a main clock oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock. Caution When the CPU operates on the internal oscillation clock, access to the register in which a wait state is generated is prohibited. For the register in which a wait state is generated, see 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. Figure 25-1. Block Diagram of Reset Function (a) V850ES/SG2 Internal bus Reset source flag register (RESF) WDT2RF WDT2 reset signal CLMRF LVIRF Set Set Set Clear Clear Clear CLM reset signal Reset signal RESET Reset signal to LVIM/LVIS register Reset signal LVI reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: 2. LVIS: <R> Low-voltage detection register Low-voltage detection level selection register (b) V850ES/SG2-H Internal bus Reset source flag register (RESF) WDT2RF Set CLMRF Set WDT2 reset signal Reset signal CLM reset signal Clear Clear RESET Reset signal User's Manual U16541EJ5V1UD 981 CHAPTER 25 RESET FUNCTIONS 25.2 Registers to Check Reset Source <R> The V850ES/SG2 has four kinds of reset sources, and the V850ES/SG2-H has three kinds of reset sources. After a reset has been released, the source of the reset that occurred can be checked with the reset source flag register (RESF). (1) Reset source flag register (RESF) The RESF register is a special register that can be written only by a combination of specific sequences (see 3.4.8 Special registers). The RESF register indicates the source from which a reset signal is generated. This register is read or written in 8-bit or 1-bit units. RESET pin sets this register to 00H. The default value differs if the source of reset is other than the RESET pin signal. After reset: 00HNote 1 <R> RESF 0 R/W 0 Address: FFFFF888H 0 0 0 CLMRF LVIRFNote 2 Reset signal from WDT2 WDT2RF 0 Not generated 1 Generated Reset signal from CLM CLMRF 0 Not generated 1 Generated LVIRFNote 2 <R> WDT2RF Reset signal from LVI 0 Not generated 1 Generated Notes 1. The value of the RESF register is cleared to 00H when a reset is executed via the RESET pin. When a reset is executed by the watchdog timer 2 (WDT2), clock monitor (CLM), or low-voltage detector (LVI), the reset flag of that register (WDT2RF, CLMRF, or LVIRF bit) is set; however, other sources are retained. 2. That LVIRF bit is available only in the V850ES/SG2. <R> Be sure to set bit 0 to "0" in the V850ES/SG2-H. Caution Only "0" can be written to each bit of this register. If writing "0" conflicts with setting the flag (occurrence of reset), setting the flag takes precedence. 982 User's Manual U16541EJ5V1UD CHAPTER 25 RESET FUNCTIONS 25.3 Operation 25.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released. Table 25-1. Hardware Status on RESET Pin Input Item <R> During Reset After Reset Main clock oscillator (fX) Oscillation stops Oscillation starts Subclock oscillator (fXT) Oscillation continues Internal oscillator Oscillation stops Oscillation starts Peripheral clock (fXX to fXX/1,024) Operation stops Operation starts after securing oscillation stabilization time Internal system clock (fCLK), Operation stops Operation starts after securing oscillation CPU clock (fCPU) stabilization time (initialized to fXX/8) CPU Initialized Program execution starts after securing oscillation stabilization time Watchdog timer 2 Operation stops (initialized to 0) Counts up from 0 with internal oscillation clock as source clock. Internal RAM Undefined if power-on reset or CPU access and reset input conflict (data is damaged). Otherwise value immediately after reset input is retained I/O lines (ports/alternate-function High impedance Note 1 . Note 2 pins) On-chip peripheral I/O registers Initialized to specified status, OCDM register is set (01H). Other on-chip peripheral functions Operation stops Operation can be started after securing oscillation stabilization time <R> Notes 1. The firmware of the V850ES/SG2 and V850ES/SG2-H use part of the internal RAM after the internal system reset operation has been released, because they support a boot swap function. Therefore, the contents of some RAM areas are not retained on power-on reset. For details, see 25.3.5 Operation after reset release. <R> 2. When the power is turned on, the following pins may momentarily output an undefined level. * P10/ANO0 pin * P11/ANO1 pin * P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin (the DDO pin is provided only in the flash memory version) Caution The OCDM register is initialized by the RESET pin input. Therefore, note with caution that, if a high level is input to the P05/DRST pin after a reset release before the OCDM.OCDM0 bit is cleared, the V850ES/SG2 may enter on-chip debug mode (flash memory versions only). The mask ROM versions do not support the on-chip debug mode; however the OCDM register controls the pull-down resistor connected to the P05/INTP2 pin. For details, see CHAPTER 4 PORT FUNCTIONS. User's Manual U16541EJ5V1UD 983 CHAPTER 25 RESET FUNCTIONS Figure 25-2. Timing of Reset Operation by RESET Pin Input fX fCLK Initialized to fXX/8 operation RESET Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflows Figure 25-3. Timing of Power-on Reset Operation VDD fX fCLK Initialized to fXX/8 operation RESET Analog delay Internal system reset signal Oscillation stabilization time count Must be on-chip regulator stabilization time (1 ms (max.)) or longer. 984 Overflow of timer for oscillation stabilization User's Manual U16541EJ5V1UD CHAPTER 25 RESET FUNCTIONS 25.3.2 Reset operation by watchdog timer 2 (WDT2RES) When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status. Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released. The main clock oscillator is stopped during the reset period. Table 25-2. Hardware Status During Watchdog Timer 2 Reset Operation Item During Reset After Reset Main clock oscillator (fX) Oscillation stops Oscillation starts Subclock oscillator (fXT) Oscillation continues Internal oscillator Oscillation stops Oscillation starts Peripheral clock (fXX to fXX/1,024) Operation stops Operation starts after securing oscillation stabilization time <R> Internal system clock (fCLK), Operation stops CPU clock (fCPU) CPU Operation starts after securing oscillation stabilization time (initialized to fXX/8) Initialized Program execution after securing oscillation stabilization time Watchdog timer 2 Operation stops (initialized to 0) Counts up from 0 with internal oscillation clock as source clock. Internal RAM Undefined if power-on reset or CPU access and reset input conflict (data is damaged). Otherwise value immediately after reset input is retained I/O lines (ports/alternate-function Note . High impedance pins) On-chip peripheral I/O register Initialized to specified status, OCDM register retains its value. On-chip peripheral functions other Operation stops than above <R> Operation can be started after securing oscillation stabilization time. Note The firmware of the V850ES/SG2 and V850ES/SG2-H uses part of the internal RAM after the internal system reset operation has been released because it supports a boot swap function. Therefore, the contents of some RAM areas are not retained on power-on reset. For details, see 25.3.5 Operation after reset release. User's Manual U16541EJ5V1UD 985 CHAPTER 25 RESET FUNCTIONS Figure 25-4. Timing of Reset Operation by WDT2RES Signal Generation fX fCLK Initialized to fXX/8 operation WDT2RES Analog delay Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflow 986 User's Manual U16541EJ5V1UD CHAPTER 25 RESET FUNCTIONS <R> 25.3.3 Reset operation by low-voltage detector (LVIRES) (V850ES/SG2 only) If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status. The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the LVI detection voltage. The main clock oscillator is stopped during the reset period. When the LVIMD bit = 0, an interrupt request signal (INTLVI) is generated if a low voltage is detected. Table 25-3. Hardware Status During Reset Operation by Low-Voltage Detector Item <R> During Reset After Reset Main clock oscillator (fX) Oscillation stops Oscillation starts Subclock oscillator (fXT) Oscillation continues Internal oscillator Oscillation stops Oscillation starts Peripheral clock (fXX to fXX/1,024) Operation stops Operation starts after securing oscillation stabilization time <R> Internal system clock (fCLK), Operation stops CPU clock (fCPU) CPU Operation starts after securing oscillation stabilization time (initialized to fXX/8) Initialized Program execution starts after securing oscillation stabilization time WDT2 Operation stops (initialized to 0) Counts up from 0 with internal oscillation clock as source clock. Internal RAM Undefined if power-on reset or CPU access and reset input conflict (data is damaged). Otherwise value immediately after reset input is retained I/O lines (ports/alternate-function Note . High impedance pins) <R> On-chip peripheral I/O register Initialized to specified status, OCDM register retains its value. LVI Operation continues On-chip peripheral functions other Operation stops than above Operation can be started after securing oscillation stabilization time. Note The firmware of the V850ES/SG2 uses part of the internal RAM after the internal system reset operation has been released because it supports a boot swap function. Therefore, the contents of some RAM areas are not retained on power-on reset. For details, refer to 25.3.5 Operation after reset release. Remark The reset timing of the low-voltage detector, refer to CHAPTER 27 LOW-VOLTAGE DETECTOR. User's Manual U16541EJ5V1UD 987 CHAPTER 25 RESET FUNCTIONS <R> 25.3.4 Reset operation by clock monitor (CLMRES) When the clock monitor operation is enabled, the main clock is monitored by using the sampling clock (internally oscillated clock: fR). If it is detected that the main clock is stopped, the system is reset and each hardware unit is initialized to a specific status. After it has been detected that the main clock is stopped, the CPU is placed in the reset status for a specific time (of analog delay), and then it is automatically released from the reset status. After the reset status has been released, the timer for oscillation stabilization does not perform its counting operation, because the main clock is stopped. When watchdog timer 2 that is started by default overflows, the CPU starts program execution on an internally oscillated clock (fR). The status of each hardware unit during the reset period executed by the reset signal (CLMRES) of the clock monitor operation and after the reset status is released is shown below. For the reset timing by the clock monitor operation, refer to Figure 25-5. Table 25-4. Hardware Status During Reset Operation by Clock Monitor Item During Reset After Reset Oscillation starts Note Main clock oscillator (fX) Oscillation stops Subclock oscillator (fXT) Oscillation continues Internal oscillator Oscillation stops Oscillation starts Peripheral clock (fXX to fXX/1,024) Operation stops Operation starts after securing oscillation stabilization time Internal system clock (fCLK), Operation stops CPU clock (fCPU) Note . Operation starts after securing oscillation stabilization time (initialized to fXX/8). However, if watchdog timer 2 overflows before the CPU execution, operation starts with the internal oscillation clock (fR). CPU Initialized Program execution starts after securing oscillation stabilization time. However, if watchdog timer 2 overflows before the CPU execution, operation starts with the internal oscillation clock (fR). WDT2 Operation stops (initialized to 0) Operation starts. WDT2RES is not generated, however, if only watchdog timer 2 overflows before CPU execution. Internal RAM Undefined I/O lines (ports/alternate-function pins) High impedance On-chip peripheral I/O register Initialized to specified status, OCDM register retains its value. On-chip peripheral functions other than Operation stops above Operation can be started after securing oscillation stabilization time Note When the main clock starts oscillation after the reset operation by the clock monitor. Remark 988 For details of the clock monitor, refer to CHAPTER 26 CLOCK MONITOR. User's Manual U16541EJ5V1UD Note . CHAPTER 25 RESET FUNCTIONS Figure 25-5. Reset Timing by Clock Monitor fX fR Keep oscillation stabilization time (count operation stop) fCLK Main clock operation stop fR operation Program fetch start CLMRES Main clock stop detection CLM.CLME bit RESF.CLMRF bit WDT2 count Count operation or count stop Stop Count operation Watchdog timer 2 count operation start Remark Count operation continue Watchdog timer 2 overflow (WDT2RES not occur) The mode cannot be restored by software to the normal operation mode from the internally oscillated clock operation mode. The normal operation mode can be restored only when the main clock oscillation (fX) operates normally after reset (generation of RESET, WDT2RES, or LVIRES (V850ES/SG2 only) signals). User's Manual U16541EJ5V1UD 989 CHAPTER 25 RESET FUNCTIONS 25.3.5 Operation after reset release After the reset is released, the main clock starts oscillation and oscillation stabilization time (OSTS register initial value: 216/fX) is secured, and the CPU starts program execution. WDT2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source clock. Figure 25-6. Operation After Reset Release Main clock Internal oscillation clock <R> V850ES/SG2, V850ES/SG2-H WDT2 Reset Counting of oscillation stabilization time Operation stops Normal operation (fCPU = Main clock) Operation in progress Operation stops Operation in progress Clock monitor (1) Emergent operation mode If an anomaly occurs in the main clock before oscillation stabilization time is secured, the WDT2 overflows before executing the CPU program. At this time, the CPU starts program execution by using the internal oscillation clock as the source clock. Figure 25-7. Operation After Reset Release Main clock Internal oscillation clock <R> V850ES/SG2, V850ES/SG2-H WDT2 Reset Operation stops Counting of oscillation stabilization time Operation in progress Emergency mode (fCPU = internal oscillation clock) Operation in progress (re-count) Operation stops Clock monitor WDT overflows The CPU operation clock states can be checked with the CPU operation clock status register (CCLS). 990 User's Manual U16541EJ5V1UD CHAPTER 25 RESET FUNCTIONS (2) Firmware operation (flash memory version only) In the flash memory version, after a reset is released, the on-chip firmware operates before starting the user program to support the boot switch function. Firmware operation Reset Oscillation stabilization time User program operation start V850ES/SG2: Firmware operation time: 14,974 x (1/fX) (sec.) <R> V850ES/SG2-H: Firmware operation time: 11,994 x (1/fX) (sec.) <R> Caution To accurately start the user program operation, fix the FLMD0 pin to the low level, since the reset status has been released until the stabilization oscillation time elapses and the firmware operation has been completed. Remark fX: Main clock oscillation frequency (MHz) Since the firmware uses a portion of the internal RAM, the contents of the following RAM areas are not retained through a reset even in power on status. * Version with 32 KB RAM: 03FF7000H to 03FF7095H, 03FFEFBAH to 03FFEFFFH * Version with 48 KB RAM: 03FF3000H to 03FF3095H, 03FFEFBAH to 03FFEFFFH (a) Version with 32 KB RAM (b) Version with 48 KB RAM 0 3 F F E F F F H RAM retention disabled area (70 bytes) 03FFEFBAH 03FFEFB9H 0 3 F F E F F F H RAM retention disabled area (70 bytes) 03FFEFBAH 03FFEFB9H RAM retention enabled area 03FF7096H 03FF7095H 03FF7000H RAM retention disabled area (150 bytes) RAM retention enabled area 32 KB 03FF3096H 03FF3095H 48 KB RAM retention disabled area (150 bytes) 03FF3000H User's Manual U16541EJ5V1UD 991 CHAPTER 25 RESET FUNCTIONS 25.3.6 Reset function operation flow (1/2) Start (reset source generated) Set RESF registerNote 1 Reset occurs reset release Internal oscillation and main clock oscillation start, WDT2 count up starts (reset mode) Main clock oscillation stabilization time secured? No Yes (in normal operation mode) No WDT2 overflow? Yes (in emergent operation mode) fCPU = fRNote 2 CCLS.CCLSF bit 1 WDT2 restart fCPU = fX Firmware operationNote 3 CPU operation starts from reset address (fCPU = fX/8, fR) Software processing No CCLS.CCLSF bit = 1? Yes Emergent operation No (in emergent operation mode) Normal operation No (in normal operation mode) Reset source generated? Yes 992 User's Manual U16541EJ5V1UD CHAPTER 25 RESET FUNCTIONS (2/2) Notes 1. Bit to be set differs depending on the reset source. Reset Source WDT2RF Bit CLMRF Bit LVIRF Bit (V850ES/SG2 Only) RESET pin 0 0 0 WDT2 1 Value before reset is Value before reset is retained. retained. 1 Value before reset is CLM Value before reset is retained. retained. LVI Value before reset is Value before reset is (V850ES/SG2 only) retained. retained. 1 2. The internal oscillator cannot be stopped. 3. Flash memory version only. 25.4 Valid/Invalid of Internal RAM Data (1) Internal RAM data status register (RAMS) The RAMS register is a special register. This can be written only in a special combination of sequences (see 3.4.8 Special registers). This register is a flag register that indicates whether the internal RAM is valid or not. This register can be read or written in 8-bit or 1-bit units. The set/clear conditions for the RAMF bit are shown below. * Setting conditions: Detection of voltage lower than specified level Set by instruction Generation of reset signal by WDT2 and CLM Generation of reset signal while RAM is being accessed Generation of reset signal via the RESET pin while internal RAM is being accessed. * Clearing condition: Writing of 0 in specific sequence After reset: 01H RAMS Note R/W Address: FFFFF892H 7 6 5 4 3 2 1 <0> 0 0 0 0 0 0 0 RAMF RAMF Internal RAM data valid/invalid 0 Valid 1 Invalid Note This register is set to 01H after reset by the RESET pin input (only for RAM access), watchdog timer 2 overflow, or clock monitor. After reset by other sources, the register value at that time will be retained. User's Manual U16541EJ5V1UD 993 CHAPTER 26 CLOCK MONITOR 26.1 Functions The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal (CLMRES) when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. When a reset (CLMRES) by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 25.2 Registers to Check Reset Source. The clock monitor automatically stops under the following conditions. * During oscillation stabilization time after STOP mode is released * When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS bit = 0 during main clock operation) * When the sampling clock (internal oscillation clock) is stopped * When the CPU operates with the internal oscillation clock 26.2 Configuration The clock monitor consists of the following hardware. Table 26-1. Configuration of Clock Monitor Item Configuration Control register Clock monitor mode register (CLM) Figure 26-1. Timing of Reset via Clock Monitor Main clock Internal oscillation clock Internal reset signal (CLMRES) Enable/disable CLME Clock monitor mode register (CLM) 994 User's Manual U16541EJ5V1UD CHAPTER 26 CLOCK MONITOR 26.3 Register The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.8 Special registers). This register is used to set the operation mode of the clock monitor. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H CLM R/W Address: FFFFF870H 7 6 5 4 3 2 1 <0> 0 0 0 0 0 0 0 CLME CLME Clock monitor operation enable or disable 0 Disable clock monitor operation. 1 Enable clock monitor operation. Cautions 1. Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other than reset. 2. When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the RESF.CLMRF bit is set to 1. User's Manual U16541EJ5V1UD 995 CHAPTER 26 CLOCK MONITOR 26.4 Operation This section explains the functions of the clock monitor. The start and stop conditions are as follows. <Start condition> Enabling operation by setting the CLM.CLME bit to 1 <Stop conditions> * While oscillation stabilization time is being counted after STOP mode is released * When the main clock is stopped (from when PCC.MCK bit = 1 during subclock operation to when PCC.CLS bit = 0 during main clock operation) * When the sampling clock (internal oscillation clock) is stopped * When the CPU operates with the internal oscillation clock Table 26-2. Operation Status of Clock Monitor (When CLM.CLME Bit = 1, During Internal Oscillation Clock Operation) CPU Operating Clock Operation Mode Status of Internal Status of Main Clock Status of Clock Monitor Oscillation Clock Main clock Subclock (MCK bit of Note 1 Operates Note 1 Operates Note 1 Stops Note 1 Operates Note 1 Stops HALT mode Oscillates Oscillates IDLE1, IDLE2 modes Oscillates Oscillates STOP mode Stops Oscillates Sub-IDLE mode Oscillates Oscillates Sub-IDLE mode Stops Oscillates Note 2 Note 2 Note 2 PCC register = 0) Subclock (MCK bit of PCC register = 1) Internal oscillation clock - Stops Oscillates Stops During reset - Stops Stops Stops Note 3 Notes 1. Internal oscillator can be stopped by setting the RCM.RSTOP bit to 1. 2. The clock monitor is stopped while internal oscillator is stopped. 3. Internal oscillator cannot be stopped by software. 996 User's Manual U16541EJ5V1UD CHAPTER 26 CLOCK MONITOR (1) Operation when main clock oscillation is stopped (CLME bit = 1) If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal (CLMRES) is generated as shown in Figure 26-2. Figure 26-2. Reset Period Due to That Oscillation of Main Clock Is Stopped Four internal oscillation clocks Main clock Internal oscillation clock CLMRES CLM.CLME bit RESF.CLMRF bit (2) Clock monitor status after RESET input RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When CLME bit is set to 1 by software at the end of the oscillation stabilization time of the main clock, monitoring is started. Figure 26-3. Clock Monitor Status After RESET Input (CLM.CLME bit = 1 is set after RESET input and at the end of main clock oscillation stabilization time) CPU operation Normal operation Reset Clock supply stopped Normal operation Main clock Oscillation stabilization time Internal oscillation clock RESET Set to 1 by software CLME bit Clock monitor status Monitoring Monitoring stopped User's Manual U16541EJ5V1UD Monitoring 997 CHAPTER 26 CLOCK MONITOR (3) Operation in STOP mode or after STOP mode is released If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is automatically started. Figure 26-4. Operation in STOP Mode or After STOP Mode Is Released CPU Normal operation operation STOP Oscillation stabilization time Normal operation Main clock Oscillation stops Oscillation stabilization time (set by OSTS register) Internal oscillation clock CLME bit Clock monitor status During monitor Monitor stops During monitor (4) Operation when main clock is stopped (arbitrary) During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to 1, the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor operation is automatically started when the main clock operation is started. Figure 26-5. Operation When Main Clock Is Stopped (Arbitrary) Subclock operation CPU operation PCC.MCK bit = 1 Main clock operation Oscillation stabilization time count by software Main clock Oscillation stops Oscillation stabilization time (set by OSTS register) Internal oscillation clock CLME bit Clock monitor status During monitor Monitor stops Monitor stops During monitor (5) Operation while CPU is operating on internal oscillation clock (CCLS.CCLSF bit = 1) The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1. 998 User's Manual U16541EJ5V1UD CHAPTER 27 LOW-VOLTAGE DETECTOR Low-voltage detector (LVI) is provided only to the V850ES/SG2. <R> RAM retention voltage detection operation and emulation function are provided to both the V850ES/SG2 and V850ES/SG2-H. 27.1 Functions The low-voltage detector (LVI) has the following functions. * Compares the supply voltage (VDD) and detected voltage (VLVI) and generates an internal interrupt signal or internal reset signal (LVIRES) when VDD < VLVI. * The level of the supply voltage to be detected can be changed by software (in two steps). * Interrupt or reset signal can be selected by software. If the low-voltage detector is used to generate a reset signal, the RESF.LVIRF bit is set to 1 when the LVIRES signal is generated. For details of the RESF register, refer to CHAPTER 25 RESET FUNCTION. 27.2 Configuration Figure 27-1 shows the block diagram of the low-voltage detector. Figure 27-1. Block Diagram of Low-Voltage Detector VDD VDD Low voltage detection level selector N-ch Internal reset signal (LVIRES) Selector <R> + - INTLVI Detected voltage source (VLVI) LVIS0 LVION LVIMD Low voltage detection level selection register (LVIS) LVIF Low voltage detection register (LVIM) Internal bus User's Manual U16541EJ5V1UD 999 CHAPTER 27 LOW-VOLTAGE DETECTOR 27.3 Registers The low-voltage detector is controlled by the following registers. * Low voltage detection register (LVIM) * Low voltage detection level selection register (LVIS) (1) Low voltage detection register (LVIM) The LVIM register is a special register. This can be written only in the special combination of the sequences (refer to 3.4.8 Special register). The LVIM register is used to enable or disable low voltage detection, and to set the operation mode of the lowvoltage detector. This register can be read or written in 8-bit or 1-bit units. However, the LVIF bit is read-only. After reset: Note 1 LVIM R/W Address: FFFFF890H <7> 6 5 4 3 2 <1> <0> LVION 0 0 0 0 0 LVIMD LVIF LVION Low voltage detection operation enable or disable 0 Disable operation. 1 Enable operation. LVIMD Selection of operation mode of low voltage detection 0 Generate interrupt request signal (INTLVI) when supply voltage < detected voltage. 1 Generate internal reset signal (LVIRES) when supply voltage < detected voltage. Note 2 LVIF Low voltage detection flag 0 When supply voltage > detected voltage, or when operation is disabled 1 Supply voltage of connected power supply < detected voltage Notes 1. Reset by low-voltage detection: 82H Reset due to other source: 00H 2. The value of the LVIF flag is output as the interrupt request signal (INTLVI) when the LVION bit = 1 and LVIMD bit = 0. Cautions 1. When the LVION and LVIMD bits to 1, the low-voltage detector cannot be stopped until the reset request due to other than the low-voltage detection is generated. 2. When the LVION bit is set to 1, the comparator in the LVI circuit starts operating. Wait 0.2 ms or longer by software before checking the voltage at the LVIF bit after the LVION bit is set. <R> 3. In the V850ES/SG2-H, writing to the address (FFFFF890H) of the LVIM register is prohibited. 4. Be sure to clear bits 6 to 2 to "0". 1000 User's Manual U16541EJ5V1UD CHAPTER 27 LOW-VOLTAGE DETECTOR (2) Low voltage detection level selection register (LVIS) The LVIS register is used to select the level of low voltage to be detected. This register can be read or written in 8-bit or 1-bit units. After reset: Note LVIS R/W Address: FFFFF891H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LVIS0 LVIS0 Detection level 0 3.0 V 0.15 V 1 2.85 V 0.15 V (setting prohibited) Note Reset by low-voltage detection: Retained Reset due to other source: 00H Cautions 1. This register cannot be written until a reset request due to something other than low-voltage detection is generated after the LVIM.LVION and LVIM.LVIMD bits are set to 1. <R> 2. In the V850ES/SG2-H, writing to the address (FFFFF891H) of the LVIS register is disabled. 3. Be sure to clear bits 7 to 1 to "0". User's Manual U16541EJ5V1UD 1001 CHAPTER 27 LOW-VOLTAGE DETECTOR 27.4 Operation Depending on the setting of the LVIM.VIMD bit, an interrupt signal (INTLVI) or an internal reset signal (LVIRES) is generated. How to specify each operation is described below, together with timing charts. 27.4.1 To use for internal reset signal (LVIRES) <To start operation> <1> Mask the interrupt of LVI. <2> Select the voltage to be detected by using the LVIS.LVIS0 bit. <3> Set the LVIM.LVION bit to 1 (to enable operation). <4> Insert a wait cycle of 0.2 ms (max.) or more by software. <5> By using the LVIM.LVIF bit, check if the supply voltage > detected voltage. <6> Set the LVIMD bit to 1 (to generate an internal reset signal (LVIRES)). Caution If LVIMD bit is set to 1, the contents of the LVIM and LVIS registers cannot be changed until a reset request other than LVI is generated. Figure 27-2. Operation Timing of Low-Voltage Detector (LVIMD Bit = 1) Supply voltage (VDD) LVI detected voltage (3.0 0.15 V) Time LVION bit Clear Delay Delay LVI detected signal LVI reset request signal LVIRES (active low) 1002 User's Manual U16541EJ5V1UD CHAPTER 27 LOW-VOLTAGE DETECTOR 27.4.2 To use for interrupt (INTLVI) <To start operation> <1> Mask the interrupt of LVI. <2> Select the voltage to be detected by using the LVIS.LVIS0 bit. <3> Set the LVIM.LVION bit to 1 (to enable operation). <4> Insert a wait cycle of 0.2 ms (max.) or more by software. <5> By using the LVIM.LVIF bit, check if the supply voltage > detected voltage. <6> Clear the interrupt request flag of LVI. <7> Unmask the interrupt of LVI. <To stop operation> Clear the LVION bit to 0. Figure 27-3. Operation Timing of Low-Voltage Detector (LVIMD Bit = 0) Supply voltage (VDD) LVI detected voltage (3.0 0.15 V) External RESET IC detected voltage Time LVION bit Clear Delay Delay LVI detected signal INTLVI signal Delay RESET pin Internal reset signal (active low) User's Manual U16541EJ5V1UD 1003 CHAPTER 27 LOW-VOLTAGE DETECTOR 27.5 RAM Retention Voltage Detection Operation (Provided to Both V850ES/SG2 and V850ES/SG2-H) The supply voltage and detected voltage are compared. When the supply voltage drops below the detected voltage (including on power application), the RAMS.RAMF bit is set to 1. Figure 27-4. Operation Timing of RAM Retention Voltage Detection Function Initialize RAM (RAMF bit is also cleared) VDD < 2.0 V detected Set RAMF bit Initialize RAM (RAMF bit is also cleared) Supply voltage (VDD) 2.0 V (minimum RAM retention voltage) RESET pin RAMS.RAMF bit RAM data is retained When power application, RAMF bit is set RAM data is not retained RAMF bit = 0 is retained regardless of RESET pin if VDD > 2.0 V Remarks 1. The RAMF bit is set to 1 if the supply voltage drops under the minimum RAM retention voltage (2.0 V (TYP.)). 2. The RAMF bit operates regardless of the RESET pin status. 1004 User's Manual U16541EJ5V1UD CHAPTER 27 LOW-VOLTAGE DETECTOR 27.6 Emulation Function (Provided to Both V850ES/SG2 and V850ES/SG2-H) When an in-circuit emulator is used, the operation of the RAM retention flag (RAMS.RAMF bit) can be pseudocontrolled and emulated by manipulating the PEMU1 register on the debugger. This register is valid only in the emulation mode. It is invalid in the normal mode. (1) Peripheral emulation register 1 (PEMU1) After reset: 00H PEMU1 Address: FFFFF9FEH 7 6 5 4 3 2 1 0 0 0 0 0 0 EVARAMIN 0 0 EVARAMIN Caution R/W Pseudo specification of RAM retention voltage detection signal 0 Do not detect voltage lower than RAM retention voltage. 1 Detect voltage lower than RAM retention voltage (set RAMF flag). This bit is not automatically cleared. [Usage] When an in-circuit emulator is used, pseudo emulation of RAMF is realized by rewriting this register on the debugger. <1> CPU break (CPU operation stops.) <2> Set the EVARAMIN bit to 1 by using a register write command. By setting the EVARAMIN bit to 1, the RAMF bit is set to 1 on hardware (the internal RAM data is invalid). <3> Clear the EVARAMIN bit to 0 by using a register write command again. Unless this operation is performed (clearing the EVARAMIN bit to 0), the RAMF bit cannot be cleared to 0 by a CPU operation instruction. <4> Run the CPU and resume emulation. User's Manual U16541EJ5V1UD 1005 CHAPTER 28 REGULATOR 28.1 Outline <R> The V850ES/SG2 and V850ES/SG2-H include a regulator to reduce power consumption and noise. This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffers). The regulator output voltage is set to 2.5 V (TYP.). Figure 28-1. Regulator <R> AVREF0 AVREF1 A/D converter BVDD I/O buffer BVDD D/A converter FLMD0 VDD Regulator Flash memory REGC Main/sub oscillator EVDD Internal digital circuits 2.5 V (TYP.) EVDD I/O buffer Bidirectional level shifter Caution Use the regulator with a setting of VDD = EVDD = AVREF0 = AVREF1 BVDD. 1006 User's Manual U16541EJ5V1UD CHAPTER 28 REGULATOR 28.2 Operation The regulator of this product always operates in any mode (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, or during reset). Be sure to connect a capacitor (4.7 F (recommended value)) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connection method is shown below. Figure 28-2. REGC Pin Connection Input voltage VDD REG Voltage supply to oscillator/internal logic = 2.5 V (TYP.) REGC 4.7 F (recommended) VSS User's Manual U16541EJ5V1UD 1007 CHAPTER 29 ROM CORRECTION FUNCTION 29.1 Overview The ROM correction function is used to replace part of the program in the internal ROM with the program of an external memory or the internal RAM. By using this function, program bugs found in the internal ROM can be corrected. Up to four addresses can be specified for correction. Figure 29-1. Block Diagram of ROM Correction Instruction address bus Correction address register n (CORADn) Comparator Correction control register (CORENn bit) Remark 1008 DBTRAP instruction generation block ROM Block replaced by DBTRAP instruction n = 0 to 3 User's Manual U16541EJ5V1UD Instruction data bus CHAPTER 29 ROM CORRECTION FUNCTION 29.2 Registers (1) Correction address registers 0 to 3 (CORAD0 to CORAD3) The CORAD0 to CORAD3 registers set the first address of the program to be corrected in the ROM. The program can be corrected at up to four places because four CORADn registers are provided (n = 0 to 3). The CORADn register can be read or written in 32-bit units. If the higher 16 bits of the CORADn register are used as the CORADnH register, and the lower 16 bits as the CORADnL register, these registers can be read or written in 16-bit units. Reset input clears these registers to 00000000H. Because the ROM capacity differs from one product to another, set the correction addresses in the following ranges. * PD703260, 703260Y, 703270, 703270Y, 703280, 703280Y (256 KB): 0000000H to 003FFFFH * PD703261, 703261Y, 703271, 703271Y, 703281, 703281Y, 70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y (384 KB): 0000000H to 005FFFFH <R> * D703262, 703262Y, 703272, 703272Y, 703282, 703282Y, 703262HY, 703272HY, 703282HY (512 KB): 0000000H to 007FFFFH <R> * PD703263, 703263Y, 703273, 703273Y, 703283, 703283Y, 70F3263, 70F3263Y, 70F3273, 70F3273Y, 70F3283, 70F3283Y, 703263HY, 703273HY, 703283HY, 70F3263HY, 70F3273HY, 70F3283HY (640 KB): 0000000H to 009FFFFH User's Manual U16541EJ5V1UD 1009 CHAPTER 29 ROM CORRECTION FUNCTION After reset: 00000000H R/W Address: CORAD0 FFFFF840H, CORAD0L FFFFF840H, CORAD0H FFFFF842H, CORAD1 FFFFF844H, CORAD1L FFFFF844H, CORAD1H FFFFF846H, CORAD2 FFFFF848H, CORAD2L FFFFF848H, CORAD2H FFFFF84AH, CORAD3 FFFFF84CH, CORAD3L FFFFF84CH, CORAD3H FFFFF84EH (a) 256 KB 31 18 17 1 0 CORADn Fixed to 0 Note Correction address 0 (n = 0 to 3) (b) 384 KB, 512 KB 19 18 CORADn Fixed to 0 Note 31 1 0 Correction address 0 (n = 0 to 3) (c) 640 KB 31 20 19 1 0 CORADn Fixed to 0 Correction address (n = 0 to 3) Note Cleared to 0. 1010 User's Manual U16541EJ5V1UD 0 CHAPTER 29 ROM CORRECTION FUNCTION (2) Correction control register (CORCN) The CORCN register disables or enables the correction operation at the addresses set in the CORADn register (n = 0 to 3). Each channel can be enabled or disabled by this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H CORCN R/W Address: FFFFF880H 7 6 5 4 0 0 0 0 CORENn Remark 3 2 1 0 COREN3 COREN2 COREN1 COREN0 Enables/disables correction operation 0 Disabled 1 Enabled n = 0 to 3 Table 29-1. Correspondence Between CORCN Register Bits and CORADn Registers CORCN Register Bit Corresponding CORADn Register COREN3 CORAD3 COREN2 CORAD2 COREN1 CORAD1 COREN0 CORAD0 29.3 ROM Correction Operation and Program Flow <1> If the address to be corrected and the fetch address of the internal ROM match, the fetch code is replaced by the DBTRAP instruction. <2> When the DBTRAP instruction is executed, execution branches to address 00000060H. <3> Software processing after branching causes the result of ROM correction to be judged (the fetch address and ROM correction operation are confirmed) and execution to branch to the correction software. <4> After the correction software has been executed, the return address is set, and return processing is started by the DBRET instruction. Caution The software that performs <3> and <4> must be executed in the internal ROM/RAM. User's Manual U16541EJ5V1UD 1011 CHAPTER 29 ROM CORRECTION FUNCTION Figure 29-2. ROM Correction Operation and Program Flow Reset & start Perform initial settings of microcontroller Set CORADn register Read data for setting ROM correction from external memory Load program for judgment of ROM correction and correction codes Set CORCN register CORENn bit = 1? No Yes Fetch address = CORADn? Execute fetch code No Execute fetch code Yes Change fetch code to DBTRAP instruction Execute DBTRAP instruction Jump to address 00000060H Branch to ROM correction judgment address CORADn = DBPC-2? Yes No ILGOP processing Branch to correction code address of corresponding channel n Execute correction code Write return address to DBPC. Write value of PSW to DBPSW as necessary. Execute DBRET instruction Remarks 1. : Processing by user program (software) : Processing by ROM correction (hardware) 2. n = 0 to 3 1012 User's Manual U16541EJ5V1UD CHAPTER 29 ROM CORRECTION FUNCTION 29.4 Cautions (1) When setting an address to be corrected in the CORADn register, clear the higher bits to 0 in accordance with the capacity of the internal ROM. (2) The ROM correction function cannot be used to correct data in the internal ROM. It can only be used to correct instruction codes. If ROM correction is used to correct data, that data is replaced with a DBTRAP instruction code. (3) ROM correction is not performed in regards to the ROM code before writing in the CORCNn register ends. (4) After executing a DBTRAP instruction, the PSW.NP, EP, and DI bits are set to 111, and interrupt/exception cannot be acknowledged. After executing a DBTRAP instruction, change the PSW register value as required. (5) The DBPC and DBPSW registers can be accessed while DBTRAP instructions are being executed. (6) If the addresses of the instructions executed immediately after the CORCNn register setting (enabled) are set as the correction addresses, normal operation may not be obtained (DBTRAP is not generated). User's Manual U16541EJ5V1UD 1013 CHAPTER 30 FLASH MEMORY <R> The following products are the flash memory versions of the V850ES/SG2 and V850ES/SG2-H. Caution There are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask ROM versions. When considering changing from a flash memory version to a mask ROM version during the process from experimental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions. For the electrical specifications related to the flash memory rewriting, see CHAPTER 32 ELECTRICAL SPECIFICATIONS. * PD70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y: 384 KB on-chip flash memory * PD70F3263, 70F3263Y, 70F3273, 70F3273Y, 70F3283, 70F3283Y, 70F3263HY, 70F3273HY, <R> 70F3283HY: 640 KB on-chip flash memory Flash memory versions are commonly used in the following development environments and mass production applications. <R> { For altering software after the V850ES/SG2 or V850ES/SG2-H is soldered onto the target system. { For data adjustment when starting mass production. { For differentiating software according to the specification in small scale production of various models. { For facilitating inventory management. { For updating software after shipment. 30.1 Features { 4-byte/1-clock access (when instruction is fetched) { Capacity: 640 KB/384 KB { Write voltage: Erase/write with a single power supply { Rewriting method * Rewriting by communication with dedicated flash memory programmer via serial interface (on-board/off-board programming) * Rewriting flash memory by user program (self programming) { Flash memory write prohibit function supported (security function) { Safe rewriting of entire flash memory area by self programming using boot swap function { Interrupts can be acknowledged during self programming. 1014 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY 30.2 Memory Configuration <R> The internal flash memory area of the V850ES/SG2 and V850ES/SG2-H is divided into block, as follows. * V850ES/SG2 640 KB: 16 blocks 384 KB: 12 blocks <R> * V850ES/SG2-H 640 KB: 8 blocks Can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory located at the addresses of blocks 0 and 1 is replaced by the physical memory located at the addresses of blocks 2 and 3. For details of the boot swap function, see 30.5 Rewriting by Self Programming. User's Manual U16541EJ5V1UD 1015 CHAPTER 30 FLASH MEMORY Figure 30-1. Flash Memory Mapping (1/2) (a) V850ES/SG2 (640 KB/384 KB) 000A0000H 0009FFFFH Block 15 (64 KB) 3FFFFFFH 3FFF000H 3FFEFFFH 00090000H 0008FFFFH On-chip peripheral I/O area (4 KB) Block 14 (64 KB) 00080000H 0007FFFFH Internal RAM area (48/32 KB) Block 13 (64 KB) 3FF0000H 3FEFFFFH Use prohibited 00070000H 0006FFFFH Block 21 (64 KB) 00060000H 0005FFFFH Block 11 (64 KB) Block 11 (64 KB) Use prohibited 00050000H 0004FFFFH Block 10 (64 KB) Block 10 (64 KB) 00040000H 0003FFFFH 1000000H 0FFFFFFH Block 9 (64 KB) Block 9 (64 KB) 00030000H 0002FFFFH External memory area (15 MB) 0100000H 00FFFFFH Use prohibited Block 8 (64 KB) Block 8 (64 KB) Block 7 (4 KB) Block 7 (4 KB) Block 6 (4 KB) Block 6 (4 KB) Block 5 (4 KB) Block 5 (4 KB) Block 4 (4 KB) Block 4 (4 KB) Block 3 (28 KB) Block 3 (28 KB) Block 2 (28 KB) Block 2 (28 KB) Block 1 (28 KB) 00007000H 00006FFFH Block 0 (28 KB) Block 0 (28 KB) 384 KB 640 KB 0000000H 00000000H Note Blocks 0 and 1: Boot area Blocks 2 and 3: Area used to replace boot area via boot swap function 1016 00015000H 00014FFFH 0000E000H 0000DFFFH Note Block 1 (28 KB) Internal flash memory area (640/384 KB) 00020000H 0001FFFFH 0001F000H 0001EFFFH 0001E000H 0001DFFFH 0001D000H 0001CFFFH 0001C000H 0001BFFFH User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY Figure 30-1. Flash Memory Mapping (2/2) <R> (b) V850ES/SG2-H (640 KB) 3FFFFFFH 3FFF000H 3FFEFFFH 3FF0000H 3FEFFFFH 000A0000H 0009FFFFH On-chip peripheral I/O area (4 KB) Internal RAM area (48 KB) Block 7 (128 KB) Use prohibited 00080000H 0007FFFFH Block 6 (128 KB) Use prohibited 00060000H 0005FFFFH 1000000H 0FFFFFFH Block 5 (128 KB) 00040000H 0003FFFFH External memory area (15 MB) Block 4 (128 KB) Block 3 (8 KB) 0100000H 00FFFFFH 00020000H 0001FFFFH 0001E000H 0001DFFFH Block 2 (56 KB) Use prohibited Note Block 1 (8 KB) 00A0000H 009FFFFH Internal flash memory area (640 KB) 00010000H 0000FFFFH 0000E000H 0000DFFFH Block 0 (56 KB) 0000000H 00000000H Note Blocks 0 and 1: Boot area Blocks 2 and 3: Area used to replace boot area via boot swap function User's Manual U16541EJ5V1UD 1017 CHAPTER 30 FLASH MEMORY 30.3 Functional Outline <R> The internal flash memory of the V850ES/SG2 and V850ES/SG2-H can be rewritten by using the rewrite function of the dedicated flash memory programmer, regardless of whether the V850ES/SG2 or V850ES/SG2-H has already been mounted on the target system or not (off-board/on-board programming). In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program cannot be changed by an unauthorized person. The rewrite function using the user program (self programming) is ideal for an application where it is assumed that the program is changed after production/shipment of the target system. A boot swap function that rewrites the entire flash memory area safely is also supported. In addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. Table 30-1. Rewrite Method Rewrite Method On-board programming Off-board programming Functional Outline Flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash memory programmer. Operation Mode Flash memory programming mode Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash memory programmer and a dedicated program adapter board (FA series). Self programming Flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of off-board/onboard programming. (During self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. Therefore, the rewrite program must be transferred to the internal RAM or external memory in advance). Remark 1018 The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. User's Manual U16541EJ5V1UD Normal operation mode CHAPTER 30 FLASH MEMORY Table 30-2. Basic Functions Function Block erasure Chip erasure Support (: Supported, x: Not supported) Functional Outline On-Board/Off-Board Programming Self Programming The contents of specified memory blocks are erased. The contents of the entire memory x x (Can be read by user program) area are erased all at once. Write Writing to specified addresses, and a verify check to see if write level is secured are performed. Verify/checksum Data read from the flash memory is compared with data transferred from the flash memory programmer. Blank check The erasure status of the entire memory is checked. Security setting Use of the block erase command, chip erase command, and program command can be prohibited. x (Supported only when setting is changed from enable to prohibit) The following table lists the security functions. The block erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. Each security function can be used in combination with the others at the same time. Table 30-3. Security Functions <R> Function Block erase command prohibit Function Outline Execution of a block erase command on all blocks is prohibited. Setting of prohibition can be initialized by execution of a chip erase command. Chip erase command prohibit Execution of block erase and chip erase commands on all the blocks is prohibited. Once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. Program command prohibit Execution of program and block erase commands on all the blocks is prohibited. Setting of prohibition can be initialized by execution of the chip erase command. Read command prohibit Not supported (permanently prohibited). Boot area rewrite prohibit Not supported. User's Manual U16541EJ5V1UD 1019 CHAPTER 30 FLASH MEMORY Table 30-4. Security Setting <R> Function Erase, Write, Read Operations When Each Security Is Set Notes on Security Setting (: Executable, x: Not Executable, -: Not Supported) On-Board/Off-Board Self Programming Programming On-Board/ Self Off-Board Programming Programming Block erase Block erase command: x Block erasure (FlashBlockErase): Setting of Supported only command prohibit Chip erase command: Chip erasure: - prohibition when setting is Program command: Read command: x Write (FlashWordWrite): Read (FlashWordRead): can be changed from enable to prohibit initialized by chip erase command. Chip erase Block erase command: x Block erasure (FlashBlockErase): Setting of command prohibit Chip erase command: x Chip erasure: - prohibition Program command: Read command: x Write (FlashWordWrite): Read (FlashWordRead): cannot be initialized. Program Block erase command: x Block erasure (FlashBlockErase): Setting of command prohibit Chip erase command: Chip erasure: - prohibition Program command: x Read command: x Write (FlashWordWrite): Read (FlashWordRead): can be Note initialized by chip erase command. Note In this case, since the erase command is invalid, data different from the data already written in the flash memory cannot be written. 1020 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY 30.4 Rewriting by Dedicated Flash Memory Programmer The flash memory can be rewritten by using a dedicated flash memory programmer after the V850ES/SG2 or <R> V850ES/SG2-H is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series). 30.4.1 Programming environment The following shows the environment required for writing programs to the flash memory of the V850ES/SG2 and <R> V850ES/SG2-H. Figure 30-2. Environment Required for Writing Programs to Flash Memory FLMD0 RS-232C FLMD1Note USB <R> Host machine XXXXXX XXXX STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx Cxxxxxx VDD VSS Dedicated flash V850ES/SG2, RESET memory programmer V850ES/SG2-H UARTA0/CSIB0/CSIB3 Note Connect the FLMD1 pin to the flash memory programmer or connect to GND via a pull-down resistor on the board. A host machine is required for controlling the dedicated flash memory programmer. UARTA0, CSIB0, or CSIB3 is used for the interface between the dedicated flash memory programmer and the <R> V850ES/SG2 or V850ES/SG2-H to perform writing, erasing, etc. A dedicated program adapter (FA series) required for off-board writing. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. User's Manual U16541EJ5V1UD 1021 CHAPTER 30 FLASH MEMORY 30.4.2 Communication mode <R> Communication between the dedicated flash memory programmer and the V850ES/SG2 or V850ES/SG2-H is performed by serial communication using the UARTA0, CSIB0, or CSIB3 interfaces of the V850ES/SG2, V850ES/SG2-H. (1) UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 30-3. Communication with Dedicated Flash Memory Programmer (UARTA0) XXXXXX XXXX STATVE PG-FP4 (Flash Pro4) Dedicated flash memory programmer <R> FLMD0 FLMD1Note VDD VDD GND VSS XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx Cxxxxxx FLMD0 FLMD1 RESET RESET RxD TXDA0 TxD RXDA0 V850ES/SG2, V850ES/SG2-H Note Connect the FLMD1 pin to the flash memory programmer or connect to GND via a pull-down resistor on the board. (2) CSIB0, CSIB3 Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 30-4. Communication with Dedicated Flash Memory Programmer (CSIB0, CSIB3) FLMD0 FLMD1 FLMD1Note VDD VDD GND VSS XXXXXX XXXX Bxxxxx Cxxxxxx STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx FLMD0 RESET Dedicated flash memory programmer <R> SI SO SCK RESET SOB0, SOB3 SIB0, SIB3 V850ES/SG2, V850ES/SG2-H SCKB0, SCKB3 Note Connect the FLMD1 pin to the flash memory programmer or connect to GND via a pull-down resistor on the board. 1022 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY (3) CSIB0 + HS, CSIB3 + HS Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 30-5. Communication with Dedicated Flash Memory Programmer (CSIB0 + HS, CSIB3 + HS) XXXXXX XXXX Cxxxxxx STATVE PG-FP4 (Flash Pro4) FLMD0 FLMD1 FLMD1 VDD VDD GND VSS XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx FLMD0 RESET <R> Dedicated flash memory programmer SI SO SCK HS RESET SOB0, SOB3 SIB0, SIB3 V850ES/SG2, V850ES/SG2-H SCKB0, SCKB3 PCM0 Note Connect the FLMD1 pin to the flash memory programmer or connect to GND via a pull-down resistor on the board. <R> The dedicated flash memory programmer outputs the transfer clock, and the V850ES/SG2 and V850ES/SG2-H operate as a slave. <R> When the PG-FP4 or PG-FP5 is used as the dedicated flash memory programmer, it generates the following <R> signals to the V850ES/SG2 and V850ES/SG2-H. For details, refer to the PG-FP4 User's Manual (U15260E) and the PG-FP5 User's Manual (U18865E). User's Manual U16541EJ5V1UD 1023 CHAPTER 30 FLASH MEMORY <R> Table 30-5. Signal Connections of Dedicated Flash Memory Programmer (PG-FP4, PG-FP5) <R> V850ES/SG2, PG-FP4, PG-FP5 Processing for Connection V850ES/SG2-H <R> Signal Name I/O Pin Function Pin Name FLMD0 Output Write enable/disable FLMD0 FLMD1 Output Write enable/disable FLMD1 VDD - VDD voltage generation/voltage monitor VDD GND - Ground VSS Clock output to V850ES/SG2, X1, X2 CLK Output <R> UARTA0 CSIB0, CSIB0 + HS, CSIB3 CSIB3 + HS Note 1 x Note 2 Note 1 x Note 2 Note 1 x Note 2 V850ES/SG2-H RESET Output Reset signal RESET SI/RxD Input Receive signal SOB0, SOB3/ TXDA0 SO/TxD Output SIB0, SIB3/ Transmit signal RXDA0 SCK Output Transfer clock SCKB0, SCKB3 x HS Input Handshake signal for CSIB0 + HS, CSIB3 PCM0 x x + HS communication Notes 1. Wire these pins as shown in Figures 30-6 and 30-7, or connect them to GND via pull-down resistor on board. 2. Clock cannot be supplied via the CLK pin of the flash memory programmer. Create an oscillator on board and supply the clock. Remark : Must be connected. x: Does not have to be connected. 1024 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY <R> Table 30-6. Wiring of V850ES/SG2, V850ES/SG2-H Flash Writing Adapters (FA-100GF-3BA-A, FA-100GC-8EU-A) (1/2) <R> Flash Memory Programmer Name of FA (PG-FP4, PG-FP5) Connection Pin Board Pin Signal I/O Pin Function CSIB0 + HS Used Pin Name Name SI/RxD Input Receive signal SI P41/SOB0/ CSIB0 Used Pin No. GF GC 25 23 P41/SOB0/ Pin No. GF GC 25 23 P30/TXDA0/ Pin No. GF GC 27 25 28 26 Output Transmit signal SO SCK Output Transfer clock SCK P42/SCKB0 26 24 P42/SCKB0 26 24 Not needed - - CLK Output Clock to X1 Not needed - - Not needed - - Not needed - - V850ES/SG2-H X2 Not needed - - Not needed - - Not needed - - SO/TxD V850ES/SG2, <R> 24 22 SDA01 P40/SIB0/ Pin Name SOB4 SCL01 SCL01 P40/SIB0/ Pin Name UARTA0 Used 24 22 SDA01 P31/RXDA0 /INTP7/SIB4 /RESET Output Reset signal /RESET RESET 16 14 RESET 16 14 RESET 16 14 FLMD0 Output Write voltage FLMD0 FLMD0 10 8 FLMD0 10 8 FLMD0 10 8 FLMD1 Output Write voltage FLMD1 PLD5/AD5/ 78 76 PLD5/AD5/ 78 76 PLD5/AD5/ 78 76 FLMD1 HS Input Handshake RESERVE/ signal for CSI0 HS FLMD1 FLMD1 PCM0/WAIT 63 61 Not needed - - Not needed - - VDD 11 9 VDD 11 9 VDD 11 9 BVDD 72 70 BVDD 72 70 BVDD 72 70 EVDD 36 34 EVDD 36 34 EVDD 36 34 AVREF0 3 1 AVREF0 3 1 AVREF0 3 1 + HS communication VDD - VDD voltage VDD generation/volt age monitor GND - Ground GND AVREF1 7 5 AVREF1 7 5 AVREF1 7 5 VSS 13 11 VSS 13 11 VSS 13 11 AVSS 4 2 AVSS 4 2 AVSS 4 2 BVSS 71 69 BVSS 71 69 BVSS 71 69 EVSS 35 33 EVSS 35 33 EVSS 35 33 Cautions 1. Be sure to connect the REGC pin to GND via 4.7 F capacitor. 2. Clock cannot be supplied from the CLK pin of the flash memory programmer. Create an oscillator on the board and supply clock. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) User's Manual U16541EJ5V1UD 1025 CHAPTER 30 FLASH MEMORY <R> Table 30-6. Wiring of V850ES/SG2, V850ES/SG2-H Flash Writing Adapters (FA-100GF-3BA-A, FA-100GC-8EU-A) (2/2) <R> Flash Memory Programmer Name of FA (PG-FP4, PG-FP5) Connection Pin Board Pin Signal I/O CSIB0 + HS Used Pin Function Pin Name Name CSIB3 Used Pin Name Pin No. GF GC Pin No. GF GC SI/RxD Input Receive signal SI P911/A11/SOB3 56 54 P911/A11/SOB3 56 54 SO/TxD Output Transmit signal SO P910/A10/SIB3 55 53 P910/A10/SIB3 55 53 SCK Output Transfer clock SCK P912/A12/SCKB3 57 55 P912/A12/SCKB3 57 55 CLK Output Clock to X1 Not needed - - Not needed - - X2 Not needed - - Not needed - - /RESET RESET 16 14 RESET 16 14 V850ES/SG2, <R> V850ES/SG2-H /RESET Output FLMD0 Output Write voltage FLMD0 FLMD0 10 8 FLMD0 10 8 FLMD1 Output Write voltage FLMD1 PLD5/AD5/FLMD1 78 76 PLD5/AD5/FLMD1 78 76 Handshake signal RESERVE/HS PCM0/WAIT 63 61 Not needed - - VDD VDD 11 9 VDD 11 9 BVDD 72 70 BVDD 72 70 EVDD 36 34 EVDD 36 34 AVREF0 3 1 AVREF0 3 1 AVREF1 7 5 AVREF1 7 5 VSS 13 11 VSS 13 11 AVSS 4 2 AVSS 4 2 BVSS 71 69 BVSS 71 69 EVSS 35 33 EVSS 35 33 HS Reset signal Input for CSI0 + HS communication VDD - VDD voltage generation/voltage monitor GND - Ground GND Cautions 1. Be sure to connect the REGC pin to GND via 4.7 F capacitor. 2. Clock cannot be supplied from the CLK pin of the flash memory programmer. Create an oscillator on the board and supply clock. Remark GF: 100-pin plastic QFP (14 x 20) GC: 100-pin plastic LQFP (fine pitch) (14 x 14) 1026 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY <R> Figure 30-6. Wiring Example of V850ES/SG2 Flash Writing Adapter (FA-100GF-3BA-A) (In CSIB0 + HS Mode) (1/2) D VD D N G D VD D N G 80 75 Note 2 70 65 60 55 81 51 50 Note 1 85 45 90 V850ES/SG2 40 95 35 Connect this pin to GND. Connect this pin to VDD. 100 Note 3 5 10 20 25 30 D N G D VD D VD D N G SI 31 Note 4 15 4.7 F 1 SO RFU-3 RFU-2 RFU-1 VDE SCK X1 X2 /RESET User's Manual U16541EJ5V1UD FLMD1 FLMD0 VPP RESERVE/HS 1027 CHAPTER 30 FLASH MEMORY <R> Figure 30-6. Wiring Example of V850ES/SG2 Flash Writing Adapter (FA-100GF-3BA-A) (In CSIB0 + HS Mode) (2/2) Notes 1. Corresponding pins when CSIB3 is used. 2. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 3. Create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. Here is an example of the oscillator. Example: X1 X2 4. Corresponding pins when UARTA0 is used. Caution Do not input a high level to the DRST pin. Remarks 1. Process the pins not shown in accordance with the handling of unused pins (see 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins). 2. This adapter is for the 100-pin plastic QFP package. 1028 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY <R> Figure 30-7. Wiring Example of V850ES/SG2, V850ES/SG2-H Flash Writing Adapter (FA-100GC-8EU-A) (In CSIB0 + HS Mode) (1/2) D VD D N G D VD D N G 75 76 70 65 60 55 51 Note 2 50 Note 1 80 45 85 40 V850ES/SG2, V850ES/SG2-H <R> 90 35 95 Connect this pin to GND. 30 ot e 4 Connect this pin to VDD. N 100 Note 3 5 10 15 20 26 25 D N G D VD D N G 4.7 F 1 SI SO RFU-3 RFU-2 RFU-1 VDE SCK X1 X2 /RESET User's Manual U16541EJ5V1UD D VD FLMD1 FLMD0 VPP RESERVE/HS 1029 CHAPTER 30 FLASH MEMORY <R> Figure 30-7. Wiring Example of V850ES/SG2, V850ES/SG2-H Flash Writing Adapter (FA-100GC-8EU-A) (In CSIB0 + HS Mode) (2/2) Notes 1. Corresponding pins when CSIB3 is used. 2. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor. 3. Create an oscillator on the flash writing adapter (shown in broken lines) and supply a clock. Here is an example of the oscillator. Example: X1 X2 4. Corresponding pins when UARTA0 is used. Caution Do not input a high level to the DRST pin. Remarks 1. Process the pins not shown in accordance with the handling of unused pins (see 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins). 2. This adapter is for the 100-pin plastic LQFP package. 1030 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY 30.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 30-8. Procedure for Manipulating Flash Memory Start Switch to flash memory programming mode <R> Supplies FLMD0 pulse Select communication system Manipulate flash memory End? No Yes End User's Manual U16541EJ5V1UD 1031 CHAPTER 30 FLASH MEMORY 30.4.4 Selection of communication mode <R> In the V850ES/SG2 and V850ES/SG2-H, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash memory programmer. The following shows the relationship between the number of pulses and the communication mode. Figure 30-9. Selection of Communication Mode VDD VDD VSS VDD RESET (input) VSS VDD FLMD1 (input) VSS VDD FLMD0 (input) VSS (Note) VDD RXDA0 (input) VSS VDD TXDA0 (output) Oscillation stabilized VSS Power on Communication mode selected Flash control command communication (erasure, write, etc.) Reset released Note The number of clocks is as follows depending on the communication mode. FLMD0 Pulse Communication Mode Remarks 0 UARTA0 Communication rate: 9,600 bps (after reset), LSB first <R> 8 CSIB0 V850ES/SG2, V850ES/SG2-H perform slave operation, MSB first <R> 9 CSIB3 V850ES/SG2, V850ES/SG2-H perform slave operation, MSB first <R> 11 CSIB0 + HS V850ES/SG2, V850ES/SG2-H perform slave operation, MSB first <R> 12 CSIB3 + HS V850ES/SG2, V850ES/SG2-H perform slave operation, MSB first Other RFU Setting prohibited Caution When UARTA0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash memory programmer after receiving the FLMD0 pulse. 1032 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY 30.4.5 Communication commands <R> <R> <R> The V850ES/SG2 and V850ES/SG2-H communicate with the dedicated flash memory programmer by means of commands. The signals sent from the dedicated flash memory programmer to the V850ES/SG2 and V850ES/SG2-H are called "commands". The response signals sent from the V850ES/SG2 and V850ES/SG2-H to the dedicated flash memory programmer are called "response commands". Figure 30-10. Communication Commands Command XXXXXX XXXX STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx Cxxxxxx Response command <R> Dedicated flash memory programmer V850ES/SG2, V850ES/SG2-H <R> The following shows the commands for flash memory control in the V850ES/SG2 and V850ES/SG2-H. All of these <R> commands are issued from the dedicated flash memory programmer, and the V850ES/SG2 and V850ES/SG2-H perform the processing corresponding to the commands. Table 30-7. Flash Memory Control Commands Classification Blank check Command Name Block blank check Support CSIB0, CSIB0 + HS, CSIB3 CSIB3 + HS Function UARTA0 command Erase Checks if the contents of the memory in the specified block have been correctly erased. Chip erase command Erases the contents of the entire memory. Block erase command Erases the contents of the memory of the specified block. Write Write command Writes the specified address range, and executes a contents verify check. Verify Verify command Compares the contents of memory in the specified address range with data transferred from the flash memory programmer. Checksum command Reads the checksum in the specified address range. System setting, Silicon signature control command Security setting Reads silicon signature information. Disables the chip erase command, enables command the block erase command, and disables the write command. User's Manual U16541EJ5V1UD 1033 CHAPTER 30 FLASH MEMORY 30.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash memory programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. Therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) FLMD0 pin In the normal operation mode, input a voltage of VSS level to the FLMD0 pin. In the flash memory programming mode, supply a write voltage of VDD level to the FLMD0 pin. Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of VDD level must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, see 30.5.5 (1) FLMD0 pin. Figure 30-11. FLMD0 Pin Connection Example V850ES/SG2, V850ES/SG2-H <R> Dedicated flash memory programmer connection pin FLMD0 Pull-down resistor (RFLMD0) (2) FLMD1 pin When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When VDD is supplied to the FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 30-12. FLMD1 Pin Connection Example <R> V850ES/SG2, V850ES/SG2-H FLMD1 Other device Pull-down resistor (RFLMD1) Caution If the VDD signal is input to the FLMD1 pin from another device during on-board writing and immediately after reset, isolate this signal. 1034 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY Table 30-8. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released FLMD0 FLMD1 0 Don't care VDD 0 VDD VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited (3) Serial interface pin The following shows the pins used by each serial interface. Table 30-9. Pins Used by Serial Interfaces Serial Interface Pins Used UARTA0 TXDA0, RXDA0 CSIB0 SOB0, SIB0, SCKB0 CSIB3 SOB3, SIB3, SCKB3 CSIB0 + HS SOB0, SIB0, SCKB0, PCM0 CSIB3 + HS SOB3, SIB3, SCKB3, PCM0 When connecting a dedicated flash memory programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) Conflict of signals When the dedicated flash memory programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 30-13. Conflict of Signals (Serial Interface Input Pin) <R> V850ES/SG2, V850ES/SG2-H Conflict of signals Dedicated flash memory programmer connection pins Input pin Other device Output pin In the flash memory programming mode, the signal that the dedicated flash memory programmer sends out conflicts with signals another device outputs. Therefore, isolate the signals on the other device side. User's Manual U16541EJ5V1UD 1035 CHAPTER 30 FLASH MEMORY (b) Malfunction of other device When the dedicated flash memory programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. To avoid this, isolate the connection to the other device. Figure 30-14. Malfunction of Other Device V850ES/SG2, V850ES/SG2-H <R> Dedicated flash memory programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the V850ES/SG2 and V850ES/SG2-H output affects the other device, isolate the signal on the other device side. <R> V850ES/SG2, V850ES/SG2-H <R> Dedicated flash memory programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the dedicated flash memory programmer outputs affects the other device, isolate the signal on the other device side. 1036 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY (4) RESET pin When the reset signals of the dedicated flash memory programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash memory programmer. Figure 30-15. Conflict of Signals (RESET Pin) <R> V850ES/SG2, V850ES/SG2-H Conflict of signals Dedicated flash memory programmer connection pin RESET Reset signal generator Output pin In the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash memory programmer outputs. Therefore, isolate the signals on the reset signal generator side. (5) Port pins (including NMI) When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to VDD via a resistor or connecting to VSS via a resistor. (6) Other signal pins Connect X1, X2, XT1, XT2, and REGC in the same status as that in the normal operation mode. During flash memory programming, input a low level to the DRST pin or leave it open. Do not input a high level. (7) Power supply Supply the same power (VDD, VSS, EVDD, EVSS, BVDD, BVSS, AVREF0, AVREF1, AVSS) as in normal operation mode. User's Manual U16541EJ5V1UD 1037 CHAPTER 30 FLASH MEMORY 30.5 Rewriting by Self Programming 30.5.1 Overview <R> The V850ES/SG2 and V850ES/SG2-H support a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory. Consequently, the user program can be upgraded and constant data can be rewritten in the field. Figure 30-16. Concept of Self Programming Application program Self programming library Flash function execution Flash information Flash macro service Erase, write Flash memory 1038 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY 30.5.2 Features (1) Secure self programming (boot swap function) <R> The V850ES/SG2 and V850ES/SG2-H support a boot swap function that can exchange the physical memory of blocks 0 and 1 with the physical memory of blocks 2 and 3. By writing the start program to be rewritten to blocks 2 and 3 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 and 1. Figure 30-17. Rewriting Entire Memory Area (Boot Swap) Last block Last block Block 5 Block 5 Last block Block 5 Boot swap Block 4 Block 4 Block 4 Block 3 Block 3 Block 3 Block 2 Block 2 Block 1 Block 1 Block 1 Block 0 Block 0 Block 0 Block 2 <R> Rewriting blocks 2 and 3 (2) Interrupt support The V850ES/SG2 and V850ES/SG2-H can execute interrupt servicing even while a flash function is executed during self-programming. If a maskable interrupt or non-maskable interrupt occurs, the servicing of each interrupt can be executed. Two modes of interrupt servicing are available during self-programming. * Simple mode An interrupt handler can be registered by flash function FlashSetUserHandler. Ten interrupts can be used, but the later the interrupt is registered, the lower the response of the interrupt handler. * Custom mode An interrupt handler can be registered by the user by writing an interrupt vector at the beginning of the internal RAM area. Although the beginning of the internal RAM area is occupied, as many interrupts as required can be registered and the response of the interrupts can be controlled, depending on the coding by the user. User's Manual U16541EJ5V1UD 1039 CHAPTER 30 FLASH MEMORY 30.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 30-18. Standard Self Programming Flow Flash memory manipulation Flash environment initialization processing * Disable accessing flash area * Disable setting of STOP mode * Disable stopping clock Erase processing Write processing Flash information setting processingNote 1 Internal verify processing All blocks end? No Yes Boot area swap processingNote 2 Flash environment end processing End of processing Notes 1. If a security setting is not performed, flash information setting processing does not have to be executed. 2. If boot swap is not used, flash information setting processing and boot swap processing do not have to be executed. 1040 User's Manual U16541EJ5V1UD CHAPTER 30 FLASH MEMORY 30.5.4 Flash functions Table 30-10. Flash Function List Function Name Outline Support FlashEnv Initialization of flash control macro FlashBlockErase Erasure of only specified one block FlashWordWrite Writing from specified address FlashBlockIVerify Internal verification of specified block FlashBlockBlankCheck Blank check of specified block FlashFLMDCheck Check of FLMD pin FlashStatusCheck Status check of operation specified immediately before FlashGetInfo Reading of flash information FlashSetInfo Setting of flash information FlashBootSwap Swapping of boot area FlashSetUserHandler User interrupt handler registration function 30.5.5 Pin processing (1) FLMD0 pin The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from being written during self rewriting. It is therefore necessary to keep the voltage applied to the FLMD0 pin at 0 V when reset is released and a normal operation is executed. It is also necessary to apply a voltage of VDD level to the FLMD0 pin during the self programming mode period via port control before the memory is rewritten. When self programming has been completed, the voltage on the FLMD0 pin must be returned to 0 V. <R> Caution With the flash memory version, the internal firmware operates to support the boot swapping function after reset release and before the start of the user program. To accurately start the user program operation, therefore, fix the FLMD0 pin to the low level for the duration of the oscillation stabilization time after the reset signal is released, and until the firmware operation is completed (firmware operation time of the V850ES/SG2 = 14,974 x (1/fX) seconds, firmware operation time of the V850ES/SG2-H = 11,994 x (1/fX) seconds). Figure 30-19. Mode Change Timing RESET signal VDD 0V Self programming mode VDD FLMD0 pin 0V Normal operation mode Caution Normal operation mode Make sure that the FLMD0 pin is at 0 V when reset is released. User's Manual U16541EJ5V1UD 1041 CHAPTER 30 FLASH MEMORY 30.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 30-11. Internal Resources Used Resource Name Description Entry RAM area Routines and parameters used for the flash macro service are located in this area. The (124 bytes of either internal RAM/external RAM) entry program and default parameters are copied by calling a library initialization function. Stack area (user stack + 300 bytes) An extension of the stack used by the user is used by the library (can be used in both the internal RAM and external RAM). Library code (1,900 bytes) Program entity of library (can be used anywhere other than the flash memory block to be manipulated). Application program Executed as user application. Calls flash functions. Maskable interrupt Can be used in user application execution status or self programming status. To use this interrupt in the self programming status, the interrupt servicing start address must be registered in advance by a registration function. NMI interrupt Can be used in user application execution status or self programming status. To use this interrupt in the self programming status the interrupt servicing start address must be registered in advance by a registration function. 1042 User's Manual U16541EJ5V1UD CHAPTER 31 ON-CHIP DEBUG FUNCTION The V850ES/SG2 and V850ES/SG2-H have an on-chip debug function that uses the JTAG (Joint Test Action Group) interface (DRST, DCK, DMS, DDI, and DDO pins) and that can be used via an on-chip debug emulator (IE<R> V850E1-CD-NW, QB-V850MINI). Caution The on-chip debug function is provided only in the flash memory version. It is not provided with the mask ROM version. However, the OCDM register also exists in the mask ROM version and it controls the pull-down resistor connected to the P05/INTP2 pin, so set the OCDM register even for the mask ROM version. 31.1 Features { Hardware break function: 2 points { Software break function: 4 points { Real-time RAM monitor function: Memory contents can be read during program execution. { Dynamic memory modification function (DMM function): RAM contents can be rewritten during program execution. { Mask function: RESET, NMI, HLDRQ, WAIT { ROM security function: 10-byte ID code authentication Caution The following functions are not supported. * Trace function * Event function * Debug interrupt interface function (DBINT) User's Manual U16541EJ5V1UD 1043 CHAPTER 31 ON-CHIP DEBUG FUNCTION <R> 31.2 Connection Circuit Example VDD, EVDD VDD STATUS DCK DCK DMS DMS DDI DDI DDO DDO DRSTNote 2 DRST POWER TARGET Note 1 RESET RESET FLMD0 FLMD0Note 3 FLMD1/PDL5 GND EVSS IE-V850E1-CD-NW QB-V850MINI <R> Note 4 V850ES/SG2, V850ES/SG2-H Notes 1. Example of pin processing when on-chip debug emulator is not connected 2. A pull-down resistor is provided on chip. 3. For flash memory rewriting 4. This pin processing is necessary for rewriting the internal flash memory by connecting a flash memory programmer. 31.3 Interface Signals The interface signals are described below. (1) DRST This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously initializes the debug control unit. The on-chip debug emulator raises the DRST signal when it detects VDD of the target system after the integrated debugger is started, and starts the on-chip debug unit of the device. When the DRST signal goes high, a reset signal is also generated in the CPU. When starting debugging by starting the integrated debugger, a CPU reset is always generated. (2) DCK <R> This is a clock input signal. It supplies a 20 MHz or 10 MHz clock from the on-chip debug emulator. In the onchip debug unit, the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling edge. 1044 User's Manual U16541EJ5V1UD CHAPTER 31 ON-CHIP DEBUG FUNCTION (3) DMS This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of the DMS signal. (4) DDI This is a data input signal. It is sampled in the on-chip debug unit at the rising edge of DCK. (5) DDO This is a data output signal. It is output from the on-chip debug unit at the falling edge of the DCK signal. (6) VDD, EVDD This signal is used to detect VDD of the target system. If VDD from the target system is not detected, the signals output from the on-chip debug emulator (DRST, DCK, DMS, DDI, FLMD0, and RESET) go into a highimpedance state. (7) FLMD0 The flash self programming function is used for the function to download data to the flash memory via the integrated debugger. During flash self programming, the FLMD0 pin must be kept high. In addition, connect a pull-down resistor to the FLMD0 pin. The FLMD0 pin can be controlled in either of the following two ways. <1> To control from on-chip debug emulator Connect the FLMD0 signal of the on-chip debug emulator to the FLMD0 pin. In the normal mode, nothing is driven by the on-chip debug emulator (high impedance). During a break, the on-chip debug emulator raises the FLMD0 pin to the high level when the download function of the integrated debugger is executed. <2> To control from port Connect any port of the device to the FLMD0 pin. The same port as the one used by the user program to realize the flash self programming function may be used. On the console of the integrated debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pin after executing the download function. For details, refer to the ID850QB (Integrated Debugger) Operation User's Manual. (8) RESET This is a system reset input pin. If the DRST pin is made invalid by the value of the OCDM0 bit of the OCDM register set by the user program, on-chip debugging cannot be executed. Therefore, reset is effected by the on-chip debug emulator, using the RESET pin, to make the DRST pin valid (initialization). User's Manual U16541EJ5V1UD 1045 CHAPTER 31 ON-CHIP DEBUG FUNCTION 31.4 Register (1) On-chip debug mode register (OCDM) The OCDM register is used to select the normal operation mode or on-chip debug mode. This register is a special register and can be written only in a combination of specific sequences (see 3.4.8 Special registers). This register is also used to specify whether a pin provided with an on-chip debug function is used as an onchip debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pulldown resistor of the P05/INTP2/DRST pin. The OCDM register can be written only while a low level is input to the DRST pin. This register can be read or written in 8-bit or 1-bit units. 1046 User's Manual U16541EJ5V1UD CHAPTER 31 ON-CHIP DEBUG FUNCTION After reset: 01HNote R/W Address: FFFFF9FCH < > OCDM 0 0 0 OCDM0 0 0 0 0 0 OCDM0 Operation mode Selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the P05/INTP2/DRST pin. 1 When DRST pin is low: Normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) When DRST pin is high: On-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) Note Reset by the RESET pin sets this register to 01H. <R> After reset by the overflow of watchdog timer (WDT2RES), reset by the low-voltage detector (LVI) (LVIRES) (V850ES/SG2 only), or reset by the clock monitor (CLM) (CLMRES), however, the value of the OCDM register is retained. Cautions 1. When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as port pins after external reset, any of the following actions must be taken. * Input a low level to the P05/INTP2/DRST pin. * Set the ODCM0 bit. In this case, take the following actions. <1> Clear the OCDM0 bit to 0. <2> Fix the P05/INTP2/DRST pin to the low level until <1> is completed. 2. The DRST pin has an on-chip pull-down resistor. This resistor is disconnected when the OCDM0 flag is cleared to 0. The mask ROM version does not have an on-chip debug function but it has the above pull-down resistor. With the mask ROM version also, therefore, the on-chip pull-down resistor must be disconnected by clearing the OCDM0 bit to 0. DRST OCDM0 flag (1: Pull-down ON, 0: Pull-down OFF) 10 to 100 k (30 k (TYP.)) User's Manual U16541EJ5V1UD 1047 CHAPTER 31 ON-CHIP DEBUG FUNCTION 31.5 Operation The on-chip debug function is made invalid under the conditions shown in the table below. When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0. OCDM0 Flag 0 1 L Invalid Invalid H Invalid Valid DRST Pin Remark L: Low-level input H: High-level input Figure 31-1. Timing When On-Chip Debug Function Is Not Used Releasing reset RESET Clearing OCDM0 bit OCDM0 P05/INTP2/DRST Low-level input 1048 User's Manual U16541EJ5V1UD After OCDM0 bit is cleared, high level can be input/output. CHAPTER 31 ON-CHIP DEBUG FUNCTION 31.6 ROM Security Function 31.6.1 Security ID The flash memory versions of the V850ES/SG2 and V850ES/SG2-H perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator. Set the ID code in the 10-byte on-chip flash memory area from 0000070H to 0000079H to allow the debugger perform ID authentication. If the IDs match, the security is released and reading flash memory and using the on-chip debug emulator are enabled. * Set the 10-byte ID code to 0000070H to 0000079H. * Bit 7 of 0000079H is the on-chip debug emulator enable flag. (0: Disable, 1: Enable) * When the on-chip debug emulator is started, the debugger requests ID input. When the ID code input on the debugger and the ID code set in 0000070H to 0000079H match, the debugger starts. * Debugging cannot be performed if the on-chip debug emulator enable flag is 0, even if the ID codes match. 0000080H 000007FH 000007BH 000007AH 0000079H System reserved area System reserved area (00H)Note Security ID (10 bytes) 0000070H 0000000H Note Values other than 00H can also be set. * PD70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y: Ver.1.0 <R> * PD70F3263, 70F3263Y, 70F3273, 70F3273Y, 70F3283, 70F3283Y, 70F3263HY, 70F3273HY, 70F3283HY: No applicable versions With products other than the above, operations are not affected even if 00H is set to 0000007AH. Caution When the data in the flash memory has been deleted, all the bits are set to 1. User's Manual U16541EJ5V1UD 1049 CHAPTER 31 ON-CHIP DEBUG FUNCTION <R> 31.6.2 Setting Example When the following values are set to addresses 0x70 to 0x79 Address Value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9A 0x75 0xBC 0x76 0xDE 0x77 0xF1 0x78 0x23 0x79 0xD4 0x7A 0x00 Reserved code (See 3.4.9 (3).) The following shows program examples when the CA850 is used. [Program example 1] Following the "ILGOP" section (address 0x60), enter the 10-byte security code and 1-byte system reserved area data (00H). #--------------------------------------# ILGOP handler #--------------------------------------.section "ILGOP" -- Interrupt handler address 0x60 -- Input ILGOP handler code .org 0x10 -- Skip handler address to 0x70 #--------------------------------------# SECURITYID (continue ILGOP handler) #--------------------------------------.word 0x78563412 --0-3 byte code .word 0xF1DEBC9A --4-7 byte code .hword 0xD423 --8-9 byte code .byte 0x00 --Reserve code Caution When using the CA850 Ver. 3.00 or later, specify the option for disabling the generation of the security ID. The security ID addition function by linker is added from the CA850 Ver. 3.00. As a result, errors occur during linking in the above program example. Error message: F4264: start address (0x00000070) of section "SECURITY_ID" overlaps previous section "ILGOP" ended before address (0xXXXXXXXX). 1050 User's Manual U16541EJ5V1UD CHAPTER 31 ON-CHIP DEBUG FUNCTION [Program example 2] Enter the 10-byte security code using the "SECURITY_ID" section (address 0x70). #--------------------------------------# SECURITY_ID #--------------------------------------.section "SECURITY_ID" .word 0x78563412 --0-3 byte code .word 0xF1DEBC9A --4-7 byte code .hword 0xD423 --8-9 byte code Caution Data that can be set to the "SECURITY_ID" section is limited to 10 bytes. For this reason, data cannot be set to the system reserved area (0x7A) following the security code. Consequently, when using a device that needs to set data to the system reserved area, set the security code and system reserved area data using the method shown in "Program example 1". For details on devices that need to set data to the system reserved area, refer to 3.4.9 (3) System reserved area. User's Manual U16541EJ5V1UD 1051 CHAPTER 31 ON-CHIP DEBUG FUNCTION 31.7 Cautions (1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN (program execution), the break function may malfunction. (2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal is input from a pin. (3) Because a software breakpoint set in the internal flash memory is realized by the ROM correction function, it is made temporarily invalid by target reset or internal reset generated by watchdog timer 2. The breakpoint becomes valid again when a hardware break or forced break occurs, but a software break does not occur until then. (4) Pin reset during a break is masked and the CPU and peripheral I/O are not reset. If pin reset or internal reset <R> is generated as soon as the flash memory is rewritten by DMM (Dynamic Memory Modification) or read by the RAM monitor function while the user program is being executed, the CPU and peripheral I/O may not be correctly reset. (5) Emulation of ROM correction cannot be executed. (6) When the following conditions (a) and (b) are satisfied and operation is stopped on the emulator (QB- <R> V850ESSX2, IE-703288-G1-EM1, IE-V850E1-CD-NW, QB-V850MINI) due to a break, etc., watchdog timer 2 does not stop and a reset or non-maskable interrupt occurs. When a reset occurs, the debugger hangs up. (a) The main clock or subclock is used as the source clock for watchdog timer 2. (b) The internal oscillation clock is stopped (RCM.RSTOP bit = 1). To avoid this, perform either of the following. * When an emulator is used, the internal oscillation clock is used as the source clock. * When an emulator is used, do not stop the internal oscillator. (7) When the following conditions (a) and (b) are satisfied and operation is stopped on the emulator (QB- <R> V850ESSX2, IE-703288-G1-EM1, IE-V850E1-CD-NW, QB-V850MINI) due to a break, etc., TMM does not stop even if the peripheral break function is set to "Break". (a) Either the INTWT, internal oscillation clock (fR/8), or subclock is selected as the TMM source clock. (b) The main clock is stopped. To avoid this, perform either of the following. * When an emulator is used, the main clock (fXX, fXX/2, fXX/4, fXX/64, fXX/512) is used as the source clock. * When an emulator is used, do not stop the main clock oscillation. (8) In the on-chip debug mode, the DDO pin is forcibly set to the high-level output. 1052 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.1 Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD Conditions VDD = EVDD = AVREF0 = AVREF1 BVDD Input voltage Ratings Unit -0.5 to +4.6 V -0.5 to +4.6 V EVDD VDD = EVDD = AVREF0 = AVREF1 -0.5 to +4.6 V AVREF0 VDD = EVDD = AVREF0 = AVREF1 -0.5 to +4.6 V AVREF1 VDD = EVDD = AVREF0 = AVREF1 -0.5 to +4.6 V VSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V AVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V BVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 V EVSS VSS = EVSS = BVSS = AVSS -0.5 to +0.5 VI1 VI2 RESET, FLMD0 Note 1 , PDH4, PDH5 PCM0 to PCM3, PCT0, PCT1, PCT4, PCT6, V -0.5 to EVDD + 0.5 Note 2 V -0.5 to BVDD + 0.5 Note 2 V PDH0 to PDH3, PDL0 to PDL15 P10, P11 -0.5 to AVREF1 + 0.5 Note 2 V VI4 X1, X2, XT1, XT2 -0.5 to VRO Note 2 V VI5 P02 to P06, P30 to P39, P40 to P42, P50 to VI3 Note 3 + 0.5 -0.5 to +6.0 V P55, P90 to P915 Analog input voltage VIAN P70 to P711 -0.5 to AVREF0 + 0.5 Note 2 V Notes 1. Flash memory version only 2. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 3. On-chip regulator output voltage (2.5 V (TYP.)) User's Manual U16541EJ5V1UD 1053 CHAPTER 32 ELECTRICAL SPECIFICATIONS (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions IOH Per pin 4 mA P50 to P55, P90 to P915, PDH4, PDH5 Total of all pins 50 mA PCM0 to PCM3, PCT0, PCT1, PCT4, mA Per pin 4 PCT6, PDH0 to PDH3, PDL0 to PDL15 Total of all pins 50 mA P10, P11 Per pin 4 mA Total of all pins 8 mA Per pin 4 mA Total of all pins 20 mA P02 to P06, P30 to P39, P40 to P42, Per pin -4 mA P50 to P55, P90 to P915, PDH4, PDH5 Total of all pins -50 mA PCM0 to PCM3, PCT0, PCT1, PCT4, mA Per pin -4 PCT6, PDH0 to PDH3, PDL0 to PDL15 Total of all pins -50 mA P10, P11 Per pin -4 mA Total of all pins -8 mA Per pin -4 mA Total of all pins -20 mA -40 to +85 C Mask ROM versions -65 to +150 C Flash memory versions -40 to +125 C P70 to P711 Operating ambient temperature TA Storage temperature Tstg Unit P02 to P06, P30 to P39, P40 to P42, P70 to P711 Output current, high Ratings Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 1054 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.2 Capacitance <R> (TA = 25C, VDD = EVDD = BVDD = AVREF0 = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V) Parameter I/O capacitance Symbol Conditions MIN. TYP. fX = 1 MHz CIO MAX. Unit 10 pF Unmeasured pins returned to 0 V 32.3 Operating Conditions (1) V850ES/SG2 (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Internal System Clock Supply Voltage Conditions Frequency VDD EVDD Unit AVREF0, BVDD AVREF1 fXX = 2.5 to 20 MHz C = 4.7 F, 2.85 to 3.6 2.85 to 3.6 2.7 to 3.6 2.85 to 3.6 V 3.0 to 3.6 3.0 to 3.6 2.7 to 3.6 3.0 to 3.6 V 2.85 to 3.6 2.85 to 3.6 2.7 to 3.6 2.85 to 3.6 V A/D converter stop, D/A converter stop C = 4.7 F, A/D converter operating, D/A converter operating fXT = 32.768 kHz C = 4.7 F, A/D converter stop, D/A converter stop <R> (2) V850ES/SG2-H (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Internal System Clock Conditions Frequency VDD fXX = 2.5 to 32 MHz Stabilization capacitance C = 4.7 F fXT = 32.768 kHz connected to REGC pin, Unit Supply Voltage EVDD BVDD AVREF0 AVREF1 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V All function operating User's Manual U16541EJ5V1UD 1055 CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.4 Oscillator Characteristics 32.4.1 Main clock oscillator characteristics (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Resonator <R> Circuit Example Parameter Ceramic Oscillation resonator/ frequency (fX) Conditions MIN. V850ES/SG2 2.5 V850ES/SG2-H 2.5 TYP. MAX. Unit 10 MHz 8 MHz Note 1 X1 Crystal resonator X2 Oscillation After reset is stabilization released time 16 Note 2 After STOP mode is 1 Note 4 2 /fX s Note 3 ms Note 3 s released After IDLE2 mode is Note 4 350 released Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/SG2 so that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC Characteristics. 2. Time required from start of oscillation until the resonator stabilizes. 3. The value varies depending on the setting of the OSTS register. 4. Time required to set up the flash memory (flash memory version only). Secure the setup time using the OSTS register. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. 1056 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS <R> (i) KYOCERA KINSEKI CORPORATION: Crystal resonator (TA = -40 to +85C) Manufacturer Circuit Example KYOCERA KINSEKI CORPORATION - CX-5FD (capacitance : 8 pF) X1 X2 - CX-49G (capacitance : 8 pF) - HC-49/U-S (capacitance : 8 pF) Recommended Circuit Constant Oscillation Voltage Range fX (kHz) C1 (pF) C2 (pF) Rd (k) MIN. (V) MAX. (V) 4,000 8 8 - 2.85 3.6 5,000 8 8 - 2.85 3.6 8,000 8 8 - 2.85 3.6 10,000 8 8 - 2.85 3.6 3,145.72 8 8 - 2.85 3.6 4,718.592 8 8 - 2.85 3.6 6,291.456 8 8 - 2.85 3.6 Rd C1 About other resonator's type name, refer to the resonator manufacturer. Caution Oscillation Frequency (Part Number) C2 This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/SG2 and V850ES/SG2-H so that the internal operating conditions are within the specifications of the DC and AC characteristics. Remark Contact : KYOCERA Electronic components & devices http://global.kyocera.com/prdct/electro/index.html Resonator vs. IC matching search http://www3.kyocera.co.jp/electro/app/en/searchTopShow.do User's Manual U16541EJ5V1UD 1057 CHAPTER 32 ELECTRICAL SPECIFICATIONS <R> (ii) Murata Mfg. Co. Ltd.: Ceramic resonator (TA = -40 to +85C) Manufacturer Oscillation Circuit Example Part Number Recommended Circuit Oscillation Voltage Constant Range Frequency fX (MHz) Murata Mfg. 4.000 CSTCR4M00G55B-R0 C1 C2 Rd MIN. MAX. (pF) (pF) (k) (V) (V) 0 2.85 3.6 0 2.85 3.6 0 2.85 3.6 0 2.85 3.6 0 2.85 3.6 0 2.85 3.6 0 2.85 3.6 0 2.85 3.6 0 2.85 3.6 0 2.85 3.6 on-chip on-chip (39) Co. Ltd. CSTCR4M00G15C**-R0 on-chip on-chip (39) 5.000 CSTCR5M00G55B-R0 (39) X2 6.000 CSTCR6M00G55B-R0 Rd C1 on-chip on-chip (39) C2 CSTCR6M00G15C**-R0 8.000 CSTCE8M00G55A-R0 CSTCE10M0G55A-R0 (33) on-chip on-chip (33) CSTCE10M0G15C**-R0 (33) on-chip on-chip (33) 10.000 (39) on-chip on-chip (33) CSTCE8M00G15C**-R0 (39) on-chip on-chip (39) (33) on-chip on-chip (33) Caution (39) on-chip on-chip (39) X1 (39) on-chip on-chip (39) CSTCR5M00G15C**-R0 (39) (33) This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/SG2 and V850ES/SG2-H so that the internal operating conditions are within the specifications of the DC and AC characteristics. Remarks 1. The total tolerance of a product having "**" in its part number can be adjusted up to 3000 ppm. 2. Contact: Product Engineering Service Section Piezoelectric Components Department I Piezoelectric Components Division Device Business Unit Murata Mfg. Co., Ltd. TEL: +81-75-955-6915 E-mail: piezo@murata.co.jp IC Part Number -> Ceramic Resonator Search: http://search.murata.co.jp/Ceramy/CeMenu_en.do 1058 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.4.2 Subclock oscillator characteristics (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Resonator Crystal Circuit Example XT1 XT2 Parameter Conditions Oscillation frequency MIN. TYP. MAX. Unit 32 32.768 35 kHz 10 s Note 1 (fXT) resonator Oscillation stabilization time Note 2 Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/SG2 and V850ES/SG2-H so that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC Characteristics. 2. Time required from when VDD reaches the following oscillation voltage range to when the crystal resonator stabilizes. <R> * V850ES/SG2: 2.85 V (MIN.) * V850ES/SG2-H: 3.0 V (MIN.) Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. 3. For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. User's Manual U16541EJ5V1UD 1059 CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.4.3 PLL characteristics (1) V850ES/SG2 (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Input frequency fX Output frequency fXX Lock time tPLL Conditions MIN. TYP. MAX. Unit x4 mode 2.5 5 MHz x8 mode 2.5 2.5 MHz x4 mode 10 20 MHz x8 mode 20 20 MHz 800 s MAX. Unit 5 MHz After VDD reaches 2.85 V (MIN.) <R> (2) V850ES/SG2-H (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Input frequency fX Output frequency fXX Lock time tPLL Conditions MIN. TYP. x4 mode 2.5 x8 mode 2.5 4 MHz x4 mode 10 20 MHz x8 mode 20 32 MHz 800 s After VDD reaches 3.0 V (MIN.) 32.4.4 Internal oscillator characteristics (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Output frequency 1060 Symbol Conditions fR User's Manual U16541EJ5V1UD MIN. TYP. MAX. Unit 100 200 400 kHz CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.5 Regulator Characteristics (1) V850ES/SG2 (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Input voltage VDD Output voltage VRO Regulator output tREG Conditions MIN. fXX = 20 MHz (MAX.) TYP. 2.85 MAX. Unit 3.6 V 2.5 After VDD reaches 2.85 V (MIN.), V 1 ms MAX. Unit 3.6 V 1 ms Stabilization capacitance C = 4.7 F stabilization time connected to REGC pin <R> (2) V850ES/SG2-H (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input voltage Symbol VDD Output voltage VRO Regulator output tREG Conditions MIN. fXX = 32 MHz (MAX.) TYP. 3.0 2.5 After VDD reaches 3.0 V (MIN.), V Stabilization capacitance C = 4.7 F stabilization time connected to REGC pin VDD tREG VRO RESET User's Manual U16541EJ5V1UD 1061 CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.6 DC Characteristics 32.6.1 I/O level (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input voltage, high Symbol VIH1 Conditions PDH4, PDH5 Note VIH2 RESET, FLMD0 VIH3 P02 to P06, P30 to P37, P42, P50 to P55, MIN. TYP. MAX. Unit 0.7EVDD EVDD V 0.8EVDD EVDD V 0.8EVDD 5.5 V P92 to P915 VIH4 P38, P39, P40, P41, P90, P91 0.7EVDD 5.5 V VIH5 PCM0 to PCM3, PCT0, PCT1, PCT4, 0.7BVDD BVDD V PCT6, PDH0 to PDH3, PDL0 to PDL15 Input voltage, low VIH6 P70 to P711 0.7AVREF0 AVREF0 V VIH7 P10, P11 0.7AVREF1 AVREF1 V VIL1 PDH4, PDH5 EVSS 0.3EVDD V EVSS 0.2EVDD V EVSS 0.2EVDD V Note VIL2 RESET, FLMD0 VIL3 P02 to P06, P30 to P37, P42, P50 to P55, P92 to P915 VIL4 P38, P39, P40, P41, P90, P91 EVSS 0.3EVDD V VIL5 PCM0 to PCM3, PCT0, PCT1, PCT4, BVSS 0.3BVDD V PCT6, PDH0 to PDH3, PDL0 to PDL15 VIL6 P70 to P711 AVSS 0.3AVREF0 V VIL7 P10, P11 AVSS 0.3AVREF1 V Input leakage current, high ILIH VI = VDD = EVDD = BVDD = AVREF0 = AVREF1 5 A Input leakage current, low ILIL VI = 0 V -5 A Output leakage current, high ILOH VO = VDD = EVDD = BVDD = AVREF0 = 5 A -5 A AVREF1 Output leakage current, low ILOL VO = 0 V Note Flash memory version only Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 1062 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Output voltage, high VOH1 <R> Conditions MIN. P02 to P06, Per pin Total of all pins P30 to P39, IOH = -1.0 mA -20 mA P40 to P42, Per pin Total of all pins P50 to P55, IOH = -100 A -4.2 mA Per pin Total of all pins P90 to P915, TYP. MAX. Unit EVDD - 1.0 EVDD V EVDD - 0.5 EVDD V BVDD - 1.0 BVDD V BVDD - 0.5 BVDD V AVREF0 - 1.0 AVREF0 V AVREF0 - 0.5 AVREF0 V AVREF1 - 1.0 AVREF1 V AVREF1 - 0.5 AVREF1 V 0 0.4 V 0 0.4 V 0 0.4 V 0 0.4 V 100 k PDH4, PDH5 VOH2 PCM0 to PCM3, PCT0, IOH = -1.0 mA -20 mA PCT1, PCT4, Per pin Total of all pins PCT6, PDH0 IOH = -100 A -2.8 mA Per pin Total of all pins IOH = -0.4 mA -4.8 mA Per pin Total of all pins IOH = -100 A -1.2 mA Per pin Total of all pins IOH = -0.4 mA -0.8 mA Per pin Total of all pins IOH = -100 A -0.2 mA P02 to P06, Per pin Total of all pins P30 to P37, IOL = 1.0 mA 20 mA to PDH3, PDL0 to PDL15 VOH3 VOH4 Output voltage, low VOL1 P70 to P711 P10, P11 P42, P50 to P55, P92 to P915, PDH4, PDH5 VOL2 P38, P39, Per pin P40, P41, IOL = 3.0 mA P90, P91 VOL3 PCM0 to Per pin PCM3, PCT0, IOL = 1.0 mA Total of all pins 20 mA PCT1, PCT4, PCT6, PDH0 to PDH3, PDL0 to PDL15 VOL4 Software pull-down R1 P10, P11, Per pin Total of all pins P70 to P711 IOL = 0.4 mA 5.6 mA P05 VI = VDD 10 30 resistor Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 2. When the IOH and IOL conditions are not satisfied for a pin but the total value of all pins is satisfied, only that pin does not satisfy the DC characteristics. User's Manual U16541EJ5V1UD 1063 CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.6.2 Supply current (1) V850ES/SG2 (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Supply current Symbol Note 1 IDD1 (mask ROM version) IDD2 Conditions Normal fXX = 20 MHz (fX = 5 MHz), operation peripheral function operating HALT mode MIN. fXX = 20 MHz (fX = 5 MHz), TYP. MAX. Unit 21 32 mA 15 24 mA peripheral function operating IDD3 IDLE1 mode fXX = 5 MHz (fX = 5 MHz), PLL off 0.3 0.8 mA IDD4 IDLE2 mode fXX = 5 MHz (fX = 5 MHz), PLL off 0.3 0.8 mA IDD5 Subclock fXT = 32.768 kHz, 50 100 A operating mode main clock, internal oscillator stopped 15 70 A 6 50 A 10 60 A 10 60 A Note 2 32 48 mA Note 3 30 45 mA Note 2 17 26 mA Note 3 16 24 mA IDD6 Sub-IDLE mode fXT = 32.768 kHz, main clock, internal oscillator stopped IDD7 STOP mode Subclock stopped, internal oscillator stopped Subclock operating, internal oscillator stopped Subclock stopped, internal oscillator operating Supply current Note 1 IDD1 (flash memory Normal fXX = 20 MHz (fX = 5 MHz), operation peripheral function operating version) IDD2 HALT mode fXX = 20 MHz (fX = 5 MHz), peripheral function operating IDD3 IDLE1 mode fXX = 5 MHz (fX = 5 MHz), PLL off 0.8 1.6 mA IDD4 IDLE2 mode fXX = 5 MHz (fX = 5 MHz), PLL off 0.3 0.8 mA IDD5 Subclock fXT = 32.768 kHz, main clock, Note 2 300 600 A operating mode internal oscillator stopped Note 3 200 400 A Note 2 18 100 A Note 3 18 80 A 6 50 A 10 60 A 10 60 A Note 2 35 54 mA Note 3 33 51 mA IDD6 Sub-IDLE mode fXT = 32.768 kHz, main clock, internal oscillator stopped IDD7 STOP mode Subclock stopped, internal oscillator stopped Subclock operating, internal oscillator stopped Subclock stopped, internal oscillator operating IDD8 Flash memory fXX = 20 MHz (fX = 5 MHz) programming mode Notes 1. Total of VDD, EVDD, and BVDD currents. Current flowing through the output buffers, A/D converter, D/A converter, and on-chip pull-down resistor is not included. 2. 640 KB flash memory version: PD70F3263, 70F3263Y, 70F3273, 70F3273Y, 70F3283, 70F3283Y 3. 384 KB flash memory version: PD70F3261, 70F3261Y, 70F3271, 70F3271Y, 70F3281, 70F3281Y 1064 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS <R> (2) V850ES/SG2-H (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Supply current Note Symbol Conditions IDD1 Normal operation fXX = 32 MHz (fX = 4 MHz), peripheral function operating IDD2 HALT mode (mask ROM version) fXX = 32 MHz (fX = 4 MHz), MIN. TYP. MAX. Unit 35 55 mA 27 40 mA 0.3 0.8 mA 0.3 0.8 mA 50 100 A 15 70 A 6 50 A 10 60 A 10 60 A 50 70 mA 30 40 mA 0.8 1.6 mA 0.3 0.8 mA 300 600 A 18 100 A 7 50 A 10 60 A 10 60 A 55 80 mA peripheral function operating IDD3 fXX = 4 MHz (fX = 4 MHz), IDLE1 mode PLL off IDD4 fXX = 4 MHz (fX = 4 MHz), IDLE2 mode PLL off IDD5 IDD6 Subclock fXT = 32.768 kHz, main clock, operating mode internal oscillator stopped Sub-IDLE mode fXT = 32.768 kHz, main clock, internal oscillator stopped IDD7 Subclock stopped, STOP mode internal oscillator stopped Subclock operating, internal oscillator stopped Subclock stopped, internal oscillator operating Supply current Note IDD1 Normal operation fXX = 32 MHz (fX = 4 MHz), peripheral function operating (flash memory version) IDD2 fXX = 32 MHz (fX = 4 MHz), HALT mode peripheral function operating IDD3 fXX = 4 MHz (fX = 4 MHz), IDLE1 mode PLL off IDD4 fXX = 4 MHz (fX = 4 MHz), IDLE2 mode PLL off IDD5 IDD6 Subclock fXT = 32.768 kHz, main clock, operating mode internal oscillator stopped Sub-IDLE mode fXT = 32.768 kHz, main clock, internal oscillator stopped IDD7 Subclock stopped, internal STOP mode oscillator stopped Subclock operating, internal oscillator stopped Subclock stopped, internal oscillator operating IDD8 Flash memory fXX = 32 MHz (fX = 4 MHz) programming mode Note Total of VDD, EVDD, and BVDD currents. Current flowing through the output buffers, A/D converter, D/A converter, and on-chip pull-down resistor is not included. User's Manual U16541EJ5V1UD 1065 CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.7 Data Retention Characteristics (1) In STOP mode (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Symbol Data retention voltage VDDDR Conditions MIN. STOP mode (all functions TYP. 1.9 MAX. Unit 3.6 V 50 A stopped) <R> Data retention current IDDDR STOP mode (all functions 6 stopped) Supply voltage rise time tRVD s 200 Supply voltage fall time tFVD 200 s Supply voltage retention time tHVD After STOP mode setting 0 ms STOP release signal input time tDREL Note 0 ms Data retention input voltage, high VIHDR VDD = EVDD = BVDD = VDDDR 0.9VDDDR VDDDR V Data retention input voltage, low VILDR VDD = EVDD = BVDD = VDDDR 0 0.1VDDDR V Note V850ES/SG2: <R> After VDD reaches 2.85 V (MIN.) V850ES/SG2-H: After VDD reaches 3.0 V (MIN.) Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit VDD/EVDD/BVDD tHVD tFVD tRVD VDDDR VIHDR RESET (input) STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) 1066 VIHDR VILDR User's Manual U16541EJ5V1UD STOP release signal input tDREL CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.8 AC Characteristics (1) AC Test Input Measurement Points (VDD, AVREF0, AVREF1, EVDD, BVDD) VDD VIH VIH Measurement points 0V VIL VIL (2) AC Test Output Measurement Points VOH VOH Measurement points VOL VOL (3) Load Conditions DUT (Device under measurement) Caution CL = 50 pF If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. User's Manual U16541EJ5V1UD 1067 CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.8.1 CLKOUT output timing (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Output cycle Symbol tCYK <1> <R> Conditions tWKH MAX. 50 ns 31.25 s 31.25 ns 31.25 s V850ES/SG2 V850ES/SG2-H High-level width MIN. <2> tCYK/2 - 10 tCYK/2 - 10 Unit ns Low-level width tWKL <3> Rise time tKR <4> 10 ns ns Fall time tKF <5> 10 ns Clock Timing <1> <2> <3> CLKOUT (output) <4> <5> 32.8.2 Bus timing (1) In multiplexed bus mode <R> Caution When the V850ES/SG2-H is operated at fXX > 20 MHz, be sure to insert the address hold wait and the address setup wait. 1068 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS (a) Read/write cycle (CLKOUT asynchronous) (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. tSAST <6> (0.5 + tASW)T - 20 ns Address hold time (from ASTB) tHSTA <7> (0.5 + tAHW)T - 15 ns Delay time from RD to address float tFRDA <8> Data input setup time from address tSAID <9> Data input setup time from RD tSRID <10> (1 + n)T - 25 ns Delay time from ASTB to RD, WRm tDSTRDWR <11> (0.5 + tAHW)T - 15 ns Data input hold time (from RD) tHRDID <12> 0 ns Address output time from RD tDRDA <13> Note 1 (1 + i)T - 15 ns Note 2 (1 + i)T - 10 ns 0.5T - 15 ns <R> Note 1 16 ns 10 ns (2 + n + tASW + tAHW)T - 35 ns Delay time from RD, WRm to ASTB tDRDWRST <14> Note 1 Note 2 0.5T - 10 ns Delay time from RD to ASTB tDRDST <15> Note 1 (1.5 + i + tASW)T - 15 ns Note 2 (1.5 + i + tASW)T - 10 ns Note 1 (1 + n)T - 15 ns Note 2 (1 + n)T - 10 ns Note 1 (1 + i + tASW)T - 15 ns Note 2 (1 + i + tASW)T - 10 ns <R> <R> RD, WRm low-level width tWRDWRL <16> <R> <R> Unit Address setup time (to ASTB) Note 2 <R> MAX. ASTB high-level width tWSTH <17> <R> Data output time from WRm tDWROD Data output setup time (to WRm) tSODWR <19> (1 + n)T - 20 ns Data output hold time (from WRm) tHWROD <20> T - 15 ns WAIT setup time (to address) tSAWT1 <21> tSAWT2 <22> tHAWT1 <23> tHAWT2 <24> tSSTWT1 <25> tSSTWT2 <26> tHSTWT1 <27> tHSTWT2 <28> WAIT hold time (from address) WAIT setup time (to ASTB) WAIT hold time (from ASTB) <18> 15 n1 n1 ns (1.5 + tASW + tAHW)T - 35 ns (1.5 + n + tASW + tAHW)T - 35 ns (0.5 + n + tASW + tAHW)T ns (1.5 + n + tASW + tAHW)T ns n1 n1 (1 + tAHW)T - 25 ns (1 + n + tAHW)T - 25 ns (n + tAHW)T ns (1 + n + tAHW)T ns Notes 1. V850ES/SG2 <R> 2. V850ES/SG2-H Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: Number of idle states inserted after a read cycle (0 or 1) 6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16541EJ5V1UD 1069 CHAPTER 32 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode T1 T2 TW T3 CLKOUT (output) A16 to A21 (output) <9> AD0 to AD15 (I/O) Hi-Z Address <6> Data <7> <12> ASTB (output) <17> <14> <8> <11> <10> <13> <15> RD (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Remark 1070 WR0 and WR1 are high level. User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode T1 T2 TW T3 CLKOUT (output) A16 to A21 (output) AD0 to AD15 (I/O) Address <6> ASTB (output) Data <7> <17> <18> <11> <14> <19> <20> WR0, WR1 (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Remark RD is high level. User's Manual U16541EJ5V1UD 1071 CHAPTER 32 ELECTRICAL SPECIFICATIONS (b) Read/write cycle (CLKOUT synchronous): In multiplexed bus mode (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit Delay time from CLKOUT to address tDKA <29> 0 25 ns Delay time from CLKOUT to address tFKA <30> 0 19 ns Delay time from CLKOUT to ASTB tDKST <31> -12 7 ns Delay time from CLKOUT to RD, WRm tDKRDWR <32> -5 14 ns Data input setup time (to CLKOUT) tSIDK <33> 15 ns Data input hold time (from CLKOUT) tHKID <34> 5 ns Data output delay time from CLKOUT tDKOD <35> WAIT setup time (to CLKOUT) tSWTK <36> 20 ns WAIT hold time (from CLKOUT) tHKWT <37> 5 ns float 19 ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. Read Cycle (CLKOUT Synchronous): In Multiplexed Bus Mode T1 T2 TW T3 CLKOUT (output) <29> A16 to A21 (output) <33> <34> <30> AD0 to AD15 (I/O) Hi-Z Address Data <31> <31> ASTB (output) <32> <32> RD (output) WAIT (input) <36> Remark 1072 <37> <36> WR0 and WR1 are high level. User's Manual U16541EJ5V1UD <37> CHAPTER 32 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous): In Multiplexed Bus Mode T1 T2 TW T3 CLKOUT (output) <29> A16 to A21 (output) <35> AD0 to AD15 (I/O) Address Data <31> <31> ASTB (output) WR0, WR1 (output) <32> <32> WAIT (input) <36> Remark <37> <36> <37> RD is high level. User's Manual U16541EJ5V1UD 1073 CHAPTER 32 ELECTRICAL SPECIFICATIONS (2) In separate bus mode <R> Cautions 1. When the V850ES/SG2-H is operated at fXX > 20 MHz, be sure to insert an address hold wait and an address setup wait. 2. When the V850ES/SG2-H is operated at fXX > 20 MHz, be sure to insert at least one data wait. <R> (a) Read cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Address setup time (to RD) Symbol tSARD Conditions Unit (0.5 + tASW)T - 23 ns V850ES/SG2-H (0.5 + tASW)T - 25 ns <39> iT + 1 ns RD low-level width tWRDL <40> (1.5 + n + tAHW)T - 10 ns Data setup time (to RD) tSISD <41> 23 ns Data hold time (from RD) tHISD <42> 0 ns Data setup time (to address) tSAID <43> (2 + n + tASW + tAHW)T - 40 ns WAIT setup time (to RD) tSRDWT1 <44> (0.5 + tAHW)T - 25 ns tSRDWT2 <45> (0.5 + n + tAHW)T - 25 ns tHRDWT1 <46> (n - 0.5 + tAHW)T ns tHRDWT2 <47> (n + 0.5 + tAHW)T ns tSAWT1 <48> (1 + tASW + tAHW)T - 45 ns tSAWT2 <49> (1 + n + tASW + tAHW)T - 45 ns tHAWT1 <50> (n + tASW + tAHW)T ns tHAWT2 <51> (1 + n + tASW + tAHW)T ns WAIT hold time (from RD) WAIT setup time (to address) <R> tHARD MAX. V850ES/SG2 <38> <R> Address hold time (from RD) MIN. WAIT hold time (from address) Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted 4. i: Number of idle states inserted after a read cycle (0 or 1) 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 1074 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Separate Bus Mode TW T1 T2 CLKOUT (output) A0 to A21 (output) <39> <43> AD0 to AD15 (I/O) Hi-Z Hi-Z <42> <38> <41> <40> RD (output) <47> <45> <46> <44> WAIT (input) <48> <50> <49> <51> Remark WR0 and WR1 are high level. User's Manual U16541EJ5V1UD 1075 CHAPTER 32 ELECTRICAL SPECIFICATIONS (b) Write cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit V850ES/SG2 (1 + tASW + tAHW)T - 23 V850ES/SG2-H (1 + tASW + tAHW)T - 25 ns 0.5T - 10 ns <54> (0.5 + n)T - 10 ns tDOSDW <55> -5 ns Data setup time (to WRm) tSOSDW <56> (0.5 + n)T - 20 ns Data hold time (from WRm) tHOSDW <57> 0.5T - 10 ns Data setup time (to address) tSAOD <58> (1 + tASW + tAHW)T - 25 ns WAIT setup time (to WRm) tSWRWT1 <59> 22 ns tSWRWT2 <60> WAIT hold time (from WRm) tHWRWT1 <61> 0 ns tHWRWT2 <62> nT ns tSAWT1 <63> (1 + tASW + tAHW)T - 45 ns tSAWT2 <64> (1 + n + tASW + tAHW)T - 45 ns tHAWT1 <65> (n + tASW + tAHW)T ns tHAWT2 <66> (1 + n + tASW + tAHW)T ns Address setup time (to WRm) tSAWR <52> Address hold time (from WRm) tHAWR <53> WRm low-level width tWWRL Data output time from WRm <R> WAIT setup time (to address) WAIT hold time (from address) ns nT - 22 ns Remarks 1. m = 0, 1 2. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 3. T = 1/fCPU (fCPU: CPU operating clock frequency) 4. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 1076 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Separate Bus Mode TW T1 T2 CLKOUT (output) A0 to A21 (output) <53> <58> AD0 to AD15 (I/O) Hi-Z Hi-Z <55> <57> <52> <56> <54> WR0, WR1 (output) <62> <60> <59> <61> WAIT (input) <63> <65> <64> <66> Remark RD is high level. User's Manual U16541EJ5V1UD 1077 CHAPTER 32 ELECTRICAL SPECIFICATIONS (c) Read cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Delay time from CLKOUT to address Symbol tDKSA Conditions <67> <R> Data input setup time (to CLKOUT) tSISDK <68> Data input hold time (from CLKOUT) tHKISD <69> Delay time from CLKOUT to RD tDKSR <70> <R> MIN. MAX. Unit V850ES/SG2 2 25 ns V850ES/SG2-H 2 27 ns 20 ns 0 ns V850ES/SG2 -2 12 ns V850ES/SG2-H -2 14 ns WAIT setup time (to CLKOUT) tSWTK <71> 20 ns WAIT hold time (from CLKOUT) tHKWT <72> 0 ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode T1 TW T2 CLKOUT (output) <67> <67> A0 to A21 (output) <68> AD0 to AD15 (I/O) Hi-Z Hi-Z <70> <70> RD (output) <71> <72> <71> WAIT (input) Remark 1078 <69> WR0 and WR1 are high level. User's Manual U16541EJ5V1UD <72> CHAPTER 32 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Delay time from CLKOUT to address Symbol tDKSA Conditions <73> <R> Delay time from CLKOUT to data output tDKSD <74> Delay time from CLKOUT to WRm tDKSW <75> <R> MIN. MAX. Unit V850ES/SG2 2 25 ns V850ES/SG2-H 2 27 ns 2 15 ns V850ES/SG2 -2 12 ns V850ES/SG2-H -2 14 ns WAIT setup time (to CLKOUT) tSWTK <76> 20 ns WAIT hold time (from CLKOUT) tHKWT <77> 0 ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. Write Cycle (CLKOUT Synchronous): In Separate Bus Mode T1 TW T2 CLKOUT (output) <73> <73> A0 to A21 (output) <74> AD0 to AD15 (I/O) <74> Hi-Z Hi-Z <75> <75> WR0, WR1 (output) <76> <77> <76> <77> WAIT (input) Remark RD is high level. User's Manual U16541EJ5V1UD 1079 CHAPTER 32 ELECTRICAL SPECIFICATIONS (3) Bus hold (a) CLKOUT asynchronous (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter HLDRQ high-level width Symbol Conditions tWHQH <78> HLDAK low-level width tWHAL <79> Delay time from HLDAK to bus output tDHAC <80> <R> Delay time from HLDRQ to HLDAK tDHQHA1 <81> Delay time from HLDRQ to HLDAK tDHQHA2 <82> MIN. MAX. Unit T + 10 ns T - 15 ns V850ES/SG2 -3 ns V850ES/SG2-H -5 ns 0.5T (2n + 7.5)T + 25 ns 1.5T + 25 ns Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. Bus Hold (CLKOUT Asynchronous) TI TH TH TH TI CLKOUT (output) <78> HLDRQ (input) <82> <81> HLDAK (output) <79> Address bus (output) Data bus (I/O) Hi-Z Hi-Z ASTB (output) Hi-Z RD (output), WR0, WR1 (output) 1080 User's Manual U16541EJ5V1UD <80> CHAPTER 32 ELECTRICAL SPECIFICATIONS (b) CLKOUT synchronous (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit HLDRQ setup time (to CLKOUT) tSHQK <83> 20 ns HLDRQ hold time (from CLKOUT) tHKHQ <84> 5 ns Delay time from CLKOUT to bus float tDKF <85> 19 ns Delay time from CLKOUT to HLDAK tDKHA <86> 19 ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. Bus Hold (CLKOUT Synchronous) T2 T3 TI TH TH TH TI CLKOUT (output) <83> <83> <84> HLDRQ (input) <86> <86> HLDAK (output) <85> Address bus (output) Data bus (I/O) Hi-Z Hi-Z ASTB (output) Hi-Z RD (output), WR0, WR1 (output) User's Manual U16541EJ5V1UD 1081 CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.9 Basic Operation (1) Power on/power off/reset timing (TA = -40 to +85C, VSS = AVSS = BVSS = EVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. EVDD VDD tREL <87> 0 EVDD BVDD tREB <88> 0 EVDD AVREF0, AVREF1 tREA <89> 0 EVDD RESET tRER <90> RESET low-level width tWRSL <91> MAX. ns tREL ns tREL ns Note 500 + tREG Analog noise elimination (during flash Unit ns 500 ns 500 ns erase/writing) Analog noise elimination RESET VDD tFRE <92> 500 ns VDD EVDD tFEL <93> 0 ns BVDD EVDD tFEB <94> 0 tFEL ns AVREF0, AVREF1 EVDD tFEA <95> 0 tFEL ns Note Depends on the on-chip regulator characteristics. VDD <87> <93> <88> <94> <89> <95> EVDD BVDD AVREF0, AVREF0 <90> RESET (input) 1082 <91> VI VI User's Manual U16541EJ5V1UD <92> VI VI CHAPTER 32 ELECTRICAL SPECIFICATIONS (2) Interrupt, FLMD0 pin timing (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter <R> <R> Symbol Conditions MAX. Unit NMI high-level width tWNIH Analog noise elimination 500 ns NMI low-level width tWNIL Analog noise elimination 500 ns n = 0 to 7 (Analog noise elimination) 500 ns INTPn Note high-level width tWITH INTPn Note low-level width tWITL n = 3 (Digital noise elimination) n = 0 to 7 (Analog noise elimination) n = 3 (Digital noise elimination) <R> MIN. 3TSMP + 20 ns 500 ns 3TSMP + 20 ns FLMD0 high-level width tWMDH 500 ns FLMD0 low-level width tWMDL 500 ns Note The DRST pin has the same characteristics as the INTP2 pin. Remark TSMP: Noise elimination sampling clock cycle (3) Key return timing (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit KRn high-level width tWKRH Analog noise elimination 500 ns KRn low-level width tWKRL Analog noise elimination 500 ns Remark n = 0 to 7 (4) Timer timing (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TI high-level width TI low-level width Symbol Conditions MIN. MAX. Unit tTIH TIP00, TIP01, TIP10, TIP11, TIP20, TIP21, 2T + 20 ns tTIL TIP30, TIP31, TIP40, TIP41, TIP50, TIP51, 2T + 20 ns TIQ00 to TIQ03 Remark T = 1/fXX (5) UART timing (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions Transmit rate ASCK0 cycle time User's Manual U16541EJ5V1UD MIN. MAX. Unit 312.5 kbps 10 MHz 1083 CHAPTER 32 ELECTRICAL SPECIFICATIONS (6) CSIB timing (a) Master mode (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKBn cycle time SCKBn high-/low-level width Symbol Conditions MIN. MAX. Unit tKCY1 <96> 125 ns tKH1, <97> tKCY1/2 - 5 ns tKL1 SIBn setup time (to SCKBn) tSIK1 <98> 30 ns SIBn hold time (from SCKBn) tKSI1 <99> 30 ns Delay time from SCKBn to SOBn output tKSO1 <100> Remark 30 ns n = 0 to 4 (b) Slave mode (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKBn cycle time SCKBn high-/low-level width Symbol Conditions MIN. MAX. Unit tKCY2 <96> 125 ns tKH2, <97> 57.5 ns tKL2 SIBn setup time (to SCKBn) tSIK2 <98> 30 ns SIBn hold time (from SCKBn) tKSI2 <99> 30 ns Delay time from SCKBn to SOBn output tKSO2 <100> <R> Remark V850ES/SG2 30 ns V850ES/SG2-H 35 ns n = 0 to 4 <96> <97> <97> SCKBn (I/O) <98> <99> Hi-Z Hi-Z SIBn (input) Input data <100> Output data SOBn (output) Remark 1084 n = 0 to 4 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS (7) I2C bus mode (I2C bus versions (Y products) only) (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Normal Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. 0 100 0 400 kHz SCL0n clock frequency fCLK Bus free time tBUF <101> 4.7 - 1.3 - s (Between start and stop conditions) tHD: STA <102> 4.0 - 0.6 - s SCL0n clock low-level width tLOW <103> 4.7 - 1.3 - s SCL0n clock high-level width tHIGH <104> 4.0 - 0.6 - s Setup time for start/restart conditions tSU: STA <105> 4.7 - 0.6 - s tHD: DAT <106> 5.0 - - - s Hold time Note 1 CBUS compatible Data hold time master 2 0 I C mode Data setup time SDA0n and SCL0n signal rise time tSU: DAT tR - Note 2 <107> 250 <108> - 0 - 1000 Note 2 100 0.9 Note 3 s - ns Note 5 300 ns Note 5 Note 4 20 + 0.1Cb SDA0n and SCL0n signal fall time tF <109> - 300 300 ns Stop condition setup time tSU: STO <110> 4.0 - 0.6 - s Pulse width of spike suppressed by tSP <111> - - 0 50 ns - 400 - 400 pF 20 + 0.1Cb input filter Capacitance load of each bus line Cb Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDA0n signal (at VIHmin. of SCL0n signal) in order to occupy the undefined area at the falling edge of SCL0n. 3. If the system does not extend the SCL0n signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 2 2 4. The high-speed mode I C bus can be used in the normal-mode I C bus system. In this case, set the high-speed mode I2C bus so that it meets the following conditions. * If the system does not extend the SCL0n signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCL0n signal's low state hold time: Transmit the following data bit to the SDA0n line prior to the SCL0n line release (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0 to 2 User's Manual U16541EJ5V1UD 1085 CHAPTER 32 ELECTRICAL SPECIFICATIONS <103> <104> SCL0n (I/O) <109> <108> <107> <105> <106> <102> <111> <110> <102> SDA0n (I/O) <101> Stop condition Remark <108> <109> Start condition Restart condition Stop condition n = 0 to 2 (8) IEBus controller (products with IEBus controller only) (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter IEBus system clock frequency Symbol fS Conditions Communication mode: Modes 1, 2 MIN. 5.91 6.20 TYP. User's Manual U16541EJ5V1UD Unit 6.09 MHz Note 6.38 MHz 6.00 6.29 Note IEBus system clock frequencies 6.0 MHz and 6.29 MHz cannot be used together. 1086 MAX. Note CHAPTER 32 ELECTRICAL SPECIFICATIONS (9) CAN timing (products with CAN controller only) (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. Transmit rate Internal delay time tNODE MAX. Unit 1 Mbps 100 ns CAN internal clock (fCAN) tOUTPUT CTXD0 pin (transmit data) tINPUT CRXD0 pin (receive data) Remark CAN internal clock (fCAN): CAN baud rate clock Internal delay time (tNODE) = Internal transmission delay time (tOUTPUT) + Internal reception delay time (tINPUT) <R> V850ES/SG2, V850ES/SG2-H Internal transmission delay time (tOUTPUT) CTXD0 pin CAN controller Internal reception delay time (tINPUT) User's Manual U16541EJ5V1UD CRXD0 pin 1087 CHAPTER 32 ELECTRICAL SPECIFICATIONS (10) A/D converter (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, 3.0 V AVREF0 3.6 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 bit 0.6 %FSR 24 s Zero scale error 0.5 %FSR Full scale error 0.5 %FSR Non-linearity error 4.0 LSB Differential linearity error 4.0 LSB AVSS AVREF0 V 3.0 3.6 V Resolution 3.0 AVREF0 3.6 V Note Overall error Conversion time tCONV Analog input voltage VIAN Reference voltage AVREF0 AVREF0 current AIREF0 2.6 Normal conversion mode 3 6.5 mA High-speed conversion mode 4 10 mA 5 A When A/D converter unused Note Excluding quantization error (0.05 %FSR). Caution Do not set (read/write) alternate-function ports during A/D conversion; otherwise the conversion resolution may be degraded. Remark LSB: Least Significant Bit FSR: Full Scale Range (11) D/A Converter (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, 3.0 V AVREF1 3.6 V, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Conditions MIN. TYP. Resolution MAX. Unit 8 bit Overall error R = 2 M 1.2 %FSR Settling time C = 20 pF 3 s Note 1 Output resistor RO Reference voltage AVREF1 AVREF1 current Note 2 AIREF1 Output data 55H 3.5 3.0 D/A conversion operating D/A conversion stopped Notes 1. Excluding quantization error (0.5 LSB). 2. Value of 1 channel of D/A converter Remark 1088 R is the output pin load resistance and C is the output pin load capacitance. User's Manual U16541EJ5V1UD 1 k 3.6 V 2.5 mA 5 A CHAPTER 32 ELECTRICAL SPECIFICATIONS <R> (12) LVI circuit specification (V850ES/SG2 only) (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Detection voltage Conditions VLVI0 Note Response time tLD MIN. TYP. MAX. Unit 2.85 3.0 3.15 V 0.2 2.0 ms After VDD reaches VLVI0/VLVI1 (MAX.), or After VDD drops to VLVI0/VLVI1 (MAX.) Minimum pulse width tLW Reference voltage stabilization tLWAIT 0.2 ms After VDD reaches 2.85 V (MIN.) 0.1 0.2 ms waiting time Note Time required to detect the detection voltage and output the interrupt or reset signal. Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) Operating voltage (MIN.) tLW tLWAIT LVION bit = 0 1 User's Manual U16541EJ5V1UD tLD tLD Time 1089 CHAPTER 32 ELECTRICAL SPECIFICATIONS (13) RAM retention detection (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Detection voltage VRAMH Supply voltage rise time tRAMHTH <R> Conditions VDD = 0 to 2.85 V (V850ES/SG2) MIN. TYP. MAX. Unit 1.9 2.0 2.1 V 0.002 ms VDD = 0 to 3.0 V (V850ES/SG2-H) Note Response time tRAMHD Minimum pulse width tRAMHW After VDD reaches 2.1 V 0.2 2.0 0.2 ms Note Time required to detect the detection voltage and set the RAMS.RAMF bit. Supply voltage (VDD) Operating voltage (MIN.) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tRAMHTH tRAMHD tRAMHW tRAMHD Time RAMS.RAMF bit Cleared by instruction 1090 User's Manual U16541EJ5V1UD ms CHAPTER 32 ELECTRICAL SPECIFICATIONS 32.10 Flash Memory Programming Characteristics (TA = -40 to +85C, BVDD VDD = EVDD = AVREF0 = AVREF1, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. Unit 20 MHz Operating frequency fCPU V850ES/SG2 V850ES/SG2-H 2.5 32 MHz Supply voltage VDD V850ES/SG2 2.85 3.6 V V850ES/SG2-H 3.0 3.6 V 100 times +85 C MAX. Unit 3,000 ms <R> <R> Number of rewrites CWRT Programming temperature tPRG 2.5 MAX. -40 (2) Serial write operation characteristics Parameter Symbol FLMD0, FLMD1 setup time tMDSET FLMD0 count start time from RESET tRFCF Conditions MIN. TYP. 2 fX = 2.5 to 10 MHz 17,855/fX + s (V850ES/SG2) fX = 2.5 to 8 MHz <R> (V850ES/SG2-H) FLMD0 counter high-level width/ tCH/tCL 10 s 100 low-level width FLMD0 counter rise time/fall time Remark tR/tF 50 ns = oscillation stabilization time Flash write mode setup timing VDD RESET (input) 0V tCH VDD FLMD0 0V tMDSET tRFCF tF VDD tR tCL FLMD1 0V User's Manual U16541EJ5V1UD 1091 CHAPTER 32 ELECTRICAL SPECIFICATIONS (3) Programming characteristics (a) V850ES/SG2 Parameter Symbol Block erase time Conditions fXX = 20 MHz Write time per 256 bytes fXX = 20 MHz Block internal verify time fXX = 20 MHz Block blank check time Flash memory information fXX = 20 MHz MIN. Note 1 TYP. 304 MAX. Unit ms Note 2 1,405 ms Note 3 3,057 ms 8.1 ms Note 1 20 ms Note 2 141 ms Note 3 322 ms Note 1 9.2 ms Note 2 64 ms Note 3 147 ms 1.0 ms fXX = 20 MHz setting time Notes 1. Block size = 4 KB 2. Block size = 28 KB 3. Block size = 64 KB Caution When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites 1092 User's Manual U16541EJ5V1UD CHAPTER 32 ELECTRICAL SPECIFICATIONS <R> (b) V850ES/SG2-H Parameter Symbol Block erase time Conditions fXX = 32 MHz Write time per 256 bytes fXX = 32 MHz Block internal verify time fXX = 32 MHz Block blank check time Flash memory information fXX = 32 MHz MIN. TYP. MAX. Unit Note 1 651.3 ms Note 2 3,081.9 ms Note 3 6,727.7 ms 8.7 ms Note 1 49.0 ms Note 2 342.9 ms Note 3 783.9 ms Note 1 22.7 ms Note 2 159.2 ms Note 3 364.0 ms 1.1 ms fXX = 32 MHz setting time Notes 1. Block size = 8 KB 2. Block size = 56 KB 3. Block size = 128 KB Caution When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites User's Manual U16541EJ5V1UD 1093 CHAPTER 33 PACKAGE DRAWINGS 100-PIN PLASTIC QFP (14x20) A B 80 81 51 50 detail of lead end S C D R Q 31 30 100 1 F H G I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 23.20.2 B 20.00.2 C 14.00.2 D 17.20.2 F 0.825 G 0.575 H 0.32+0.08 -0.07 I 0.13 J 0.65 (T.P.) K L 1.60.2 0.80.2 M 0.17+0.06 -0.05 N 0.10 P 2.70.1 Q 0.1250.075 R 3+7 -3 S 3.0 MAX. S100GF-65-JBT-2 1094 User's Manual U16541EJ5V1UD CHAPTER 33 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D Q R 26 25 100 1 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 16.000.20 B 14.000.20 C 14.000.20 D 16.000.20 F 1.00 G 1.00 H 0.22 +0.05 -0.04 I J 0.08 0.50 (T.P.) K 1.000.20 L 0.500.20 M 0.17 +0.03 -0.07 N 0.08 P 1.400.05 Q 0.100.05 R 3 +7 -3 S 1.60 MAX. S100GC-50-8EU, 8EA-2 User's Manual U16541EJ5V1UD 1095 CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS <R> These products should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 34-1. Surface Mounting Type Soldering Conditions (1/2) (1) 100-pin plastic LQFP (fine pitch) (14 x 14) PD703260GC-xxx-8EA, 703260YGC-xxx-8EA, 703261GC-xxx-8EA, 703261YGC-xxx-8EA, 703262GC-xxx-8EA, 703262YGC-xxx-8EA, 703263GC-xxx-8EA, 703263YGC-xxx-8EA, 703270GC-xxx-8EA, 703270YGC-xxx-8EA, 703271GC-xxx-8EA, 703271YGC-xxx-8EA, 703272GC-xxx-8EA, 703272YGC-xxx-8EA, 703273GC-xxx-8EA, 703273YGC-xxx-8EA, 703280GC-xxx-8EA, 703280YGC-xxx-8EA, 703281GC-xxx-8EA, 703281YGC-xxx-8EA, 703282GC-xxx-8EA, 703282YGC-xxx-8EA, 703283GC-xxx-8EA, 703283YGC-xxx-8EA, 70F3261GC-8EA, 70F3261YGC-8EA, 70F3263GC-8EA, 70F3263YGC-8EA, 70F3271GC-8EA, 70F3271YGC-8EA, 70F3273GC-8EA, 70F3273YGC-8EA, 70F3281GC-8EA, 70F3281YGC-8EA, 70F3283GC-8EA, 70F3283YGC-8EA, 703262HYGC-xxx-8EA-A, 703263HYGC-xxx-8EA-A, 703272HYGC-xxx-8EA-A, 703273HYGC-xxx-8EA-A, 703282HYGC-xxx-8EA-A, 703283HYGC-xxx-8EA-A, 70F3263HYGC-8EA-A, 70F3273HYGC-8EA-A, 70F3283HYGC-8EA-A Soldering Method Recommended Soldering Conditions Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or Note higher), Count: 3 times or less, Exposure limit: 7 days IR60-207-3 (after that, prebake at 125C for 20 to 72 hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remarks 1. The V850ES/SG2 and V850ES/SG2-H are lead-free products. 2. For soldering methods and conditions other than those recommended above, please contact an NEC Electronics sales representative. 1096 User's Manual U16541EJ5V1UD CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Table 34-1. Surface Mounting Type Soldering Conditions (2/2) (2) 100-pin plastic QFP (14 x 20) PD703260GF-xxx-JBT, 703260YGF-xxx-JBT, 703261GF-xxx-JBT, 703261YGF-xxx-JBT, 703270GF-xxx-JBT, 703270YGF-xxx-JBT, 703271GF-xxx-JBT, 703271YGF-xxx-JBT, 70F3261GF-JBT, 70F3261YGF-JBT, 70F3271GF-JBT, 70F3271YGF-JBT Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Note 3 times or less, Exposure limit: 7 days IR60-207-3 (after that, prebake at 125C for 20 to 72 hours) Wave soldering For details, contact an NEC Electronics sales representative. - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remarks 1. The V850ES/SG2 is a lead-free product. 2. For soldering methods and conditions other than those recommended above, please contact an NEC Electronics sales representative. User's Manual U16541EJ5V1UD 1097 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/SG2 or <R> V850ES/SG2-H. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * WindowsTM Unless otherwise specified, "Windows" means the following OSs. * Windows 98 * Windows 2000 * Windows Me * Windows XP * Windows NTTM Ver. 4.0 1098 User's Manual U16541EJ5V1UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/4) (1) When using in-circuit emulator IE-V850ES-G1 Software package Debugging software Language processing software * C compiler package * Integrated debugger * Device file * System simulator Control software * Project manager Embedded software (Windows only)Note 1 * Real-time OS * Network library * File system Host machine (PC or EWS) Interface adapter Power supply unit Flash memory write environment In-circuit emulator (IE-V850ES-G1)Note 2 Flash memory programmer Flash memory write adapter Flash memory Conversion socket or conversion adapter Target system Notes 1. The project manager PM+ is included in the C compiler package. The PM+ is only used for Windows. 2. Products other than in-circuit emulator IE-V850ES-G1 are all sold separately. User's Manual U16541EJ5V1UD 1099 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/4) (2) When using IECUBE(R) QB-V850ESSX2 Software package Debugging software Language processing software * C compiler package * Integrated debugger * Device file * System simulator Control software * Project manager Embedded software (Windows only)Note 1 * Real-time OS * Network library * File system Host machine (PC or EWS) USB interface cable Power supply unit Flash memory write environment In-circuit emulator (QB-V850ESKX1H)Note 2 Flash memory programmer Flash memory write adapter Flash memory Conversion socket or conversion adapter Target system Notes 1. The project manager PM+ is included in the C compiler package. The PM+ is only used for Windows. 2. In-circuit emulator QB-V850ESSX2 is supplied with integrated debugger ID850QB, a simple programmer PG-FPL, power supply unit, and USB interface cable. Any other products are sold separately. 1100 User's Manual U16541EJ5V1UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (3/4) <R> (3) When using on-chip debug emulator IE-V850E1-CD-NW Software package Debugging software Language processing software * C compiler package * Integrated debugger * Device file * System simulator Control software * Project manager Embedded software (Windows only)Note 1 * Real-time OS * Network library * File system Host machine (PC or EWS) Interface adapterNote 2 Flash memory write environment Flash memory programmer On-chip debug emulator (IE-V850E1-CD-NW)Note 3 Flash memory write adapter Flash memory Target device (N-Wire interface) Target connector Connector conversion board Target system Notes 1. The project manager PM+ is included in the C compiler package. The PM+ is only used for Windows. 2. The IE-V850E1-CD-NW supports only the PCMCIA card interface. 3. The IE-V850E1-CD-NW is supplied with an ID850QB, IE connection cable, IE connector, and connector conversion board. All other products are sold separately. User's Manual U16541EJ5V1UD 1101 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (4/4) <R> (4) When using MINICUBE(R) QB-V850MINI Software package Debugging software Language processing software * C compiler package * Integrated debugger * Device file * System simulator Control software * Project manager Embedded software (Windows only)Note 1 * Real-time OS * Network library * File system Host machine (PC or EWS) USB interface cableNote 2 Flash memory write environment Flash memory programmer On-chip debug emulator (QB-V850MINI)Note 3 Flash memory write adapter OCD cable Flash memory Target device (N-Wire interface) Target connector Connector conversion board Target system Notes 1. The project manager PM+ is included in the C compiler package. The PM+ is only used for Windows. 2. The QB-V850MINI supports the USB interface. 3. The QB-V850MINI is supplied with a KEL connector and KEL adapter as target connectors and connector conversion board in addition to an ID850QB, USB interface cable, and OCD cable. All other target connectors are sold separately. 1102 User's Manual U16541EJ5V1UD APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) common to the V850 microcontroller are combined in this V850 microcontroller software package. package Part number: SxxxxSP850 Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSP850 xxxx Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) Supply Medium CD-ROM A.2 Language Processing Software CA850 This compiler converts programs written in C language into object codes executable with C compiler package a microcontroller. This compiler is started from project manager PM+. Part number: SxxxxCA703000 <R> DF703283/DF703283H This file contains information peculiar to the device. <R> Device file This device file should be used in combination with a tool (CA850 or ID850). Note The corresponding OS and host machine differ depending on the tool to be used. <R> Note V850ES/SG2: DF703283 V850ES/SG2-H: DF703283H Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxCA703000 xxxx Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) 3K17 SPARCstation TM SunOS TM TM Solaris Supply Medium CD-ROM (Rel. 4.1.4), (Rel. 2.5.1) A.3 Control Software PM+ This is control software designed to enable efficient user program development in the Project manager Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from PM+. <Caution> PM+ is included in the C compiler package CA850. It can only be used in Windows. User's Manual U16541EJ5V1UD 1103 APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using in-circuit emulator IE-V850ES-G1 The system configuration when connecting the IE-703288-G1-EM1 to the IE-V850ES-G1 and use it connecting to the host machine (PC-9800 series, PC/AT compatible) is shown below. Figure A-2. System Configuration (IE-V850ES-G1 Used) <2> <3> <9> <10> <8> <1> <4> Target system <5> <6> <7> <1> Host machine (PC-9800 series, PC/AT compatibles) <2> Debugger <3> Device file <4> PC interface board (for PCI bus or PCMCIA) <5> PC interface cable (supplied with the IE-V850ES-G1) <6> Power supply cable (supplied with the IE-V850ES-G1) <7> In-circuit emulator (IE-V850ES-G1) <8> In-circuit emulator emulation board (IE-703288-G1-EM1) <9> Probe (supplied with the IE-703288-G1-EM1) <10> EV-703288GF100 (for GF package) or EV-703288GC100 (for GC package) 1104 User's Manual U16541EJ5V1UD APPENDIX A DEVELOPMENT TOOLS <7> IE-V850ES-G1 In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a V850 microcontroller product. It corresponds to the integrated debugger ID850. This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. <4> IE-70000-CD-IF-A PC card interface <4> IE-70000-PCI-IF-A This is PC card and interface cable required when using a notebook-type computer as the host machine (PCMCIA socket compatible). This adapter is required when using a computer with a PCI bus as the host machine. Interface adapter <8> IE-703288-G1-EM1 Emulation board <9> GXP-CABLE This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This probe is used to connect the in-circuit emulator and target system. This is supplied with Emulation probe emulation board IE-703288-G1-EM1. <10> EV-703288GF100 This conversion adapter is used to connect the emulation probe and target system board on Conversion adapter <10> EV-703288GC100 Conversion adapter which a 100-pin plastic LQFP (GF-JBT type) can be mounted. This conversion adapter is used to connect the emulation probe and target system board on which a 100-pin plastic LQFP (GC-8EA type) can be mounted. Remarks 1. The numbers in the square brackets correspond to the numbers in Figure A-2. 2. EV-703288GF100 and EV-703288GC100 are products of Application Corporation. TEL: +81-42-732-1377 Application Corporation User's Manual U16541EJ5V1UD 1105 APPENDIX A DEVELOPMENT TOOLS A.4.2 When using IECUBE QB-V850ESSX2 The system configuration when connecting the QB-V850ESSX2 to the host machine (PC-9821 series, PC/AT compatible) is shown below. If no option products are prepared, connection is possible. Figure A-3. System Configuration (QB-V850ESSX2 Used) (1/2) System configuration Accessories <1> <3> USB cable <5> IECUBE Required Optional <R> <6> Check pin adapter (under development) Enables signal monitoring (S and T types) <4> Power supply <2> CD-ROM QB-MINI2 <7> Extension probe Probe can be connected (S and T types) <8> Exchange adapter Exchanges pins among different microcontroller types <8> Exchange adapter Exchanges pins among different microcontroller types <10> Space adapter Each adapter can adjust height by 3.2 mm. <9> Check pin adapter (S type only) Enables signal monitoring <11> YQ connector Connector for connecting to emulator <10> Space adapter Each adapter can adjust height by 5.6 mm. <12> Mount adapter For device mounting <12> Mount adapter For device mounting <13> Target connector For mounting on target system <13> Target connector For mounting on target system <14> Target system <14> Target system S-type socket configuration T-type socket configuration <1> Host machine (PC-9821 series, IBM-PC/AT compatibles) <2> Debugger, USB driver, manuals, etc. (ID850QB Disk, Accessory DiskNote 1) <3> USB interface cable <4> AC adapter <5> In-circuit emulator (QB-V850ESSX2) <R> <6> Check pin adapter (common to S and T types) (QB-144-CA-01) (option) <7> Extension probe coaxial type (common to S and T types) (QB-144-EP-01S) (option) <8> Exchange adapterNote 2 (S type: QB-100GF-EA-01S (for GF package), QB-100GC-EA-01S (for GF package), T type: QB-100GF-EA-01T (for GF package), QB-100GC-EA-01T (for GC package) <9> Check pin adapterNote 3 (S type only) (QB-100-CA-01S) (option) <10> Space adapter Note 3 (S type: QB-100-SA-01S, T type: QB-100GF-YS-01T (for GF package), QB-100GC- YS-01T (for GC package)) (option) <11> YQ connectorNote 2 (T type only) (QB-100GF-YQ-01T (for GF package), QB-100GC-YQ-01T (for GC package)) <12> Mount adapter (S type: QB-100GF-MA-01S (for GF package), QB-100GC-MA-01S (for GC package), T type: QB-100GF-HQ-01T (for GF package), QB-100GC-HQ-01T (GC package) (option) 1106 User's Manual U16541EJ5V1UD APPENDIX A DEVELOPMENT TOOLS Figure A-3. System Configuration (QB-V850ESSX2 Used) (2/2) <13> Target connectorNote 2 (S type: QB-100GF-TC-01S (for GF package), QB-100GC-TC-01S (for GC package), T type: QB-100GF-NQ-01T (for GF package), QB-100GC-NQ-01T (for GF package)) <14> Target system Notes 1. Obtain the device file from the NEC Electronics website. http://www.necel.com/micro/ods/jpn/index.html 2. Depending on the ordering number, supplied with the device. * When QB-V850ESSX2-ZZZ is ordered The exchange adapter and the target connector are not supplied. * When QB-V850ESSX2-S100GF is ordered The QB-100GF-EA-01S and QB-100GF-TC-01S are supplied. * When QB-V850ESSX2-S100GC is ordered The QB-100GC-EA-01S and QB-100GC-TC-01S are supplied. * When QB-V850ESSX2-T100GF is ordered The QB-100GF-EA-01T, QB-100GF-YQ-01T, and QB-100GF-NQ-01T are supplied. * When QB-V850ESSX2-T100GC is ordered The QB-100GC-EA-01T, QB-100GC-YQ-01T, and QB-100GC-NQ-01T are supplied. 3. When using both <9> and <10>, the order between <9> and <10> is not cared. User's Manual U16541EJ5V1UD 1107 APPENDIX A DEVELOPMENT TOOLS <5> QB-V850ESSX2 <R> Note In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a V850ES/SG2 or V850ES/SG2-H product. It supports the integrated debugger ID850QB. This emulator should be used in combination with a power supply unit and emulation probe. Use USB to connect this emulator to the host machine. <3> USB interface cable Cable to connect the host machine and the QB-V850ESSX2. <4> AC adapter 100 to 240 V can be supported by replacing the AC plug. <8> QB-100GF-EA-01S, Adapter to perform pin conversion. QB-100GC-EA-01S, * QB-100GF-EA-01S, QB-100GF-EA-01T: For 100-pin plastic QFP (GF-JBT type) QB-100GF-EA-01T, * QB-100GC-EA-01S, QB-100GC-EA-01T: For 100-pin plastic LQFP (GC-8EA type) QB-100GC-EA-01T Exchange adapter <9> QB-100-CA-01S Adapter used in waveform monitoring using the oscilloscope, etc. Check pin adapter <10> QB-100-SA-01S, Adapter to adjust the height. QB-100GF-YS-01T, * QB-100-SA-01S, QB-100GF-YS-01T: For 100-pin plastic QFP (GF-JBT type) QB-100GC-YS-01T * QB-100-SA-01S, QB-100GC-YS-01T: For 100-pin plastic LQFP (GC-8EA type) Space adapter <R> <12> QB-100GF-MA-01S, Adapter to mount the V850ES/SG2 or V850ES/SG2-H with socket. QB-100GC-MA-01S, * QB-100GF-MA-01S, QB-100GF-HQ-01T: For 100-pin plastic QFP (GF-JBT type) QB-100GF-HQ-01T, * QB-100GC-MA-01S, QB-100GC-HQ-01T: For 100-pin plastic LQFP (GC-8EA type) QB-100GC-HQ-01T Mount adapter <13> QB-100GF-TC-01S, Connector to solder on the target system. QB-100GC-TC-01S, * QB-100GF-TC-01S, QB-100GF-NQ-01T: For 100-pin plastic QFP (GF-JBT type) QB-100GF-NQ-01T, * QB-100GC-TC-01S, QB-100GC-NQ-01T: For 100-pin plastic LQFP (GC-8EA type) QB-100GC-NQ-01T Target connector <R> Note The QB-V850ESSX2 is supplied with a power supply unit, USB interface cable, and QB-MINI2. It is also supplied with integrated debugger ID850QB as control software. Remark 1108 The numbers in the square brackets correspond to the numbers in Figure A-3. User's Manual U16541EJ5V1UD APPENDIX A DEVELOPMENT TOOLS <R> A.4.3 When using on-chip debug emulator IE-V850E1-CD-NW The system configuration when connecting the IE-V850E1-CD-NW to the host machine (PC-9821 series, PC/AT compatible) is shown below. Figure A-4. System Configuration (IE-V850E1-CD-NW Used) <1> <3> <2> <4> V850ES/SG2, V850ES/SG2-H Flash memory version <5> <6> Target system Personal computer including PCMCIA compliant with the PCMCIA2.1/JEIDA standard <1> Host machine Ver. 4.2. When using a product which does not have a PCMCIA slot, use a PCI-PCMCIA conversion board or the like. For details on the conversion board, consult an NEC Electronics sales representative. Note 1 The integrated debugger ID850QB, N-Wire Checker, device driver, documents and so <2> CD-ROM on in the CD-ROM format are included. This CD-ROM is supplied with the IEV850E1-CD-NW. <3> IE-V850E1-CD-NW On-chip debug emulator This on-chip debug emulator is used to debug hardware and software when application systems using the V850ES/SG2 and V850ES/SG2-H are developed. It supports the integrated debugger ID850QB. <4> IE-V850E1-CD-NW connection cable This connection cable is used to connect the IE-V850E1-CD-NW and the target system. It is supplied with the IE-V850E1-CD-NW. The cable length is approximately 50 cm. <5> Connector conversion board It is supplied with the IE-V850E1-CD-NW. KEL adapter <6> IE-V850E1-CD-NW connector KEL connector Notes 1. Note 2 8830E-026-170S (It is supplied with the IE-V850E1-CD-NW.) 8830E-026-170L (sold separately) Obtain the device file from the NEC Electronics website. http://www.necel.com/micro/ods/eng/index.html 2. Remark Product of KEL Corporation The numbers in the table correspond to the numbers in Figure A-4. User's Manual U16541EJ5V1UD 1109 APPENDIX A DEVELOPMENT TOOLS <R> A.4.4 When using MINICUBE QB-V850MINI The system configuration when connecting the QB-V850MINI to the host machine (PC-9821 series, PC/AT compatible) is shown below. Figure A-5. System Configuration (QB-V850MINI Used) STATUS TARGET <4> POWER <1> <6> <5> <7> <2> <3> Device file V850ES/SG2, V850ES/SG2-H Flash memory version <9> Target system <8> Target system <1> Host machine (with on-chip USB port) <2> ID850QB Disk (Software tools for debugging are packaged.) <3> Device fileNote 1 <4> USB interface cable (supplied with <5>) <5> On-chip debug emulator (QB-V850MINI) <6> OCD cable (supplied with <5>) <7> KEL adapter (supplied with <5>)Notes 2, 3 <8> KEL connector (supplied with <5>)Notes 2, 3 <9> 2.54 mm pitch 20-pin general-purpose connector (sold separately)Note 3 Notes 1. Obtain the device file from the NEC Electronics website. http://www.necel.com/micro/ods/eng/index.html 2. Product of KEL Corporation 3. A connector other than KEL connectors can also be used as the target connector. For details, refer to the QB-V850MINI User's Manual. 1110 User's Manual U16541EJ5V1UD APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) <R> SM+ for V850ES/Sx2 This is a system simulator for the V850 microcontrollers. The SM+ are Windows-based System simulator softwares. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM+ allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM850 and SM+ should be used in combination with the device file (sold separately). Part number: SxxxxSM703289-B <R> ID850 This debugger supports the in-circuit emulators for the V850 microcontrollers. The ID850 Integrated debugger and ID850QB are Windows-based software. (supporting in-circuit emulator It has improved C-compatible debugging functions and can display the results of tracing IE-V850ES-G1) with the source program using an integrating window function that associates the source ID850QB program, disassemble display, and memory display with the trace result. Integrated debugger It should be used in combination with the device file (sold separately). (supporting in-circuit emulator Part number: SxxxxID703000, SxxxxID703000-GC (ID850) QB-V850ESSX2) <R> Remark xxxx in the part number differs depending on the OS used. SxxxxSM703289-B SxxxxID703000 SxxxxID703000-GC xxxx Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) User's Manual U16541EJ5V1UD Supply Medium CD-ROM 1111 APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software RX850, RX850 Pro The RX850 and RX850 Pro are real-time OSs conforming to ITRON 3.0 specifications. Real-time OS A tool (configurator) for generating multiple information tables is supplied. RX850 Pro has more functions than RX850. Part number: SxxxxRX703000- (RX850) SxxxxRX703100- (RX850 Pro) V850mini-NET (provisional name) This is a network library conforming to RFC. (Network library) It is a lightweight TCP/IP of compact design, requiring only a small memory. In addition to the TCP/IP standard set, an HTTP server, SMTP client, and POP client are also supported. RX-FS850 This is a FAT file system function. (File system) It is a file system that supports the CD-ROM file system function. This file system is used with the real-time OS RX850 Pro. Caution To purchase the RX850 or RX850 Pro, first fill in the purchase application form and sign the user agreement. Remark xxxx and in the part number differ depending on the host machine and OS used. SxxxxRX703000- SxxxxRX703100- Product Outline Maximum Number for Use in Mass Production 001 Evaluation object Do not use for mass-produced product. 100K Mass-production object 0.1 million units 001M 1 million units 010M 10 million units S01 xxxx Source program Object source program for mass production Host Machine OS AB17 PC-9800 series, Windows (Japanese version) BB17 IBM PC/AT compatibles Windows (English version) 3K17 SPARCstation Solaris (Rel. 2.5.1) Supply Medium CD-ROM A.7 Flash Memory Writing Tools Flashpro IV (part number: PG-FP4) Flash memory programmer dedicated to microcontrollers with on-chip flash memory. Flash memory programmer <R> Flashpro V (part number: PG-FP5) Flash memory programmer FA-100GF-3BA-A Flash memory writing adapter used connected to Flashpro IV. Flash memory writing adapter * FA-100GF-3BA-A: For 100-pin plastic QFP (GF-JBT type) FA-100GC-8EU-A Flash memory writing adapter used connected to Flashpro IV. Flash memory writing adapter * FA-100GC-8EU-A: For 100-pin plastic LQFP (GC-8EA type) Remark <R> FA-100GF-3BA-A and FA-100GC-8EU-A are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-42-750-4172 Naito Densei Machida Mfg. Co., Ltd. 1112 User's Manual U16541EJ5V1UD <R> APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/SG2 AND V850ES/SG2-H Differences between the V850ES/SG2 and V850ES/SG2-H are shown below. For details, refer to each corresponding section. For each part numbers of the V850ES/SG2 and V850ES/SG2-H, refer to remark of Table 1-1. Table B-1. Major Differences Between V850ES/SG2 and V850ES/SG2-H (1/2) V850ES/SG2-H Refer to: Minimum instruction Internal flash memory 384/640 KB 640 KB Internal ROM 256/384/512/640 KB 512/640 KB Internal RAM 24/32/40/48 KB 40/48 KB 3.4.4 (2) Special register PSC, CKC, PCC, CLM, RESF, LVIM, PSC, CKC, PCC, CLM, RESF, RAMS, 3.4.8 RAMS, OCDM registers OCDM registers Set Value of VSWC 00H/01H 00H/01H/11H 3.4.9 (1) (a) Number of access clock Instruction fetch (branch) of internal Instruction fetch (branch) of Internal 5.5.1 ROM (32-bit): 2 ROM (32-bit): 3 Operand data access of internal ROM Operand data access of internal ROM (32-bit): 3 (32-bit): 4 None Provided 5.6.1 (1) None Provided 5.6.4 (1) fX = 2.5 to 10 MHz (fXX = 2.5 to 10 MHz) fX = 2.5 to 8 MHz (fXX = 2.5 to 8 MHz) 6.1 Bus control function Introduction V850ES/SG2 CPU function Major Differences 50 ns 31.25 ns 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (14 x 14) 1.2 execution time Package 100-pin plastic LQFP (14 x 14) DWC0 register: Cautions 3.4.4 (1) on data wait AWC register: Cautions on address hold wait, Main clock oscillation frequency address setup wait Clock through mode PLL mode fX = 2.5 to 5 MHz fX = 2.5 to 5 MHz (fXX = 10 to 20 MHz) (x4: fXX = 10 to 20 MHz) fX = 2.5 to 4 MHz (x8: fXX = 20 to 32 MHz) None Provided 13.4 (2) IEBus controller: Clock fXX, fXX/2, fXX/3 fXX, fXX/2, fXX/3, fXX/4, fXX/5 18.3 (17) DMA function: DTFRn register The procedure to change the setting differs. 20.3 (6) Interrupt A/D converter: 47/51 46/50 22.1 Restriction for xxICn register None Provided 22.3.4 Interrupt response time 7 22.7 ADA0M1.ADA0FR3 bit Number of maskable interrupts 6 (internal interrupt (maximum)) User's Manual U16541EJ5V1UD 1113 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/SG2 AND V850ES/SG2-H Table B-1. Major Differences Between V850ES/SG2 and V850ES/SG2-H (2/2) Reset Major Differences V850ES/SG2 V850ES/SG2-H Refer to: RESF.LVIRF bit Provided None 25.2 (1) Reset by low-voltage detector Provided None 25.3.3 Firmware operation time (sec.) 14,974 x (1/fX) 11,994 x (1/fX) 25.3.5 (2) Provided None Chapter Low-voltage detector Electrical specifications Flash memory 27 Internal flash memory: 384/640 KB Internal flash memory: 640 KB Blocks 0 to 3: 28 KB each Blocks 0, 2: 56 KB each Blocks 4 to 7: 4 KB each Blocks 1, 3: 8 KB each Block 8 to last block: 64 KB each Blocks 4 to 7: 128 KB each Boot area 56 KB 64 KB Operating condition When using main clock (ADC, DAC stopped), When using main clock, subclock: sub clock (ADC, DAC stopped): VDD = EVDD = BVDD = AVREF0 = AVREF1 = VDD = EVDD = AVREF0 = AVREF1 = 2.85 to 3.6 V 3.0 to 3.6 V Block configuration 30.2 32.3 BVDD = 2.7 to 3.6 V When using main clock (ADC, DAC operating): VDD = EVDD = AVREF0 = AVREF1 = 3.0 to 3.6 V BVDD = 2.7 to 3.6 V Main clock oscillator Oscillator frequency (fX) = 10 MHz Oscillator frequency (fX) = 8 MHz characteristics (MAX.) (MAX.) PLL characteristics Using input frequency, x8 mode Using input frequency, x8 mode fX = 2.5 MHz (MAX.) fX = 4 MHz (MAX.) Using output frequency, x8 mode Using output frequency, x8 mode fXX = 20 MHz (MAX.) fXX = 32 MHz (MAX.) VDD = 2.85 to 3.6 V VDD = 3.0 to 3.6 V Regulator characteristics 32.4.1 32.4.3 32.5 (input voltage (VDD)) DC characteristics (supply The value of each parameter differs. 32.6.2 current) CLKOUT output timing 50 ns (MIN.) 31.25 ns (MIN.) 32.8.1 (output cycle) Bus timing The value of some parameters differs. 32.8.2 CSIB timing Delay time from SCKBn to SOBn Delay time from SCKBn to SOBn 32.9 (6) (slave mode) output (tKSO2): 30 ns (MAX.) output (tKSO2): 35 ns (MAX.) (b) LVI circuit characteristics Provided None 32.9 (12) Flash memory programming fCPU = 2.5 to 20 MHz fCPU = 2.5 to 32 MHz 32.10 (1) VDD = 2.85 to 3.6 V VDD = 3.0 to 3.6 V characteristics (basic characteristics, operating frequency) Flash memory programming characteristics (basic characteristics, supply voltage) Flash memory programming The value of each parameter differs. 32.10 (3) characteristics (programming specification) Recommended soldering Infrared reflow conditions Wave soldering 1114 Infrared reflow User's Manual U16541EJ5V1UD Chapter 34 APPENDIX C REGISTER INDEX (1/12) Symbol ADA0CR0 Name A/D conversion result register 0 Unit ADC Page 473 ADA0CR0H A/D conversion result register 0H ADC 473 ADA0CR1 A/D conversion result register 1 ADC 473 ADA0CR10 A/D conversion result register 10 ADC 473 ADA0CR10H A/D conversion result register 10H ADC 473 ADA0CR11 A/D conversion result register 11 ADC 473 ADA0CR11H A/D conversion result register 11H ADC 473 ADA0CR1H A/D conversion result register 1H ADC 473 ADA0CR2 A/D conversion result register 2 ADC 473 ADA0CR2H A/D conversion result register 2H ADC 473 ADA0CR3 A/D conversion result register 3 ADC 473 ADA0CR3H A/D conversion result register 3H ADC 473 ADA0CR4 A/D conversion result register 4 ADC 473 ADA0CR4H A/D conversion result register 4H ADC 473 ADA0CR5 A/D conversion result register 5 ADC 473 ADA0CR5H A/D conversion result register 5H ADC 473 ADA0CR6 A/D conversion result register 6 ADC 473 ADA0CR6H A/D conversion result register 6H ADC 473 ADA0CR7 A/D conversion result register 7 ADC 473 ADA0CR7H A/D conversion result register 7H ADC 473 ADA0CR8 A/D conversion result register 8 ADC 473 ADA0CR8H A/D conversion result register 8H ADC 473 ADA0CR9 A/D conversion result register 9 ADC 473 ADA0CR9H A/D conversion result register 9H ADC 473 ADA0M0 A/D converter mode register 0 ADC 466 ADA0M1 A/D converter mode register 1 ADC 468 ADA0M2 A/D converter mode register 2 ADC 471 ADA0PFM Power fail comparison mode register ADC 475 ADA0PFT Power fail comparison threshold value register ADC 476 ADA0S A/D converter channel specify register ADC 472 ADIC Interrupt control register INTC 933 AWC Address wait control register BCU 200 BCC Bus cycle control register BCU 201 BCR IEBus control register IEBus 693 BPC Peripheral I/O area select control register BCU 89 BSC Bus size configuration register BCU 189 C0BRP CAN0 module bit rate prescaler register CAN 807 C0BTR CAN0 bit rate register CAN 808 C0CTRL CAN0 module control register CAN 797 User's Manual U16541EJ5V1UD 1115 APPENDIX C REGISTER INDEX (2/12) Symbol Name Unit Page C0ERC CAN0 module error counter register CAN 803 C0GMABT CAN0 global automatic block transmit control register CAN 792 C0GMABTD CAN0 global automatic block transmit delay setting register CAN 794 C0GMCS CAN0 global clock select register CAN 791 C0GMCTRL CAN0 global control register CAN 789 C0IE CAN0 module interrupt enable register CAN 804 C0INFO CAN0 module information register CAN 802 C0INTS CAN0 module interrupt status register CAN 806 C0LEC CAN0 module last error information register CAN 801 C0LIPT CAN0 module last receive pointer register CAN 810 C0LOPT CAN0 module last transmit pointer register CAN 812 C0MASK1H CAN0 module mask 1 register H CAN 795 C0MASK1L CAN0 module mask 1 register L CAN 795 C0MASK2H CAN0 module mask 2 register H CAN 795 C0MASK2L CAN0 module mask 2 register L CAN 795 C0MASK3H CAN0 module mask 3 register H CAN 795 C0MASK3L CAN0 module mask 3 register L CAN 795 C0MASK4H CAN0 module mask 4 register H CAN 795 C0MASK4L CAN0 module mask 4 register L CAN 795 C0MCONFm CAN0 massage configuration register m CAN 819 C0MCTRLm CAN0 message control register m CAN 821 C0MDATA01m CAN0 massage data byte 01 register m CAN 816 C0MDATA0m CAN0 massage data byte 0 register m CAN 816 C0MDATA1m CAN0 massage data byte 1 register m CAN 816 C0MDATA23m CAN0 massage data byte 23 register m CAN 816 C0MDATA2m CAN0 massage data byte 2 register m CAN 816 C0MDATA3m CAN0 massage data byte 3 register m CAN 816 C0MDATA45m CAN0 massage data byte 45 register m CAN 816 C0MDATA4m CAN0 massage data byte 4 register m CAN 816 C0MDATA5m CAN0 massage data byte 5 register m CAN 816 C0MDATA67m CAN0 massage data byte 67 register m CAN 816 C0MDATA6m CAN0 massage data byte 6 register m CAN 816 C0MDATA7m CAN0 massage data byte 7 register m CAN 816 C0MDLCm CAN0 message data length register m CAN 818 C0MIDHm CAN0 message ID register mH CAN 820 C0MIDLm CAN0 message ID register mL CAN 820 C0RGPT CAN0 module receive history list register CAN 811 C0TGPT CAN0 module transmit history list register CAN 813 C0TS CAN0 module time stamp register CAN 814 CB0CTL0 CSIB0 control register 0 CSIB 547 CB0CTL1 CSIB0 control register 1 CSIB 551 CB0CTL2 CSIB0 control register 2 CSIB 552 CB0RIC Interrupt control register INTC 933 Remark 1116 m = 00 to 31 User's Manual U16541EJ5V1UD APPENDIX C REGISTER INDEX (3/12) Symbol Name Unit Page CB0RX CSIB0 receive data register CSIB 546 CB0RXL CSIB0 receive data register L CSIB 546 CB0STR CSIB0 status register CSIB 554 CB0TIC Interrupt control register INTC 933 CB0TX CSIB0 transmit data register CSI 546 CB0TXL CSIB0 transmit data register L CSI 546 CB1CTL0 CSIB1 control register 0 CSI 547 CB1CTL1 CSIB1 control register 1 CSI 551 CB1CTL2 CSIB1 control register 2 CSI 552 CB1RIC Interrupt control register INTC 933 CB1RX CSIB1 receive data register CSI 546 CB1RXL CSIB1 receive data register L CSI 546 CB1STR CSIB1 status register CSI 554 CB1TIC Interrupt control register INTC 933 CB1TX CSIB1 transmit data register CSI 546 CB1TXL CSIB1 transmit data register L CSI 546 CB2CTL0 CSIB2 control register 0 CSI 547 CB2CTL1 CSIB2 control register 1 CSI 551 CB2CTL2 CSIB2 control register 2 CSI 552 CB2RIC Interrupt control register INTC 933 CB2RX CSIB2 receive data register CSI 546 CB2RXL CSIB2 receive data register L CSI 546 CB2STR CSIB2 status register CSI 554 CB2TIC Interrupt control register INTC 933 CB2TX CSIB2 transmit data register CSI 546 CB2TXL CSIB2 transmit data register L CSI 546 CB3CTL0 CSIB3 control register 0 CSI 547 CB3CTL1 CSIB3 control register 1 CSI 551 CB3CTL2 CSIB3 control register 2 CSI 552 CB3RIC Interrupt control register INTC 933 CB3RX CSIB3 receive data register CSI 546 CB3RXL CSIB3 receive data register L CSI 546 CB3STR CSIB3 status register CSI 554 CB3TIC Interrupt control register INTC 933 CB3TX CSIB3 transmit data register CSI 546 CB3TXL CSIB3 transmit data register L CSI 546 CB4CTL0 CSIB4 control register 0 CSI 547 CB4CTL1 CSIB4 control register 1 CSI 551 CB4CTL2 CSIB4 control register 2 CSI 552 CB4RIC Interrupt control register INTC 933 CB4RX CSIB4 receive data register CSI 546 CB4RXL CSIB4 receive data register L CSI 546 CB4STR CSIB4 status register CSI 554 CB4TIC Interrupt control register INTC 933 CB4TX CSIB4 transmit data register CSI 546 User's Manual U16541EJ5V1UD 1117 APPENDIX C REGISTER INDEX (4/12) Symbol Name Unit Page CB4TXL CSIB4 transmit data register L CSI 546 CCLS CPU operation clock status register CG 218 CCR IEBus communication count register IEBus 720 CDR IEBus control data register IEBus 711 CKC Clock control register CG 221 CLM Clock monitor mode register CLM 995 CORAD0 Correction address register 0 ROMC 1009 CORAD0H Correction address register 0H ROMC 1009 CORAD0L Correction address register 0L ROMC 1009 CORAD1 Correction address register 1 ROMC 1009 CORAD1H Correction address register 1H ROMC 1009 CORAD1L Correction address register 1L ROMC 1009 CORAD2 Correction address register 2 ROMC 1009 CORAD2H Correction address register 2H ROMC 1009 CORAD2L Correction address register 2L ROMC 1009 CORAD3 Correction address register 3 ROMC 1009 CORAD3H Correction address register 3H ROMC 1009 CORAD3L Correction address register 3L ROMC 1009 CORCN Correction control register ROMC 1011 CRCD CRC data register CRC 913 CRCIN CRC input register CRC 913 CTBP CALLT base pointer CPU 63 CTPC CALLT execution status saving register CPU 62 CTPSW CALLT execution status saving register CPU 62 DA0CS0 D/A converter value setting register 0 DAC 501 DA0CS1 D/A converter value setting register 1 DAC 501 DA0M D/A converter mode register DAC 500 DADC0 DMA addressing control register 0 DMAC 894 DADC1 DMA addressing control register 1 DMAC 894 DADC2 DMA addressing control register 2 DMAC 894 DADC3 DMA addressing control register 3 DMAC 894 DBC0 DMA transfer count register 0 DMAC 893 DBC1 DMA transfer count register 1 DMAC 893 DBC2 DMA transfer count register 2 DMAC 893 DBC3 DMA transfer count register 3 DMAC 893 DBPC Exception/debug trap status saving register CPU 63 DBPSW Exception/debug trap status saving register CPU 63 DCHC0 DMA channel control register 0 DMAC 895 DCHC1 DMA channel control register 1 DMAC 895 DCHC2 DMA channel control register 2 DMAC 895 DCHC3 DMA channel control register 3 DMAC 895 DDA0H DMA destination address register 0H DMAC 892 DDA0L DMA destination address register 0L DMAC 892 DDA1H DMA destination address register 1H DMAC 892 DDA1L DMA destination address register 1L DMAC 892 1118 User's Manual U16541EJ5V1UD APPENDIX C REGISTER INDEX (5/12) Symbol Name Unit Page DDA2H DMA destination address register 2H DMAC 892 DDA2L DMA destination address register 2L DMAC 892 DDA3H DMA destination address register 3H DMAC 892 DDA3L DMA destination address register 3L DMAC 892 DLR IEBus telegraph length register IEBus 716 DMAIC0 Interrupt control register INTC 933 DMAIC1 Interrupt control register INTC 933 DMAIC2 Interrupt control register INTC 933 DMAIC3 Interrupt control register INTC 933 DR IEBus data register IEBus 717 DSA0H DMA source address register 0H DMAC 891 DSA0L DMA source address register 0L DMAC 891 DSA1H DMA source address register 1H DMAC 891 DSA1L DMA source address register 1L DMAC 891 DSA2H DMA source address register 2H DMAC 891 DSA2L DMA source address register 2L DMAC 891 DSA3H DMA source address register 3H DMAC 891 DSA3L DMA source address register 3L DMAC 891 DTFR0 DMA trigger source register 0 DMAC 896 DTFR1 DMA trigger source register 1 DMAC 896 DTFR2 DMA trigger source register 2 DMAC 896 DTFR3 DMA trigger source register 3 DMAC 896 DWC0 Data wait control register 0 BCU 197 ECR Interrupt source register CPU 60 EIPC Interrupt status saving register CPU 59 EIPSW Interrupt status saving register CPU 59 ERRIC Interrupt control register INTC 933 ERRIC0 Interrupt control register INTC 933 ESR IEBus error status register IEBus 705 EXIMC External bus interface mode control register BCU 187 FEPC NMI status saving register CPU 60 FEPSW NMI status saving register CPU 60 FSR IEBus field status register IEBus 718 IEIC1 Interrupt control register INTC 933 IEIC2 Interrupt control register INTC IIC0 IIC shift register 0 IC IIC1 IIC shift register 1 IC 615 2 615 2 615 2 601 2 601 2 601 2 611 2 611 2 611 2 609 IIC2 IIC shift register 2 IC IICC0 IIC control register 0 IC IICC1 IIC control register 1 IC IICC2 IIC control register 2 IC IICCL0 IIC clock select register 0 IC IICCL1 IIC clock select register 1 IC IICCL2 IIC clock select register 2 IC IICF0 IIC flag register 0 IC User's Manual U16541EJ5V1UD 933 2 1119 APPENDIX C REGISTER INDEX (6/12) Symbol Name Unit Page 2 609 IC 2 609 Interrupt control register INTC 933 Interrupt control register INTC 933 Interrupt control register INTC 933 IICF1 IIC flag register 1 IC IICF2 IIC flag register 2 IICIC0 IICIC1 IICIC2 2 606 2 606 2 606 2 612 2 612 2 IICS0 IIC status register 0 IC IICS1 IIC status register 1 IC IICS2 IIC status register 2 IC IICX0 IIC function extension register 0 IC IICX1 IIC function extension register 1 IC IICX2 IIC function extension register 2 IC 612 IMR0 Interrupt mask register 0 INTC 936 IMR0H Interrupt mask register 0H INTC 936 IMR0L Interrupt mask register 0L INTC 936 IMR1 Interrupt mask register 1 INTC 936 IMR1H Interrupt mask register 1H INTC 936 IMR1L Interrupt mask register 1L INTC 936 IMR2 Interrupt mask register 2 INTC 936 IMR2H Interrupt mask register 2H INTC 936 IMR2L Interrupt mask register 2L INTC 936 IMR3 Interrupt mask register 3 INTC 936 IMR3H Interrupt mask register 3H INTC 936 IMR3L Interrupt mask register 3L INTC 936 INTF0 External interrupt falling edge specification register 0 INTC 948 INTF3 External interrupt falling edge specification register 3 INTC 949 INTF9H External interrupt falling edge specification register 9H INTC 950 INTR0 External interrupt rising edge specification register 0 INTC 948 INTR3 External interrupt rising edge specification register 3 INTC 949 INTR9H External interrupt rising edge specification register 9H INTC 950 ISPR In-service priority register INTC 938 ISR IEBus interrupt status register IEBus 702 KRIC Interrupt control register INTC 933 KRM Key return mode register KR 957 LOCKR Lock register CG 222 LVIIC Interrupt control register INTC 933 LVIM Low voltage detection register LVI 1000 LVIS Low voltage detection level select register LVI 1001 NFC Noise elimination control register INTC 951 OCDM On-chip debug mode register Debug 1046 OCKS0 IIC divided clock select register 0 IC OCKS1 IIC divided clock select register 1 IC OCKS2 IEBus clock select register IEBus 721 OSTS Oscillation stabilization time select register Standby 962 P0 Port 0 register Port 104 P1 Port 1 register Port 107 1120 User's Manual U16541EJ5V1UD 2 615 2 615 APPENDIX C REGISTER INDEX (7/12) Symbol Name Unit Page P3 Port 3 register Port 109 P3H Port 3 register H Port 109 P3L Port 3 register L Port 109 P4 Port 4 register Port 115 P5 Port 5 register Port 118 P7H Port 7 register H Port 122 P7L Port 7 register L Port 122 P9 Port 9 register Port 125 P9H Port 9 register H Port 125 P9L Port 9 register L Port 125 PAR IEBus partner address register IEBus 710 PC Program counter CPU 57 PCC Processor clock control register CG 214 PCM Port CM register Port 132 PCT Port CT register Port 134 PDH Port DH register Port 136 PDL Port DL register Port 139 PDLH Port DL register H Port 139 PDLL Port DL register L Port 139 PEMU1 Peripheral emulation register 1 CPU 1005 PF0 Port 0 function register Port 106 PF3 Port 3 function register Port 114 PF3H Port 3 function register H Port 114 PF3L Port 3 function register L Port 114 PF4 Port 4 function register Port 117 PF5 Port 5 function register Port 121 PF9 Port 9 function register Port 131 PF9H Port 9 function register H Port 131 PF9L Port 9 function register L Port 131 PFC0 Port 0 function control register Port 106 PFC3 Port 3 function control register Port 112 PFC3H Port 3 function control register H Port 112 PFC3L Port 3 function control register L Port 112 PFC4 Port 4 function control register Port 116 PFC5 Port 5 function control register Port 120 PFC9 Port 9 function control register Port 128 PFC9H Port 9 function control register H Port 128 PFC9L Port 9 function control register L Port 128 PFCE3L Port 3 function control extension register L Port 112 PFCE5 Port 5 function control extension register Port 120 PFCE9 Port 9 function control extension register Port 128 PFCE9H Port 9 function control extension register H Port 128 PFCE9L Port 9 function control extension register L Port 128 PIC0 Interrupt control register INTC 933 PIC1 Interrupt control register INTC 933 User's Manual U16541EJ5V1UD 1121 APPENDIX C REGISTER INDEX (8/12) Symbol Name Unit Page PIC2 Interrupt control register INTC 933 PIC3 Interrupt control register INTC 933 PIC4 Interrupt control register INTC 933 PIC5 Interrupt control register INTC 933 PIC6 Interrupt control register INTC 933 PIC7 Interrupt control register INTC 933 PLLCTL PLL control register CG 220 PLLS PLL lockup time specification register CG 223 PM0 Port 0 mode register Port 105 PM1 Port 1 mode register Port 107 PM3 Port 3 mode register Port 109 PM3H Port 3 mode register H Port 109 PM3L Port 3 mode register L Port 109 PM4 Port 4 mode register Port 115 PM5 Port 5 mode register Port 119 PM7H Port 7 mode register H Port 123 PM7L Port 7 mode register L Port 123 PM9 Port 9 mode register Port 125 PM9H Port 9 mode register H Port 125 PM9L Port 9 mode register L Port 125 PMC0 Port 0 mode control register Port 105 PMC3 Port 3 mode control register Port 110 PMC3H Port 3 mode control register H Port 110 PMC3L Port 3 mode control register L Port 110 PMC4 Port 4 mode control register Port 116 PMC5 Port 5 mode control register Port 119 PMC9 Port 9 mode control register Port 126 PMC9H Port 9 mode control register H Port 126 PMC9L Port 9 mode control register L Port 126 PMCCM Port CM mode control register Port 133 PMCCT Port CT mode control register Port 135 PMCDH Port DH mode control register Port 137 PMCDL Port DL mode control register Port 140 PMCDLH Port DL mode control register H Port 140 PMCDLL Port DL mode control register L Port 140 PMCM Port CM mode register Port 132 PMCT Port CT mode register Port 134 PMDH Port DH mode register Port 136 PMDL Port DL mode register Port 139 PMDLH Port DL mode register H Port 139 PMDLL Port DL mode register L Port 139 PRCMD Command register CPU 91 PRSCM0 Prescaler compare register 0 WT 444 PRSCM1 BRG1 prescaler compare register BRG 591 PRSCM2 BRG2 prescaler compare register BRG 591 1122 User's Manual U16541EJ5V1UD APPENDIX C REGISTER INDEX (9/12) Symbol Name Unit Page PRSCM3 BRG3 prescaler compare register BRG 591 PRSM0 Prescaler mode register 0 WT 443 PRSM1 BRG1 prescaler mode register BRG 590 PRSM2 BRG2 prescaler mode register BRG 590 PRSM3 BRG3 prescaler mode register BRG 590 PSC Power save control register CG 960 PSMR Power save mode register CG 961 PSR IEBus power save register IEBus 697 PSW Program status word CPU 61 r0 to r31 General-purpose registers CPU 57 RAMS Internal RAM data status register CG 993 RCM Internal oscillation mode register CG 218 RECIC0 Interrupt control register INTC 933 RESF Reset source flag register Reset 982 RSA IEBus receive slave address register IEBus 711 RTBH0 Real-time output buffer register 0H RTP 457 RTBL0 Real-time output buffer register 0L RTP 457 RTPC0 Real-time output port control register 0 RTP 459 RTPM0 Real-time output port mode register 0 RTP 458 SAR IEBus slave address register IEBus 710 SCR IEBus success count register IEBus 719 SELCNT0 Selector operation control register 0 Timer 322 SSR IEBus slave status register IEBus 698 STAIC Interrupt control register INTC SVA0 Slave address register 0 IC 933 SVA1 Slave address register 1 IC SVA2 Slave address register 2 IC SYS System status register 0 CPU 92 TM0CMP0 TMM0 compare register 0 Timer 433 TM0CTL0 TMM0 control register 0 Timer 434 TM0EQIC0 Interrupt control register INTC 933 TP0CCIC0 Interrupt control register INTC 933 2 616 2 616 2 616 TP0CCIC1 Interrupt control register INTC 933 TP0CCR0 TMP0 capture/compare register 0 Timer 235 TP0CCR1 TMP0 capture/compare register 1 Timer 237 TP0CNT TMP0 counter read buffer register Timer 239 TP0CTL0 TMP0 control register 0 Timer 228 TP0CTL1 TMP0 control register 1 Timer 228 TP0IOC0 TMP0 I/O control register 0 Timer 230 TP0IOC1 TMP0 I/O control register 1 Timer 232 TP0IOC2 TMP0 I/O control register 2 Timer 233 TP0OPT0 TMP0 option register 0 Timer 234 TP0OVIC Interrupt control register INTC 933 TP1CCIC0 Interrupt control register INTC 933 TP1CCIC1 Interrupt control register INTC 933 User's Manual U16541EJ5V1UD 1123 APPENDIX C REGISTER INDEX (10/12) Symbol Name Unit Page TP1CCR0 TMP1 capture/compare register 0 Timer 235 TP1CCR1 TMP1 capture/compare register 1 Timer 237 TP1CNT TMP1 counter read buffer register Timer 239 TP1CTL0 TMP1 control register 0 Timer 228 TP1CTL1 TMP1 control register 1 Timer 228 TP1IOC0 TMP1 I/O control register 0 Timer 230 TP1IOC1 TMP1 I/O control register 1 Timer 232 TP1IOC2 TMP1 I/O control register 2 Timer 233 TP1OPT0 TMP1 option register 0 Timer 234 TP1OVIC Interrupt control register INTC 933 TP2CCIC0 Interrupt control register INTC 933 TP2CCIC1 Interrupt control register INTC 933 TP2CCR0 TMP2 capture/compare register 0 Timer 235 TP2CCR1 TMP2 capture/compare register 1 Timer 237 TP2CNT TMP2 counter read buffer register Timer 239 TP2CTL0 TMP2 control register 0 Timer 228 TP2CTL1 TMP2 control register 1 Timer 228 TP2IOC0 TMP2 I/O control register 0 Timer 230 TP2IOC1 TMP2 I/O control register 1 Timer 232 TP2IOC2 TMP2 I/O control register 2 Timer 233 TP2OPT0 TMP2 option register 0 Timer 234 TP2OVIC Interrupt control register INTC 933 TP3CCIC0 Interrupt control register INTC 933 TP3CCIC1 Interrupt control register INTC 933 TP3CCR0 TMP3 capture/compare register 0 Timer 235 TP3CCR1 TMP3 capture/compare register 1 Timer 237 TP3CNT TMP3 counter read buffer register Timer 239 TP3CTL0 TMP3 control register 0 Timer 228 TP3CTL1 TMP3 control register 1 Timer 228 TP3IOC0 TMP3 I/O control register 0 Timer 230 TP3IOC1 TMP3 I/O control register 1 Timer 232 TP3IOC2 TMP3 I/O control register 2 Timer 233 TP3OPT0 TMP3 option register 0 Timer 234 TP3OVIC Interrupt control register INTC 933 TP4CCIC0 Interrupt control register INTC 933 TP4CCIC1 Interrupt control register INTC 933 TP4CCR0 TMP4 capture/compare register 0 Timer 235 TP4CCR1 TMP4 capture/compare register 1 Timer 237 TP4CNT TMP4 counter read buffer register Timer 239 TP4CTL0 TMP4 control register 0 Timer 228 TP4CTL1 TMP4 control register 1 Timer 228 TP4IOC0 TMP4 I/O control register 0 Timer 230 TP4IOC1 TMP4 I/O control register 1 Timer 232 TP4IOC2 TMP4 I/O control register 2 Timer 233 TP4OPT0 TMP4 option register 0 Timer 234 1124 User's Manual U16541EJ5V1UD APPENDIX C REGISTER INDEX (11/12) Symbol Name Unit Page TP4OVIC Interrupt control register INTC 933 TP5CCIC0 Interrupt control register INTC 933 TP5CCIC1 Interrupt control register INTC 933 TP5CCR0 TMP5 capture/compare register 0 Timer 235 TP5CCR1 TMP5 capture/compare register 1 Timer 237 TP5CNT TMP5 counter read buffer register Timer 239 TP5CTL0 TMP5 control register 0 Timer 228 TP5CTL1 TMP5 control register 1 Timer 228 TP5IOC0 TMP5 I/O control register 0 Timer 230 TP5IOC1 TMP5 I/O control register 1 Timer 232 TP5IOC2 TMP5 I/O control register 2 Timer 233 TP5OPT0 TMP5 option register 0 Timer 234 TP5OVIC Interrupt control register INTC 933 TQ0CCIC0 Interrupt control register INTC 933 TQ0CCIC1 Interrupt control register INTC 933 TQ0CCIC2 Interrupt control register INTC 933 TQ0CCIC3 Interrupt control register INTC 933 TQ0CCR0 TMQ0 capture/compare register 0 Timer 334 TQ0CCR1 TMQ0 capture/compare register 1 Timer 336 TQ0CCR2 TMQ0 capture/compare register 2 Timer 338 TQ0CCR3 TMQ0 capture/compare register 3 Timer 340 TQ0CNT TMQ0 counter read buffer register Timer 342 TQ0CTL0 TMQ0 control register 0 Timer 328 TQ0CTL1 TMQ0 control register 1 Timer 329 TQ0IOC0 TMQ0 I/O control register 0 Timer 330 TQ0IOC1 TMQ0 I/O control register 1 Timer 331 TQ0IOC2 TMQ0 I/O control register 2 Timer 332 TQ0OPT0 TMQ0 option register 0 Timer 333 TQ0OVIC Interrupt control register INTC 933 TRXIC0 Interrupt control register INTC 933 UA0CTL0 UARTA0 control register 0 UARTA 510 UA0CTL1 UARTA0 control register 1 UARTA 512, 534 UA0CTL2 UARTA0 control register 2 UARTA 512, 535 UA0OPT0 UARTA0 option control register 0 UARTA 512 UA0RIC Interrupt control register INTC 933 UA0RX UARTA0 receive data register UARTA 516 UA0STR UARTA0 status register UARTA 514 UA0TIC Interrupt control register INTC 933 UA0TX UARTA0 transmit data register UARTA 516 UA1CTL0 UARTA1 control register 0 UARTA 510 UA1CTL1 UARTA1 control register 1 UARTA 512, 534 UA1CTL2 UARTA1 control register 2 UARTA 512, 535 UA1OPT0 UARTA1 option control register 0 UARTA 512 UA1RIC Interrupt control register INTC 933 UA1RX UARTA1 receive data register UARTA 516 User's Manual U16541EJ5V1UD 1125 APPENDIX C REGISTER INDEX (12/12) Symbol Name Unit Page UA1STR UARTA1 status register UARTA 514 UA1TIC Interrupt control register INTC 933 UA1TX UARTA1 transmit data register UARTA 516 UA2CTL0 UARTA2 control register 0 UARTA 510 UA2CTL1 UARTA2 control register 1 UARTA 512, 534 UA2CTL2 UARTA2 control register 2 UARTA 512, 535 UA2OPT0 UARTA2 option control register 0 UARTA 512 UA2RIC Interrupt control register INTC 933 UA2RX UARTA2 receive data register UARTA 516 UA2STR UARTA2 status register UARTA 514 UA2TIC Interrupt control register INTC 933 UA2TX UARTA2 transmit data register UARTA 516 UAR IEBus unit address register IEBus 710 USR IEBus unit status register IEBus 699 VSWC System wait control register CPU 93 WDTE Watchdog timer enable register WDT 454 WDTM2 Watchdog timer mode register 2 WDT 452, 939 WTIC Interrupt control register INTC 933 WTIIC Interrupt control register INTC 933 WTM Watch timer operation mode register WT 445 WUPIC0 Interrupt control register INTC 933 1126 User's Manual U16541EJ5V1UD APPENDIX D INSTRUCTION SET LIST D.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immX X bit immediate data dispX X bit displacement data regID System register number vector 5-bit data that specifies the trap vector (00H to 1FH) cccc 4-bit data that shows the conditions code sp Stack pointer (r3) ep Element pointer (r30) listX X item register list (2) Register symbols used to describe opcodes Register Symbol Explanation R 1-bit data of a code that specifies reg1 or regID r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data I 1-bit immediate data (indicates the higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes CCCC 4-bit data that shows the condition codes of Bcond instruction bbb 3-bit data for specifying the bit number L 1-bit data that specifies a program register in the register list User's Manual U16541EJ5V1UD 1127 APPENDIX D INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a. store-memory (a, b, c) Write data b into address a in size c. load-memory-bit (a, b) Read bit b of address a. store-memory-bit (a, b, c) Write c to bit b of address a. saturated (n) Execute saturated processing of n (n is a 2's complement). If, as a result of calculations, n 7FFFFFFFH, let it be 7FFFFFFFH. n 80000000H, let it be 80000000H. result Reflects the results in a flag. Byte Byte (8 bits) Halfword Half word (16 bits) Word Word (32 bits) + Addition - Subtraction ll Bit concatenation x Multiplication / Division % Remainder from division results AND Logical product OR Logical sum XOR Exclusive OR NOT Logical negation logically shift left by Logical shift left logically shift right by Logical shift right arithmetically shift right by Arithmetic shift right (4) Register symbols used in execution clock Register Symbol i Explanation If executing another instruction immediately after executing the first instruction (issue). r If repeating execution of the same instruction immediately after executing the first instruction (repeat). l If using the results of instruction execution in the instruction immediately after the execution (latency). 1128 User's Manual U16541EJ5V1UD APPENDIX D INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change 0 Clear to 0 X Set or cleared in accordance with the results. R Previously saved values are restored. (6) Condition codes Condition Code Condition Formula Explanation (cccc) 0 0 0 0 OV = 1 Overflow 1 0 0 0 OV = 0 No overflow 0 0 0 1 CY = 1 Carry Lower (Less than) 1 0 0 1 No carry CY = 0 Not lower (Greater than or equal) 0 0 1 0 Z=1 Zero 1 0 1 0 Z=0 Not zero 0 0 1 1 (CY or Z) = 1 Not higher (Less than or equal) 1 0 1 1 (CY or Z) = 0 Higher (Greater than) 0 1 0 0 S=1 Negative 1 1 0 0 S=0 Positive - 0 1 0 1 Always (Unconditional) 1 1 0 1 SAT = 1 Saturated 0 1 1 0 (S xor OV) = 1 Less than signed 1 1 1 0 (S xor OV) = 0 Greater than or equal signed 0 1 1 1 ((S xor OV) or Z) = 1 Less than or equal signed 1 1 1 1 ((S xor OV) or Z) = 0 Greater than signed User's Manual U16541EJ5V1UD 1129 APPENDIX D INSTRUCTION SET LIST D.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock ADD ADDI reg1,reg2 i r l CY OV S Z SAT 1 1 1 x x x x r r rr r0 01 11 0 RRRRR GR[reg2]GR[reg2]+GR[reg1] imm5,reg2 rrrrr010010iiiii GR[reg2]GR[reg2]+sign-extend(imm5) 1 1 1 x x x x imm16,reg1,reg2 r r rr r1 10 00 0 RRRRR GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 x x x x i i i i i i i i i i i i i i i i AND reg1,reg2 r r rr r0 01 01 0 RRRRR GR[reg2]GR[reg2]AND GR[reg1] 1 1 1 0 x x ANDI imm16,reg1,reg2 r r rr r1 10 11 0 RRRRR GR[reg2]GR[reg1]AND zero-extend(imm16) 1 1 1 0 x x 2 2 2 i i i i i i i i i i i i i i i i Bcond disp9 ddddd1011dddcccc if conditions are satisfied Note 1 then PCPC+sign-extend(disp9) When conditions are satisfied Note 2 Note 2 Note 2 Note 22 Note 22 Note 22 <R> When conditions 1 1 1 1 1 1 x 0 x x 1 1 1 x 0 x x 4 4 4 are not satisfied BSH reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) BSW reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24) <R> CALLT imm6 0000001000iiiiii CTPCPC+2(return PC) CTPSWPSW Note 22 Note 22 Note 22 adrCTBP+zero-extend(imm6 logically shift left by 1) PCCTBP+zero-extend(Load-memory(adr,Halfword)) CLR1 bit#3,disp16[reg1] 10bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) 3 3 x 3 Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,0) reg2,[reg1] r r rr r1 11 11 1 RRRRR adrGR[reg1] 0000000011100100 Z flagNot(Load-memory-bit(adr,reg2)) 3 3 x 3 Note 3 Note 3 Note 3 Store-memory-bit(adr,reg2,0) CMOV cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i wwwww011000cccc0 if conditions are satisfied 1 1 1 1 1 1 then GR[reg3]sign-extended(imm5) else GR[reg3]GR[reg2] cccc,reg1,reg2,reg3 r r rr r1 11 11 1 RRRR if conditions are satisfied wwwww011001cccc0 then GR[reg3]GR[reg1] else GR[reg3]GR[reg2] CMP CTRET <R> DBRET <R> 1130 reg1,reg2 r r rr r0 01 11 1 RRRRR resultGR[reg2]-GR[reg1] 1 1 1 x x x x imm5,reg2 rrrrr010011iiiii resultGR[reg2]-sign-extend(imm5) 1 1 1 x x x x 0000011111100000 PCCTPC 3 3 3 R R R R R 0000000101000100 PSWCTPSW 0000011111100000 PCDBPC R R R R R 0000000101000110 PSWDBPSW User's Manual U16541EJ5V1UD Note 22 Note 22 Note 22 3 3 3 Note 22 Note 22 Note 22 APPENDIX D INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock DBTRAP 1111100001000000 <R> DBPCPC+2 (restored PC) DBPSWPSW i r l 3 3 3 CY OV S Z SAT Note 22 Note 22 Note 22 PSW.NP1 PSW.EP1 PSW.ID1 PC00000060H DI 0000011111100000 PSW.ID1 1 1 1 0000000101100000 DISPOSE imm5,list12 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) n+1 n+1 n+1 LLLLLLLLLLL00000 GR[reg in list12]Load-memory(sp,Word) Note 4 Note 4 Note 4 spsp+4 repeat 2 steps above until all regs in list12 is loaded imm5,list12,[reg1] 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) LLLLLLLLLLLRRRRR GR[reg in list12]Load-memory(sp,Word) n+3 n+3 n+3 Note 4 Note 4 Note 4 Note 5 spsp+4 repeat 2 steps above until all regs in list12 is loaded PCGR[reg1] DIV reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] 35 35 35 x x x wwwww01011000000 GR[reg3]GR[reg2]%GR[reg1] DIVH reg1,reg2 reg1,reg2,reg3 r r rr r0 00 01 0 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 35 35 35 x x x r r rr r1 11 11 1 RRRRR Note 6 35 35 35 x x x 34 34 34 x x x 34 34 34 x x x 0 x x GR[reg2]GR[reg2]/GR[reg1] wwwww01010000000 GR[reg3]GR[reg2]%GR[reg1] DIVHU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 wwwww01010000010 GR[reg3]GR[reg2]%GR[reg1] DIVU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] wwwww01011000010 GR[reg3]GR[reg2]%GR[reg1] EI 1000011111100000 PSW.ID0 1 1 1 Stop 1 1 1 GR[reg3]GR[reg2](15 : 0) ll GR[reg2] (31 : 16) 1 1 1 2 2 2 0000000101100000 HALT 0000011111100000 0000000100100000 HSW reg2,reg3 rrrrr11111100000 x wwwww01101000100 JARL disp22,reg2 <R> rrrrr11110dddddd GR[reg2]PC+4 ddddddddddddddd0 PCPC+sign-extend(disp22) Note 22 Note 22 Note 22 Note 7 JMP [reg1] 00000000011RRRRR PCGR[reg1] <R> 3 3 3 Note 22 Note 22 Note 22 JR disp22 <R> 0000011110dddddd PCPC+sign-extend(disp22) ddddddddddddddd0 2 2 2 Note 22 Note 22 Note 22 Note 7 LD.B LD.BU disp16[reg1],reg2 disp16[reg1],reg2 r r rr r1 11 00 0 RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd GR[reg2]sign-extend(Load-memory(adr,Byte)) r r rr r1 11 10 b RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddd1 GR[reg2]zero-extend(Load-memory(adr,Byte)) 1 1 Note 1 1 Note 11 11 Notes 8, 10 User's Manual U16541EJ5V1UD 1131 APPENDIX D INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock LD.H disp16[reg1],reg2 rrrrr111001RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 GR[reg2]sign-extend(Load-memory(adr,Halfword)) i r l 1 1 Note CY OV S Z SAT 11 Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]GR[reg2] 0000000000100000 Other than regID = PSW 1 1 1 regID = PSW 1 1 1 1 1 Note x x x x 0 x x Note 12 LD.HU disp16[reg1],reg2 r r rr r1 11 11 1 RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 GR[reg2]zero-extend(Load-memory(adr,Halfword) 11 Note 8 LD.W disp16[reg1],reg2 r r rr r1 11 00 1 RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 GR[reg2]Load-memory(adr,Word) 1 1 Note 11 Note 8 MOV reg1,reg2 r r rr r0 00 00 0 RRRRR GR[reg2]GR[reg1] 1 imm5,reg2 rrrrr010000iiiii GR[reg2]sign-extend(imm5) imm32,reg1 00000110001RRRRR GR[reg1]imm32 1 1 1 1 1 2 2 2 GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 GR[reg2]GR[reg1]+(imm16 ll 016) 1 1 1 GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 4 5 GR[reg3] ll GR[reg2]GR[reg2]xsign-extend(imm9) 1 4 5 GR[reg2]GR[reg2]Note 6xGR[reg1]Note 6 i i i i i i i i i i i i i i i i IIIIIIIIIIIIIIII MOVEA imm16,reg1,reg2 r r rr r1 10 00 1 RRRRR i i i i i i i i i i i i i i i i MOVHI imm16,reg1,reg2 r r rr r1 10 01 0 RRRRR i i i i i i i i i i i i i i i i MUL reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR wwwww01000100000 Note 14 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 00 Note 13 MULH reg1,reg2 imm5,reg2 MULHI imm16,reg1,reg2 r r rr r0 00 11 1 RRRRR rrrrr010111iiiii r r rr r1 10 11 1 RRRRR 1 1 2 GR[reg2]GR[reg2] Note 6 1 1 2 GR[reg2]GR[reg1] Note 6 1 1 2 1 4 5 1 4 5 xsign-extend(imm5) ximm16 i i i i i i i i i i i i i i i i MULU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] wwwww01000100010 Note 14 imm9,reg2,reg3 rrrrr111111iiiii GR[reg3] ll GR[reg2]GR[reg2]xzero-extend(imm9) wwwww01001IIII 10 Note 13 NOP NOT reg1,reg2 NOT1 bit#3,disp16[reg1] 0000000000000000 Pass at least one clock cycle doing nothing. 1 1 1 r r rr r0 00 00 1 RRRRR 1 1 1 3 3 3 GR[reg2]NOT(GR[reg1]) 01bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) x Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,Z flag) reg2,[reg1] r r rr r1 11 11 1 RRRRR adrGR[reg1] 0000000011100010 Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,Z flag) 1132 User's Manual U16541EJ5V1UD 3 3 3 Note 3 Note 3 Note 3 x x APPENDIX D INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock OR reg1,reg2 ORI imm16,reg1,reg2 i r l CY OV S Z SAT r r rr r0 01 00 0 RRRRR GR[reg2]GR[reg2]OR GR[reg1] 1 1 1 0 x x r r rr r1 10 10 0 RRRRR GR[reg2]GR[reg1]OR zero-extend(imm16) 1 1 1 0 x x R R R R i i i i i i i i i i i i i i i i PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) LLLLLLLLLLL00001 spsp-4 n+1 n+1 n+1 Note 4 Note 4 Note 4 repeat 1 step above until all regs in list12 is stored spsp-zero-extend(imm5) list12,imm5, 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) sp/immNote 15 LLLLLLLLLLLff011 spsp+4 imm16/imm32 repeat 1 step above until all regs in list12 is stored Note 16 spsp-zero-extend (imm5) epsp/imm RETI 0000011111100000 if PSW.EP=1 <R> 0000000101000000 then PC n+2 n+2 n+2 Note 4 Note 4 Note 4 Note17 Note17 Note17 3 EIPC 3 3 R Note 22 Note 22 Note 22 PSW EIPSW else if PSW.NP=1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW SAR reg1,reg2 imm5,reg2 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]arithmetically shift right 0000000010100000 by GR[reg1] rrrrr010101iiiii GR[reg2]GR[reg2]arithmetically shift right 1 1 1 x 0 x x 1 1 1 x 0 x x 1 1 1 by zero-extend (imm5) SASF cccc,reg2 rrrrr1111110cccc if conditions are satisfied 0000001000000000 then GR[reg2](GR[reg2]Logically shift left by 1) OR 00000001H else GR[reg2](GR[reg2]Logically shift left by 1) OR 00000000H SATADD reg1,reg2 r r rr r0 00 11 0 RRRRR GR[reg2]saturated(GR[reg2]+GR[reg1]) 1 1 1 x x x x x imm5,reg2 rrrrr010001iiiii GR[reg2]saturated(GR[reg2]+sign-extend(imm5) 1 1 1 x x x x x SATSUB reg1,reg2 r r rr r0 00 10 1 RRRRR GR[reg2]saturated(GR[reg2]-GR[reg1]) 1 1 1 x x x x x SATSUBI imm16,reg1,reg2 r r rr r1 10 01 1 RRRRR GR[reg2]saturated(GR[reg1]-sign-extend(imm16) 1 1 1 x x x x x x x x x x i i i i i i i i i i i i i i i i SATSUBR reg1,reg2 r r rr r0 00 10 0 RRRRR GR[reg2]saturated(GR[reg1]-GR[reg2]) 1 1 1 SETF rrrrr1111110cccc If conditions are satisfied 1 1 1 0000000000000000 then GR[reg2]00000001H cccc,reg2 else GR[reg2]00000000H User's Manual U16541EJ5V1UD 1133 APPENDIX D INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit(adr,bit#3)) i r l 3 3 3 CY OV S Z SAT x Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) reg2,[reg1] r r rr r1 11 11 1 RRRRR adrGR[reg1] 0000000011100000 Z flagNot(Load-memory-bit(adr,reg2)) 3 3 x 3 Note 3 Note 3 Note 3 Store-memory-bit(adr,reg2,1) SHL reg1,reg2 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2] logically shift left by GR[reg1] 1 1 1 x 0 x x GR[reg2]GR[reg2] logically shift left 1 1 1 x 0 x x GR[reg2]GR[reg2] logically shift right by GR[reg1] 1 1 1 x 0 x x GR[reg2]GR[reg2] logically shift right 1 1 1 x 0 x x 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000000011000000 imm5,reg2 rrrrr010110iiiii by zero-extend(imm5) SHR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010000000 imm5,reg2 rrrrr010100iiiii by zero-extend(imm5) SLD.B disp7[ep],reg2 rrrrr0110ddddddd adrep+zero-extend(disp7) GR[reg2]sign-extend(Load-memory(adr,Byte)) SLD.BU disp4[ep],reg2 r r r r r 0 0 0 0 1 1 0 d d d d adrep+zero-extend(disp4) Note 18 GR[reg2]zero-extend(Load-memory(adr,Byte)) SLD.H disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d adrep+zero-extend(disp8) Note 19 GR[reg2]sign-extend(Load-memory(adr,Halfword)) SLD.HU disp5[ep],reg2 r r r r r 0 0 0 0 1 1 1 d d d d adrep+zero-extend(disp5) Notes 18, 20 GR[reg2]zero-extend(Load-memory(adr,Halfword)) SLD.W disp8[ep],reg2 r r r r r 1 0 1 0 d d d d d d 0 adrep+zero-extend(disp8) Note 21 GR[reg2]Load-memory(adr,Word) SST.B reg2,disp7[ep] rrrrr0111ddddddd adrep+zero-extend(disp7) Store-memory(adr,GR[reg2],Byte) SST.H reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d adrep+zero-extend(disp8) Note 19 Store-memory(adr,GR[reg2],Halfword) SST.W reg2,disp8[ep] r r r r r 1 0 1 0 d d d d d d 1 adrep+zero-extend(disp8) Note 21 Store-memory(adr,GR[reg2],Word) ST.B ST.H reg2,disp16[reg1] reg2,disp16[reg1] r r rr r1 11 01 0 RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Store-memory(adr,GR[reg2],Byte) r r rr r1 11 01 1 RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 Store-memory (adr,GR[reg2], Halfword) Note 8 ST.W reg2,disp16[reg1] rrrrr111011RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 Store-memory (adr,GR[reg2], Word) Note 8 STSR regID,reg2 r r rr r1 11 11 1 RRRRR GR[reg2]SR[regID] 0000000001000000 1134 User's Manual U16541EJ5V1UD APPENDIX D INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock SUB reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]GR[reg2]-GR[reg1] GR[reg2]GR[reg1]-GR[reg2] SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR SWITCH reg1 00000000010RRRRR adr(PC+2) + (GR [reg1] logically shift left by 1) i r l 1 1 1 x x x x x x x x 0 x x 1 1 1 5 5 5 1 1 1 1 1 1 3 3 3 CY OV S Z SAT PC(PC+2) + (sign-extend (Load-memory (adr,Halfword)) logically shift left by 1 SXB reg1 00000000101RRRRR GR[reg1]sign-extend (GR[reg1] (7 : 0)) SXH reg1 00000000111RRRRR GR[reg1]sign-extend (GR[reg1] (15 : 0)) TRAP vector <R> 00000111111iiiii EIPC PC+4 (Restored PC) 0000000100000000 EIPSW PSW Note 22 Note 22 Note 22 ECR.EICC Interrupt code PSW.EP 1 PSW.ID 1 PC 00000040H (when vector is 00H to 0FH) 00000050H (when vector is 10H to 1FH) TST reg1,reg2 TST1 bit#3,disp16[reg1] reg2, [reg1] XOR reg1,reg2 XORI imm16,reg1,reg2 r r rr r0 01 01 1 RRRRR resultGR[reg2] AND GR[reg1] 11bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit (adr,bit#3)) 1 1 1 3 3 3 x Note 3 Note 3 Note 3 3 3 x 3 r r rr r1 11 11 1 RRRRR adrGR[reg1] 0000000011100110 Z flagNot (Load-memory-bit (adr,reg2)) r r rr r0 01 00 1 RRRRR GR[reg2]GR[reg2] XOR GR[reg1] 1 1 1 0 x x r r rr r1 10 10 1 RRRRR GR[reg2]GR[reg1] XOR zero-extend (imm16) 1 1 1 0 x x Note 3 Note 3 Note 3 i i i i i i i i i i i i i i i i ZXB reg1 00000000100RRRRR GR[reg1]zero-extend (GR[reg1] (7 : 0)) 1 1 1 ZXH reg1 00000000110RRRRR GR[reg1]zero-extend (GR[reg1] (15 : 0)) 1 1 1 Notes 1. 2. dddddddd: Higher 8 bits of disp9. 3 if there is an instruction that rewrites the contents of the PSW immediately before. 3. If there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (According to the number of wait states. Also, if there 5. RRRRR: other than 00000. are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1) 6. The lower halfword data only are valid. 7. ddddddddddddddddddddd: The higher 21 bits of disp22. 8. ddddddddddddddd: The higher 15 bits of disp16. 9. According to the number of wait states (1 if there are no wait states). 10. b: bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states). User's Manual U16541EJ5V1UD 1135 APPENDIX D INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. I I I I : Higher 4 bits of imm9. 14. Do not specify the same register for general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: Load sp in ep. 01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18. r r r r r : Other than 00000. 19. ddddddd: Higher 7 bits of disp8. 20. dddd: Higher 4 bits of disp5. 21. dddddd: Higher 6 bits of disp8. <R> 22. +1 clock for the V850ES/SG2-H. 1136 User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition (1/10) Page Throughout Description * All product are changed to lead-free products. * Addition of V850ES/SG2-H pp. 26, 27 Modification of description in 1.2 Features pp. 31, 33 Addition of Note to 1.5 Pin Configuration (Top View) p. 35 Addition of description of Note to 1.6.1 Internal block diagram p. 39 Addition of description of Note to 2.1 (1) Port pins p. 43 Addition of description to 2.1 (2) Non-port pins p. 49 Modification of description in Table 2-2 Pin Operation States in Various Modes pp. 50, 51 Modification of description in 2.3 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins p. 53 Addition of description to Figure 2-1 Pin I/O Circuits p. 54 Modification of description in 2.4 (1) Cautions on power application p. 54 Addition of 2.4 (2) Cautions on FLMD0 pin p. 55 Addition of description to 3.1 Features p. 58 Addition of Note in Table 3-2 System Register Numbers p. 63 Addition of description to 3.2.2 (6) Exception/debug trap status saving registers (DBPC and DBPSW) p. 64 Modification of description in 3.3.1 Specifying operation mode p. 73 Addition of Caution to 3.4.4 (3) On-chip peripheral I/O area p. 74 Modification of Caution in 3.4.4 (5) External memory area pp. 79, 86 Addition of Note to 3.4.6 Peripheral I/O registers p. 89 Modification and addition of Note to 3.4.8 Special registers p. 92 Modification of description in 3.4.8 (3) (a) Set condition (PRERR flag = 1) p. 93 Addition of description to 3.4.9 (1) (a) System wait control register (VSWC) p. 94 Modification of description in 3.4.9 (2) Accessing specific on-chip peripheral I/O registers p. 106 Addition of Caution to 4.3.1 (5) Port 0 function register (PF0) p. 107 Modification of Caution in Table 4-5 Port 1 Alternate-Function Pins p. 107 Addition of Caution to 4.3.2 (1) Port 1 register (P1) p. 108 Modification of Caution in Table 4-6 Port 3 Alternate-Function Pins p. 114 Addition of Caution to 4.3.3 (7) Port 3 function register (PF3) p. 117 Addition of Caution to 4.3.4 (5) Port 4 function register (PF4) p. 118 Modification of Caution in Table 4-8 Port 5 Alternate-Function Pins p. 121 Addition of Caution to 4.3.5 (7) Port 5 function register (PF5) p. 122 Modification of description in 4.3.6 (1) Port 7 register H, port 7 register L (P7H, P7L) p. 124 Modification of Caution in Table 4-10 Port 9 Alternate-Function Pins p. 127 Modification of Caution in 4.3.7 (3) Port 9 mode control register (PMC9) p. 128 Modification of Caution in 4.3.7 (4) Port 9 function control register (PFC9) p. 131 Addition of Caution to 4.3.7 (7) Port 9 function register (PF9) User's Manual U16541EJ5V1UD 1137 APPENDIX E REVISION HISTORY (2/10) Page Description pp. 144, 146 to Modification of Figure 4-6, Figure 4-8 to Figure 4-11, Figure 4-13 to Figure 4-15, Figure 4-18, Figure 4-20 149, 151, 153, to Figure 4-32 156, 158 to 170 pp. 175 to 177 Modification of Note to Table 4-15 Using Port Pin as Alternate-Function Pin p. 183 Addition of Caution to 4.6.3 Cautions on on-chip debug pins p. 183 Modification of description in 4.6.5 Cautions on P10, P11, and P53 pins when power is turned on p. 183 Modification of description in 4.6.6 Hysteresis characteristics p. 183 Addition of 4.6.7 Cautions on separate bus mode p. 184 Deletion of description to 5.1 Features p. 188 Addition of 5.5.1 (2) In V850ES/SG2-H p. 197 Modification of description in 5.6.1 (1) Data wait control register 0 (DWC0) p. 200 Modification of description in 5.6.4 (1) Address wait control register (AWC) p. 211 Addition of description to 6.1 Overview p. 213 Addition of description to 6.2 (1) Main clock oscillator p. 218 Addition of Note to 6.3 (3) CPU operation clock status register (CCLS) p. 220 Addition of description to 6.5.1 Overview p. 220 Addition of Caution to 6.5.2 (1) PLL control register (PLLCTL) p. 221 Addition of description to 6.5.2 (2) Clock control register (CKC) p. 223 Modification of description in 6.5.3 (1) (b) To set IDLE2/STOP mode in PLL operation mode p. 228 Modification of Note in 7.4 (1) TMPn control register 0 (TPnCTL0) p. 229 Addition of description to 7.4 (2) TMPn control register 1 (TPnCTL1) p. 231 Addition of Note and Caution to 7.4 (3) TMPn I/O control register 0 (TPnIOC0) p. 232 Modification of description in 7.4 (4) TMPn I/O control register 1 (TPnIOC1) p. 234 Addition of description to 7.4 (6) TMPn option register 0 (TPnOPT0) p. 236 Addition of description to 7.4 (7) (a) Function as compare register p. 236 Addition of description to 7.4 (7) (b) Function as capture register p. 236 Addition of Note and Remark to Table 7-2 Function of Capture/Compare Register in Each Mode and How to Write Compare Register p. 238 Addition of description to 7.4 (8) (a) Function as compare register p. 238 Addition of description to 7.4 (8) (b) Function as capture register p. 238 Addition of Note and Remark to Table 7-3 Function of Capture/Compare Register in Each Mode and How to Write Compare Register p. 242 Addition of 7.6 (1) Counter basic operation p. 243 Addition of 7.6 (2) Anytime write and batch write p. 248 Modification of description in 7.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) pp. 249 to 251 Modification of description in Figure 7-8 Register Setting for Interval Timer Mode Operation p. 252 Addition of description to Figure 7-9 Software Processing Flow in Interval Timer Mode p. 253 Modification of description and Figure in 7.6.1 (2) (a) Operation if TPnCCR0 register is set to 0000H pp. 257,258 Addition of description to 7.6.1 (2) (d) Operation of TPnCCR1 register p. 259 Addition of 7.6.1 (3) Operation by external event count input (TIPn0) pp. 260 to 263 Modification of description in 7.6.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) p. 261 Modification of description in Figure 7-14 Basic Timing in External Event Count Mode 1138 User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY (3/10) Page Description p. 263 Modification of description in Figure 7-15 Register Setting for Operation in External Event Count Mode p. 265 Modification of description in 7.6.2 (2) (a) Operation if TPnCCR0 register is set to FFFFH p. 266 Modification of description in 7.6.2 (2) (b) Notes on rewriting the TPnCCR0 register p. 268 Addition of description to 7.6.2 (2) (c) Operation of TPnCCR1 register p. 269 Addition of Note and Caution to Figure 7-20 Configuration in External Trigger Pulse Output Mode pp. 270, 271 Modification of description in Figure 7-22 Setting of Registers in External Trigger Pulse Output Mode p. 277 Modification of description in 7.6.3 (2) (b) 0%/100% output of PWM waveform p. 281 Addition of Note and Caution to Figure 7-24 Configuration in One-Shot Pulse Output Mode p. 282 Modification of description in 7.6.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) pp. 283, 284 Modification of description in Figure 7-26 Setting of Registers in One-Shot Pulse Output Mode p. 288 Modification of Figure 7-28 Configuration in PWM Output Mode p. 295 Modification of description in 7.6.5 (2) (b) 0%/100% output of PWM waveform p. 297 Addition of Note to Figure 7-32 Configuration in Free-Running Timer Mode p. 301 Addition of Note to Figure 7-35 Register Setting in Free-Running Timer Mode p. 314 Addition of 7.6.6 (3) Note on capture operation p. 315 Modification of Figure and Caution in Figure 7-38 Configuration in Pulse Width Measurement Mode pp. 317, 318 Modification of description in Figure 7-40 Register Setting in Pulse Width Measurement Mode p. 319 Deletion of description in Figure 7-41 Software Processing Flow in Pulse Width Measurement Mode p. 320 Addition of 7.6.7 (3) Notes p. 328 Modification of Note to 8.4 (1) TMQ0 control register 0 (TQ0CTL0) p. 329 Addition of description to 8.4 (2) TMQ0 control register 1 (TQ0CTL1) p. 330 Addition of Note and Caution to 8.4 (3) TMQ0 I/O control register 0 (TQ0IOC0) p. 333 Addition of description to 8.4 (6) TMQ0 option register 0 (TQ0OPT0) p. 335 Addition of description to 8.4 (7) (a) Function as compare register p. 335 Addition of description to 8.4 (7) (b) Function as capture register p. 335 Addition of Note and Remark in Table 8-2 Function of Capture/Compare Register in Each Mode and How to Write Compare Register p. 337 Addition of description to 8.4 (8) (a) Function as compare register p. 337 Addition of description to 8.4 (8) (b) Function as capture register p. 337 Addition of Note and Remark in Table 8-3 Function of Capture/Compare Register in Each Mode and How to Write Compare Register p. 339 Addition of description to 8.4 (9) (a) Function as compare register p. 339 Addition of description to 8.4 (9) (b) Function as capture register p. 339 Addition of Note and Remark in Table 8-4 Function of Capture/Compare Register in Each Mode and How to Write Compare Register p. 341 Addition of description to 8.4 (10) (a) Function as compare register p. 341 Addition of description to 8.4 (10) (b) Function as capture register p. 341 Addition of Note and Remark in Table 8-5 Function of Capture/Compare Register in Each Mode and How to Write Compare Register p. 344 Addition of 8.6 (1) Counter basic operation p. 346 Addition of 8.6 (2) Anytime write and batch write p. 351 Modification of description in 8.6.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) User's Manual U16541EJ5V1UD 1139 APPENDIX E REVISION HISTORY (4/10) Page Description pp. 352 to 354 Modification of description in Figure 8-8 Register Setting for Interval Timer Mode Operation p. 355 Addition of description to Figure 8-9 Software Processing Flow in Interval Timer Mode p. 356 Modification of description and Figure in 8.6.1 (2) (a) Operation if TQ0CCR0 register is set to 0000H pp. 359, 360 Addition of description to 8.6.1 (2) (d) Operation of TQ0CCR1 to TQ0CCR3 registers p. 361 Addition of 8.6.1 (3) Operation by external event count input (TIQ00) pp. 362, 364 Addition of description to 8.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) p. 363 Modification of description in Figure 8-14 Basic Timing in External Event Count Mode p. 365 Modification of description in Figure 8-15 Register Setting for Operation in External Event Count Mode p. 367 Modification of description in 8.6.2 (2) (a) Operation if TQ0CCR0 register is set to FFFFH p. 368 Modification of description in 8.6.2 (2) (b) Notes on rewriting the TQ0CCR0 register p. 369 Addition of description to 8.6.2 (2) (c) Operation of TQ0CCR1 to TQ0CCR3 registers p. 372 Modification of description in 8.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) p. 372 Addition of Note and Caution to Figure 8-20 Configuration in External Trigger Pulse Output Mode pp. 374 to 376 Modification of description in Figure 8-22 Setting of Registers in External Trigger Pulse Output Mode p. 381 Modification of description in 8.6.3 (2) (b) 0%/100% output of PWM waveform p. 385 Addition of Note and Caution to Figure 8-24 Configuration in One-Shot Pulse Output Mode p. 385 Modification of description in 8.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) pp. 387 to 389 Modification of description in Figure 8-26 Setting of Registers in One-Shot Pulse Output Mode p. 394 Modification of Figure 8-28 Configuration in PWM Output Mode p. 403 Modification of description in 8.6.5 (2) (b) 0%/100% output of PWM waveform p. 406 Addition of Note to Figure 8-32 Configuration in Free-Running Timer Mode p. 410 Addition of Note to Figure 8-35 Register Setting in Free-Running Timer Mode p. 425 Addition of 8.6.6 (3) Note on capture operation p. 426 Modification of Figure and additioin of Caution to Figure 8-38 Configuration in Pulse Width Measurement Mode pp. 428, 429 Modification of description in Figure 8-40 Register Setting in Pulse Width Measurement Mode p. 430 Deletion of description in Figure 8-41 Software Processing Flow in Pulse Width Measurement Mode p. 431 Addition of 8.6.7 (3) Note p. 435 Modification of Figure 9-3 Basic Timing of Operation in Interval Timer Mode p. 438 Modification of figure in 9.4.1 (2) (a) Operation if TM0CMP0 register is set to 0000H p. 438 Modification of figure in 9.4.1 (2) (b) Operation if TM0CMP0 register is set to N p. 439 Addition of 9.4.2 (3) Do not set the TM0CMP0 register to FFFFH p. 452 Modification and addition of Caution to 11.3 (1) Watchdog timer mode register 2 (WDTM2) p. 453 Modification of description in Table 11-2 Watchdog Timer 2 Clock Selection p. 454 Addition of Caution to 11.3 (2) Watchdog timer enable register (WDTE) p. 467 Modification and addition of Note to 13.4 (1) A/D converter mode register 0 (ADA0M0) p. 468 Addition and modification of Note to 13.4 (2) A/D converter mode register 1 (ADA0M1) p. 469 Modification of description in Table 13-2 Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) p. 470 Modification of description in Table 13-3 Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) p. 471 1140 Addition of Caution to 13.4 (3) A/D converter mode register 2 (ADA0M2) User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY (5/10) Page Description p. 472 Addition of Caution to 13.4 (4) Analog input channel specification register (ADA0S) p. 475 Addition of Caution to 13.4 (6) Power-fail compare mode register (ADA0PFM) p. 476 Addition of Caution to 13.4 (7) Power-fail compare threshold value register (ADA0PFT) p. 477 Addition of Remark to 13.5.1 Basic operation p. 478 Modification of description in Figure 13-3 Conversion Operation Timing (Continuous Conversion) p. 479 Addition of description to 13.5.3 (1) Software trigger mode p. 479 Addition of description to 13.5.3 (2) External trigger mode p. 480 Addition of description to 13.5.3 (3) Timer trigger mode p. 491 Modification of description in 13.6 (4) Alternate I/O p. 492 Modification of description in Figure 13-14 Internal Equivalent Circuit of ANIn Pin p. 493 Modification of description in 13.6 (8) Reading ADA0CRn register p. 494 Modification of description in 13.6 (10) Restriction for each mode p. 507 Addition of description to 15.2 Features p. 508 Modification of Block Diagram in Figure 15-4 Block Diagram of Asynchronous Serial Interface An p. 511 Modification of description in 15.4 (1) UARTAn control register 0 (UAnCTL0) pp. 512, 513 Addition of description to 15.4 (4) UARTAn option control register 0 (UAnOPT0) p. 514 Addition of Caution to 15.4 (5) UARTAn status register (UAnSTR) p. 516 Addition of description to 15.4 (6) UARTAn receive data register (UAnRX) p. 516 Addition of description to 15.4 (7) UARTAn transmit data register (UAnTX) p. 519 Modification of description in Figure 15-5 UARTA Transmit/Receive Data Format p. 523 Addition of Caution to 15.6.4 SBF reception p. 527 Modification of Figure 15-12 Continuous Transmission Operation Timing p. 533 Addition of Caution to Figure 15-16 Configuration of Baud Rate Generator p. 533 Addition of description to 15.7 (1) (a) Base clock p. 537 Addition of description to Table 15-3 Baud Rate Generator Setting Data p. 544 Addition of description to 16.2 Features pp. 547, 549 Addition of Note and Caution in 16.4 (1) CSIBn control register 0 (CBnCTL0) p. 550 Addition of 16.4 (1) (a) How to use CBnSCE bit p. 551 Addition of Note to 16.4 (2) CSIBn control register 1 (CBnCTL1) p. 554 Addition of Caution to 16.4 (4) CSIBn status register (CBnSTR) p. 555 Addition of 16.5 Interrupt Request Signals p. 556 Addition of 16.6.1 Single transfer mode (master mode, transmission mode) p. 558 Modification of description in 16.6.2 Single transfer mode (master mode, reception mode) p. 560 Modification of description in 16.6.3 Single transfer mode (master mode, transmission/reception mode) p. 562 Addition of 16.6.4 Single transfer mode (slave mode, transmission mode) p. 564 Addition of 16.6.5 Single transfer mode (slave mode, reception mode) p. 566 Addition of 16.6.6 Single transfer mode (slave mode, transmission/reception mode) p. 568 Addition of 16.6.7 Continuous transfer mode (master mode, transmission mode) p. 570 Modification of description in 16.6.8 Continuous transfer mode (master mode, reception mode) p. 573 Modification of description in 16.6.9 Continuous transfer mode (master mode, transmission/reception mode) User's Manual U16541EJ5V1UD 1141 APPENDIX E REVISION HISTORY (6/10) Page Description p. 577 Addition of 16.6.10 Continuous transfer mode (slave mode, transmission mode) p. 579 Modification of description in 16.6.11 Continuous transfer mode (slave mode, reception mode) p. 582 Modification of description in 16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) p. 586 Modification of description in 16.6.13 Reception error pp. 587, 588 Modification of description in 16.6.14 Clock timing p. 591 Addition of Caution to 16.8.1 Baud rate generation p. 603 Deletion of description in 17.4 (1) IIC control registers 0 to 2 (IICC0 to IICC2) p. 612 Addition of description to 17.4 (6) I C0n transfer clock setting method pp. 613, 614 Addition of description and Note to Table 17-2 Clock Settings p. 624 Modification of description in 17.6.6 Wait state p. 625 Addition of Note to 17.6.7 Wait state cancellation method p. 627 Addition of Note to 17.7.1 (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) p. 628 2 Addition of Note and deletion of description to 17.7.1 (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) p. 629 Addition of Note to 17.7.1 (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) p. 633 Modification of description in 17.7.2 (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop p. 634 Addition of description to 17.7.3 Slave device operation (when receiving extension code) p. 637 Modification of description in 17.7.3 (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop p. 639 Addition of description to 17.7.5 Arbitration loss operation (operation as slave after arbitration loss) p. 641 Addition of description to 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) p. 645 Modification of description in 17.7.6 (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition p. 647 Modification of description in 17.7.6 (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition p. 650 p. 653 Addition of description to 17.11 Extension Code Modification of description in 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) p. 654 Addition of Note to Table 17-6 Wait Periods p. 655 Modification of Figure 17-15 Communication Reservation Timing p. 657 Modification of description in Table 17-7 Wait Periods p. 659 Modification of description in 17.16 Communication Operations p. 666 Modification of Figure 17-21 Slave Operation Flowchart (1) p. 667 Modification of Figure 17-22 Slave Operation Flowchart (2) pp. 669 to 671 Modification of Figure 17-23 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) pp. 672 to 674 Modification of Figure 17-24 Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) p. 690 Modification of description in Figure 18-10 IEBus Controller Block Diagram p. 721 Addition of description to 18.3 (17) IEBus clock select register (OCKS2) p. 743 Addition of Caution to CHAPTER 19 CAN CONTROLLER p. 744 Deletion of description in Table 19-1 Overview of Functions 1142 User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY (7/10) Page Description p. 759 Modification of description in 19.3.6 (4) (b) Error counter p. 760 Addition of Caution to 19.3.6 (5) (a) Recovery from bus-off state through normal recovery sequence p. 762 Modification of description in Figure 19-18 Segment Setting p. 790 Addition of Caution to 19.6 (1) CAN0 global control register (C0GMCTRL) p. 793 Addition of Caution to 19.6 (3) CAN0 global automatic block transmission control register (C0GMABT) pp. 797 to 799 Modification of description in 19.6 (6) CAN0 module control register (C0CTRL) p. 806 Addition of Caution to 19.6 (11) CAN0 module interrupt status register (C0INTS) p. 811 Addition of Note to 19.6 (15) CAN0 module receive history list register (C0RGPT) p. 813 Addition of Note to 19.6 (17) CAN0 module transmit history list register (C0TGPT) p. 820 Addition of Caution to 19.6 (22) CAN0 message ID register m (C0MIDLm, C0MIDHm) pp. 822, 823 Addition of Caution to 19.6 (23) CAN0 message control register m (C0MCTRLm) p. 830 Addition of 19.9.2 Reading reception data p. 831 Addition of Caution to 19.9.3 Receive history list function p. 838 Addition of Remark to 19.10.1 Message transmission p. 839 Addition of Caution to 19.10.2 Transmit history list function p. 845 Addition of description to 19.11.1 (2) Status in CAN sleep mode p. 845 Addition of description to 19.11.1 (3) Releasing CAN sleep mode p. 846 Addition of Caution to 19.11.2 (1) Entering CAN stop mode p. 846 Addition of description to 19.11.2 (2) Status in CAN stop mode p. 847 Addition of description to 19.11.3 Example of using power saving modes p. 851 Addition of description to 19.13.3 Self-test mode p. 852 Addition of 19.13.4 Transmission/reception operation in each operation mode p. 855 Addition of description to 19.15.1 Bit rate setting conditions p. 866 Addition of Note to Figure 19-39 Message Buffer Redefinition p. 870 Addition of Remark to Figure 19-43 Transmission via Interrupt (Using C0LOPT register) p. 871 Addition of Remark to Figure 19-44 Transmission via Interrupt (Using C0TGPT Register) p. 872 Addition of Remark to Figure 19-45 Transmission via Software Polling p. 873 Addition of Note and Caution to Figure 19-46 Transmission Abort Processing (Other Than in Normal Operation Mode with ABT) p. 874 Addition of Note and Caution to Figure 19-47 Transmission Abort Processing Except for ABT Transmission (Normal Operation Mode with ABT) p. 877 Addition of Remark to Figure 19-49 Reception via Interrupt (Using C0LIPT Register) p. 878 Modification of Figure and addition of Remark to Figure 19-50 Reception via Interrupt (Using C0RGPT Register) p. 879 Modification of Figure and addition of Remark to Figure 19-51 Reception via Software Polling p. 880 Modification of Figure and deletion of Caution in Figure 19-52 Setting CAN Sleep Mode/Stop Mode p. 881 Modification of Figure 19-53 Clear CAN Sleep/Stop Mode p. 882 Addition of Figure and addition of Caution to Figure 19-54 Bus-off Recovery (Other Than in Normal Operation Mode with ABT) p. 883 Addition of Figure 19-55 Bus-off Recovery (Normal Operation Mode with ABT) p. 884 Deletion of a part of Figure 19-56 Normal Shutdown Process p. 887 Modification of Figure 19-59 Setting CPU Standby (from CAN Sleep Mode) User's Manual U16541EJ5V1UD 1143 APPENDIX E REVISION HISTORY (8/10) Page p. 888 pp. 896, 887 Description Modification of Figure 19-60 Setting CPU Standby (from CAN Stop Mode) Modification of Note and addition of Caution to 20.3 (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) p. 911 Modification of description in 20.13 (8) Bus arbitration for CPU p. 911 Modification of description in 20.13 (11) DMA start factor p. 917 Modification of description in CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION p. 917 Addition of description to 22.1 Features p. 918 Addition of Note to Table 22-1 Interrupt Source List p. 926 Modification of description in 22.3 Maskable Interrupts p. 933 Addition of Caution to 22.3.4 Interrupt control register (xxICn) p. 935 Addition of Note to Table 22-2 Interrupt Control Register (xxICn) p. 937 Addition of Note and deletion of description in 22.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) p. 944 Addition of Caution to 22.5.1 (2) Restore p. 951 Modification of description in 22.6.2 (4) Noise elimination control register (NFC) p. 952 Addition of description to 22.7 Interrupt Acknowledge Time of CPU p. 953 Modification of description in Figure 22-15 Pipeline Operation at Interrupt Request Signal Acknowledgment of V850ES/SG2 (Outline) p. 954 Addition of Figure 22-16 Pipeline Operation at Interrupt Request Signal Acknowledgment of V850ES/SG2-H (Outline) p. 955 Addition of 22.9 (2) Interrupt control register (xxICn) of V850ES/SG2-H p. 955 Addition of 22.9 (3) Interrupt control register (xxICn) of V850ES/SG2 and V850ES/SG2-H p. 955 Addition of 22.9 (4) In-service priority register (ISPR) p. 960 Addition of Caution to 24.2 (1) Power save control register (PSC) p. 963 Addition of Note to 24.3.2 Releasing HALT mode p. 966 Addition of Note to 24.4.2 Releasing IDLE1 mode p. 968 Addition of Note to 24.5.2 Releasing IDLE2 mode p. 969 Addition of description to Table 24-7 Operating Status in IDLE2 Mode p. 971 Addition of Note to 24.6.2 Releasing STOP mode p. 973 Addition of description to Table 24-9 Operating Status in STOP Mode p. 975 Modification of Caution to 24.7.1 Setting and operation status p. 975 Addition of Note to 24.7.2 Releasing subclock operation mode p. 976 Modification of description in Table 24-10 Operating Status in Subclock Operation Mode p. 978 Addition of Note to 24.8.2 Releasing sub-IDLE mode p. 979 Addition of description to Table 24-12 Operating Status in Sub-IDLE Mode p. 980 Addition of Note to 25.1 (1) Reset sources p. 981 Modification of description in 25.1 (2) Emergency operation mode p. 981 Addition of Figure 25-1 (b) V850ES/SG2-H p. 982 Addition of description to 25.2 Registers to Check Reset Source p. 982 Addition of Note to 25.2 (1) Reset source flag register (RESF) p. 983 Modification of description in Table 25-1 Hardware Status on RESET Pin Input p. 985 Modification of description in Table 25-2 Hardware Status During Watchdog Timer 2 Reset Operation p. 987 Modification of title of 25.3.3 Reset operation by low-voltage detector (LVIRES) (V850ES/SG2 only) 1144 User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY (9/10) Page p. 987 Description Modification of description in Table 25-3 Hardware Status During Reset Operation by Low-Voltage Detector p. 988 p. 991 Addition of 25.3.4 Reset operation by clock monitor (CLMRES) Addition of description to and addition of Caution to 25.3.5 (2) Firmware operation (flash memory version only) p. 999 Addition of description in CHAPTER 27 LOW-VOLTAGE DETECTOR p. 999 Deletion of description to 27.1 Functions p. 1000 Addition of Caution to 27.3 (1) Low voltage detection register (LVIM) p. 1001 Addition of Caution to 27.3 (2) Low voltage detection level selection register (LVIS) p. 1006 Deletion of description in Figure 28-1 Regulator p. 1015 Addition of description to 30.2 Memory Configuration p. 1017 Addition of Figure 30-1 (b) V850ES/SG2-H (640 KB) p. 1019 Modification of description in Table 30-3 Security Functions p. 1020 Addition of Table 30-4 Security Setting p. 1022 Addition of description to 30.4.2 Communication mode p. 1024 Addition of description to Table 30-5 Signal Connections of Dedicated Flash memory programmer (PG- pp. 1025, 1026 Modification of description in Table 30-6 Wiring of V850ES/SG2, V850ES/SG2-H Flash Writing Adapters FP4, PG-FP5) (FA-100GF-3BA-A, FA-100GC-8EU-A) pp. 1027, 1028 Modification of title of Figure 30-6 Wiring Example of V850ES/SG2 Flash Writing Adapter (FA-100GF3BA-A) (In CSIB0 + HS Mode) pp. 1029, 1030 Modification of title of Figure 30-7 Wiring Example of V850ES/SG2, V850ES/SG2-H Flash Writing Adapter (FA-100GC-8EU-A) (In CSIB0 + HS Mode) p. 1031 Modification of description in Figure 30-8 Procedure for Manipulating Flash Memory p. 1039 Modification of description in 30.5.2 (2) Interrupt support p. 1041 Addition of Caution to 30.5.5 (1) FLMD0 pin p. 1043 Addition of description to CHAPTER 31 ON-CHIP DEBUG FUNCTION p. 1044 Addition of description to 31.2 Connection Circuit Example p. 1044 Modification of description in 31.3 (2) DCK p. 1047 Addition of Note in 31.4 (1) On-chip debug mode register (OCDM) p. 1052 Modification of description in 31.7 (4), (6), (7) p. 1055 Modification of description in 32.2 Capacitance p. 1055 Addition of 32.3 (2) V850ES/SG2-H p. 1057 Addition of description to 32.4.1 Main clock oscillator characteristics p. 1057 Modification of description in 32.4.1 (i) KYOCERA KINSEKI CORPORATION: Crystal resonator p. 1058 Addition of 32.4.1 (ii) Murata Mfg. Co. Ltd.: Ceramic resonator p. 1059 Addition of Note to 32.4.2 Subclock oscillator characteristics p. 1060 Addition of 32.4.3 (2) V850ES/SG2-H p. 1061 Addition of 32.5 (2) V850ES/SG2-H p. 1063 Modification of description in 32.6.1 I/O level p. 1065 Addition of 32.6.2 (2) V850ES/SG2-H p. 1066 Deletion of description and addition of Note in 32.7 (1) In STOP mode p. 1068 Addition of description to 32.8.1 CLKOUT output timing User's Manual U16541EJ5V1UD 1145 APPENDIX E REVISION HISTORY (10/10) Page Description p. 1068 Addition of Caution to 32.8.2 (1) In multiplexed bus mode p. 1069 Modification and addition of description in 32.8.2 (1) (a) Read/write cycle (CLKOUT asynchronous) p. 1074 Addition of Caution to 32.8.2 (2) In separate bus mode p. 1074 Addition and modification of description in 32.8.2 (2) (a) Read cycle (CLKOUT asynchronous): In separate bus mode p. 1076 Addition of description to 32.8.2 (2) (b) Write cycle (CLKOUT asynchronous): In separate bus mode p. 1078 Addition of description to 32.8.2 (2) (c) Read cycle (CLKOUT synchronous): In separate bus mode p. 1079 Addition of description to 32.8.2 (2) (d) Write cycle (CLKOUT synchronous): In separate bus mode p. 1080 Addition of description to 32.8.2 (3) (a) CLKOUT asynchronous p. 1083 Addition of Note to 32.9 (2) Interrupt, FLMD0 pin timing p. 1084 Addition of description to 32.9 (6) (b) Slave mode p. 1089 Modification of title of 32.9 (12) LVI circuit specification (V850ES/SG2 only) p. 1090 Addition of description to 32.9 (13) RAM retention detection p. 1091 Addition of description to 32.10 (1) Basic characteristics p. 1091 Addition of description to 32.10 (2) Serial write operation characteristics p. 1093 Addition of 32.10 (3) (b) V850ES/SG2-H p. 1096 Modification of description in CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS p. 1101 Addition of Figure A-1 (3) When using on-chip debug emulator IE-V850E1-CD-NW p. 1102 Addition of Figure A-1 (4) When using MINICUBE QB-V850MINI p. 1103 Modification of description in A.2 Language Processing Software p. 1106 Modification of description in Figure A-3 System Configuration (QB-V850ESSX2 Used) p. 1108 Modification of Note in A.4.2 When using IECUBE QB-V850ESSX2 p. 1109 Addition of A.4.3 When using on-chip debug emulator IE-V850E1-CD-NW p. 1110 Addition of A.4.4 When using MINICUBE QB-V850MINI p. 1111 Modification of description in A.5 Debugging Tools (Software) p. 1112 Modification of description in A.7 Flash Memory Writing Tools p. 1113 Addition of APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/SG2 AND V850ES/SG2-H pp. 1130, 1131, Addition of Note to D.2 Instruction Set (in Alphabetical Order) 1133, 1135, 1136 1146 User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY E.2 Revision History of Previous Editions A history of the revisions up to this edition is shown below. "Applied to:" indicates the chapters to which the revision was applied. (1/11) Edition 2nd Description Applied to: Addition of Note 2 in 1.5 Pin Configuration (Top View) CHAPTER 1 INTRODUCTION Modification of 2.1 (1) Port pins CHAPTER 2 PIN FUNCTIONS Modification of 2.1 (2) Non-port pins Modification of Table 2-2 Pin Operation States in Various Modes Modification of Figure 2-1 Pin I/O Circuits Addition of 3.3.1 Specifying operation mode CHAPTER 3 CPU FUNCTION Addition of Caution in 3.4.5 Recommended use of address space Addition of Notes in 3.4.6 Peripheral I/O registers Addition of 3.4.9 (2) Accessing specific on-chip peripheral I/O registers Addition of 3.4.9 (3) Cautions on using flash memory version Modification of 4.3 Port Configuration CHAPTER 4 PORT FUNCTIONS Addition of 4.4 Block Diagrams Addition of 4.6 Cautions Modification of 5.2.1 Pin status when internal ROM, internal RAM, or on-chip CHAPTER 5 BUS CONTROL peripheral I/O is accessed FUNCTION Addition of Cautions in 5.6.4 Programmable address wait function Modification of 5.10 Bus Timing Modification of 6.3 (1) (a) Example of setting main clock operation subclock CHAPTER 6 CLOCK operation GENERATION FUNCTION Modification of 6.3 (1) (b) Example of setting subclock operation main clock operation Modification of 6.5.3 (1) To use PLL Modification of CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Modification of CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Modification of 9.4.1 Interval timer mode CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Addition of 9.4.2 Cautions CHAPTER 10 WATCH TIMER Modification of 10.2 Configuration Modification of 10.4.1 Operation as watch timer Addition of Caution in 11.3 (1) Watchdog timer mode register 2 (WDTM2) FUNCTIONS CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 User's Manual U16541EJ5V1UD 1147 APPENDIX E REVISION HISTORY (2/11) Edition 2nd Description Applied to: Addition of Caution 2 in 12.2 (1) Real-time output buffer registers 0L, 0H CHAPTER 12 REAL-TIME (RTBL0, RTBH0) OUTPUT FUNCTION (RTO) Addition of Caution 3 in 12.3 (1) Real-time output port mode register 0 (RTPM0) Addition of 13.2 Functions CHAPTER 13 A/D CONVERTER Modification of 13.3 Configuration Addition of Caution 4 in 13.4 (1) A/D converter mode register 0 (ADA0M0) Addition of Caution 2 in 13.4 (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) Addition of 13.5.1 <9> Addition of 13.6 (8) Standby mode Modification of Figure 14-1 Block Diagram of D/A Converter Modification of 14.4.2 Operation in real-time output mode CHAPTER 14 D/A CONVERTER Addition of 14.4.3 (7) Modification of 15.4 (1) UARTAn control register 0 (UAnCTL0) CHAPTER 15 Addition of Remark in 15.6.2 SBF transmission/reception format ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Addition of Figure 15-15 Timing of RXDAn Signal Judged as Noise Addition of Caution in 15.7 (2) UARTAn control register 1 (UAnCTL1) Addition of Caution in 15.7 (3) UARTAn control register 2 (UAnCTL2) Addition of 15.8 Cautions Addition of Remark in 16.3 Configuration CHAPTER 16 3-WIRE Modification of 16.4 (1) CSIBn control register 0 (CBnCTL0) VARIABLE-LENGTH SERIAL I/O (CSIB) Addition of Note 1 in 16.4 (2) CSIBn control register 1 (CBnCTL1) Addition of Note in 16.4 (3) CSIBn control register 2 (CBnCTL2) Modification of 16.5 Operation Modification of 16.6 (1) SCKBn pin Modification of 16.7 Operation Flow Addition of Note in 17.4 (1) IIC control registers 0 to 2 (IICC0 to IICC2) 2 CHAPTER 17 I C BUS Addition of Caution in 17.4 (2) IIC status registers 0 to 2 (IICS0 to IICS2) Addition of 17.16.3 Slave operation Modification of 18.3 (17) IEBus clock select register (OCKS2) CHAPTER 18 IEBus CONTROLLER Modification of 20.3 Control Registers CHAPTER 20 DMA Modification of 20.4 Transfer Targets FUNCTION (DMA CONTROLLER) Modification of 20.5 Transfer Modes Modification of 20.6 Transfer Types Modification of 20.7 DMA Channel Priorities Addition of 20.8 Time Related to DMA Transfer Modification of 20.9 DMA Transfer Start Factors Modification of 20.10 DMA Abort Factors 1148 User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY (3/11) Edition 2nd Description Applied to: Modification of 20.11 End of DMA Transfer CHAPTER 20 DMA Addition of 20.12 Operation Timing FUNCTION (DMA CONTROLLER) Modification of 20.13 Cautions Modification of Caution in 21.3 (2) CRC data register (CRCD) CHAPTER 21 CRC FUNCTION Addition of Note 1 in Table 22-1 Interrupt Source List CHAPTER 22 Addition of Note and Caution in 22.3.5 Interrupt mask registers 0 to 3 (IMR0 to INTERRUPT/EXCEPTION PROCESSING FUNCTION IMR3) Modification of Figure 22-14 Pipeline Operation at Interrupt Request Signal Acknowledgment (Outline) Addition of 22.9 Cautions Addition of Caution in 23.1 Function CHAPTER 23 KEY INTERRUPT FUNCTION Addition of Note in Table 24-5 Operating Status in IDLE1 Mode Addition of Note in Table 24-7 Operating Status in IDLE2 Mode CHAPTER 24 STANDBY FUNCTION Addition of Caution 2 in 24.7.1 Setting and operation status Addition of Caution in Table 24-10 Operating Status in Subclock Operation Mode Modification of 25.2 (1) Reset source flag register (RESF) CHAPTER 25 RESET FUNCTIONS Addition of Caution in Figure 26-1 Regulator CHAPTER 26 REGULATOR Addition of Note in 27.2 (1) Correction address registers 0 to 3 (CORAD0 to CHAPTER 27 ROM CORAD3) CORRECTION FUNCTION Modification of CHAPTER 28 FLASH MEMORY CHAPTER 28 FLASH MEMORY Addition of CHAPTER 29 ON-CHIP DEBUG FUNCTION CHAPTER 29 ON-CHIP DEBUG FUNCTION Addition of CHAPTER 30 ELECTRICAL SPECIFICATIONS (TARGET VALUES) CHAPTER 30 ELECTRICAL SPECIFICATIONS (TARGET VALUES) Addition of CHAPTER 31 PACKAGE DRAWING CHAPTER 31 PACKAGE DRAWING Addition of APPENDIX A REGISTER INDEX APPENDIX A REGISTER INDEX Addition of APPENDIX B INSTRUCTION SET LIST APPENDIX B INSTRUCTION SET LIST Addition of APPENDIX C REVISION HISTORY APPENDIX C REVISION HISTORY User's Manual U16541EJ5V1UD 1149 APPENDIX E REVISION HISTORY (4/11) Edition 3rd Description Deletion of indication of the preliminary version, addition of Note to the products Applied to: Throughout under development Modification of 1.4 Ordering Information CHAPTER 1 INTRODUCTION Addition of Note 1 in 2.1 (1) Port pins CHAPTER 2 PIN FUNCTIONS Modification of 2.1 (2) Non-port pins Modification of Table 2-2 Pin Operation States in Various Modes Modification of Table 3-2 System Register Numbers CHAPTER 3 CPU FUNCTION Modification of 3.2.2 (4) Program status word (PSW) Addition of description in 3.2.2 (6) Exception/debug trap status saving registers (DBPC and DBPSW) Addition of Caution in Figure 3-1 Image on Address Space Addition of Note 2 in Figure 3-2 Data Memory Map (Physical Addresses) Addition of 3.4.4 (4) Programmable peripheral I/O area Modification of Figure 3-14 Recommended Memory Map Modification of 3.4.6 Peripheral I/O registers Modification of 3.4.9 (1) Registers to be set first Modification of 3.4.9 (2) Accessing specific on-chip peripheral I/O registers Modification of 3.4.9 (3) Cautions on using flash memory version Addition of 3.4.9 (4) Restriction on conflict between sld instruction and interrupt request Modification of Table 4-4 Port 0 Alternate-Function Pins CHAPTER 4 PORT Modification of Table 4-8 Port 5 Alternate-Function Pins FUNCTIONS Addition of Remark in 4.3.6 (1) (a), (b) Modification of Figure 4-8 Block Diagram of Type E-3 Modification of Figure 4-18 Block Diagram of Type N-3 Addition of Note 3 in Table 4-15 Using Port Pin as Alternate-Function Pin Modification of 4.6.1 (1) Modification of 4.6.4 Cautions on P05/INTP2/DRST pin Modification of 5.1 Features Addition of Note 2 in Figure 5-1 Data Memory Map: Physical Address CHAPTER 5 BUS CONTROL FUNCTION Addition of description in 5.6.2 External wait function Modification of Figure 6-1 Clock Generator Addition of Cautions in 6.3 (2) Internal oscillation mode register (RCM) Addition of Note in 6.3 (3) CPU operation clock status register (CCLS) Addition to Table 6-1 Operation Status of Each Clock Addition of Caution 3 in 6.5.2 (2) Clock control register (CKC) Addition of description in 6.5.2 (3) Lock register (LOCKR) Modification of 6.5.3 (1) When PLL is used 1150 User's Manual U16541EJ5V1UD CHAPTER 6 CLOCK GENERATION FUNCTION APPENDIX E REVISION HISTORY (5/11) Edition 3rd Description Applied to: Addition of Caution 3 in 7.4 (5) TMPn I/O control register 2 (TPnIOC2) CHAPTER 7 16-BIT Modification of 7.5.1 (2) (a) Operation if TPnCCR0 register is set to 0000H TIMER/EVENT COUNTER P (TMP) Modification of Figure 7-10 Basic Timing in External Event Count Mode Modification of 7.5.2 (2) Operation timing in external event count mode Modification of 7.5.3 (2) (b) 0%/100% output of PWM waveform Modification of 7.5.5 (2) (b) 0%/100% output of PWM waveform Modification of 7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) Addition of 7.6 Selector Function Addition of 7.7 Cautions Addition of Caution 3 in 8.4 (5) TMQ0 I/O control register 2 (TQ0IOC2) CHAPTER 8 16-BIT Modification of 8.5.1 (2) (a) Operation if TQ0CCR0 register is set to 0000H TIMER/EVENT COUNTER Q (TMQ) Modification of Figure 8-10 Basic Timing in External Event Count Mode Modification of 8.5.2 (2) Operation timing in external event count mode Addition of Remark 2 in Figure 8-18 Setting of Registers in External Trigger Pulse Output Mode Modification of 8.5.3 (2) (b) 0%/100% output of PWM waveform Addition of Remark 2 in Figure 8-26 Register Setting in PWM Output Mode Modification of 8.5.5 (2) (b) 0%/100% output of PWM waveform Modification of Figure 8-31 Register Setting in Free-Running Timer Mode Modification of 8.5.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) Addition of 8.6 Selector Function Addition of 8.7 Cautions Modification of 9.3 (1) TMM0 control register (TM0CTL0) CHAPTER 9 16-BIT Addition of Caution in 9.4 Operation INTERVAL TIMER M (TMM) Modification of 9.4.1 Interval timer mode Modification of 10.3 (1) Prescaler mode register 0 (PRSM0) CHAPTER 10 WATCH TIMER Addition of description in 10.3 (2) Prescaler compare register 0 (PRSCM0) FUNCTIONS Addition of description in 10.3 (3) Watch timer operation mode register (WTM) Addition of description in 11.3 (1) Watchdog timer mode register 2 (WDTM2) CHAPTER 11 FUNCTIONS Addition of description in 11.4 Operation OF WATCHDOG TIMER 2 Modification of Table 13-2 and Table 13-3 CHAPTER 13 A/D Modification of 13.5.1 Basic operation CONVERTER Addition of 13.5.2 Conversion operation timing Addition of description in 13.6 (4) Alternate I/O Addition of 13.6 (6) Internal equivalent circuit Addition of description in 13.6 (9) Standby mode User's Manual U16541EJ5V1UD 1151 APPENDIX E REVISION HISTORY (6/11) Edition 3rd Description Applied to: Modification of 15.4 (1) UARTAn control register 0 (UAnCTL0) CHAPTER 15 Modification of 15.4 (4) UARTAn option control register 0 (UAnOPT0) ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Addition of description in 15.6.8 Reception errors Modification of 15.7 (1) (a) Base clock Modification of Table 15-3 Baud Rate Generator Setting Data Addition of description in 15.8 Cautions Modification of 16.2 Features CHAPTER 16 3-WIRE Modification of 16.4 (1) CSIBn control register 0 (CBnCTL0) VARIABLE-LENGTH SERIAL I/O (CSIB) Modification of 16.4 (2) CSIBn control register 1 (CBnCTL1) Addition of description in 16.4 (4) CSIBn status register (CBnSTR) Modification of 16.5.7 Continuous mode (slave mode, reception mode) Modification of 16.5.8 Clock timing Modification of 16.6 (1) SCKBn pin Addition of 16.9 Cautions 2 Modification of Figure 17-4 Block Diagram of I C0n 2 CHAPTER 17 I C BUS Addition of description in 7.4 (1) IIC control registers 0 to 2 (IICC0 to IICC2) Addition of Remark in 17.4 (4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2) Modification of Table 17-2 Clock Settings Addition of Caution in 17.6.1 Start condition Addition of description in 17.15 Cautions Revision of CHAPTER 19 CAN CONTROLLER CHAPTER 19 CAN CONTROLLER Modification of Figure 20-2 Priority of DMA (2) CHAPTER 20 DMA FUNCTION (DMA CONTROLLER) Modification of 22.3.4 Interrupt control register (xxICn) CHAPTER 22 Modification of 22.3.8 Watchdog timer mode register 2 (WDTM2) INTERRUPT/EXCEPTION PROCESSING FUNCTION Modification of 22.8 Periods in Which Interrupts Are Not Acknowledged by CPU Addition of description in 22.9 Cautions Modification of 23.2 (1) Key return mode register (KRM) CHAPTER 23 KEY Addition of 23.3 Cautions INTERRUPT FUNCTION Modification of Table 24-1 Standby Modes CHAPTER 24 STANDBY Modification of Figure 24-1 Status Transition FUNCTION Modification of 24.2 (2) Power save mode register (PSMR) Modification of 24.6.1 Setting and operation status Modification of 24.8.1 Setting and operation status 1152 Revision of CHAPTER 25 RESET FUNCTIONS CHAPTER 25 RESET FUNCTIONS Addition of CHAPTER 26 CLOCK MONITOR CHAPTER 26 CLOCK MONITOR Addition of CHAPTER 27 LOW-VOLTAGE DETECTOR (LVI) CHAPTER 27 LOWVOLTAGE DETECTOR (LVI) User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY (7/11) Edition 3rd Description Applied to: Modification of 29.2 (1) Correction address registers 0 to 3 (CORAD0 to CHAPTER 29 ROM CORAD3) CORRECTION FUNCTION Addition of 29.4 Cautions Modification of CHAPTER 30 FLASH MEMORY CHAPTER 30 FLASH Modification of Figure 30-1 Flash Memory Mapping MEMORY Modification of Table 30-4 Signal Connections of Dedicated Flash Programmer (PG-FP4) Modification of Table 30-5 Wiring of V850ES/SG2 Flash Writing Adapters (FA100GF-JBT and FA-100GC-8EA) Modification of Figures 30-6 and 30-7 Modification of Table 30-10 Internal Resources Used Addition of Caution in CHAPTER 31 ON-CHIP DEBUG FUNCTION CHAPTER 31 ON-CHIP Addition of Note in 31.6.1 Security ID DEBUG FUNCTION Addition of description in 31.7 Cautions Revision of CHAPTER 32 ELECTRICAL SPECIFICATIONS CHAPTER 32 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS Addition of D.2 Revision History of Previous Editions APPENDIX D REVISION HISTORY 4th Deletion of indication "under development" for the following products (developed) Throughout * GF package PD703260, 703260Y, 703261, 703261Y, 703270, 703270Y, 703271, 703271Y * GC package PD703260, 703260Y, 703262, 703262Y, 703263, 703263Y, 703270, 703270Y, 703272, 703272Y, 703273, 703273Y, 703280, 703280Y, 703281, 703281Y, 703282, 703282Y, 703283, 703283Y Modification of Table 1-2 V850ES/SJ2 Product List CHAPTER 1 INTRODUCTION CHAPTER 2 PIN Modification of 2.2 Pin States FUNCTIONS Addition of 2.4 Cautions Modification of 3.4.9 (2) Accessing specific on-chip peripheral I/O registers and CHAPTER 3 CPU FUNCTION (3) System reserved area Addition of Caution to Table 4-5 Port 1 Alternate-Function Pins Modification of Caution 1 and addition of Caution 2 in 4.3.2 (2) Port 1 mode CHAPTER 4 PORT FUNCTIONS register (PM1) Modification of Table 4-6 Port 3 Alternate-Function Pins Modification of Table 4-7 Port 4 Alternate-Function Pins Addition of Caution 1 to Table 4-8 Port 5 Alternate-Function Pins Modification of Figure 4-7 Block Diagram of Type D-3 Modification of Figure 4-8 Block Diagram of Type E-3 User's Manual U16541EJ5V1UD 1153 APPENDIX E REVISION HISTORY (8/11) Edition 4th Description Modification of Figure 4-13 Block Diagram of Type G-5 Modification of Figure 4-14 Block Diagram of Type G-6 Applied to: CHAPTER 4 PORT FUNCTIONS Addition of Figure 4-15 Block Diagram of Type G-12 Modification of Figure 4-18 Block Diagram of Type N-2 Modification of Figure 4-19 Block Diagram of Type N-3 Modification of Figure 4-26 Block Diagram of Type U-10 Modification of Figure 4-27 Block Diagram of Type U-11 Modification of Caution in Table 4-15 Using Port Pin as Alternate-Function Pin Addition of 4.6.5 Cautions on P10, P11, and P53 pins when power is turned on Modification of 5.1 Features CHAPTER 5 BUS CONTROL FUNCTION Addition and modification of description in 6.3 (1) Processor clock control register (PCC) CHAPTER 6 CLOCK GENERATION FUNCTION Addition of description in 6.3 (1) (a) Example of setting main clock operation subclock operation Addition of Caution in 6.3 (1) (b) Example of setting subclock operation main clock operation Addition of Caution 2 to 6.5.2 (4) PLL lockup time specification register (PLLS) Modification of 7.4 (7) TMPn capture/compare register 0 (TPnCCR0) CHAPTER 7 16-BIT Modification of 7.4 (8) TMPn capture/compare register 1 (TPnCCR1) TIMER/EVENT COUNTER P (TMP) Modification of 7.4 (9) TMPn counter read buffer register (TPnCNT) Modification of Figure 7-4 Register Setting for Interval Timer Mode Operation Modification of Figure 7-10 Basic Timing in External Event Count Mode Modification of Figure 7-11 Register Setting for Operation in External Event Count Mode Addition of Caution 2 to 7.5.2 (2) Operation timing in external event count mode Modification of 7.5.2 (2) (c) Operation of TPnCCR1 register Modification of Figure 7-17 Basic Timing in External Trigger Pulse Output Mode Addition of description to 7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) Addition of Note 2 to Figure 7-18 Setting of Registers in External Trigger Pulse Output Mode Addition of Note 2 to Figure 7-22 Setting of Registers in One-Shot Pulse Output Mode Modification of Figure 7-23 Software Processing Flow in One-Shot Pulse Output Mode Addition of Note 2 and modification of Figure 7-26 Setting of Registers in PWM Output Mode Modification of 7.7 (1) Capture operation 1154 Modification of 8.4 (7) TMQ0 capture/compare register 0 (TQ0CCR0) CHAPTER 8 16-BIT Modification of 8.4 (8) TMQ0 capture/compare register 1 (TQ0CCR1) TIMER/EVENT COUNTER Q (TMQ) User's Manual U16541EJ5V1UD APPENDIX E REVISION HISTORY (9/11) Edition 4th Description Applied to: Modification of 8.4 (9) TMQ0 capture/compare register 2 (TQ0CCR2) CHAPTER 8 16-BIT Modification of 8.4 (10) TMQ0 capture/compare register 3 (TQ0CCR3) TIMER/EVENT COUNTER Q (TMQ) Modification of 8.4 (11) TMQ0 counter read buffer register (TQ0CNT) Modification of Figure 8-4 Register Setting for Interval Timer Mode Operation Modification of Figure 8-10 Basic Timing in External Event Count Mode Modification of Figure 8-11 Register Setting for Operation in External Event Count Mode Addition of Caution 2 to 8.5.2 (2) Operation timing in external event count mode Modification of 8.5.2 (2) (c) Operation of TQ0CCR1 to TQ0CCR3 registers Modification of Figure 8-17 Basic Timing in External Trigger Pulse Output Mode Addition of description to 8.5.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) Addition of Note to Figure 8-18 Setting of Registers in External Trigger Pulse Output Mode Addition of Note to Figure 8-22 Setting of Registers in One-Shot Pulse Output Mode Modification of Figure 8-23 Software Processing Flow in One-Shot Pulse Output Mode Addition of Note and modification of Figure 8-26 Setting of Registers in PWM Output Mode Modification of 8.7 (1) Capture operation Modification of Figure 10-1 Block Diagram of Watch Timer CHAPTER 10 WATCH TIMER FUNCTIONS Modification of Figure 11-1 Block Diagram of Watchdog Timer 2 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 Modification of 11.3 (1) Watchdog timer mode register 2 (WDTM2) Modification of 12.2 (1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0) CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) Modification of description and addition of Caution 3 in 13.4 (1) A/D converter mode register 0 (ADA0M0) CHAPTER 13 A/D CONVERTER Addition of Caution 1 in 13.4 (2) A/D converter mode register 1 (ADA0M1) Modification of Table 13-2 Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) and Table 13-3 Conversion Time Selection in HighSpeed Conversion Mode (ADA0HS1 Bit = 1) Modification of 13.4 (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) Modification of Figure 13-3 Conversion Operation Timing (Continuous Conversion) Modification of (9) and addition of (10) to (13) in 13.6 Cautions Addition of description to 13.7 (6) Differential linearity error CHAPTER 14 D/A CONVERTER Modification of 14.1 Functions Modification of 14.4.3 Cautions User's Manual U16541EJ5V1UD 1155 APPENDIX E REVISION HISTORY (10/11) Edition 4th Description Applied to: Addition of Caution to 15.4 (4) UARTAn option control register 0 (UAnOPT0) CHAPTER 15 Modification of 15.7 (4) Baud rate ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Addition of description and modification of 16.4 (1) CSIBn control register 0 (CBnCTL0) Modification of 16.5.1 Single transfer mode (master mode, transmission/reception mode) CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) Modification of 16.5.2 Single transfer mode (master mode, reception mode) Modification of 16.5.3 Continuous mode (master mode, transmission/reception mode) Modification of 16.5.4 Continuous mode (master mode, reception mode) Modification of 16.5.5 Continuous reception mode (error) Modification of 16.5.6 Continuous mode (slave mode, transmission/reception mode) Modification of 16.5.7 Continuous mode (slave mode, reception mode) Addition of Caution to 16.5.8 Clock timing Modification of 16.6 (1) SCKBn pin Addition of 16.9 Cautions (3) 2 Modification of Figure 17-4 Block Diagram of I C0n Addition of 17.3 Configuration (13) Addition and modification of description in 17.4 (1) IIC control registers 0 to 2 (IICC0 to IICC2) Addition and modification of description in 17.4 (2) IIC status registers 0 to 2 (IICS0 to IICS2) Addition of description to 17.4 (3) IIC flag registers 0 to 2 (IICF0 to IICF2) Addition of description to 17.4 (4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2) Addition of description to 17.4 (5) IIC function expansion registers 0 to 2 (IICX0 to IICX2) Addition of description to 17.4 (8) IIC shift registers 0 to 2 (IIC0 to IIC2) Addition of description to 17.4 (9) Slave address registers 0 to 2 (SVA0 to SVA2) Addition of 17.6.7 Wait state cancellation method Modification of 17.7.1 (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) Modification of 17.7.1 (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) Addition of <1> to 17.7.6 (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition Addition of <1> to 17.7.6 (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition Addition of <1> to 17.7.6 (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition Modification of Figure 17-21 Slave Operation Flowchart (1) 1156 User's Manual U16541EJ5V1UD 2 CHAPTER 17 I C BUS APPENDIX E REVISION HISTORY (11/11) Edition 4th Description Applied to: Modification of Figure 18-32 Slave Transmission (Interval of Interrupt Request CHAPTER 18 IEBus Signal Occurrence) and Figure 18-33 Slave Reception (Interval of Interrupt Request Signal Occurrence) CONTROLLER Addition of Caution to 19.6 Registers CHAPTER 19 CAN CONTROLLER Addition of Caution 4 to 20.3 (1) DMA source address registers 0 to 3 (DSA0 to DSA3) CHAPTER 20 DMA Addition of Caution 4 to 20.3 (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) FUNCTION (DMA CONTROLLER) Addition of Caution 2 to 20.3 (3) DMA byte count registers 0 to 3 (DBC0 to DBC3) Modification of 21.3 (2) CRC data register (CRCD) CHAPTER 21 CRC FUNCTION Addition of Note in Figure 22-4 Software Reset Processing CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION Modification of 23.3 Cautions CHAPTER 23 KEY INTERRUPT FUNCTION Modification of Figure 24-1 Status Transition CHAPTER 24 STANDBY FUNCTION Addition of Caution 2 to 24.4.1 Setting and operation status Addition of Caution 2 to 24.5.1 Setting and operation status Addition of Caution 2 to 24.6.1 Setting and operation status Modification of Table 24-9 Operating Status in STOP Mode Modification of 24.6.3 Securing oscillation stabilization time when releasing STOP mode Addition of Caution 2 to 24.8.1 Setting and operation status Addition of Note 2 to Table 25-1 Hardware Status on RESET Pin Input Modification of 25.3.5 Reset function operation flow Modification of 27.3 (1) Low voltage detection register (LVIM) Addition of Note to 27.3 (3) Internal RAM data status register (RAMS) CHAPTER 25 RESET FUNCTIONS CHAPTER 27 LOWVOLTAGE DETECTOR CHAPTER 31 ON-CHIP DEBUG FUNCTION Modification of 31.6.1 Security ID Modification of 31.6.2 Setting Modification of CHAPTER 32 ELECTRICAL SPECIFICATIONS CHAPTER 32 ELECTRICAL SPECIFICATIONS Modification of CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS Modification of A.4.2 When using IECUBE QB-V850ESSX2 Modification of A.7 Flash Memory Writing Tools User's Manual U16541EJ5V1UD APPENDIX A DEVELOPMENT TOOLS 1157 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] 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