General Description
The MAX9205/MAX9207 serializers transform 10-bit-
wide parallel LVCMOS/LVTTL data into a serial high-
speed bus low-voltage differential signaling (LVDS)
data stream. The serializers typically pair with deserial-
izers like the MAX9206/MAX9208, which receive the
serial output and transform it back to 10-bit-wide paral-
lel data.
The MAX9205/MAX9207 transmit serial data at speeds
up to 400Mbps and 660Mbps, respectively, over PCB
traces or twisted-pair cables. Since the clock is recov-
ered from the serial data stream, clock-to-data and
data-to-data skew that would be present with a parallel
bus are eliminated.
The serializers require no external components and few
control signals. The input data strobe edge is selected
by TCLK_R/F. PWRDN is used to save power when the
devices are not in use. Upon power-up, a synchroniza-
tion mode is activated, which is controlled by two SYNC
inputs, SYNC1 and SYNC2.
The MAX9205 can lock to a 16MHz to 40MHz system
clock, while the MAX9207 can lock to a 40MHz to
66MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock, or when the device is in power-
down mode.
Both the devices operate from a single +3.3V supply,
are specified for operation from -40°C to +85°C, and
are available in 28-pin SSOP packages.
Applications
Features
oStandalone Serializer (vs. SERDES) Ideal for
Unidirectional Links
oFraming Bits for Deserializer Resync Allow Hot
Insertion Without System Interruption
oLVDS Serial Output Rated for Point-to-Point and
Bus Applications
oWide Reference Clock Input Range
16MHz to 40MHz (MAX9205)
40MHz to 66MHz (MAX9207)
oLow 140ps (pk-pk) Deterministic Jitter (MAX9207)
oLow 34mA Supply Current (MAX9205)
o10-Bit Parallel LVCMOS/LVTTL Interface
oUp to 660Mbps Payload Data Rate (MAX9207)
oProgrammable Active Edge on Input Latch
oPin-Compatible Upgrades to DS92LV1021 and
DS92LV1023
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
________________________________________________________________
Maxim Integrated Products
1
PCB OR
TWISTED PAIR
TCLK
PLL PLL
EN EN
PWRDN
INPUT LATCH
PARALLEL-TO-SERIAL
OUTPUT LATCH
SERIAL-TO-PARALLEL
TIMING AND
CONTROL
TIMING AND
CONTROL
CLOCK
RECOVERY
RCLK
LOCK
SYNC 1
SYNC 2
OUT+
OUT-
IN+
IN-
100Ω100Ω
TCLK_R/F
RCLK_R/F
REFCLK
OUT_
IN_
10 10
BUS
LVDS
MAX9205
MAX9207
MAX9206
MAX9208
Ordering Information
19-2029; Rev 1; 11/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP
RANGE
PIN-
PACKAGE
REF CLOCK
RANGE
(MHz)
MAX9205EAI+ -40°C to +85°C 28 SSOP 16 to 40
M AX 9205E AI/V + -40°C to +85°C 28 SSOP 16 to 40
MAX9207EAI+ -40°C to +85°C 28 SSOP 40 to 66
Pin Configuration and Functional Diagram appear at end of
data sheet.
Typical Application Circuit
Cellular Phone Base
Stations
Add Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VAVCC = VDVCC = +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VAVCC =
VDVCC = +3.3V and TA= +25°C, unless otherwise noted.) (Notes 1, 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, DVCC to GND..........................……………-0.3V to +4.0V
IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK,
PWRDN to GND......................................-0.3V to (VCC + 0.3V)
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Output Short-Circuit Duration.....................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, SYNC1, SYNC2, TCLK, TCLK_R/F, PWRDN)
High-Level Input Voltage VIH 2.0 VCC V
Low-Level Input Voltage VIL GND 0.8 V
Input Current IIN VIN_ = 0V or V_VCC -20 +20 µA
BUS LVDS OUTPUTS (OUT+, OUT-)
RL = 27Ω200 286 400 mV
Differential Output Voltage VOD Figure 1 RL = 50Ω250 460 600 mV
Change in VOD Between
Complementary Output States ΔVOD Figure 1 1 35 mV
Output Offset Voltage VOS Figure 1 0.9 1.15 1.3 V
Change in VOS Between
Complementary Output States ΔVOS Figure 1 3 35 mV
Output Short-Circuit Current IOS VOUT+ or VOUT- = 0V,
IN0 to IN9 = PWRDN = EN = high -13 -15 mA
Output High-Impedance Current IOZ VPWRDN or VEN = 0.8V,
VOUT+ or VOUT- = 0V or V_VCC -10 +10 µA
Power-Off Output Current IOX V_VCC = 0V, VOUT+ or VOUT- = 0V or 3.6V -10 +10 µA
POWER SUPPLY
16MHz 23 35
MAX9205 40MHz 34 45
40MHz 32 50
Supply Current ICC
RL = 27_ or 50_
worst-case pattern
(Figures 2, 4) MAX9207 66MHz 45 60
mA
Power-Down Supply Current ICCX PWRDN = low 8 mA
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VAVCC = VDVCC = +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VAVCC =
VDVCC = +3.3V and TA= +25°C, unless otherwise noted.) (Notes 2, 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS
MAX9205 16 40 MHz
TCLK Center Frequency fTCCF MAX9207 40 66 MHz
TCLK Frequency Variation TCFV -200 200 ppm
MAX9205 25 62.5
TCLK Period tTCP MAX9207 15.15 25
ns
TCLK Duty Cycle TCDC 40 60 %
TCLK Input Transition Time tCLKT Figure 3 3 6 ns
TCLK Input Jitter tJIT 150 ps
(RMS)
SWITCHING CHARACTERISTICS
RL = 27150 300 400
Low-to-High Transition Time tLHT Figure 4 RL = 50150 350 500 ps
RL = 27150 300 400
High-to-Low Transition Time tHLT Figure 4 RL = 50150 350 500 ps
IN_ Setup to TCLK tS Figure 5 1 ns
IN_ Hold from TCLK tH Figure 5 3 ns
OUTPUT High State to High-
Impedance Delay tHZ Figures 6, 7 4.5 10 ns
OUTPUT Low State to High-
Impedance Delay tLZ Figures 6, 7 4.5 10 ns
OUTPUT High Impedance to
High-State Delay tZH Figures 6, 7 4.5 10 ns
OUTPUT High Impedance to
Low-State Delay tZL Figures 6, 7 4.5 10 ns
SYNC Pulse Width tSPW 6 x tTCP ns
PLL Lock Time tPL Figure 7 2048 x
tTCP
2049 x
tTCP ns
Bus LVDS Bit Width tBIT t
TCP/12 ns
Serializer Delay tSD Figure 8 tTCP / 6 (tTCP/6)
+ 5 ns
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VAVCC = VDVCC = +3.3V, RL= 27Ω, CL = 10pF, TA = +25°C, unless otherwise noted.)
10
30
20
40
50
3.0 3.3 3.6
WORST-CASE PATTERN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9205 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TCLK = 40MHz
MAX9205
10
30
20
40
50
3.0 3.3 3.6
WORST-CASE PATTERN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9205 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TCLK = 40MHz
MAX9205
AC ELECTRICAL CHARACTERISTICS (continued)
(VAVCC = VDVCC = +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VAVCC =
VDVCC = +3.3V and TA= +25°C, unless otherwise noted.) (Notes 2, 4)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VOD, ΔVOD, and VOS.
Note 2: CLincludes scope probe and test jig capacitance.
Note 3: Parameters 100% tested at TA = +25°C. Limits over operating temperature range guaranteed by design and characterization.
Note 4: AC parameters are guaranteed by design and characterization.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
16MHz 200
MAX9205 40MHz 140
40MHz 140
Deterministic Jitter (Figure 9) tDJIT
MAX9207 66MHz 140
ps
(pk-pk)
16MHz 13
MAX9205 40MHz 9
40MHz 9
Random Jitter (Figure 10) tRJIT
MAX9207 66MHz 6
ps
(RMS)
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1, 2 SYNC 1,
SYNC 2
LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins
are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024
SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns
continue to be sent until the SYNC pin is asserted low. Toggling a SYNC pin after six TCLK cycles
high and before 1024 SYNC patterns have been transmitted does not affect the output of the 1024
SYNC patterns.
3–12 IN0–IN9 LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the selected TCLK edge.
13 TCLK_R/FLVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK
falling-edge data strobe.
14 TCLK
LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The
MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and
strobes parallel data into the input latch.
15, 16 DGND Digital Circuit Ground. Connect to ground plane.
17, 26 AVCC Analog Circuit Power Supply (Includes PLL). Bypass AVCC to ground with a 0.1µF capacitor and a
0.001µF capacitor. Place the 0.001µF capacitor closest to AVCC.
18, 20,
23, 25 AGND Analog Circuit Ground. Connect to ground plane.
19 EN LVCMOS/LVTTL Logic Input. High enables serial data output. Low puts the bus LVDS output into
high impedance.
21 OUT- Inverting Bus LVDS Differential Output
22 OUT+ Noninverting Bus LVDS Differential Output
24 PWRDN LVCMOS/LVTTL Logic Input. Low puts the device into power-down mode and the output into high
impedance.
27, 28 DVCC Digital Circuit Power Supply. Bypass DVCC to ground with a 0.1µF capacitor and a 0.001µF
capacitor. Place the 0.001µF capacitor closest to DVCC.
Detailed Description
The MAX9205/MAX9207 are 10-bit serializers designed
to transmit data over balanced media that may be a
standard twisted-pair cable or PCB traces at 160Mbps
to 660Mbps. The interface may be double-terminated
point-to-point or a heavily loaded multipoint bus. The
characteristic impedance of the media and connected
devices can range from 100Ωfor a point-to-point inter-
face to 54Ωfor a heavily loaded multipoint bus. A dou-
ble-terminated point-to-point interface uses a
100Ω-termination resistor at each end of the interface,
resulting in a load of 50Ω. A heavily loaded multipoint
bus requires a termination as low as 54Ωat each end
of the bus, resulting in a termination load of 27Ω. The
serializer requires a deserializer such as the
MAX9206/MAX9208 for a complete data transmission
application.
A high-state start bit and a low-state stop bit, added
internally, frame the 10-bit parallel input data and
ensure a transition in the serial data stream. Therefore,
12 serial bits are transmitted for each 10-bit parallel
input. The MAX9205 accepts a 16MHz to 40MHz refer-
ence clock, producing a serial data rate of 192Mbps
(12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The
MAX9207 accepts a 40MHz to 66MHz reference clock,
producing 480Mbps to 792Mbps. However, since only
10 bits are from input data, the actual throughput is 10
times the TCLK frequency.
To transmit data, the serializers sequence through
three modes: initialization mode, synchronization mode,
and data transmission mode.
MAX9205/MAX9207
Initialization Mode
When VCC is applied, the outputs are held in high
impedance and internal circuitry is disabled by on-chip
power-on-reset circuitry. When the supply voltage
reaches 2.35V, the PLL starts to lock to a local refer-
ence clock (16MHz to 40MHz for MAX9205 and 40MHz
to 66MHz for MAX9207). The reference clock, TCLK, is
provided by the system. A serializer locks within 2049
cycles of TCLK. Once locked, a serializer is ready to
send data or SYNC patterns depending on the levels of
SYNC 1 and SYNC 2.
Synchronization Mode
To rapidly synchronize with a deserializer, SYNC pat-
terns can be sent. A SYNC pattern is six consecutive
ones followed by six consecutive zeros repeating every
TCLK period. When one or both SYNC inputs are
asserted high for at least six cycles of TCLK, the serial-
izer will initiate the transmission of 1024 SYNC patterns.
The serializer will continue to send SYNC patterns if
either of the SYNC input pins remains high. Toggling
one SYNC input with the other SYNC input low before
1024 SYNC patterns are output does not interrupt the
output of the 1024 SYNC patterns.
Data Transmission Mode
After initialization, both SYNC input pins must be set
low by users or through a control signal from the dese-
rializer before data transmission begins. Provided that
SYNC inputs are low, input data at IN0–9 are clocked
into the serializer by the TCLK input. Setting TCLK_R/F
high selects the rising edge of TCLK for data strobe
and low selects the falling edge. If either of the SYNC
inputs goes high for six TCLK cycles at any time during
data transmission, the data at IN0–9 are ignored and
SYNC patterns are sent for at least 1024 TCLK cycles.
A start bit high and a stop bit low frame the 10-bit data
and function as the embedded clock edge in the serial
data stream. The serial rate is the TCLK frequency
times the data and appended bits. For example, if
TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) =
480Mbps. Since only 10 bits are from input data, the
payload rate is 40 x 10 = 400Mbps.
Power-Down
Power-down mode is entered when the PWRDN pin is
driven low. In power-down mode, the PLL of the serial-
izer is stopped and the outputs (OUT+ and OUT-) are
in high impedance, disabling drive current and also
reducing supply current. When PWRDN is driven high,
the serializer must reinitialize and resynchronize before
data can be transferred.
High-Impedance State
The serializer output pins (OUT+ and OUT-) are held in
high impedance when the supply voltage is first
applied and while the PLL is locking to the local refer-
ence clock. Setting EN or PWRDN low puts the device
in high impedance. After initialization, EN functions
asynchronously. For example, the serializer output can
be put into high impedance while SYNC patterns are
being sent without affecting the internal timing of the
SYNC pattern generation. However, if the serializer
goes into high impedance, a deserializer loses PLL
lock and needs to resynchronize before data transfer
can resume.
10-Bit Bus LVDS Serializers
6 _______________________________________________________________________________________
Table 1. Input /Output Function Table
INPUTS OUTPUTS
EN PWRDN SYNC 1 SYNC 2 OUT+, OUT-
HH
When either or both SYNC 1
and SYNC 2 are held high for
at least six TCLK cycles
Synchronization Mode. SYNC patterns of six 1s and six 0s are
transmitted every TCLK cycle for at least 1024 TCLK cycles.
Data at IN0–9 are ignored.
HH L L
Data Transmission Mode. IN0–9 and 2 frame bits are
transmitted every TCLK cycle.
XL X X
LX X X
Output in high-impedance.
X = Don’t care.
Applications Information
Power-Supply Bypassing
Bypass AVCC with high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to AVCC. Bypass DVCC with high-fre-
quency surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smaller valued capacitor closest to DVCC.
Differential Traces and Termination
Output trace characteristics affect the performance of
the MAX9205/MAX9207. Use controlled-impedance
media and terminate at both ends of the transmission
line in the media's characteristic impedance.
Termination with a single resistor at the end of a point-
to-point link typically provides acceptable performance.
However, the MAX9205/MAX9207 output levels are
specified for double-terminated point-to-point and mul-
tipoint applications. With a single 100Ωtermination, the
output swing is larger.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
The differential output signals should be routed close to
each other to cancel their external magnetic field.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90° turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
_______________________________________________________________________________________ 7
OUT+
OUT-
VOD VOS
RL
2
RL
2
Figure 1. Output Voltage Definitions
TCLK
ODD IN_
EVEN IN_
TCLK_R/F = LOW
Figure 2. Worst-Case ICC Test Pattern
TCLK
tCLKT
10%
90%
90%
10%
tCLKT
0
3V
Figure 3. Input Clock Transition Time Requirement
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
8 _______________________________________________________________________________________
VDIFF
VDIFF = 0
tHLT
20%
80%
80%
20%
tLHT
OUT+
10pF
10pF
OUT-
RL
VDIFF = (OUT+) - (OUT-)
Figure 4. Output Load and Transition Times
TCLK
IN_ 1.5V
1.5V1.5V
tH
tS
tTCP
1.5V
TIMING SHOWN FOR TCLK_R/F = LOW
1.5V
Figure 5. Data Input Setup and Hold Times
1.5V 1.5V
tLZ
tHZ
tZL
tZH
3V
0
1.1V
VOL
VOH
OUT±
1.1V
50%50%
50%50%
EN
OUT+
OUT-
PARASITIC PACKAGE AND
TRACE CAPACITANCE
+1.1V
10pF
13.5Ω
13.5Ω
10pF
EN
Figure 6. High-Impedance Test Circuit and Timing
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
_______________________________________________________________________________________ 9
PWRDN
TCLK
OUT±
tPL
ACTIVE
2.0V 0.8V
1.5V
tHZ OR tLZ
tZH OR tZL
SYNC 1 = SYNC 2 = LOW
EN = HIGH
TCLK_R/F = HIGH
HIGH IMPEDANCEHIGH IMPEDANCE
Figure 7. PLL Lock Time and PWRDN High-Impedance Delays
TCLK
OUT±
IN IN0 - IN9 SYMBOL N IN0 - IN9 SYMBOL N + 1
tSD
START BIT
VDIFF = 0 VDIFF = (OUT+) - (OUT-)TCLK_ R/F = HIGH
1.5V
STOP BIT START BIT STOP BIT
OUT0 - OUT9 SYMBOL N+1
OUT0 - OUT9 SYMBOL N
TIMING SHOWN FOR TCLK_R/F = HIGH
Figure 8. Serializer Delay
(OUT+) - (OUT-)
WAVEFORM
SUPERIMPOSED RANDOM DATA
O DIFFERENTIAL
tDJIT
Figure 9. Definition of Deterministic Jitter (tDJIT)
(OUT+) - (OUT-)
WAVEFORM
"CLOCK" PATTERN (1010...)
tRJIT
tRJIT
O DIFFERENTIAL
Figure 10. Definition of Random Jitter (tRJIT)
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
10 ______________________________________________________________________________________
Topologies
The serializers can operate in a variety of topologies.
Examples of double-terminated point-to-point, mul-
tidrop, point-to-point broadcast, and multipoint topolo-
gies are shown in Figures 11 through 14. Use 1%
surface-mount termination resistors.
A point-to-point connection terminated at each end in
the characteristic impedance of the cable or PCB
traces is shown in Figure 11. The total load seen by the
serializer is 50Ω. The double termination typically
reduces reflections compared to a single 100Ωtermi-
nation. A single 100Ωtermination at the deserializer
input is feasible and will make the differential signal
swing larger.
A serializer located at one end of a backplane bus dri-
ving multiple deserializers in a multidrop configuration
is shown in Figure 12. A 54Ωresistor at the far end ter-
minates the bus. This topology allows “broadcast” of
data with a minimum of interconnect.
100ΩPARALLEL
DATA OUT
PARALLEL
DATA IN
MAX9206
MAX9208
MAX9205
MAX9207
100Ω
SERIALIZED DATA
Figure 11. Double-Terminated Point-to-Point
54Ω
ASIC ASIC ASIC ASIC ASIC
MAX9205
MAX9207 MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
Figure 12. Multidrop
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
______________________________________________________________________________________ 11
100Ω100Ω
ASIC ASIC ASIC
100Ω
100Ω
MAX9205
MAX9207
MAX9150
REPEATER
MAX9206
MAX9208
MAX9206
MAX9208
Figure 13. Point-to-Point Broadcast Using MAX9150 Repeater
A point-to-point version of the multidrop bus is shown in
Figure 13. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to the multidrop bus, more interconnect is
traded for more robust hot-plug capability.
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter subtracts from the serial-
izer-deserializer timing margin, a low-jitter repeater is
essential in most high data rate applications.
Multiple serializers and deserializers bused over a dif-
ferential serial connection on a backplane are shown in
Figure 14. The second serializer can be a backup to
the primary serializer. The typical close spacing (1in or
less) of cards on a backplane reduces the characteris-
tic impedance by as much as half the initial, unloaded
value. Termination resistors that match the loaded char-
acteristic impedance are required at each end of the
bus. The total loaded seen by the serializer is 27Ωin
this case.
Board Layout
For bus LVDS applications, a four-layer PCB that pro-
vides separate power, ground, and input/output signals
is recommended. Separate LVTTL/LVCMOS and bus
LVDS signals from each other to prevent coupling into
the bus LVDS lines.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
12 ______________________________________________________________________________________
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
MAX9205
MAX9207
SYNC1
SYNC2
IN0
IN1
IN2
IN3
TCLK
IN4
IN5
IN6
IN7
IN8
IN9
TCLK_R/F
DGND
DGND
AVCC
AGND
EN
AGND
OUT-
OUT+
AGND
PWRDN
AGND
AVCC
DVCC
DVCC
+
SSOP
OUT+
OUT-
EN
10
IN_
TCLK_R/F
TCLK
SYNC 1
SYNC 2
PLL
INPUT LATCH
PARALLEL-TO-SERIAL
TIMING AND
CONTROL PWRDN
MAX9205
MAX9207
Functional DiagramPin Configuration
54Ω
ASIC ASIC ASIC ASIC ASIC
54Ω
MAX9205
MAX9207
MAX9205
MAX9207 MAX9206
MAX9208
MAX9206
MAX9208
MAX9206
MAX9208
Figure 14. Multipoint
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 SSOP A28+4 21-0056 90-0095
Chip Information
PROCESS: CMOS
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
13
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/01 Initial release —
1 11/10 Updated Ordering Information,Absolute Maximum Ratings, and Package Information 1, 2, 13
