Preliminary User's Manual 78K0S/KA1+ 8-Bit Single-Chip Microcontrollers PD78F9221 PD78F9222 Document No. U16898EJ1V0UD00 (1st edition) Date Published November 2003 N CP(K) (c) Printed in Japan 2003 [MEMO] 2 Preliminary User's Manual U16898EJ1V0UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash(R) is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Preliminary User's Manual U16898EJ1V0UD 3 Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, inc. * The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. * Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M5D 02. 11-1 4 Preliminary User's Manual U16898EJ1V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65 03 01 Hong Kong Tel: 2886-9318 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J03.4 Preliminary User's Manual U16898EJ1V0UD 5 INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KA1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. * 78K0S/KA1+: PD78F9221, 78F9222 Purpose This manual is intended to give users on understanding of the functions described in the Organization below. Organization Two manuals are available for the 78K0S/KA1+: this manual and the Instruction Manual (common to the 78K/0S Series). 78K/0S Series 78K0S/KA1+ Instructions User's Manual User's Manual * Pin functions * CPU function * Internal block functions * Instruction set * Interrupts * Instruction description * Other internal peripheral functions * Electrical specifications (target) How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of 78K0S/KA1+ Read this manual in the order of the CONTENTS. How to read register formats The name of a bit whose number is enclosed with <> is reserved in the assembler and is defined in the C compiler by the header file sfrbit.h. To learn the detailed functions of a register whose register name is known See APPENDIX C REGISTER INDEX. To learn the details of the instruction functions of the 78K/0S Series Refer to 78K/0S Series Instructions User's Manual (U11047E) separately available. To learn the electrical specifications (target) of the 78K0S/KA1+ See CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES). 6 Preliminary User's Manual U16898EJ1V0UD Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0S/KA1+ Subseries User's Manual This manual 78K/0S Series Instructions User's Manual U11047E Documents Related to Development Software Tools (User's Manuals) Document Name RA78K0S Assembler Package CC78K0S C Compiler Document No. Operation U14876E Language U14877E Structured Assembly Language U11623E Operation U14871E Language ID78K Series Integrated Debugger Ver. 2.30 or Later U14872E TM Operation (Windows Based) Project Manager Ver. 3.12 or Later (Windows Based) U15185E U14610E Documents Related to Development Hardware Tools (User's Manuals) Document Name Document No. IE-78K0S-NS In-Circuit Emulator U13549E IE-78K0S-NS-A In-Circuit Emulator U15207E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Preliminary User's Manual U16898EJ1V0UD 7 Documents Related to Flash Memory Writing Document Name PG-FP4 Flash Memory Programmer User's Manual Document No. U15260E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 8 Preliminary User's Manual U16898EJ1V0UD CONTENTS CHAPTER 1 OVERVIEW......................................................................................................................... 14 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features ...................................................................................................................................... 14 Application Fields ...................................................................................................................... 14 Ordering Information ................................................................................................................. 15 Pin Configuration (Top View) ................................................................................................... 15 78K0S/Kx1+ Product Lineup..................................................................................................... 16 Block Diagram............................................................................................................................ 17 Functional Outline ..................................................................................................................... 18 CHAPTER 2 PIN FUNCTIONS............................................................................................................... 19 2.1 2.2 Pin Function List........................................................................................................................ 19 Pin Functions ............................................................................................................................. 21 2.2.1 2.3 P20 to P23 (Port 2)...................................................................................................................... 21 2.2.2 P30, P31, and P34 (Port 3) ......................................................................................................... 21 2.2.3 P40 to P45 (Port 4)...................................................................................................................... 22 2.2.4 P121 to P123 (Port 12)................................................................................................................ 22 2.2.5 P130 (Port 13) ............................................................................................................................. 22 2.2.6 RESET ........................................................................................................................................ 22 2.2.7 X1 and X2 ................................................................................................................................... 22 2.2.8 AVREF........................................................................................................................................... 22 2.2.9 VDD .............................................................................................................................................. 23 2.2.10 VSS............................................................................................................................................... 23 Pin I/O Circuits and Connection of Unused Pins ................................................................... 23 CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 25 3.1 3.2 3.3 3.4 Memory Space............................................................................................................................ 25 3.1.1 Internal program memory space.................................................................................................. 27 3.1.2 Internal data memory space ........................................................................................................ 27 3.1.3 Special function register (SFR) area ........................................................................................... 28 3.1.4 Data memory addressing ............................................................................................................ 28 Processor Registers .................................................................................................................. 30 3.2.1 Control registers .......................................................................................................................... 30 3.2.2 General-purpose registers........................................................................................................... 32 3.2.3 Special function registers (SFRs) ................................................................................................ 33 Instruction Address Addressing .............................................................................................. 36 3.3.1 Relative addressing..................................................................................................................... 36 3.3.2 Immediate addressing ................................................................................................................. 37 3.3.3 Table indirect addressing ............................................................................................................ 37 3.3.4 Register addressing .................................................................................................................... 38 Operand Address Addressing.................................................................................................. 39 3.4.1 Direct addressing ........................................................................................................................ 39 Preliminary User's Manual U16898EJ1V0UD 9 3.4.2 Short direct addressing................................................................................................................40 3.4.3 Special function register (SFR) addressing .................................................................................41 3.4.4 Register addressing.....................................................................................................................42 3.4.5 Register indirect addressing ........................................................................................................43 3.4.6 Based addressing........................................................................................................................44 3.4.7 Stack addressing .........................................................................................................................44 CHAPTER 4 PORT FUNCTIONS ...........................................................................................................45 4.1 4.2 4.3 4.4 Functions of Ports .....................................................................................................................45 Port Configuration .....................................................................................................................46 4.2.1 Port 2...........................................................................................................................................47 4.2.2 Port 3...........................................................................................................................................48 4.2.3 Port 4...........................................................................................................................................49 4.2.4 Port 12.........................................................................................................................................54 4.2.5 Port 13.........................................................................................................................................56 Registers Controlling Port Functions ......................................................................................56 Operation of Port Function .......................................................................................................61 4.4.1 Writing to I/O port ........................................................................................................................61 4.2.2 Reading from I/O port ..................................................................................................................61 4.4.3 Operations on I/O port .................................................................................................................61 CHAPTER 5 CLOCK GENERATORS...................................................................................................62 5.1 5.2 5.3 5.4 5.5 5.6 Functions of Clock Generators ................................................................................................62 5.1.1 System clock oscillators...............................................................................................................62 5.1.2 Clock oscillator for interval time generation .................................................................................62 Configuration of Clock Generators ..........................................................................................63 Registers Controlling Clock Generators .................................................................................65 System Clock Oscillators ..........................................................................................................68 5.4.1 High-speed Ring-OSC oscillator ..................................................................................................68 5.4.2 Crystal/ceramic oscillator.............................................................................................................69 5.4.3 External clock input circuit ...........................................................................................................71 5.4.4 Prescaler .....................................................................................................................................71 Operation of CPU Clock Generator ..........................................................................................72 Operation of Clock Generator Supplying Clock to Peripheral Hardware.............................77 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 .............................................................................79 6.1 6.2 6.3 6.4 10 Functions of 16-Bit Timer/Event Counter 00 ...........................................................................79 Configuration of 16-Bit Timer/Event Counter 00 ....................................................................80 Registers to Control 16-Bit Timer/Event Counter 00..............................................................84 Operation of 16-Bit Timer/Event Counter 00 ...........................................................................90 6.4.1 Interval timer operation ................................................................................................................90 6.4.2 External event counter operation.................................................................................................93 6.4.3 Pulse width measurement operations..........................................................................................96 6.4.4 Square-wave output operation...................................................................................................104 6.4.5 PPG output operations ..............................................................................................................106 Preliminary User's Manual U16898EJ1V0UD 6.4.6 6.5 One-shot pulse output operation ............................................................................................... 109 Cautions Related to 16-Bit Timer/Event Counter 00 ............................................................114 CHAPTER 7 8-BIT TIMER 80..............................................................................................................118 7.1 7.2 7.3 7.4 Function of 8-Bit Timer 80.......................................................................................................118 Configuration of 8-Bit Timer 80 ..............................................................................................119 Register Controlling 8-Bit Timer 80 .......................................................................................121 Operation of 8-Bit Timer 80.....................................................................................................122 7.4.1 7.5 Operation as interval timer ........................................................................................................ 122 Notes on 8-Bit Timer 80...........................................................................................................124 CHAPTER 8 8-BIT TIMER H1 .............................................................................................................125 8.1 8.2 8.3 8.4 Functions of 8-Bit Timer H1 .................................................................................................... 125 Configuration of 8-Bit Timer H1 .............................................................................................125 Registers Controlling 8-Bit Timer H1.....................................................................................128 Operation of 8-Bit Timer H1 ....................................................................................................131 8.4.1 Operation as interval timer/square-wave output ........................................................................ 131 8.4.2 Operation as PWM output mode ............................................................................................... 134 CHAPTER 9 WATCHDOG TIMER .......................................................................................................140 9.1 9.2 9.3 9.4 Functions of Watchdog Timer ................................................................................................140 Configuration of Watchdog Timer..........................................................................................142 Registers Controlling Watchdog Timer .................................................................................143 Operation of Watchdog Timer ................................................................................................145 9.4.1 Watchdog timer operation when "low-speed Ring-OSC cannot be stopped" is selected by option byte................................................................................................................................. 145 9.4.2 Watchdog timer operation when "low-speed Ring-OSC can be stopped by software" is selected by option byte.............................................................................................................. 147 9.4.3 Watchdog timer operation in STOP mode (when "low-speed Ring-OSC can be stopped by software" is selected by option byte)....................................................................... 149 9.4.4 Watchdog timer operation in HALT mode (when "low-speed Ring-OSC can be stopped by software" is selected by option byte)....................................................................... 151 CHAPTER 10 A/D CONVERTER .........................................................................................................152 10.1 10.2 10.3 10.4 Functions of A/D Converter ....................................................................................................152 Configuration of A/D Converter..............................................................................................155 Registers Used by A/D Converter ..........................................................................................157 A/D Converter Operations.......................................................................................................162 10.4.1 Basic operations of A/D converter ............................................................................................. 162 10.4.2 Input voltage and conversion results ......................................................................................... 164 10.4.3 A/D converter operation mode................................................................................................... 165 10.5 How to Read A/D Converter Characteristics Table ..............................................................167 10.6 Cautions for A/D Converter ....................................................................................................169 CHAPTER 11 SERIAL INTERFACE UART6......................................................................................173 Preliminary User's Manual U16898EJ1V0UD 11 11.1 11.2 11.3 11.4 Functions of Serial Interface UART6......................................................................................173 Configuration of Serial Interface UART6 ...............................................................................177 Registers Controlling Serial Interface UART6 ......................................................................180 Operation of Serial Interface UART6......................................................................................189 11.4.1 Operation stop mode .................................................................................................................189 11.4.2 Asynchronous serial interface (UART) mode.............................................................................190 11.4.3 Dedicated baud rate generator ..................................................................................................206 CHAPTER 12 INTERRUPT FUNCTIONS ............................................................................................213 12.1 12.2 12.3 12.4 Interrupt Function Types.........................................................................................................213 Interrupt Sources and Configuration .....................................................................................214 Interrupt Function Control Registers.....................................................................................216 Interrupt Servicing Operation .................................................................................................221 12.4.1 Maskable interrupt request acknowledgment operation.............................................................221 12.4.2 Multiple interrupt servicing .........................................................................................................224 12.4.3 Interrupt request pending...........................................................................................................225 CHAPTER 13 STANDBY FUNCTION ..................................................................................................226 13.1 Standby Function and Configuration.....................................................................................226 13.1.1 Standby function........................................................................................................................226 13.1.2 Registers used during standby ..................................................................................................228 13.2 Standby Function Operation...................................................................................................229 13.2.1 HALT mode ...............................................................................................................................229 13.2.2 STOP mode...............................................................................................................................232 CHAPTER 14 RESET FUNCTION .......................................................................................................236 14.1 Register for Confirming Reset Source...................................................................................243 CHAPTER 15 POWER-ON-CLEAR CIRCUIT .....................................................................................244 15.1 15.2 15.3 15.4 Functions of Power-on-Clear Circuit .....................................................................................244 Configuration of Power-on-Clear Circuit ...............................................................................245 Operation of Power-on-Clear Circuit......................................................................................245 Cautions for Power-on-Clear Circuit......................................................................................246 CHAPTER 16 LOW-VOLTAGE DETECTOR .......................................................................................248 16.1 16.2 16.3 16.4 16.5 Functions of Low-Voltage Detector .......................................................................................248 Configuration of Low-Voltage Detector .................................................................................248 Registers Controlling Low-Voltage Detector ........................................................................249 Operation of Low-Voltage Detector........................................................................................251 Cautions for Low-Voltage Detector........................................................................................254 CHAPTER 17 OPTION BYTE................................................................................................................257 CHAPTER 18 FLASH MEMORY ..........................................................................................................260 12 Preliminary User's Manual U16898EJ1V0UD 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Features ....................................................................................................................................260 Memory Configuration.............................................................................................................261 Functional Outline ...................................................................................................................262 Writing with Flash Programmer ............................................................................................. 264 Programming Environment.....................................................................................................266 Communication Mode .............................................................................................................266 Processing of Pins on Board..................................................................................................267 18.7.1 X1 and X2 pins .......................................................................................................................... 267 18.7.2 RESET pin ................................................................................................................................ 267 18.7.3 Port pins .................................................................................................................................... 267 18.7.4 Power supply............................................................................................................................. 267 18.8 Programming Method ..............................................................................................................268 18.8.1 Controlling flash memory........................................................................................................... 268 18.8.2 Flash memory programming mode............................................................................................ 269 18.8.3 Communication commands ....................................................................................................... 269 18.9 Flash Memory Programming by Self Writing ........................................................................270 CHAPTER 19 INSTRUCTION SET OVERVIEW.................................................................................271 19.1 Operation ..................................................................................................................................271 19.1.1 Operand identifiers and description methods ............................................................................ 271 19.1.2 Description of "Operation" column............................................................................................. 272 19.1.3 Description of "Flag" column...................................................................................................... 272 19.2 Operation List...........................................................................................................................273 19.3 Instructions Listed by Addressing Type ...............................................................................278 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES).............................................281 CHAPTER 21 PACKAGE DRAWING ..................................................................................................293 APPENDIX A DEVELOPMENT TOOLS ..............................................................................................294 A.1 A.2 A.3 A.4 A.5 A.6 Software Package ....................................................................................................................296 Language Processing Software .............................................................................................296 Control Software ......................................................................................................................297 Flash Memory Writing Tools...................................................................................................297 Debugging Tools (Hardware)..................................................................................................298 Debugging Tools (Software)...................................................................................................299 APPENDIX B NOTES ON TARGET SYSTEM DESIGN...................................................................300 APPENDIX C REGISTER INDEX.........................................................................................................301 C.1 C.2 Register Index (Register Name) .............................................................................................301 Register Index (Symbol)..........................................................................................................303 Preliminary User's Manual U16898EJ1V0UD 13 CHAPTER 1 OVERVIEW 1.1 Features O Minimum instruction execution time selectable from high speed (0.2 s) and low speed (3.2 s) (with CPU clock of 10 MHz) O General-purpose registers: 8 bits x 8 registers O ROM and RAM capacities Item Program Memory (Flash Memory) Memory (Internal High-Speed RAM) Part number PD78F9221 2 KB 128 bytes PD78F9222 4 KB 256 bytes O On-chip power-on clear (POC) circuit and low voltage detector (LVI) O On-chip watchdog timer (operable on internal low-speed Ring-OSC clock) O I/O ports: 17 O Timer: 4 channels * 16-bit timer/event counter: 1 channel * 8-bit timer: 2 channels * Watchdog timer: 1 channel O Serial interface: UART (LIN (Local Interconnect Network) bus supported) 1 channel O 10-bit resolution A/D converter: 4 channels O Supply voltage: VDD = 2.0 to 5.5 VNote O Operating temperature range: TA = -40 to +85C Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear (POC) circuit is 2.1 V 0.1 V. 1.2 Application Fields O Automotive electronics * System control of body instrumentation system (such as power windows and keyless entry reception) * Sub-microcontroller of control system O Household appliances * Electric toothbrushes * Electric shavers O Toys O Industrial equipment * Sensor and switch control * Power tools 14 Preliminary User's Manual U16898EJ1V0UD CHAPTER 1 OVERVIEW 1.3 Ordering Information Part Number Package PD78F9221MC-5A4 PD78F9222MC-5A4 Internal ROM 20-pin plastic SSOP (7.62 mm (300)) Flash memory 20-pin plastic SSOP (7.62 mm (300)) Flash memory 1.4 Pin Configuration (Top View) 20-pin plastic SSOP (7.62 mm (300)) PD78F9221MC-5A4 PD78F9222MC-5A4 VSSNote 1 20 AVREF P121/X1 2 19 P20/ANI0 P122/X2 3 18 P21/ANI1 P123 4 17 P22/ANI2 VDD 5 16 P23/ANI3 RESET/P34 6 15 P130 P31/TI010/TO00/INTP2 7 14 P45 P30/TI000/INTP0 8 13 P44/RxD6 P40 9 12 P43/TxD6/INTP1 10 11 P42/TOH1 P41/INTP3 Note VSS and AVSS are internally connected in the 78K0S/KA1+. Be sure to connect VSS to a stabilized GND in order to stabilize VSS via GND (= 0 V). ANI0 to ANI3: Analog input RESET: Reset AVREF: Analog reference voltage RxD6: Receive data RxD6: Receive data TI000, TI010: Timer input INTP0 to INTP3: External interrupt input TO00, TOH1: Timer output P20 to P23: Port 2 TxD6: Transmit data P30, P31, P34: Port 3 VDD: Power supply P40 to P45: Port 4 VSS: Ground P121 to P123: Port 12 X1, X2: Crystal oscillator (X1 input clock) P130: Port 13 Preliminary User's Manual U16898EJ1V0UD 15 CHAPTER 1 OVERVIEW 1.5 78K0S/Kx1+ Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number 78K0S/KU1+ 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+ 8 pins 16 pins 20 pins 30 pins 1 KB, 2 KB, 4 KB 1 KB, 2 KB, 4 KB 2 KB 128 bytes 128 bytes 128 bytes Item Number of pins Internal Flash memory memory RAM 4 KB 4 KB, 8 KB 256 256 bytes bytes Supply voltage VDD = 2.0 to 5.5 V Minimum instruction 0.20 s (10 MHz, VDD = 4.0 to 5.5 V) execution time 0.33 s (6 MHz, VDD = 3.0 to 5.5 V) 0.40 s (5 MHz, VDD = 2.7 to 5.5 V) 4.0 s (500 kHz, VDD = 2.0 to 5.5 V) Internal high-speed Ring-OSC oscillation (8 MHz (TYP.)) System clock Crystal/ceramic oscillation (1 to 10 MHz) (oscillation frequency) X1 external clock input oscillation (1 to 10 MHz) Clock for TMH1 and WDT Internal low-speed Ring-OSC oscillation (240 kHz (TYP.)) (oscillation frequency) Port Timer CMOS I/O 5 13 15 24 CMOS input 1 1 1 1 CMOS output - - 1 1 16-bit (TM0) 1 ch 8-bit (TMH) 1 ch 8-bit (TM8) - 1 ch WDT 1 ch Serial interface - LIN-Bus-supporting UART: 1 ch A/D converter 8 bits: 4 ch (2.7 to 5.5V) 10 bits: 4 ch (2.7 to 5.5V) External 2 4 Internal 6 10 Interrupts Reset RESET pin POC LVI Provided 2.1 V 0.1 V Provided (selectable by software) WDT Provided Operating temperature range -40 to +85C 16 Preliminary User's Manual U16898EJ1V0UD CHAPTER 1 OVERVIEW 1.6 Block Diagram TO00/TI010/P31 Port 2 16-bit timer event counter 00 TI000/P30 Port 3 4 P20 to P23 2 P30, P31 P34 8-bit timer 80 TOH1/P42 8-bit timer H1 78K0S CPU core Low-speed Ring-OSC Flash memory Port 4 6 P40 to P45 Port 12 3 P121 to P123 Port 13 P130 Power on clear/ low voltage indicator POC/LVI control Watchdog timer RxD6/P44 Serial interface UART6 TxD6/P43 ANI0/P20 to ANI3/P23 Internal high-speed RAM 4 Reset control A/D converter AVREF RESET/P34 INTP0/P30 INTP1/P43 System control Interrupt control X1/P121 X2/P122 INTP2/P31 High-speed Ring-OSC INTP3/P41 VDD VSSNote Note VSS and AVSS are internally connected in the 78K0S/KA1+. Be sure to connect VSS to stabilized GND in order to stabilize VSS via GND (= 0 V). Preliminary User's Manual U16898EJ1V0UD 17 CHAPTER 1 OVERVIEW 1.7 Functional Outline PD78F9221 Item Internal memory PD78F9222 Flash memory 2 KB 4 KB High-speed RAM 128 bytes 256 bytes Memory space 64 KB X1 input clock (oscillation frequency) Crystal/ceramic/external clock input: 10 MHz (VDD = 4.0 to 5.5 V), 6 MHz (VDD = 3.0 to 5.5 V), 5 MHz (VDD = 2.7 to 5.5 V), 500 kHz (VDD = 2.0 to 5.5 V) Ring-OSC High speed (oscillation clock frequency) Low speed (for TMH1 Internal Ring oscillation: 8 MHz (TYP.) Internal Ring oscillation: 240 kHz (TYP.) and WDT) General-purpose registers 8 bits x 8 registers Minimum instruction execution time 0.2 s/0.8 s (X1 input clock: fX = 10 MHz) Instruction set * 16-bit operation * Bit manipulation (set, reset, test), etc. I/O port Total: Timer Timer output 17 pins CMOS I/O: 15 pins CMOS input: 1 pin CMOS output: 1 pin * 16-bit timer/event counter: 1 channel * 8-bit timer (timer H1): 1 channel * 8-bit timer (timer 80): 1 channel * Watchdog timer: 1 channel 2 pins (PWM: 1 pin) A/D converter 10-bit resolution x 4 channels Serial interface LIN-bus-supporting UART mode: 1 channel Vectored interrupt sources External 4 Internal 10 * Reset by RESET pin * Internal reset by watchdog timer * Internal reset by power-on clear Reset * Internal reset by low-voltage detector Note Supply voltage VDD = 2.0 to 5.5 V Operating temperature range TA = -40 to +85C Package 20-pin plastic SSOP (7.62 mm (300)) Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V 0.1 V. 18 Preliminary User's Manual U16898EJ1V0UD CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port pins Pin Name I/O Function After Reset AlternateFunction Pin P20 to P23 I/O Port 2. Input ANI0 to ANI3 Input TI000/INTP0 4-bit I/O port. Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting software. P30 I/O Can be set to input or output mode in 1- Port 3 bit units. P31 TI010/TO00/ An on-chip pull-up resistor can be INTP2 connected by setting software. P34 Input P40 I/O Input only Port 4. Input - Input 6-bit I/O port. P41 RESET INTP3 Can be set to input or output mode in 1-bit units. P42 TOH1 An on-chip pull-up resistor can be connected by setting software. P43 TxD6/INTP1 P44 RxD6 - P45 P121 I/O Port 12. Input 3-bit I/O port. P122 X2 Can be set to input or output mode in 1-bit units. P123 X1 - An on-chip pull-up resistor can be connected only to P123 by setting software. P130 Output Port 13. Output - 1-bit output-only port Preliminary User's Manual U16898EJ1V0UD 19 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name I/O Function After Reset AlternateFunction Pin INTP0 Input External interrupt input for which the valid edge (rising edge, Input falling edge, or both rising and falling edges) can be specified INTP1 P30/TI000 P43/TxD6 INTP2 P31/TI010/TO00 INTP3 P41 RxD6 Input Serial data input for asynchronous serial interface Input P44 TxD6 Output Serial data output for asynchronous serial interface Input P43/INTP1 TI000 Input External count clock input to 16-bit timer/event counter 00. Input P30/INTP0 Capture trigger input to capture registers (CR000 and CR010) of 16-bit timer/event counter 00 TI010 Capture trigger input to capture register (CR000) of 16-bit P31/TO00/INTP2 timer/event counter 00 TO00 Output 16-bit timer/event counter 00 output Input P31/TI010/INTP2 TOH1 Output 8-bit timer H1 output Input P42 ANI0 to ANI3 Input Analog input of A/D converter Input P20 to P23 AVREF RESET X1 - Reference voltage of A/D converter - - Input System reset input - - Input Connection of crystal/ceramic oscillator for system clock - P121 - P122 oscillation. External clock input X2 - Connection of crystal/ceramic oscillator for system clock oscillation. VDD - Positive power supply - - VSS - Ground potential - - 20 Preliminary User's Manual U16898EJ1V0UD CHAPTER 2 PIN FUNCTIONS 2.2 Pin Functions 2.2.1 P20 to P23 (Port 2) P20 to P23 constitute a 4-bit I/O port, port 2. In addition to I/O port pins, these pins also have a function to input analog signals to the A/D converter. These pins can be set to the following operation modes in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 2 (PU2). (2) Control mode P20 to P23 function as the analog input pins (ANI0 to ANI3) of the A/D converter. When using these pins as analog input pins, refer to 10.6 Cautions for A/D converter (5) ANI0/P20 to ANI3/P23. 2.2.2 P30, P31, and P34 (Port 3) P30, P31 and P34 constitute a 2-bit I/O port, port 3. In addition to I/O port pins, these pins also have functions to input/output a timer signal, and input an external interrupt request signal. P34 is a 1-bit input-only port. This pin is also used as a RESET pin. P30 and P31 can be set to the following operation modes in 1-bit units. (1) Port mode P30 and P31 function as a 2-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 3 (PU3). P34 functions as a 1-bit input-only port. (2) Control mode P30, P31, and P34 function to input/output signals to/from internal timers, and to input an external interrupt request signal. (a) INTP0 and INTP2 These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI000 This pin inputs an external count clock to 16-bit timer/event counter 00, or a capture trigger signal to the capture registers (CR000 and CR010) of 16-bit timer/event counter 00. (c) TI010 This pin inputs a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00. (d) TO00 This pin outputs a signal from 16-bit timer/event counter 00. Preliminary User's Manual U16898EJ1V0UD 21 CHAPTER 2 PIN FUNCTIONS 2.2.3 P40 to P45 (Port 4) P40 to P45 constitute a 6-bit I/O port, port 4. In addition to I/O port pins, these pins also have functions to output a timer signal, input external interrupt request signals, and input/output the data of the serial interface. These pins can be set to the following operation modes in 1-bit units. (1) Port mode P40 and P45 function as a 6-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 4 (PU4). (2) Control mode P40 and 45 function to output a signal from an internal timer, input external interrupt request signals, and input/output data of the serial interface. (a) INTP1 and INTP3 These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TOH1 This is the output pin of 8-bit timer H1. (c) TxD6 This pin outputs serial data from the asynchronous serial interface. (d) RxD6 This pin inputs serial data to the asynchronous serial interface. 2.2.4 P121 to P123 (Port 12) P121 to P123 constitute a 3-bit I/O port, port 12. Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). An on-chip pullup resistor can be connected to P123 by using pull-up resistor option register 12 (PU12). P121 and P122 also function as the X1 and X2 pins, respectively. 2.2.5 P130 (Port 13) This is a 1-bit output-only port. 2.2.6 RESET This pin inputs an active-low system reset signal. 2.2.7 X1 and X2 These pins connect an oscillator to oscillate the X1 input clock. Supply an external clock to X1. 2.2.8 AVREF This pin inputs a reference voltage to the internal A/D converter. When the A/D converter is not used, connect this pin to VDD. 22 Preliminary User's Manual U16898EJ1V0UD CHAPTER 2 PIN FUNCTIONS 2.2.9 VDD This is the positive power supply pin. 2.2.10 VSS This is the ground pin. 2.3 Pin I/O Circuits and Connection of Unused Pins Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins Pin Name P20/ANI0 to P23/ANI3 P30/TI000/INTP0 I/O Circuit Type I/O I/O 11 Recommended Connection of Unused Pin Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. 8-A P31/TI010/TO00/INTP2 P34/RESET 2 Input Directly connect to VDD or VSS. P40 8-A I/O Input: Individually connect to VDD or VSS via resistor. Output: Leave open. P41/INTP3 P42/TOH1 P43/TxD6/INTP1 P44/RxD6 P45 P121/X1 16-B P122/X2 P123 8-A P130 3-C AVREF - Output Leave open. Input Directly connect to VDD. Preliminary User's Manual U16898EJ1V0UD 23 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 2 VDD Type 11 Pull up enable P-ch AVREF Data P-ch IN IN/OUT Output disable Schmitt-triggered input with hysteresis characteristics N-ch Comparator P-ch + N-ch VSS AVREF (Threshold voltage) Input enable Type 3-C Type 16-B Feedback cut-off P-ch VDD P-ch Data OUT X1, IN/OUT OSC enable X2, IN/OUT N-ch VDD Data P-ch Type 8-A Output disable VDD Pull up enable N-ch P-ch VDD Data Data P-ch P-ch IN/OUT Output disable 24 N-ch Output Disable Preliminary User's Manual U16898EJ1V0UD N-ch CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The 78K0S/KA1+ can access up to 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps. Figure 3-1. Memory Map (PD78F9221) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Use prohibited Data memory space 0FFFH 1000H 0FFFH Program area Program memory space Flash memory 4,096 x 8 bits 0 0 0 0 082 081 080 07F H H H H Option byte area CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H 0000H Remark The option byte is one byte at 0080H. Preliminary User's Manual U16898EJ1V0UD 25 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD78F9222) FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Use prohibited Data memory space 0FFFH 1000H 0FFFH Program area Program memory space Flash memory 4,096 x 8 bits 0 0 0 0 082 081 080 07F H H H H Option byte area CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 0000H 0000H Remark 26 The option byte is one byte at 0080H. Preliminary User's Manual U16898EJ1V0UD CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KA1+ provides the following internal ROMs (or flash memory) containing the following capacities. Table 3-1. Internal ROM Capacity Part Number Internal ROM Structure PD78F9221 Capacity 2,048 x 8 bits Flash memory PD78F9222 4,096 x 8 bits The following areas are allocated to the internal program memory space. (1) Vector table area The 34-byte area of addresses 0000H to 0021H is reserved as a vector table area. This area stores program start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 3-2. Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H Reset input 0014H INTFLC 0006H INTLVI 0016H INTP2 0008H INTP0 0018H INTP3 000AH INP1 001AH INTTM80 000CH INTTMH1 001CH INTSRE6 000EH INTTM000 001EH INTSR6 0010H INTTM010 0020H INTST6 0012H INTAD (2) CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH. (3) Option byte area The option byte area is the 1-byte area of address 0080H. For details, refer to CHAPTER 17 OPTION BYTE. 3.1.2 Internal data memory space 128-byte internal high-speed RAM is provided in the PD78F9221 and 256-byte in the PD78F9222. The internal high-speed RAM can also be used as a stack memory. Preliminary User's Manual U16898EJ1V0UD 27 CHAPTER 3 CPU ARCHITECTURE 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). 3.1.4 Data memory addressing The 78K0S/KA1+ is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. The data memory area (FE80H to FFFFH or FE00H to FFFFH) can be accessed using a unique addressing mode according to its use, such as a special function register (SFR). Figures 3-3 and 3-4 illustrate the data memory addressing. Figure 3-3. Data Memory Addressing (PD78F9221) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FE1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 128 x 8 bits FE80H FE7FH Direct addressing Register indirect addressing Based addressing Use prohibted 0800H 07FFH Flash memory 2,048 x 8 bits 0000H 28 Preliminary User's Manual U16898EJ1V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Data Memory Addressing (PD78F9222) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FE1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH FE00H FDFFH Direct addressing Register indirect addressing Based addressing Use prohibited 1000H 0FFFH Flash memory 4,096 x 8 bits 0000H Preliminary User's Manual U16898EJ1V0UD 29 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0S/KA1+ provides the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-5. Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets PSW to 02H. Figure 3-6. Program Status Word Configuration 7 PSW IE 0 Z 0 AC 0 0 1 CY (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources. This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases. 30 Preliminary User's Manual U16898EJ1V0UD CHAPTER 3 CPU ARCHITECTURE (d) Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-7. Stack Pointer Configuration 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented before writing (saving) to the stack memory and is incremented after reading (restoring) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-8 and 3-9. Caution Since reset input makes SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-8. Data to Be Saved to Stack Memory PUSH rp instruction Interrupt CALL, CALLT instructions SP SP SP _ 2 SP SP _ 2 SP _ 3 SP _ 3 PC7 to PC0 SP _ 2 Lower half register pairs SP _ 2 PC7 to PC0 SP _ 2 PC15 to PC8 SP _ 1 Upper half register pairs SP _ 1 PC15 to PC8 SP _ 1 PSW SP SP SP Figure 3-9. Data to Be Restored from Stack Memory POP rp instruction SP RETI instruction RET instruction SP Lower half register pairs SP PC7 to PC0 SP PC7 to PC0 SP + 1 Upper half register pairs SP + 1 PC15 to PC8 SP + 1 PC15 to PC8 SP + 2 PSW SP + 2 SP SP + 2 SP Preliminary User's Manual U16898EJ1V0UD SP + 3 31 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 3-10. General-Purpose Register Configuration (a) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Function names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 32 0 7 Preliminary User's Manual U16898EJ1V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying an address, describe an even address. Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol Indicates the addresses of the implemented special function registers. The symbols shown in this column are reserved words in the assembler, and have already been defined in a header file called "sfrbit.h" in the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. * R/W Indicates whether the special function register can be read or written. R/W: Read/write R: Read only W: Write only * Number of bits manipulated simultaneously Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated. * After reset Indicates the status of the special function register when a reset is input. Preliminary User's Manual U16898EJ1V0UD 33 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol R/W Number of Bits Manipulated After Reset Simultaneously FF02H Port register 2 P2 1 Bit 8 Bits 16 Bits - R/W Note 1 FF03H Port register 3 P3 - FF04H Port register 4 P4 - FF0CH Port register 12 P12 FF0DH Port register 13 P13 FF0EH 8-bit timer H compare register 01 CMP01 FF0FH 8-bit timer H compare register 11 00H - W - R/W - - CMP11 - 16-bit timer counter 00 TM00 R - - 0000H 16-bit timer capture/compare register 000 CR000 R/W - - 0000H 16-bit timer capture/compare register 010 CR010 - - 0000H 10-bit A/D conversion result register ADCR - - Undefined FF1AH 8-bit A/D conversion result register ADCRH - - FF22H Port mode register 2 PM2 - FF23H Port mode register 3 PM3 - FF24H Port mode register 4 PM4 - FF12H - Note 2 FF13H FF14H Note 2 FF15H FF16H Note 2 FF17H FF18H R Note 2 FF19H R/W FF2CH Port mode register 12 PM12 - FF32H Pull-up resistance option register 2 PU2 - FF33H Pull-up resistance option register 3 PU3 - FF34H Pull-up resistance option register 4 PU4 - FFH 00H FF3CH Pull-up resistance option register 12 PU12 - FF48H Watchdog timer mode register WDTM - - 67H FF49H Watchdog timer enable register WDTE - - 9AH FF50H Low voltage detect register LVIM - - 00H - - R - - 00H R/W - - 00H HSRCM - - 16-bit timer mode control register 00 TMC00 - Prescaler mode register 00 PRM00 - Capture/compare control register 00 CRC00 - FF63H 16-bit timer output control register 00 TOC00 - FF70H 8-bit timer H mode register 1 TMHMD1 - FF51H Low voltage detection level select register LVIS FF54H Reset control flag register RESF FF58H Low-speed Ring-OSC mode register LSRCM FF5AH High-speed Ring-OSC mode register FF60H FF61H FF62H Notes 1. Only P34 is an input-only port. 2. A 16-bit access is possible only by the short direction addressing. 3. Varies depending on the reset cause. 34 Preliminary User's Manual U16898EJ1V0UD Note 3 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol R/W Number of Bits Manipulated After Reset Simultaneously R/W 1 Bit 8 Bits 16 Bits - FF80H A/D converter mode register ADM FF81H Analog input channel specify register ADS - FF84H Port mode control register 2 PMC2 - 00H FF8CH Input switching control register ISC - FF90H Asynchronous serial interface operation mode ASIM6 - 01H - - FFH - - 00H register 6 FF92H FF93H Reception buffer register 6 RXB6 Asynchronous serial interface reception error ASIS6 R status register 6 FF94H Transmission buffer register 6 TXB6 R/W - - FFH FF95H Asynchronous serial interface transmission status ASIF6 R - - 00H R/W - - register 6 FF96H Clock selection register 6 CKSR6 FF97H Baud rate generator control register 6 BRGC6 - - FFH FF98H Asynchronous serial interface control register 6 ASICL6 - 16H FFCCH 8-bit timer mode control register 80 TMC80 - 00H FFCDH 8-bit compare register 80 CR80 W - - Undefined FFCEH 8-bit timer counter 80 TM80 R - - 00H FFE0H Interrupt request flag register 0 IF0 R/W - FFE1H Interrupt request flag register 1 IF1 - FFE4H Interrupt mask flag register 0 MK0 - FFE5H Interrupt mask flag register 1 MK1 - FFECH External interrupt mode register 0 INTM0 - - FFFDH External interrupt mode register 1 INTM1 - - FFF3H Preprocessor clock control register PPCC - FFF4H Oscillation stabilization time selection register OSTS - - FFH 00H 02H Undefined Note FFFBH Processor clock control register PCC - 02H Note The oscillation stabilization time that elapses after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Preliminary User's Manual U16898EJ1V0UD 35 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination address information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) to branch. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes the sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC is the start address of PC the next instruction of a BR instruction. + 8 15 7 6 0 S jdisp8 15 0 PC When S = 0, indicates that all bits are "0". When S = 1, indicates that all bits are "1". 36 Preliminary User's Manual U16898EJ1V0UD CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 0 CALL or BR Low addr. High addr. 15 8 7 0 PC 3.3.3 Table indirect addressing [Function] The table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH. [Illustration] Instruction code 7 6 0 1 5 1 ta4-0 0 15 Effective address 0 7 0 0 0 0 0 0 Memory (Table) 0 8 7 6 0 0 1 5 1 0 0 0 Low addr. High addr. Effective address + 1 15 8 7 0 PC Preliminary User's Manual U16898EJ1V0UD 37 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 A 15 0 7 X 8 7 PC 38 Preliminary User's Manual U16898EJ1V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP Code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (low) addr16 (high) Memory Preliminary User's Manual U16898EJ1V0UD 39 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal highspeed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to FF1FH. The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. [Operand format] Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data (even address only) [Description example] MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] 7 0 OP code saddr-offset Short direct memory 15 Effective address 1 8 1 1 1 1 1 1 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. 40 Preliminary User's Manual U16898EJ1V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH are accessed with short direct addressing. [Operand format] Identifier Description sfr Special function register name [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 0 OP code sfr-offset SFR 15 Effective address 1 8 7 1 1 1 1 1 1 0 1 Preliminary User's Manual U16898EJ1V0UD 41 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL `r' and `rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specify code INCW DE; When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code 42 Preliminary User's Manual U16898EJ1V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [DE], [HL] [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 D DE 0 8 7 E 7 0 Memory address specified by register pair DE The contents of addressed memory are transferred 7 0 A Preliminary User's Manual U16898EJ1V0UD 43 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [HL+byte] [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only. [Description example] In the case of PUSH DE Instruction code 44 1 0 1 0 1 0 Preliminary User's Manual U16898EJ1V0UD 1 0 CHAPTER 4 PORT FUNCTIONS 4.1 Functions of Ports The 78K0S/KA1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Functions P40 P20 Port 2 Port 4 P23 P45 P121 P30 P31 P34 Port 3 Port 12 P123 Port 13 P130 Preliminary User's Manual U16898EJ1V0UD 45 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name I/O Function After Reset AlternateFunction Pin P20 to P23 I/O Port 2. Input ANI0 to ANI3 Input TI000/INTP0 4-bit I/O port. Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected by setting software. I/O P30 Can be set to input or output mode in 1- Port 3 bit units. P31 TI010/TO00/ On-chip pull-up resistor can be connected by setting software. P34 Input P40 I/O Input only INTP2 Input Port 4. INTP3 Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected setting software. P42 - Input 6-bit I/O port. P41 RESET TOH1 P43 TxD6/INTP1 P44 RxD6 - P45 P121 I/O Port 12. Input 3-bit I/O port. P122 X2 Can be set to input or output mode in 1-bit units. P123 - On-chip pull-up resistor can be connected only to P123 by setting software. P130 Output Port 13. X1 Output - 1-bit output-only port. Remarks 1. P121 and P122 can be allocated when the high-speed Ring-OSC is selected as the system clock. 2. P121 can be allocated when an external clock is selected as the system clock. 4.2 Port Configuration Ports consist of the following hardware units. Table 4-2. Configuration of Ports Item Control registers Configuration Port mode registers (PM2, PM3, PM4, PM12) Port mode control register 2 (PMC2) Port registers (P2, P3, P4, P12, P13) Pull-up resistor option registers (PU2, PU3, PU4, PU12) Ports Total: 17 (CMOS I/O: 15, CMOS input: 1, CMOS output: 1) Pull-up resistor Total: 13 46 Preliminary User's Manual U16898EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 2 Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2). This port is also used as the analog input pins of the internal A/D converter. Reset input sets port 2 to the input mode. Figure 4-2 shows the block diagram of port 2. Figure 4-2. Block Diagram of P20 to P23 VDD WRPU PU2 PU20 to PU23 P-ch PMC2 PMC20 to PMC23 Selector Internal bus RD WRPORT Output latch (P20 to P23) P20/ANI0 to P23/ANI3 WRPM PM2 PM20 to PM23 A/D converter PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 RD: Read signal WRxx: Write signal Preliminary User's Manual U16898EJ1V0UD 47 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 3 Pins P30 and P31 constitute a 2-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). When the P30 to P31 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3). This port is also used as external interrupt request input pins. The P34 pin is a 1-bit input-only port and functions alternately as the RESET pin. Reset input sets port 3 to the input mode. Figures 4-3 and 4-4 show the block diagrams of port 3. Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. If a low level is input to the RESET pin before the option byte is referenced again after reset is released by the POC circuit, the 78K0S/KA1+ is reset and is held in the reset state until a high level is input to the RESET pin. Figure 4-3. Block Diagram of P30 and P31 VDD WRPU PU3 PU30, PU31 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P30, P31) P30/TI000/INTP0, P31/TI010/TO00/INTP2 WRPM PM3 PM30, PM31 Alternate function PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal 48 Preliminary User's Manual U16898EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P34 Internal bus RD P34/RESET Reset Option byte RD: 4.2.3 Read signal Port 4 Port 4 is a 6-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). When the P40 to P45 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 4 (PU4). Alternate functions include external interrupt request input, serial interface data I/O, and timer output. Reset input sets port 4 to the input mode. Figures 4-5 to 4-8 show the block diagrams of port 4. Preliminary User's Manual U16898EJ1V0UD 49 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P40 and P45 VDD WRPU PU4 PU40, PU45 P-ch Selector Internal bus RD WRPORT Output latch (P40, P45) P40, P45 WRPM PM4 PM40, PM45 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal 50 Preliminary User's Manual U16898EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P41 and P44 VDD WRPU PU4 PU41, PU44 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P41, P44) P41/INTP3, P44/RxD6 WRPM PM4 PM41, PM44 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal Preliminary User's Manual U16898EJ1V0UD 51 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P42 VDD WRPU PU4 PU42 P-ch Selector Internal bus RD WRPORT Output latch (P42) P42/TOH1 WRPM PM4 PM42 Alternate function PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal 52 Preliminary User's Manual U16898EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P43 VDD WRPU PU4 PU43 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P43) P43/Tx6/INTP1 WRPM PM4 PM43 Alternate function PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal Preliminary User's Manual U16898EJ1V0UD 53 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 12 Port 12 is a 3-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). When the P123 pin is used as an input port, an on-chip pull-up resistor can be connected by using pull-up resistor option register 12 (PU12). Reset input sets port 12 to the input mode. The P121 and P122 pins are also used as the X1 and X2 pins of the system clock oscillator. The functions of the P121 and P122 pins differ, therefore, depending on the selected system clock oscillator. The following three system clock oscillators can be used. (1) High-speed Ring-OSC circuit The P121 and P122 pins can be used as I/O port pins. (2) Crystal/ceramic oscillator The P121 and P122 pins cannot be used as I/O port pins because they are used as the X1 and X2 pins. (3) External clock input The P121 pin is used as the X1 pin to input an external clock, and therefore it cannot be used as an I/O port pin. The P122 pin can be used as an I/O port pin. The system clock oscillation is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Figures 4-9 to 4-10 show the block diagrams of port 12. Figure 4-9. Block Diagram of P121 and P122 Selector Internal bus RD WRPORT Output latch (P121, P122) P121/X1, P122/X2 WRPM PM12 PM121, PM122 Clock input PM12: Port mode register 12 RD: Read signal WRxx: Write signal 54 Preliminary User's Manual U16898EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P123 VDD WRPU PU12 PU123 P-ch Selector Internal bus RD WRPORT Output latch (P123) P123 WRPM PM12 PM123 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WRxx: Write signal Preliminary User's Manual U16898EJ1V0UD 55 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 13 This is a 1-bit output-only port. Figure 4-11 shows the block diagram of port 13. Figure 4-11. Block Diagram of P130 Internal bus RD WRPORT Output latch (P130) RD: P130 Read signal WRxx: Write signal Remark When a reset is input, P130 outputs a low level. If P130 outputs a high level immediately after reset is released, the output signal of P130 can be used as a dummy CPU reset signal. 4.3 Registers Controlling Port Functions The ports are controlled by the following four types of registers. * Port mode registers (PM2, PM3, PM4, PM12) * Port registers (P2, P3, P4, P12, P13) * Port mode control register 2 (PMC2) * Pull-up resistor option registers (PU2, PU3, PU4, PU12) (1) Port mode registers (PM2, PM3, PM4, PM12) These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets these registers to FFH. When a port pin is used as an alternate-function pin, set its port mode register and output latch as shown in Table 4-3. Caution Because P30, P31, and P43 are also used as external interrupt pins, the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. To use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. 56 Preliminary User's Manual U16898EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-12. Format of Port Mode Register Address: FF22H, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 Address: FF23H, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 1 1 PM31 PM30 Address: FF24H, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40 Address: FF2CH, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0 PM12 1 1 1 1 PM123 PM122 PM121 1 PMmn Selection of I/O mode of Pmn pin (m = 2, 3, 4, or 12; n = 0 to 7) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) (2) Port registers (P2, P3, P4, P12, P13) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read in the input mode, and the value of the output latch of the port is read in the output mode. P20 to P23, P30, P31, P34, P40 to P45, P121 to P123, and P130 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset input sets these registers to 00H. Preliminary User's Manual U16898EJ1V0UD 57 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Format of Port Register Address: FF02H, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P2 0 0 0 0 P23 P22 P21 P20 Address: FF03H, After reset: 00H Note (Output latch) R/W Note Symbol 7 6 5 4 3 2 1 0 P3 0 0 0 P34 0 0 P31 P30 Address: FF04H, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P4 0 0 P45 P44 P43 P42 P41 P40 Address: FF0CH, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P12 0 0 0 0 P123 P122 P121 0 Address: FF0DH, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0 P13 0 0 0 0 0 0 0 P130 Pmn m = 2, 3, 4, 12, or 13; n = 0-7 Controls of output data (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level Note Because P34 is read-only, its reset value is undefined. (3) Port mode control register 2 (PMC2) This register specifies the port mode or alternate function (A/D converter) of port 2. Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units. PMC2 is set by using a 1-bit or 8-bit memory manipulation instruction. Reset input sets PMC2 to 00H. 58 Preliminary User's Manual U16898EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Mode Control Register 2 Address: FF84H, After reset: R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode (n = 0 to 3) 0 Port mode 1 Alternate-function mode (A/D converter) Table 4-3. Setting of Port Mode Register, Port Register (Output Latch), and Port Mode Control Register When Alternate Function Is Used Pin Name Alternate-Function Pin PMxx Name Pxx PMC2n (n = 0 to 3) I/O P20 to P23 ANI0 to ANI3 Input 1 x 1 P30 TI000 Input 1 x - INTP0 Input 1 x - TO00 Output 0 0 - TI010 Input 1 x - INTP2 Input 1 x - P41 INTP3 Input 1 x - P42 TOH1 Output 0 0 - P43 TxD6 Output 0 1 - INTP1 Input 1 x - RxD6 Input 1 x - P31 P44 Remark x: don't care PMxx: Port mode register, Pxx: Port register (output latch of port) PMC2x: Port mode control register Preliminary User's Manual U16898EJ1V0UD 59 CHAPTER 4 PORT FUNCTIONS (4) Pull-up resistor option registers (PU2, PU3, PU4, PU12) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P30, P31, P40 to P45, and P123. By setting PU2, PU3, PU4, or PU12, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of PU2, PU3, PU4, or PU12. PU2, PU3, PU4, and PU12 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset input set these registers to 00H. Figure 4-15. Format of Pull-up Resistor Option Register Address: FF32H, After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU2 0 0 0 0 PU23 PU22 PU21 PU20 Address: FF33H, After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU3 0 0 0 0 0 0 PU31 PU30 Address: FF34H, After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU4 0 0 PU45 PU44 PU43 PU42 PU41 PU40 Address: FF3CH, After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PU12 0 0 0 0 PU123 0 0 0 PUmn 60 Selection of connection of on-chip pull-up resistor of Pmn (m = 2, 3, 4, or 12; n = 0 to 7) 0 Does not connect on-chip pull-up resistor 1 Connects on-chip pull-up resistor Preliminary User's Manual U16898EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.4 Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch by a transfer instruction. In addition, the contents of the output latch are output from the pin. Once data is written to the output latch, it is retained until new data is written to the output latch. Reset input cleans the data in the output latch. (2) In input mode A value can be written to the output latch by a transfer instruction. Because the output buffer is off, however, the pin status remains unchanged. Once data is written to the output latch, it is retained until new data is written to the output latch. 4.4.2 Reading from I/O port (1) In output mode The contents of the output latch can be read by a transfer instruction. The contents of the output latch remain unchanged. (2) In input mode The pin status can be read by a transfer instruction. The contents of the output latch remain unchanged. 4.4.3 Operations on I/O port (1) In output mode An operation is performed on the contents of the output latch and the result is written to the output latch. The contents of the output latch are output from the pin. Once data is written to the output latch, it is retained until new data is written to the output latch. Reset input clears the data in the output latch. (2) In input mode The pin level is read and an operation is performed on its contents. The operation result is written to the output latch. However, the pin status remains unchanged because the output buffer is off. Preliminary User's Manual U16898EJ1V0UD 61 CHAPTER 5 CLOCK GENERATORS 5.1 Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the watchdog timer and 8-bit timer H1 (TMH1). 5.1.1 System clock oscillators The following three types of system clock oscillators are used. * High-speed Ring-OSC oscillator This circuit internally oscillates a clock of 8 MHz (TYP.). Its oscillation can be stopped by execution of the STOP instruction. If the high-speed Ring-OSC oscillator is selected to supply the system clock, the X1 and X2 pins can be used as I/O port pins. * Crystal/ceramic oscillator This circuit oscillates a clock with a crystal/ceramic oscillator connected across the X1 and X2 pins. It can oscillate a clock of 500 kHz to 10 MHz. Oscillation of this circuit can be stopped by execution of the STOP instruction. * External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. A clock of 500 kHz to 10 MHz can be supplied. Internal clock supply can be stopped by execution of the STOP instruction. If the external clock input is selected as the system clock, the X2 pin can be used as an I/O port pin. The system clock source is selected by using the option byte. For details, refer to CHAPTER 17 OPTION BYTE. When using the X1 and X2 pins as I/O port pins, refer to CHAPTER 4 PORT FUNCTIONS for details. 5.1.2 Clock oscillator for interval time generation The following circuit is used as a clock oscillator for interval time generation. * Low-speed Ring-OSC oscillator This circuit oscillates a clock of 240 kHz (TYP.). Its oscillation can be stopped by using the low-speed Ring-OSC mode register (LSRCM) when it is specified by the option byte that its oscillation can be stopped by software. 62 Preliminary User's Manual U16898EJ1V0UD CHAPTER 5 CLOCK GENERATORS 5.2 Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Control registers Configuration Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed Ring-OSC mode register (LSRCM) High-speed Ring-OSC mode register (HSRCM) Oscillation stabilization time select register (OSTS) Oscillators Crystal/ceramic oscillator High-speed Ring-OSC oscillator External clock input circuit Low-speed Ring-OSC oscillator Preliminary User's Manual U16898EJ1V0UD 63 CHAPTER 5 CLOCK GENERATORS Figure 5-1. Block Diagram of Clock Generators Internal bus Oscillation stabilization time select register (OSTS) OSTS1 OSTS0 Preprocessor clock control register (PPCC) PPCC1 PPCC0 Processor clock control register (PCC) PCC1 System clock oscillation stabilization time counter CPU Controller STOP System clock oscillatorNote Crystal/ceramic oscillation fX 2 X2/P122 External clock input fX 22 fRH Selector High-speed Ring-OSC oscillation Prescaler fX Selector X1/P121 CPU clock (fCPU) fXP 22 fXP Prescaler Clock to peripheral hardware (fXP) Clock for flash memory self programming control Low-speed Ring-OSC oscillator fRL 8-bit timer H1, watchdog timer Option byte 1: Cannot be stopped. 0: Can be stopped. High-speed Ring-OSC is selected as system clock source HSRSTOP High-speed Ring-OSC mode register (HSRCM) LSRSTOP Low-speed Ring-OSC mode register (LSRCM) Internal bus Note Select the high-speed Ring-OSC oscillator, crystal/ceramic oscillator, or external clock input as the system clock source by using the option byte. 64 Preliminary User's Manual U16898EJ1V0UD CHAPTER 5 CLOCK GENERATORS 5.3 Registers Controlling Clock Generators The clock generators are controlled by the following five registers. * Processor clock control register (PCC) * Preprocessor clock control register (PPCC) * Low-speed Ring-OSC mode register (LSRCM) * High-speed Ring-OSC mode register (HSRCM) * Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) and pre-processor clock control register (PPCC) These registers are used to specify the division ratio of the system clock. PCC and PPCC are set by using a 1-bit or 8-bit memory manipulation instruction. Reset input sets PCC and PPCC to 02H. Figure 5-2. Format of Processor Clock Control Register (PCC) Address: FFFBH, After reset: 02H, R/W Symbol 7 6 5 4 3 2 1 0 PCC 0 0 0 0 0 0 PCC1 0 Figure 5-3. Format of Preprocessor Clock Control Register (PPCC) Address: FFF3H, After reset: 02H, R/W Symbol 7 6 5 4 3 2 1 0 PPCC 0 0 0 0 0 0 PPCC1 PPCC0 PPCC1 PPCC0 PCC1 0 0 0 fX 0 1 0 fX/2 0 0 1 fX/2 2 1 0 0 fX/2 2 Note 2 0 1 1 fX/2 3 Note 1 1 0 1 fX/2 4 Note 2 Other than above Selection of CPU clock (fCPU) Note 1 Setting prohibited Notes 1. If PPCC = 01H, the clock (fXP) supplied to the peripheral hardware is fX/2. 2. If PPCC = 02H, the clock (fXP) supplied to the peripheral hardware is fX/22. Preliminary User's Manual U16898EJ1V0UD 65 CHAPTER 5 CLOCK GENERATORS The fastest instruction of the 78K0S/KA1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Note Minimum Instruction Execution Time: 2/fCPU High-speed Ring-OSC clock (at 8.0 MHz (TYP.)) fX Crystal/ceramic oscillation clock or external clock input (at 10.0 MHz) 0.25 s 0.2 s 0.5 s 0.4 s fX/2 2 1.0 s 0.8 s fX/2 3 2.0 s 1.6 s fX/2 4 4.0 s 3.2 s fX/2 Note The CPU clock (high-speed Ring-OSC clock, crystal/ceramic oscillation clock, or external clock input) is selected by the option byte. (2) Low-speed Ring-OSC mode register (LSRCM) This register is used to select the operation mode of the low-speed Ring-OSC oscillator (240 kHz (TYP.)). This register is valid when it is specified by the option byte that the low-speed Ring-OSC oscillator can be stopped by software. If it is specified by the option byte that the low-speed Ring-OSC oscillator cannot be stopped by software, setting of this register is invalid, and the low-speed Ring-OSC oscillator continues oscillating. In addition, the source clock of WDT is fixed to the low-speed Ring-OSC oscillator. For details, refer to CHAPTER 9 WATCHDOG TIMER. LSRCM can be set by using an 8-bit memory manipulation instruction. Reset input sets LSRCM to 00H. Figure 5-4. Format of Low-Speed Ring-OSC Mode Register (LSRCM) Address: FF58H, After reset: 00H, R/W Symbol 7 6 5 4 3 2 1 0 LSRCM 0 0 0 0 0 0 0 LSRSTOP LSRSTOP Oscillation/stop of low-speed Ring-OSC 0 Low-speed Ring-OSC oscillates 1 Low-speed Ring-OSC stops (3) High-speed Ring-OSC mode register (HSRCM) This register is used to select the operation mode of the high-speed Ring-OSC oscillator that generates a clock (8 MHz (TYP.)) for controlling self programming of the flash memory. This register is valid when crystal/ceramic oscillation or external clock input is selected as the system clock source by the option byte. Setting of this register is invalid when the high-speed Ring-OSC oscillator is selected by the option byte. 66 Preliminary User's Manual U16898EJ1V0UD CHAPTER 5 CLOCK GENERATORS If crystal/ceramic oscillation or external clock input is selected as the system clock source, the high-speed RingOSC oscillator must be oscillated during self-programming of the flash memory. While self-programming is not executed, stop oscillation of the high-speed Ring-OSC oscillator to reduce the current consumption. For selfprogramming of the flash memory, refer to CHAPTER 18 FLASH MEMORY. HSRCM is set by using an 8-bit memory manipulation instruction. Reset input sets HSRCM to 00H. Figure 5-5. Format of High-Speed Ring-OSC Mode Register (HSRCM) Address: FF5AH, After reset: 00H, R/W Symbol 7 6 5 4 3 2 1 0 HSRCM 0 0 0 0 0 0 0 HSRSTOP HSRSTOP Oscillation/stops of high-speed Ring-OSC 0 High-speed Ring-OSC oscillates 1 High-speed Ring-OSC oscillates stops (4) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released. If the high-speed Ring-OSC oscillator or external clock input is selected as the system clock source, no wait time elapses. The system clock oscillator and the oscillation stabilization time that elapses after power application or release of reset are selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. OSTS is set by using an 8-bit memory manipulation instruction. Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFF4H, After reset: Undefined, R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 2 /fX102.4 s 0 1 2 /fX409.6 s 1 0 2 /fX3.27 ms 1 1 2 /fX13.1 ms 10 12 15 17 Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows. Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS 2. The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset input or interrupt generation. Preliminary User's Manual U16898EJ1V0UD 67 CHAPTER 5 CLOCK GENERATORS STOP mode is released Voltage waveform of X1 pin a Caution 3. The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Remarks 1. ( ): fX = 10 MHz 2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used. 5.4 System Clock Oscillators The following three types of system clock oscillators are available. * High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.). * Crystal/ceramic oscillator: Oscillates a clock of 500 kHz to 10 MHz. * External clock input circuit: Supplies a clock of 500 kHz to 10 MHz to the X1 pin. 5.4.1 High-speed Ring-OSC oscillator The 78K0S/KA1+ includes a high-speed Ring-OSC oscillator (8 MHz (TYP.)). If the high-speed Ring-OSC is selected by the option byte as the clock source, the X1 and X2 pins can be used as I/O port pins. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. 68 Preliminary User's Manual U16898EJ1V0UD CHAPTER 5 CLOCK GENERATORS 5.4.2 Crystal/ceramic oscillator The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2 pins. If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are used as crystal or ceramic resonator connection pins. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. Figure 5-7 shows the external circuit of the crystal/ceramic oscillator. Figure 5-7. External Circuit of Crystal/Ceramic Oscillator VSS X1 X2 Crystal resonator or ceramic resonator Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines in Figure 5-7 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Preliminary User's Manual U16898EJ1V0UD 69 CHAPTER 5 CLOCK GENERATORS Figure 5-8 shows examples of incorrect resonator connection. Figure 5-8. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORT VSS X1 X2 VSS (c) Wiring near high fluctuating current X1 X2 (d) Current flowing through ground line of oscillator (Potential at points A, B, and C fluctuates.) VDD PORT X1 X2 VSS X1 A B X2 High current VSS High current 70 Preliminary User's Manual U16898EJ1V0UD C CHAPTER 5 CLOCK GENERATORS Figure 5-8. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched VSS 5.4.3 X1 X2 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O port pin. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. Figure 5-9 shows an external circuit of the external clock input circuit. Figure 5-9. External Circuit of External Clock Input Circuit External clock 5.4.4 X1 Prescaler The prescaler divides the clock (fX) output by the system clock oscillator to generate a clock (fXP) to be supplied to the peripheral hardware. It also divides the clock to peripheral hardware (fXP) to generate a clock to be supplied to the CPU. Remark The clock output by the oscillator selected by the option byte (high-speed Ring-OSC oscillator, crystal/ceramic oscillator, or external clock input circuit) is divided. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. Preliminary User's Manual U16898EJ1V0UD 71 CHAPTER 5 CLOCK GENERATORS 5.5 Operation of CPU Clock Generator A clock (fCPU) is supplied to the CPU from the system clock (fX) oscillated by one of the following three types of oscillators. * High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.). * Crystal/ceramic oscillator: Oscillates a clock of 500 kHz to 10 MHz. * External clock input circuit: Supplies a clock of 500 kHz to 10 MHz to X1 pin. The system clock oscillator is selected by the option byte. For details of the option byte, refer to CHAPTER 17 OPTION BYTE. (1) High-speed Ring-OSC oscillator When the high-speed Ring-OSC oscillator is selected by the option byte, the following is possible. * Shortening of start time If the high-speed Ring-OSC oscillator is selected as the oscillator, the CPU can be started without having to wait for the oscillation stabilization time of the system clock. Therefore, the start time can be shortened. * Improvement of expandability If the high-speed Ring-OSC oscillator is selected as the oscillator, the X1 and X2 pins can be used as I/O port pins. For details, refer to CHAPTER 4 PORT FUNCTIONS. Figures 5-10 and 5-11 show the timing chart and status transition diagram of the default start by the high-speed Ring-OSC oscillator. Remark When the high-speed Ring-OSC oscillator is used, the clock accuracy is 5%. Figure 5-10. Timing Chart of Default Start by High-Speed Ring-OSC Oscillator (a) VDD RESET H Internal reset (b) System clock CPU clock High-speed Ring-OSC clock PCC = 02H, PPCC = 02H Option byte is read. System clock is selected. (Operation stops: 8/fRL + 96/fRH) Remark fRL: Low-speed Ring-OSC clock oscillation frequency fRH: High-speed Ring-OSC clock oscillation frequency 72 Preliminary User's Manual U16898EJ1V0UD CHAPTER 5 CLOCK GENERATORS (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the high-speed Ring-OSC clock operates as the system clock. Figure 5-11. Status Transition of Default Start by High-Speed Ring-OSC Power application VDD > 2.1 V 0.1 V Reset by power-on clear Reset signal High-speed Ring-OSC selected by option byte Start with PCC = 02H, PPCC = 02H Clock division ratio variable during CPU operation Interrupt Interrupt HALT instruction STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register (2) Crystal/ceramic oscillator If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 500 kHz to 10 MHz can be selected and the accuracy of processing is improved because the frequency deviation is small, as compared with high-speed Ring-OSC oscillation (8 MHz (TYP.)). Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by the crystal/ceramic oscillator. Preliminary User's Manual U16898EJ1V0UD 73 CHAPTER 5 CLOCK GENERATORS Figure 5-12. Timing Chart of Default Start by Crystal/Ceramic Oscillator (a) VDD RESET H Internal reset (b) System clock (c) Crystal/ceramic oscillator clock PCC = 02H, PPCC = 02H CPU clock Option byte is read. System clock is selected. (Operation stops: 8/fRL + 96/fRH) Clock oscillation stabilization timeNote Note The clock oscillation stabilization time for default start is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is released is selected by the oscillation stabilization time select register (OSTS). Remark fRL: Low-speed Ring-OSC clock oscillation frequency fRH: High-speed Ring-OSC clock oscillation frequency (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) After high-speed Ring-OSC clock is generated, the option byte is referenced and the system clock is selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock. (c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. 74 Preliminary User's Manual U16898EJ1V0UD CHAPTER 5 CLOCK GENERATORS Figure 5-13. Status Transition of Default Start by Crystal/Ceramic Oscillation Power application VDD > 2.1 V 0.1 V Reset by power-on clear Reset signal Crystal/ceramic oscillation selected by option byte Start with PCC = 02H, PPCC = 02H Wait for clock oscillation stabilization Clock division ratio variable during CPU operation Interrupt HALT instruction Interrupt STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register (3) External clock input circuit If external clock input is selected by the option byte, the following is possible. * High-speed operation The accuracy of processing is improved as compared with high-speed Ring-OSC oscillation (8 MHz (TYP.)) because an oscillation frequency of 500 kHz to 10 MHz can be selected and an external clock with a small frequency deviation can be supplied. * Improvement of expandability If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For details, refer to CHAPTER 4 PORT FUNCTIONS. Figures 5-14 and 5-15 show the timing chart and status transition diagram of default start by external clock input. Preliminary User's Manual U16898EJ1V0UD 75 CHAPTER 5 CLOCK GENERATORS Figure 5-14. Timing of Default Start by External Clock Input (a) VDD RESET H Internal reset (b) System clock External clock input PCC = 02H, PPCC = 02H CPU clock Option byte is read. System clock is selected. (Operation stops: 8/fRL + 96/fRH) Remark fRL: Low-speed Ring-OSC clock oscillation frequency fRH: High-speed Ring-OSC clock oscillation frequency (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the external clock operates as the system clock. Figure 5-15. Status Transition of Default Start by External Clock Input Power application VDD > 2.1 V 0.1 V Reset by power-on clear Reset signal External clock input selected by option byte Start with PCC = 02H, PPCC = 02H Clock division ratio variable during CPU operation Interrupt HALT instruction Interrupt STOP instruction HALT Remark PCC: STOP Processor clock control register PPCC: Preprocessor clock control register 76 Preliminary User's Manual U16898EJ1V0UD CHAPTER 5 CLOCK GENERATORS 5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. * Clock to peripheral hardware (fXP) * Low-speed Ring-OSC clock (fRL) (1) Clock to peripheral hardware The clock to the peripheral hardware is supplied by dividing the system clock (fX). The division ratio is selected by the pre-processor clock control register (PPCC). Three types of frequencies are selectable: "fX", "fX/2", and "fX/22". Table 5-3 lists the clocks supplied to the peripheral hardware. Table 5-3. Clocks to Peripheral Hardware PPCC1 PPCC0 Selection of clock to peripheral hardware (fXP) 0 0 fX 0 1 fX/2 1 0 fX/2 1 1 Setting prohibited 2 (2) Low-speed Ring-OSC clock The low-speed Ring-OSC oscillator of the clock oscillator for interval time generation is always started after release of reset, and oscillates at 240 kHz (TYP.). It can be specified by the option byte whether the low-speed Ring-OSC oscillator can or cannot be stopped by software. If it is specified that the low-speed Ring-OSC oscillator can be stopped by software, oscillation can be started or stopped by using the low-speed Ring-OSC mode register (LSRCM). If it is specified that it cannot be stopped by software, the clock source of WDT is fixed to the low-speed Ring-OSC clock (fRL). The low-speed Ring-OSC oscillator is independent of the CPU clock. If it is used as the source clock of WDT, therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-speed Ring-OSC oscillator is used as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status. Table 5-4 shows the operation status of the low-speed Ring-OSC oscillator when it is selected as the source clock of WDT and the count clock of 8-bit timer H1. Figure 5-16 shows the status transition of the low-speed Ring-OSC oscillator. Table 5-4. Operation Status of Low-Speed Ring-OSC Oscillator Option Byte Setting CPU Status Can be stopped by LSRSTOP = 1 software LSRSTOP = 0 LSRSTOP = 1 Operation mode Standby LSRSTOP = 0 Cannot be stopped Operation mode WDT Status TMH1 Status Stopped Stopped Operates Operates Stopped Stopped Stopped Operates Operates Standby Preliminary User's Manual U16898EJ1V0UD 77 CHAPTER 5 CLOCK GENERATORS Figure 5-16. Status Transition of Low-Speed Ring-OSC Oscillator Power application VDD > 2.1 V 0.1 V Reset by power-on clear Reset signal Select by option byte if low-speed Ring-OSC can be stopped or not Can be stopped Cannot be stopped Clock source of WDT is selected by softwareNote Clock source of WDT is fixed to fRL Low-speed Ring-OSC oscillator can be stopped Low-speed Ring-OSC oscillator cannot be stopped LSRSTOP = 1 LSRSTOP = 0 Low-speed Ring-OSC oscillator stops Note The clock source of the watchdog timer (WDT) is selected from fXP or fRL, or it may be stopped. For details, refer to CHAPTER 9 WATCHDOG TIMER. 78 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. * Number of counts: 2 to 65536 (2) External event counter 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of a signal input externally. * Valid level pulse width: 16/fXP or more (3) Pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. * Valid level pulse width: 2/fXP or more (4) Square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. * Cycle: (2 x 2 to 65536 x 2) x count clock cycle (5) PPG output 16-bit timer/event counter 00 can output a square wave that have arbitrary cycle and pulse width. * 2 < Pulse width < Cycle (FFFF + 1) H (6) One-shot pulse output 16-bit timer/event counter 00 can output a one-shot pulse for which output pulse width can be set to any desired value. Preliminary User's Manual U16898EJ1V0UD 79 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Timer counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010 Timer output TO00, output controller Control registers 16-bit timer mode control register 00 (TMC00) Capture/compare control register 00 (CRC00) 16-bit timer output control register 00 (TOC00) Prescaler mode register 00 (PRM00) Port mode register 3 (PM3) Port register 3 (P3) Figures 6-1 shows a block diagram of these counters. Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) TI010/TO00/ INTP2/P31 Selector Noise eliminator Selector CRC002CRC001 CRC000 16-bit timer capture/compare register 000 (CR000) INTTM000 Match Noise eliminator 16-bit timer counter 00 (TM00) Output controller TO00/TI010/ INTP2/P31 Match 2 Output latch (P31) Noise eliminator TI000/INTP0/P30 Clear PM31 16-bit timer capture/compare register 010 (CR010) Selector fX Selector fXP fXP/22 fXP/28 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) 80 TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00) Address: FF12H, FF13H Symbol After reset: 0000H R FF13H FF12H TM00 The count value is reset to 0000H in the following cases. <1> At reset input <2> If TMC003 and TMC002 are cleared <3> If the valid edge of TI000 is input in the clear & start mode entered by inputting the valid edge of TI000 <4> If TM00 and CR000 match in the clear & start mode entered on a match between TM00 and CR000 <5> If OSPT00 is set in the one-shot pulse output mode (2) 16-bit timer capture/compare register 000 (CR000) CR000 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control register 00 (CRC00). CR000 is set by 16-bit memory manipulation instruction. A reset clears CR000 to 0000H. Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000) Address: FF14H, FF15H Symbol After reset: 0000H R/W FF15H FF14H CR000 * When CR000 is used as a compare register The value set in CR000 is constantly compared with the 16-bit timer/counter 00 (TM00) count value, and an interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the interval time then TM00 is set to interval timer operation. * When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 62). Preliminary User's Manual U16898EJ1V0UD 81 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Rising edge 0 1 Rising edge Falling edge 0 0 No capture operation Both rising and falling edges 1 1 (2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1) CR000 Capture Trigger TI010 Pin Valid Edge ES110 ES100 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited. 2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) ES110, ES100: Bits 7 and 6 of prescaler mode register 00 (PRM00) CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00) Cautions 1. Set CR000 to a value other than 0000H in the clear & start mode entered on a match between TM00 and CR000. However, in the free-running mode and in the clear & start mode using the valid edge of TI000, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H following overflow (FFFFH). 2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR000 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR000 is changed. 3. When P31 is used as the input pin for the valid edge of TI010, it cannot be used as a timer output (TO00). Moreover, when P31 is used as TO00, it cannot be used as the input pin for the valid edge of TI010. 4. If the register read period and the input of the capture trigger conflict when CR000 is used as a capture register, the read data is undefined (the capture data itself is a normal value). Also, if the count stop input and the input of the capture trigger conflict, the capture trigger is undefined. 5. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (11) Changing compare register during timer operation. 82 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00). CR010 is set by 16-bit memory manipulation instruction. Reset input clears CR010 to 0000H. Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010) Address: FF16H, FF17H Symbol After reset: 0000H R/W FF17H FF16H CR010 * When CR010 is used as a compare register The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an interrupt request (INTTM010) is generated if they match. * When CR010 is used as a capture register It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by means of prescaler mode register 00 (PRM00) (refer to Table 6-3). Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1) CR010 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited. 2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) CRC002: Bit 2 of capture/compare control register 00 (CRC00) Cautions 1. Set CR010 to other than 0000H in the clear & start mode entered on a match between TM00 and CR000. However, in the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010 changes from 0000H to 0001H following overflow (FFFFH). 2. If the register read period and the input of the capture trigger conflict when CR010 is used as a capture register, the read data is undefined (the capture data itself is a normal value). Also, if the count stop input and the input of the capture trigger conflict, the capture data is undefined. 3 Changing the CR010 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (11) Changing compare register during timer operation. Preliminary User's Manual U16898EJ1V0UD 83 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers to Control 16-Bit Timer/Event Counter 00 The following six types of registers are used to control 16-bit timer/event counter 00. * 16-bit timer mode control register 00 (TMC00) * Capture/compare control register 00 (CRC00) * 16-bit timer output control register 00 (TOC00) * Prescaler mode register 00 (PRM00) * Port mode register 3 (PM3) * Port register 3 (P3) (1) 16-bit timer mode control register 00 (TMC00) This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output timing, and detects an overflow. TMC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of TMC00 to 00H. Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation. 84 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H Symbol 7 6 5 4 TMC00 0 0 0 0 R/W 3 2 1 <0> TMC003 TMC002 TMC001 OVF00 Operating mode and clear TMC003 TMC002 TMC001 TO00 inversion timing selection Interrupt request generation mode selection 0 0 0 Operation stop 0 0 1 (TM00 cleared to 0) 0 1 0 Free-running mode 0 1 No change Not generated Match between TM00 and Generated on match between CR000 or match between TM00 and CR000, or match TM00 and CR010 between TM00 and CR010 Match between TM00 and 1 CR000, match between TM00 and CR010 or TI000 valid edge 1 0 0 Clear & start occurs on valid - 1 0 1 edge of TI000 pin 1 1 0 Clear & start occurs on match Match between TM00 and between TM00 and CR000 CR000 or match between TM00 and CR010 1 1 Match between TM00 and 1 CR000, match between TM00 and CR010 or TI000 valid edge OVF00 Overflow detection of 16-bit timer counter 00 (TM00) 0 Overflow not detected 1 Overflow detected Cautions 1. To write different data to TMC00, stop the timer operation before writing. 2. The timer operation must be stopped before writing to bits other than the OVF00 flag. 3. Set the valid edge of the TI000/INTP0/P30 pin with prescaler mode register 00 (PRM00). 4. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at the valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1. Remark TM00: 16-bit timer counter 00 CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010 Preliminary User's Manual U16898EJ1V0UD 85 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of CRC00 to 00H. Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00) Address: FF62H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CRC00 0 0 0 0 0 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection 0 Operate as compare register 1 Operate as capture register CRC001 CR000 capture trigger selection 0 Capture on valid edge of TI010 pin 1 Capture on valid edge of TI000 pin by reverse phase CRC000 CR000 operating mode selection 0 Operate as compare register 1 Operate as capture register Cautions 1. The timer operation must be stopped before setting CRC00. 2. When the clear & start mode entered on a match between TM00 and CR000 is selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register. 3. If both the rising and falling edges have been selected as the valid edges of the TI000 pin, capture is not performed. 4. To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00) (refer to Figure 6-17). 86 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and output trigger of one-shot pulse by software. TOC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of TOC00 to 00H. Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FF63H After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software 0 No one-shot pulse trigger 1 One-shot pulse trigger OSPE00 One-shot pulse output operation control 0 Successive pulse output mode 1 One-shot pulse output mode TOC004 Note Timer output F/F control using match of CR010 and TM00 0 Disables inversion operation 1 Enables inversion operation LVS00 LVR00 0 0 No change Timer output F/F status setting 0 1 Timer output F/F reset (0) 1 0 Timer output F/F set (1) 1 1 Setting prohibited TOC001 Timer output F/F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE00 Timer output control 0 Disables output (output fixed to level 0) 1 Enables output Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur. Cautions 1. Timer operation must be stopped before setting other than OSPT00. 2. If LVS00 and LVR00 are read, 0 is read. 3. OSPT00 is automatically cleared after data is set, so 0 is read. 4. Do not set OSPT00 to 1 other than in one-shot pulse output mode. 5. A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required to write to OSPT00 successively. Preliminary User's Manual U16898EJ1V0UD 87 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges. PRM00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of PRM00 to 00H. Figure 6-8. Format of Prescaler Mode Register 00 (PRM00) Address: FF61H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PRM00 ES110 ES100 ES010 ES000 0 0 PRM001 PRM000 ES110 ES100 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES010 ES000 0 0 Falling edge 0 1 Rising edge TI010 pin valid edge selection TI000 pin valid edge selection 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 0 0 fXP (10 MHz) 0 1 fXP/2 (2.5 MHz) 1 0 fXP/2 (39.06 kHz) 1 1 TI000 pin valid edge Count clock selection 2 8 Note Note The external clock requires a pulse longer than two cycles of the internal count clock (fXP). Cautions 1. Always set data to PRM00 after stopping the timer operation. 2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin. 3. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00). Be careful when pulling up the TI000 pin or the TI010 pin. However, when re-enabling operation after the operation has been stopped once, the rising edge is not detected. 4. When using P31 as the input pin of the TI010 pin valid edge, it cannot be used as a timer output (TO00). When using P31 as the TO00 pin, it cannot be used as the input pin of the TI010 pin valid edge. Remarks 1. fXP: Oscillation frequency of clock supplied to peripheral hardware 2. ( ): fXP = 10 MHz 88 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO00/TI010/INTP2 pin for timer output, set PM31 and the output latch of P31 to 0. When using the P30/TI000/INTP0 and P31/TO00/TI010/INTP2 pins as a timer input, set PM30 and PM31 to 1. At this time, the output latches of P30 and P31 can be either 0 or 1. PM3 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of PM3 to FFH. Figure 6-9. Format of Port Mode Register 3 (PM3) Address: FF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 PM3 1 1 1 1 1 1 PM3n 1 0 PM31 PM30 P3n pin I/O mode selection (n = 0 or 1) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U16898EJ1V0UD 89 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an interval timer. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-10 for the set value). <2> Set any value to the CR000 register. <3> Set the count clock by using the PRM00 register. <4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value). Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (11) Changing compare register during timer operation. Remark For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. Interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 000 (CR000) beforehand as the interval. When the count value of 16-bit timer counter 00 (TM00) matches the value set to CR000, counting continues with the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated. The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). 90 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0/1 0 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (c) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details. Preliminary User's Manual U16898EJ1V0UD 91 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-11. Interval Timer Configuration Diagram 16-bit timer capture/compare register 000 (CR000) INTTM000 Selector fXP fXP/22 fXP/28 Note 16-bit timer counter 00 (TM00) OVF00 Noise eliminator TI000/INTP0/P30 Clear circuit fXP Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. Figure 6-12. Timing of Interval Timer Operation t Count clock TM00 count value 0000H 0001H N Timer operation enabled CR000 0000H 0001H N Clear N 0000H 0001H N Clear N N N INTTM000 Interrupt acknowledged Remark Interrupt acknowledged Interval time = (N + 1) x t N = 0001H to FFFFH When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N) before the change, it is necessary to restart the timer after changing CR000. Figure 6-13. Timing After Change of Compare Register During Timer Count Operation Count clock N CR000 TM00 count value Remark 92 X-1 M X FFFFH N>X>M Preliminary User's Manual U16898EJ1V0UD 0000H 0001H 0002H CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-14 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set any value to the CR000 register (0000H cannot be set). <4> Set the TMC00 register to start the operation (see Figure 6-14 for the set value). Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated. Input a value other than 0000H to CR000. (A count operation with a pulse cannot be carried out.) The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00). Because an operation is carried out only when the valid edge of the TI000 pin is detected twice after sampling with the internal clock (fXP), noise with a short pulse width can be removed. Preliminary User's Manual U16898EJ1V0UD 93 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0/1 0 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (c) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 1 1 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details. 94 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. External Event Counter Configuration Diagram Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear fXP 16-bit timer counter 00 (TM00) Noise eliminator OVF00Note Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. Figure 6-16. External Event Counter Operation Timing (with Rising Edge Specified) TI000 pin input TM00 count value CR000 0000H 0001H 0002H 0003H 0004H 0005H N-1 N 0000H 0001H 0002H 0003H N INTTM000 Caution When reading the external event counter count value, TM00 should be read. Preliminary User's Manual U16898EJ1V0UD 95 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin. When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-17. CR010 Capture Operation with Rising Edge Specified Count clock TM00 N-3 N-2 N-1 N N+1 TI000 Rising edge detection N CR010 INTTM010 Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set the TMC00 register to start the operation (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value). Caution To use two capture registers, set the TI000 and TI010 pins. Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 12 FUNCTIONS. 96 Preliminary User's Manual U16898EJ1V0UD INTERRUPT CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set. Specify both the rising and falling edges by using bits 4 and 5 (ES000 and ES010) of PRM00. Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-18. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR010 Are Used) (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 0/1 0 CR000 used as compare register CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES010 ES000 PRM00 0/1 0/1 1 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. Preliminary User's Manual U16898EJ1V0UD 97 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter fXP/22 fXP/2 6 Selector fXP 16-bit timer/counter 00 (TM00) OVF00 16-bit timer capture/compare register 010 (CR010) TI000/INTP0/P30 INTTM010 Internal bus Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 TI000 pin input CR010 capture value D0 D1 D2 D3 INTTM010 Note OVF00 (D1 - D0) x t (10000H - D1 + D2) x t Note OVF00 must be cleared by software. 98 Preliminary User's Manual U16898EJ1V0UD (D3 - D2) x t CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the edge specified by bits 6 and 7 (ES100 and ES110) of PRM00 is input to the TI010 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal (INTTM000) is set. Specify both the rising and falling edges as the edges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000 and ES010) and bits 6 and 7 (ES100 and ES110) of PRM00. Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-21. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 0 1 CR000 used as capture register Captures valid edge of TI010 pin to CR000. CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 1 1 1 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Specifies both edges for pulse width detection. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. Preliminary User's Manual U16898EJ1V0UD 99 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 TI000 pin input CR010 capture value D0 D2 D1 INTTM010 TI010 pin input CR000 capture value D1 D2 + 1 INTTM000 Note OVF00 (D1 - D0) x t (10000H - D1 + D2) x t (10000H - D1 + (D2 + 1)) x t Note OVF00 must be cleared by software. 100 Preliminary User's Manual U16898EJ1V0UD (D3 - D2) x t CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. When the rising or falling edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000). Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-23. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000. CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. Preliminary User's Manual U16898EJ1V0UD 101 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 TI000 pin input CR010 capture value D0 CR000 capture value D2 D1 D3 INTTM010 Note OVF00 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t Note OVF00 must be cleared by software. (4) Pulse width measurement by means of restart When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer/counter 00 (TM00) is taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count. The edge specification can be selected from two types, rising or falling edges, by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) Sampling is performed at the interval selected by prescaler mode register 00 (PRM00) and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Caution If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare register 000 (CR000) cannot perform the capture operation. 102 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 0 0/1 0 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000. CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0 1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Figure 6-26. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H TI000 pin input CR010 capture value D2 D0 D1 CR000 capture value INTTM010 D1 x t D2 x t Preliminary User's Manual U16898EJ1V0UD 103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-27 for the set value). <3> Set the TOC00 register (see Figure 6-27 for the set value). <4> Set any value to the CR000 register (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figure 6-27 for the set value). Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (11) Changing compare register during timer operation. Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 000 (CR000). The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 + 1 by setting bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave with any selected frequency to be output. Figure 6-27. Control Register Settings in Square-Wave Output Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0 0 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register 104 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 0 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited). Does not invert output on match between TM00 and CR010. Disables one-shot pulse output. (d) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details. Figure 6-28. Square-Wave Output Operation Timing Count clock TM00 count value CR000 0000H 0001H 0002H N-1 N 0000H 0001H 0002H N-1 N 0000H N INTTM000 TO00 pin output Preliminary User's Manual U16898EJ1V0UD 105 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-29 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-29 for the set value). <2> Set any value to the CR000 register as the cycle. <3> Set any value to the CR010 register as the duty factor. <4> Set the TOC00 register (see Figure 6-29 for the set value). <5> Set the count clock by using the PRM00 register. <6> Set the TMC00 register to start the operation (see Figure 6-29 for the set value). Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (11) Changing compare register during timer operation. Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. 3. n = 0 or 1 In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer capture/compare register 000 (CR000), respectively. 106 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 OVF00 1 1 0 0 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0 x 0 CR000 used as compare register CR010 used as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 0 0 1 0/1 0/1 1 1 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited). Inverts output on match between TM00 and CR010. Disables one-shot pulse output. (d) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 3 2 0 0 PRM001 PRM000 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Cautions 1. Values in the following range should be set in CR000 and CR010: 0000H CR010 < CR000 FFFFH (Setting CR000 to 0000H is prohibited.) 2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). Remark x: Don't care Preliminary User's Manual U16898EJ1V0UD 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Selector fXP fXP/22 fXP/28 Noise eliminator Output controller TI000/INTP0/P30 Clear circuit 16-bit timer counter 00 (TM00) fXP 16-bit timer capture/compare register 010 (CR010) Figure 6-31. PPG Output Operation Timing t Count clock TM00 count value N 0000H 0001H M-1 M N-1 Clear CR000 capture value N CR010 capture value M Pulse width: (M + 1) x t 1 cycle: (N + 1) x t 108 0000H 0001H Clear TO00 Remark N 0000H M < N FFFFH Preliminary User's Manual U16898EJ1V0UD TO00/TI010/ INTP2/P31 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figures 6-32 and 6-34 for the set value). <3> Set the TOC00 register (see Figures 6-32 and 6-34 for the set value). <4> Set any value to the CR000 and CR010 registers (0000H cannot be set). <5> Set the TMC00 register to start the operation (see Figures 6-32 and 6-34 for the set value). Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-32, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software. By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000 (CR000)Note. Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00 register, the TMC003 and TMC002 bits of the TMC00 register must be cleared to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Do not set N to M. Cautions 1. Do not set the OSPT00 bit while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. 2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. Preliminary User's Manual U16898EJ1V0UD 109 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 TMC003 0 0 0 0 0 TMC002 TMC001 1 OVF00 0 0 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0 0/1 0 CR000 as compare register CR010 as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 LVS00 LVR00 TOC001 TOE00 0/1 0/1 1 1 1 Enables TO00 output. Inverts output upon match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010. Sets one-shot pulse output mode. Set to 1 for output. (d) Prescaler mode register 00 (PRM00) PRM00 ES110 ES100 ES010 ES000 3 2 0/1 0/1 0/1 0/1 0 0 PRM001 PRM010 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Caution Do not set 0000H to the CR000 and CR010 registers. 110 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 0CH (TM00 count starts) Count clock TM00 count 0000H 0001H N N+1 0000H N-1 N M-1 M M+1 M+2 CR010 set value N N N N CR000 set value M M M M OSPT00 INTTM010 INTTM000 TO00 pin output Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC003 and TMC002 bits. Remark N<M (2) One-shot pulse output with external trigger A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00), capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in Figure 6-34, and by using the valid edge of the TI000 pin as an external trigger. The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES010) of prescaler mode register 00 (PRM00). The rising, falling, or both the rising and falling edges can be specified. When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 000 (CR000)Note. Note The case where N < M is described here. When N > M, the output becomes active with the CR000 register and inactive with the CR010 register. Do not set N to M. Caution Even if the external trigger is generated again while the one-shot pulse is output, it is ignored. Preliminary User's Manual U16898EJ1V0UD 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC00 7 6 5 4 0 0 0 0 TMC003 TMC002 TMC001 1 0 OVF00 0 0 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC00 7 6 5 4 3 0 0 0 0 0 CRC002 CRC001 CRC000 0 0/1 0 CR000 used as compare register CR010 used as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 1 LVS00 LVR00 TOC001 TOE00 0/1 0/1 1 1 Enables TO00 output. Inverts output upon match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010. Sets one-shot pulse output mode. (d) Prescaler mode register 00 (PRM00) PRM00 ES110 ES100 ES010 ES000 3 2 0/1 0/1 0 1 0 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies the rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Caution Do not set 0000H to the CR000 and CR010 registers. 112 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H 0000H N N+1 N+2 M-2 M-1 M M+1 M+2 CR010 set value N N N N CR000 set value M M M M TI000 pin input INTTM010 INTTM000 TO00 pin output Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC002 and TMC003 bits. Remark N<M Preliminary User's Manual U16898EJ1V0UD 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock. Figure 6-36. Start Timing of 16-Bit Timer Counter 00 (TM00) Count clock 0000H TM00 count value 0001H 0002H 0003H 0004H Timer start (2) 16-Bit timer capture/compare register setting Set 16-bit timer capture/compare register 000 (CR000) to other than 0000H in the clear & start mode entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be performed when this register is used as an external event counter. (3) Capture register data retention The values of 16-bit timer capture/compare registers 000, 010 (CR000, CR010) after 16-bit timer/event counter 00 has stopped are not guaranteed. (4) Valid edge setting Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and TMC003) of 16-bit timer mode control register 00 (TMC00) to 0, 0, respectively, and then stopping the timer operation. The valid edge is set by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00). (5) Re-triggering one-shot pulse (a) One-shot pulse output by software When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not output the one-shot pulse again until INTTM000, which occurs upon a match with the CR000 register, or INTTM010, which occurs upon a match with the CR010 register, occurs. (b) One-shot pulse output with external trigger If the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) One-shot pulse output function When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the TI000 pin or its alternate function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. 114 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (6) Operation of OVF00 flag <1> The OVF00 flag is also set to 1 in the following case. Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid edge of the TI000 pin, or free-running mode is selected. CR000 is set to FFFFH. When TM00 is counted up from FFFFH to 0000H. Figure 6-37. Operation Timing of OVF00 Flag Count clock CR000 FFFFH TM00 FFFEH FFFFH 0000H 0001H OVF00 INTTM000 <2> Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is reset newly and clear is disabled. (7) Conflicting operations <1> When the 16-bit timer capture/compare register (CR000/CR010) is used as a compare register, if the write period and the match timing of 16-bit timer counter 00 (TM00) conflict, match determination is not successfully done. Do not perform a write operation of CR000/CR010 near the match timing. When performing a write operation, refer to (11) Changing compare register during timer operation. <2> If the read period and capture trigger input conflict when CR000/CR010 is used as a capture register, capture trigger input has priority. The data read from CR000/CR010 is undefined. Figure 6-38. Capture Register Data Retention Timing Count clock TM00 count value N N+1 N+2 M M+1 M+2 Edge input INTTM010 Capture read signal CR010 capture value X N+2 Capture Preliminary User's Manual U16898EJ1V0UD M+1 Capture, but read value is not guaranteed 115 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (8) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <2> Regardless of the CPU's operation mode, when the timer stops, the signals input to pins TI000/TI010 are not acknowledged. <3> One-shot pulse output normally operates only in the free-running mode or in the clear & start mode at the valid edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a match between TM00 and CR000, one-shot pulse output is not possible. (9) Capture operation <1> If the TI000 pin is specified as the valid edge of the count clock, a capture operation by the capture register specified as the trigger for the TI000 pin is not possible. <2> If both the rising and falling edges are selected as the valid edges of the TI000 pin, capture is not performed. <3> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00). <4> The capture operation is performed at the fall of the count clock. A interrupt request input (INTTM0n0), however, occurs at the rise of the next count clock. Remark n = 0, 1 (10) Compare operation The capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger is input. (11) Changing compare register during timer operation <1> When changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during timer counting, follow the procedure below using an INTTM000 interrupt. <Changing cycle (CR000)> 1. Disable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 0). 2. Disable the INTTM000 interrupt (TMMK000 = 1). 3. Rewrite CR000. 4. Wait for 1 cycle of the TM00 count clock. 5. Enable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 1). 6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0). 7. Enable the INTTM000 interrupt (TMMK000 = 0). 116 Preliminary User's Manual U16898EJ1V0UD CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 <Changing duty (CR010)> 1. Disable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 0). 2. Disable the INTTM000 interrupt (TMMK000 = 1). 3. Rewrite CR010. 4. Wait for 1 cycle of the TM00 count clock. 5. Enable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 1). 6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0). 7. Enable the INTTM000 interrupt (TMMK000 = 0). While interrupts and timer output inversion are disabled (1 to 4 above), timer counting is continued. If the value to be set in CR0n0 is small, the value of TM00 may exceed CR0n0. Therefore, set the value, considering the time lapse of the timer clock and CPU after an INTTM000 interrupt has been generated. Remark n = 0 or 1 <2> If CR010 is changed during timer counting without performing processing <1> above, the value in CR010 may be rewritten twice or more, causing an inversion of the output level of the TO00 pin at each rewrite. (12) Edge detection <1> If the TI000 pin or the TI010 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge for the TI000 pin or TI010 pin to enable 16-bit timer counter 00 (TM00) operation, a rising edge is detected immediately. Be careful when pulling up the TI000 pin or the TI010 pin. However, the rising edge is not detected at restart after the operation has been stopped once. <2> The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger. In the former case, the count clock is fXP, and in the latter case the count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short pulse width. (13) STOP mode or system clock stop mode setting Except when TI000, TI010 input is selected, stop the timer operation before setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts. Preliminary User's Manual U16898EJ1V0UD 117 CHAPTER 7 8-BIT TIMER 80 7.1 Function of 8-Bit Timer 80 8-bit timer 80 has an 8-bit interval timer function and generates an interrupt at intervals specified in advance. Table 7-1. Interval Time of 8-Bit Timer 80 Minimum Interval Time fXP = 8.0 MHz 2 /fXP (8 s) 6 18 2 /fXP (128 s) 24 2 /fXP (8.19 ms) 14 2 /fXP (6.4 s) 16 2 /fXP (25.6 s) 18 2 /fXP (102 s) 24 2 /fXP (6.55 ms) 2 /fXP (128 s) 10 2 /fXP (32.7 ms) 2 /fXP (8.19 ms) 16 2 /fXP (2.01 s) 2 /fXP (6.4 s) 2 /fXP (1.64 ms) 2 /fXP (25.6 s) 2 /fXP (6.55 ms) 2 /fXP (102 s) 10 2 /fXP (26.2 ms) 16 2 /fXP (1.68 s) 2 /fXP (6.55 ms) 118 2 /fXP (32 s) 2 /fXP (8.19 ms) 8 Remark 2 /fXP (8 s) 2 /fXP (32 s) 6 Resolution 16 2 /fXP (2.05 ms) 8 fXP = 10.0 MHz Maximum Interval Time 14 fXP: Oscillation frequency of clock to peripheral hardware Preliminary User's Manual U16898EJ1V0UD 6 8 10 16 6 8 10 16 CHAPTER 7 8-BIT TIMER 80 7.2 Configuration of 8-Bit Timer 80 8-bit timer 80 consists of the following hardware. Table 7-2. Configuration of 8-Bit Timer 80 Item Configuration Timer counter 8-bit timer counter 80 (TM80) Register 8-bit compare register 80 (CR80) Control register 8-bit timer mode control register 80 (TMC80) Figure 7-1. Block Diagram of 8-Bit Timer 80 Internal bus 8-bit compare register 80 (CR80) Match INTTM80 fXP/28 fXP/210 Selector fXP/26 8-bit timer/counter 80 (TM80) Clear fXP/216 TCE80 TCL801 TCL800 8-bit timer mode control register 80 (TMC80) Internal bus Remark fXP: Oscillation frequency of clock to peripheral hardware Preliminary User's Manual U16898EJ1V0UD 119 CHAPTER 7 8-BIT TIMER 80 (1) 8-bit compare register 80 (CR80) This 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (TM80). It generates an interrupt request signal (INTTM80) if the two values match. CR80 is set by using an 8-bit memory manipulation instruction. A value of 00H to FFH can be set to this register. Reset input makes the contents of this register undefined. Figure 7-2. Format of 8-Bit Compare Register 80 (CR80) Address: FFCDH Symbol After reset: Undefined 7 6 5 W 4 3 2 1 0 CR80 Caution When changing the value of CR80, be sure to stop the timer operation. If the value of CR80 is changed with the timer operation enabled, a match interrupt request signal may be generated immediately. (2) 8-bit timer/counter 80 (TM80) This 8-bit register counts the count pulses. The value of TM80 can be read by using an 8-bit memory manipulation instruction. Reset input clears TM80 to 00H. Figure 7-3. Format of 8-Bit Timer Counter 80 (TM80) Address: FFCEH Symbol 7 After reset: 00H 6 5 R 4 3 TM80 120 Preliminary User's Manual U16898EJ1V0UD 2 1 0 CHAPTER 7 8-BIT TIMER 80 7.3 Register Controlling 8-Bit Timer 80 8-bit timer 80 is controlled by 8-bit timer mode control register 80 (TMC80). (1) 8-bit timer mode control register 80 (TMC80) This register is used to enable or stop the operation of 8-bit timer/counter 80 (TM80), and to set the count clock of TM80. This register is set by using a 1-bit or 8-bit memory manipulation instruction. Reset input clears TMC80 to 00H. Figure 7-4. Format of 8-Bit Timer Mode Control Register 80 (TMC80) Address: FFCCH After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 TMC80 TCE80 0 0 0 0 TCL801 TCL800 0 TCE80 Control of operation of TM80 0 Stop operation (clear TM80 to 00H). 1 Enable operation. TCL801 TCL800 Selection of count clock of 8-bit timer 80 fXP = 8.0 MHz 0 0 1 1 0 1 0 1 fXP = 10.0 MHz fXP/2 6 125 kHz 156.3 kHz fXP/2 8 31.25 kHz 39.06 kHz fXP/2 10 7.81 kHz 9.77 kHz fXP/2 16 0.12 kHz 0.15 kHz Caution Be sure to set TMC80 after stopping the timer operation. Remark fXP: Oscillation frequency of clock to peripheral hardware Preliminary User's Manual U16898EJ1V0UD 121 CHAPTER 7 8-BIT TIMER 80 7.4 7.4.1 Operation of 8-Bit Timer 80 Operation as interval timer When 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8-bit compare register 80 (CR80). To use 8-bit timer 80 as an interval timer, make the following setting. <1> Disable the operation of 8-bit timer/counter 80 (clear TCE80 (bit 7 of 8-bit timer mode control register 80 (TMC80)) to 0). <2> Set the count clock of 8-bit timer 80 (refer to Tables 7-3 and 7-4). <3> Set the count value to CR80. <4> Enable the operation of TM80 (set TCE80 to 1). When the count value of 8-bit timer/counter 80 (TM80) matches the set value of CR80, the value of TM80 is cleared to 00H and counting is continued. At the same time, an interrupt request signal (INTTM80) is generated. Tables 7-3 and 7-4 show the interval time, and Figure 7-5 shows the timing of the interval timer operation. Cautions 1. When changing the value of CR80, be sure to stop the timer operation. If the value of CR80 is changed with the timer operation enabled, a match interrupt request signal may be generated immediately. 2. If the count clock of TMC80 is set and the operation of TM80 is enabled at the same time by using an 8-bit memory manipulation instruction, the error of one cycle after the timer is started may be 1 clock or more. Therefore, be sure to follow the above sequence when using TM80 as an interval timer. Table 7-3. Interval Time of 8-Bit Timer 80 (fXP = 8.0 MHz) TCL801 TCL800 Minimum Interval Time Maximum Interval Time 0 2 /fXP (8 s) 0 1 2 /fXP (32 s) 2 /fXP (8.19 ms) 1 0 2 /fXP (128 s) 10 2 /fXP (32.7 ms) 1 1 2 /fXP (8.19 ms) 16 2 /fXP (2.01 s) 0 Remark 6 8 Resolution 14 2 /fXP (8 s) 16 2 /fXP (32 s) 18 2 /fXP (128 s) 24 2 /fXP (8.19 ms) 2 /fXP (2.05 ms) 6 8 10 16 fXP: Oscillation frequency of clock to peripheral hardware Table 7-4. Interval Time of 8-Bit Timer 80 (fXP = 10.0 MHz) TCL811 Minimum Interval Time Maximum Interval Time 0 2 /fXP (6.4 s) 0 1 2 /fXP (25.6 s) 2 /fXP (6.55 ms) 1 0 2 /fXP (102 s) 10 2 /fXP (26.2 ms) 1 1 2 /fXP (6.55 ms) 16 2 /fXP (1.68 s) 0 Remark 122 TCL810 6 8 Resolution 14 2 /fXP (6.4 s) 16 2 /fXP (25.6 s) 18 2 /fXP (102 s) 24 2 /fXP (6.55 ms) 2 /fXP (1.64 ms) fXP: Oscillation frequency of clock to peripheral hardware Preliminary User's Manual U16898EJ1V0UD 6 8 10 16 CHAPTER 7 8-BIT TIMER 80 Figure 7-5. Timing of Interval Timer Operation t Count clock TM80 count value 00H 01H N 00H 01H Clear CR80 N N 00H 01H N Clear N N N Interrupt acknowledged Interrupt acknowledged TCE80 Count start INTTM80 TO80 Interval time Remark Interval time Interval time Interval time = (N + 1) x t: N = 00H to FFH Preliminary User's Manual U16898EJ1V0UD 123 CHAPTER 7 8-BIT TIMER 80 7.5 Notes on 8-Bit Timer 80 (1) Error when timer starts The time from starting the timer to generation of the match signal includes an error of up to 1.5 clocks. This is because, if the timer is started while the count clock is high, the rising edge may be immediately detected and the counter may be incremented (refer to Figure 7-6). Figure 7-6. Case Where Error of 1.5 Clocks (Max.) Occurs Delay A Count pulse Selected clock 8-bit timer counter 80 (TM80) Clear signal TCE80 Delay B Selected clock TCE80 Clear signal Count pulse TM80 count value 00H 01H 02H 03H c Delay A Delay B If the timer is started when the selected clock is high and if delay A > delay B, an error of up to 1.5 clocks occurs. (2) Setting of 8-bit compare register 80 8-bit compare register 80 (CR80) can be set to 00H. (3) Note on setting STOP mode Before executing the STOP instruction, be sure to stop the timer operation (TCE80 = 0). 124 Preliminary User's Manual U16898EJ1V0UD CHAPTER 8 8-BIT TIMER H1 8.1 Functions of 8-Bit Timer H1 8-bit timer H1 has the following functions. * Interval timer * PWM output mode * Square-wave output 8.2 Configuration of 8-Bit Timer H1 8-bit timer H1 consists of the following hardware. Table 8-1. Configuration of 8-Bit Timer H1 Item Configuration Timer register 8-bit timer counter H1 Registers 8-bit timer H compare register 01 (CMP01) 8-bit timer H compare register 11 (CMP11) Timer output TOH1 Control registers 8-bit timer H mode register 1 (TMHMD1) Port mode register 4 (PM4) Port register 4 (P4) Figure 8-1 shows a block diagram. Preliminary User's Manual U16898EJ1V0UD 125 126 Figure 8-1. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 8-bit timer H compare register 11 (CMP11) 8-bit timer H compare register 01 (CMP01) 2 Decoder TOH1/P42 fXP fXP/22 fXP/24 fXP/26 fXP/212 fRL/27 Selector Match Interrupt generator F/F R Output controller Level inversion Output latch (P42) 8-bit timer counter H1 Clear PWM mode signal Timer H enable signal 1 0 INTTMH1 PM42 CHAPTER 8 8-BIT TIMER H1 Preliminary User's Manual U16898EJ1V0UD Selector CHAPTER 8 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 8-2. Format of 8-Bit Timer H Compare Register 01 (CMP01) Address: FF0EH Symbol 7 After reset: 00H R/W 5 6 4 3 2 1 0 CMP01 Caution CMP01 cannot be rewritten during timer count operation. (2) 8-bit timer H compare register 11 (CMP11) This register can be read or written by an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 8-3. Format of 8-Bit Timer H Compare Register 11 (CMP11) Address: FF0FH Symbol 7 After reset: 00H R/W 5 6 4 3 2 1 0 CMP11 CMP11 can be rewritten during timer count operation. If the CMP11 value is rewritten during timer operation, transferring is performed at the timing at which the count value and CMP11 value match. If the transfer timing and writing from CPU to CMP11 conflict, transfer is not performed. Caution In the PWM output mode, be sure to set CMP11 when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). Preliminary User's Manual U16898EJ1V0UD 127 CHAPTER 8 8-BIT TIMER H1 8.3 Registers Controlling 8-Bit Timer H1 The following three registers are used to control 8-Bit Timer H1. * 8-bit timer H mode register 1 (TMHMD1) * Port mode register 4 (PM4) * Port register 4 (P4) (1) 8-bit timer H mode register 1 (TMHMD1) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. 128 Preliminary User's Manual U16898EJ1V0UD CHAPTER 8 8-BIT TIMER H1 Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF70H Symbol TMHMD1 After reset: 00H R/W <7> 6 5 4 TMHE1 CKS12 CKS11 CKS10 TMHE1 3 2 <0> <1> TMMD11 TMMD10 TOLEV1 TOEN1 Timer operation enable 0 Stop timer count operation (counter is cleared to 0) 1 Enable timer count operation (count operation started by inputting clock) CKS12 CKS11 CKS10 0 0 0 0 0 1 0 1 0 0 1 1 fXP/26 1 0 0 1 0 1 Other than above Count clock (fCNT) selection (10 MHz) fXP fXP/2 2 (2.5 MHz) fXP/2 4 (625 kHz) (2.44 kHz) 7 (1.88 kHz (TYP.)) fXP/2 fRL/2 Setting prohibited TMMD11 TMMD10 Timer operation mode 0 0 Interval timer mode 1 0 PWM output mode Other than above TOLEV1 (156.25 kHz) 12 Setting prohibited Timer output level control (in default mode) 0 Low level 1 High level TOEN1 Timer output control 0 Disable output 1 Enable output Cautions 1. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. 2. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware 2. fRL: Low-speed Ring-OSC clock oscillation frequency 3. Figures in parentheses apply to operation at fXP = 10 MHz, fRL = 240 kHz (TYP.). Preliminary User's Manual U16898EJ1V0UD 129 CHAPTER 8 8-BIT TIMER H1 (2) Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P42/TOH1 pin for timer output, clear PM42 and the output latch of P42 to 0. PM4 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to FFH. Figure 8-5. Format of Port Mode Register 4 (PM4) Address: FF24H R/W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40 PM4n 130 After reset: FFH P4n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U16898EJ1V0UD CHAPTER 8 8-BIT TIMER H1 8.4 Operation of 8-Bit Timer H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode. Since a match of 8-bit timer counter H1 and the CMP11 register is not detected even if the CMP11 register is set, timer output is not affected. By setting bit 0 (TOEN1) of timer H mode register 1 (TMHMD1) to 1, a square wave of any frequency (duty = 50%) is output from TOH1. (1) Usage Generates the INTTMH1 signal repeatedly at the same interval. <1> Set each register. Figure 8-6. Register Setting During Interval Timer/Square-Wave Output Operation (i) TMHMD1 Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 0 0 0/1 TOEN1 0/1 Timer output setting Timer output level inversion setting Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (N) <2> Count operation starts when TMHE1 = 1. <3> When the values of 8-bit timer counter H1 and the CMP01 register match, the INTTMH1 signal is generated and 8-bit timer counter H1 is cleared to 00H. Interval time = (N +1)/fCNT <4> Subsequently, the INTTMH1 signal is generated at the same interval. To stop the count operation, clear TMHE1 to 0. Preliminary User's Manual U16898EJ1V0UD 131 CHAPTER 8 8-BIT TIMER H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 8-bit timer counter H1 00H 01H N 00H 01H N Clear 00H 01H 00H Clear N CMP01 TMHE1 INTTMH1 Interval time TOH1 <2> Level inversion, match interrupt occurrence, 8-bit timer counter H1 clear <1> <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter H1 clear <1> The count operation is enabled by setting the TMHE1 bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1 is cleared, the TOH1 output level is inverted, and the INTTMH1 signal is output. <3> The INTTMH1 signal and TOH1 output become inactive by clearing the TMHE1 bit to 0 during timer H1 operation. If these are inactive from the first, the level is retained. Remark 132 N = 01H to FEH Preliminary User's Manual U16898EJ1V0UD CHAPTER 8 8-BIT TIMER H1 Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 00H 01H FEH FFH 00H FEH Clear FFH 00H Clear FFH CMP01 TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1 00H CMP01 00H TMHE1 INTTMH1 TOH1 Interval time Preliminary User's Manual U16898EJ1V0UD 133 CHAPTER 8 8-BIT TIMER H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited. 8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register during timer operation is possible. The operation in PWM output mode is as follows. TOH1 output becomes active and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter H1 and the CMP01 register match after the timer count is started. TOH1 output becomes inactive when 8-bit timer counter H1 and the CMP11 register match. (1) Usage In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> Set each register. Figure 8-8. Register Setting in PWM Output Mode (i) TMHMD1 Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 0 0/1 0/1 0/1 TMMD11 TMMD10 TOLEV1 1 0 0/1 TOEN1 1 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP01 register * Compare value (N): Cycle setting (iii) Setting CMP11 register * Compare value (M): Duty setting Remark 00H CMP11 (M) < CMP01 (N) FFH <2> The count operation starts when TMHE1 = 1. <3> The CMP01 register is the compare register that is to be compared first after count operation is enabled. When the values of 8-bit timer counter H1 and the CMP01 register match, 8-bit timer counter H1 is cleared, an interrupt request signal (INTTMH1) is generated, and TOH1 output becomes active. At the same time, the compare register to be compared with 8-bit timer counter H1 is changed from the CMP01 register to the CMP11 register. 134 Preliminary User's Manual U16898EJ1V0UD CHAPTER 8 8-BIT TIMER H1 <4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. At this time, 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHE1 = 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N+1)/fCNT Duty = Active width : Total width of PWM = (M + 1) : (N + 1) Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKS12 to CKS10 bits of the TMHMD1 register) are required to transfer the CMP11 register value after rewriting the register. 2. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). Preliminary User's Manual U16898EJ1V0UD 135 CHAPTER 8 8-BIT TIMER H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. 00H CMP11 (M) < CMP01 (N) FFH Figure 8-9. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter H1 00H 01H A5H 00H 01H 02H CMP01 A5H CMP11 01H A5H 00H 01H 02H A5H 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <2> <3> <4> TOH1 (TOLEV1 = 1) <1> The count operation is enabled by setting the TMHE1 bit to 1. Start 8-bit timer counter H1 by masking one count clock to count up. At this time, TOH1 output remains inactive (when TOLEV1 = 0). <2> When the values of 8-bit timer counter H1 and the CMP01 register match, the TOH1 output level is inverted, the value of 8-bit timer counter H1 is cleared, and the INTTMH1 signal is output. <3> When the values of 8-bit timer counter H1 and the CMP11 register match, the level of the TOH1 output is returned. At this time, the 8-bit timer counter value is not cleared and the INTTMH1 signal is not output. <4> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive. 136 Preliminary User's Manual U16898EJ1V0UD CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H CMP01 FFH CMP11 00H FFH 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) (c) Operation when CMP01 = FFH, CMP11 = FEH Count clock 8-bit timer counter H1 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H CMP01 FFH CMP11 FEH FEH FFH 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) Preliminary User's Manual U16898EJ1V0UD 137 CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP01 01H CMP11 00H TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) 138 Preliminary User's Manual U16898EJ1V0UD CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 01H 03H, CMP01 = A5H) Count clock 8-bit timer counter H1 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP01 01H CMP11 01H (03H) <2> 03H <2>' TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHE1 = 1. Start 8-bit timer counter H1 by masking one count clock to count up. At this time, the TOH1 output remains inactive (when TOLEV1 = 0). <2> The CMP11 register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1 is cleared, the TOH1 output becomes active, and the INTTMH1 signal is output. <4> If the CMP11 register value is changed, the value is latched and not transferred to the register. When the values of 8-bit timer counter H1 and the CMP11 register before the change match, the value is transferred to the CMP11 register and the CMP11 register value is changed (<2>'). However, three count clocks or more are required from when the CMP11 register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of 8-bit timer counter H1 and the CMP11 register after the change match, the TOH1 output becomes inactive. 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated. <6> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive. Preliminary User's Manual U16898EJ1V0UD 139 CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 14 RESET FUNCTION. Table 9-1. Loop Detection Time of Watchdog Timer Loop Detection Time During Low-Speed Ring-OSC Clock Operation During Operation of Clock to Peripheral Hardware 11 fXP/2 (819.2 s) 12 fXP/2 (1.64 ms) 13 fXP/2 (3.28 ms) 14 fXP/2 (6.55 ms) 15 fXP/2 (13.11 ms) 16 fXP/2 (26.21 ms) 17 fXP/2 (52.43 ms) 18 fXP/2 (104.86 ms) 13 fRL/2 (8.53 ms) 14 fRL/2 (17.07 ms) 15 fRL/2 (34.13 ms) 16 fRL/2 (68.27 ms) 17 fRL/2 (136.53 ms) 18 fRL/2 (273.07 ms) 19 fRL/2 (546.13 ms) 20 fRL/2 (1.09 s) Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency 2. fXP: Oscillation frequency of clock to peripheral hardware 3. Figures in parentheses apply to operation at fRL = 240 kHz (TYP.), fXP = 10 MHz. The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip low-speed Ring-OSC oscillator as shown in Table 9-2. 140 Preliminary User's Manual U16898EJ1V0UD CHAPTER 9 WATCHDOG TIMER Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Setting Low-Speed Ring-OSC Cannot Be Stopped Watchdog timer clock Fixed to fRL Low-Speed Ring-OSC Can Be Stopped by Software * Selectable by software (fXP, fRL or stopped) Note 1 . * When reset is released: fRL source Operation after reset 18 Operation starts with the maximum interval (fRL/2 ). Operation starts with the maximum interval 18 (fRL/2 ). Operation mode The interval can be changed only once. selection The clock selection/interval can be changed only once. Features The watchdog timer cannot be stopped. Notes 1. The watchdog timer can be stopped Note 2 . As long as power is being supplied, low-speed Ring-OSC oscillation cannot be stopped (except in the reset period). 2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer. <1> If the clock source is fXP, clock supply to the watchdog timer is stopped under the following conditions. * When fXP is stopped * In HALT/STOP mode * During oscillation stabilization time <2> If the clock source is fRL, clock supply to the watchdog timer is stopped under the following conditions. * If the CPU clock is fXP and if fRL is stopped by software before execution of the STOP instruction * In HALT/STOP mode Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency 2. fXP: Oscillation frequency of clock to peripheral hardware Preliminary User's Manual U16898EJ1V0UD 141 CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 9-1. Block Diagram of Watchdog Timer fRL/22 fXP/2 4 fRL/211 to fRL/218 Clock input controller 16-bit counter 2 Watchdog timer enable register (WDTE) Selector or fXP/213 to fXP/220 3 Clear 0 1 1 Output controller 3 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 Watchdog timer mode register (WDTM) Internal bus 142 Internal reset signal Preliminary User's Manual U16898EJ1V0UD Option byte (to set "low-speed Ring-OSC cannot be stopped" or "low-speed Ring-OSC can be stopped by software") CHAPTER 9 WATCHDOG TIMER 9.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. * Watchdog timer mode register (WDTM) * Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released. Reset input sets this register to 67H. Figure 9-2. Format of Watchdog Timer Mode Register (WDTM) Address: FF48H After reset: 67H R/W Symbol 7 6 5 4 3 2 1 0 WDTM 0 1 1 WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 WDCS4 Note 1 WDCS3 Note 1 Operation clock selection 0 0 Low-speed Ring-OSC clock (fRL) 0 1 Clock to peripheral hardware (fXP) 1 x Watchdog timer operation stopped WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 Overflow time setting During low-speed Ring-OSC During operation of clock to clock operation 0 0 0 fXP/2 (819.2 s) 12 fXP/2 (1.64 ms) 13 fXP/2 (3.28 ms) 14 fXP/2 (6.55 ms) 15 fXP/2 (13.11 ms) 16 fXP/2 (26.21 ms) 17 fXP/2 (52.43 ms) 18 fXP/2 (104.86 ms) fRL/2 (8.53 ms) 0 0 1 fRL/2 (17.07 ms) 0 1 0 fRL/2 (34.13 ms) 0 1 1 fRL/2 (68.27 ms) 1 0 0 fRL/2 (136.53 ms) 1 0 1 fRL/2 (273.07 ms) 1 1 0 fRL/2 (546.13 ms) 1 1 1 fRL/2 (1.09 s) Notes 1. peripheral hardware 11 13 14 15 16 17 18 19 20 If "low-speed Ring-OSC cannot be stopped" is specified by the option byte, this cannot be set. The low-speed Ring-OSC clock will be selected no matter what value is written. 2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1). Preliminary User's Manual U16898EJ1V0UD 143 CHAPTER 9 WATCHDOG TIMER Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when "low-speed Ring-OSC cannot be stopped" is selected by the option byte, other values are ignored). 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. 3. WDTM cannot be set by a 1-bit memory manipulation instruction. Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency 2. fXP: Oscillation frequency of clock to peripheral hardware 3. x: Don't care 4. Figures in parentheses apply to operation at fRL = 240 kHz (TYP.), fXP = 10 MHz. (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset input sets this register to 9AH. Figure 9-3. Format of Watchdog Timer Enable Register (WDTE) Address: FF49H Symbol 7 After reset: 9AH 6 R/W 5 4 3 2 1 0 WDTE Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. 3. The value read from WDTE is 9AH (this differs from the written value (ACH)). 144 Preliminary User's Manual U16898EJ1V0UD CHAPTER 9 WATCHDOG TIMER 9.4 9.4.1 Operation of Watchdog Timer Watchdog timer operation when "low-speed Ring-OSC cannot be stopped" is selected by option byte The operation clock of watchdog timer is fixed to low-speed Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped. The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Low-speed Ring-OSC clock * Cycle: fRL/218 (1.09 seconds: At operation with fRL = 240 kHz (TYP.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2. * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. Notes 1. The operation clock (low-speed Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored. 2. As soon as WDTM is written, the counter of the watchdog timer is cleared. Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-speed Ring-OSC clock can be selected as the count source, so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction execution. If this processing is not performed, an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution. A status transition diagram is shown below Preliminary User's Manual U16898EJ1V0UD 145 CHAPTER 9 WATCHDOG TIMER Figure 9-4. Status Transition Diagram When "Low-Speed Ring-OSC Cannot Be Stopped" Is Selected by Option Byte Reset WDT clock: fRL Overflow time: 1.09 s (TYP.) WDTE = "ACH" Clear WDT counter. WDT clock is fixed to fRL. Select overflow time (settable only once). WDT clock: fRL Overflow time: 8.53 ms to 1.09 s (TYP.) WDT count continues. HALT instruction STOP instruction Interrupt HALT WDT count continues. 146 Interrupt STOP WDT count continues. Preliminary User's Manual U16898EJ1V0UD CHAPTER 9 WATCHDOG TIMER 9.4.2 Watchdog timer operation when "low-speed Ring-OSC can be stopped by software" is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed Ring-OSC clock or the clock to peripheral hardware. After reset is released, operation is started at the maximum cycle of the low-speed Ring-OSC clock (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1). The following shows the watchdog timer operation after reset release. 1. The status after reset release is as follows. * Operation clock: Low-speed Ring-OSC clock * Cycle: fRL/218 (1.09 seconds: At operation with fRL = 240 kHz (TYP.)) * Counting starts 2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation instructionNotes 1, 2, 3. * Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4). Low-speed Ring-OSC clock (fRL) Clock to peripheral hardware (fXP) Watchdog timer operation stopped * Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0) 3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting. Notes 1. 2. 3. As soon as WDTM is written, the counter of the watchdog timer is cleared. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and x, respectively, an internal reset signal is not generated even if the following processing is performed. * WDTM is written a second time. * A 1-bit memory manipulation instruction is executed to WDTE. * A value other than ACH is written to WDTE. Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. After HALT/STOP mode is released, counting is started again using the operation clock of the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter is not cleared to 0 but holds its value. For the watchdog timer operation during STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode. A status transition diagram is shown below. Preliminary User's Manual U16898EJ1V0UD 147 CHAPTER 9 WATCHDOG TIMER Figure 9-5. Status Transition Diagram When "Low-Speed Ring-OSC Can Be Stopped by Software" Is Selected by Option Byte Reset WDT clock: fRL Overflow time: 1.09 s (TYP.) WDCS4 = 1 WDT clock = fXP Select overflow time (settable only once). WDTE = "ACH" Clear WDT counter. WDT clock = fRL Select overflow time (settable only once). WDT operation stops. WDTE = "ACH" Clear WDT counter. WDTE = "ACH" Clear WDT counter. WDT clock: fRL Overflow time: 8.53 ms to 1.09 s (TYP.) WDT count continues. WDT clock: fXP Overflow time: fXP/213 to fXP/220 WDT count continues. LSRSTOP = 1 LSRSTOP = 0 WDT clock: fRL WDT count stops. HALT instruction HALT instruction Interrupt STOP instruction Interrupt HALT instruction STOP instruction Interrupt STOP instruction Interrupt Interrupt HALT WDT count stops. 148 STOP WDT count stops. HALT WDT count stops. Preliminary User's Manual U16898EJ1V0UD STOP WDT count stops. Interrupt CHAPTER 9 WATCHDOG TIMER 9.4.3 Watchdog timer operation in STOP mode (when "low-speed Ring-OSC can be stopped by software" is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the clock to peripheral hardware or low-speed Ring-OSC clock is being used. (1) When the watchdog timer operation clock is the clock to peripheral hardware (fXP) when the STOP instruction is executed When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 8 clocks of the low-speed Ring-OSC clock (after waiting for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic oscillation) and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware) <1> CPU clock: Crystal/ceramic oscillation clock Normal CPU operation operation Operation stopped (8/fRL) STOP Normal operation Oscillation stabilization time fCPU Oscillation stopped Watchdog timer Operating Oscillation stabilization time (set by OSTS register) Operation stopped Operating <2> CPU clock: High-speed Ring-OSC clock or external clock input CPU operation Normal operation STOP Operation stopped Normal operation (8/fRL) fCPU Oscillation stopped Watchdog timer Operating Operation stopped Preliminary User's Manual U16898EJ1V0UD Operating 149 CHAPTER 9 WATCHDOG TIMER (2) When the watchdog timer operation clock is the low-speed Ring-OSC clock (fRL) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 8 clocks of the low-speed Ring-OSC clock and then counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Ring-OSC Clock) <1> CPU clock: Crystal/ceramic oscillation clock Normal CPU operation operation STOP Operation stopped Oscillation stabilization time Normal operation (8/fRL) fCPU Oscillation stopped Oscillation stabilization time (set by OSTS register) fRL Watchdog timer Operating Operation stopped Operating <2> CPU clock: High-speed Ring-OSC clock or external clock input CPU operation Normal operation STOP Operation stopped Normal operation (8/fRL) fCPU Oscillation stopped fRL Watchdog timer Operating 150 Operation stopped Preliminary User's Manual U16898EJ1V0UD Operating CHAPTER 9 WATCHDOG TIMER 9.4.4 Watchdog timer operation in HALT mode (when "low-speed Ring-OSC can be stopped by software" is selected by option byte) The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer is the clock to peripheral hardware (fXP) or low-speed Ring-OSC clock (fRL). After HALT mode is released, counting is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value. Figure 9-8. Operation in HALT Mode CPU operation Normal operation HALT Normal operation fCPU fXP or fRL Watchdog timer Operating Operation stopped Preliminary User's Manual U16898EJ1V0UD Operating 151 CHAPTER 10 A/D CONVERTER 10.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. * 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. Figure 10-1 shows the timing of sampling and A/D conversion, and Table 10-1 shows the sampling time and A/D conversion time. Figure 10-1. Timing of A/D Converter Sampling and A/D Conversion ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Sampling time Sampling time Conversion time 152 Preliminary User's Manual U16898EJ1V0UD Conversion time CHAPTER 10 A/D CONVERTER Table 10-1. Sampling Time and A/D Conversion Time FR2 FR1 FR0 Sampling Time Note 1 Conversion Time fXP = 8 MHz fXP = 10 MHz Note 2 Conversion Sampling Time Note 1 Time Note 2 Sampling Time Note 1 Conversion Time 0 0 0 12/fXP 36/fXP 1.5 s 4.5 s 1.2 s 3.6 s 0 0 1 24/fXP 48/fXP 3.0 s 6.0 s 2.4 s 4.8 s 0 1 0 48/fXP 72/fXP 6.0 s 9.0 s 4.8 s 7.2 s 0 1 1 88/fXP 112/fXP 11.0 s 14.0 s 8.8 s 11.2 s 1 0 0 24/fXP 72/fXP 3.0 s 9.0 s 2.4 s 7.2 s 1 0 1 48/fXP 96/fXP 6.0 s 12.0 s 4.8 s 9.6 s 1 1 0 96/fXP 144/fXP 12.0 s 18.0 s 9.6 s 14.4 s 1 1 1 176/fXP 224/fXP 22.0 s 28.0 s 17.2 s 22.4 s Notes 1. Note 2 Set the sampling time as follows. * AVREF 4.5 V: 1.0 s or more * AVREF 4.0 V: 2.4 s or more * AVREF 2.85 V: 3.0 s or more * AVREF 2.7 V: 2. 11.0 s or more Set the A/D conversion time as follows. * AVREF 4.5 V: 3.0 s or more and less than 100 s * AVREF 4.0 V: 4.8 s or more and less than 100 s * AVREF 2.85 V: 6.0 s or more and less than 100 s * AVREF 2.7 V: Remark 14.0 s or more and less than 100 s fXP: Oscillation frequency of clock to peripheral hardware Preliminary User's Manual U16898EJ1V0UD 153 CHAPTER 10 A/D CONVERTER Figure 10-2 shows the block diagram of A/D converter. Figure 10-2. Block Diagram of A/D Converter AVREF ADCS bit ANI0/P20 ANI2/P22 Voltage comparator VSS ANI3/P23 Successive approximation register (SAR) Controller ADS1 ADS0 VSS INTAD A/D conversion result register (ADCR, ADCRH) 2 Analog input channel specification register (ADS) Tap selector Selector Sample & hold circuit ANI1/P21 ADCS FR2 FR1 FR0 ADCE A/D converter mode register (ADM) Internal bus Caution In the 78K0S/KA1+, VSS and AVSS are internally connected. Be sure to connect VSS to a stable GND, and stabilize VSS via GND (= 0 V). 154 Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter consists of the following hardware. Table 10-2. Registers of A/D Converter Used on Software Item Configuration Successive approximation register (SAR) Registers 10-bit A/D conversion result register (ADCR) 8-bit A/D conversion result register (ADCRH) A/D converter mode register (ADM) Analog input channel specification register (ADS) Port mode control register 2 (PMC2) Port mode register 2 (PM2) (1) ANI0 to ANI3 pins These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification register (ADS) can be used as input port pins. (2) Sample & hold circuit The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled analog input voltage value during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF and VSS, and generates a voltage to be compared with the analog input signal. Figure 10-3. Circuit Configuration of Series Resistor String AVREF ADCS P-ch Series resistor string VSS (4) Voltage comparator The voltage comparator compares the sampled analog input voltage and the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR). Preliminary User's Manual U16898EJ1V0UD 155 CHAPTER 10 A/D CONVERTER (6) 10-bit A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its lower 10 bits (the higher 6 bits are fixed to 0). (7) 8-bit A/D conversion result register (ADCRH) The result of A/D conversion is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register holds the result of A/D conversion in its higher 8 bits. (8) Controller When A/D conversion has been completed, INTAD is generated. (9) AVREF pin This pin inputs an analog power/reference voltage to the A/D converter. When the A/D converter is not used, connect this pin to VDD. The signal input to ANI0 to ANI3 is converted into a digital signal, based on the voltage applied across AVREF and VSS. In the standby mode, the current flowing through the series resistor string can be reduced by lowering the voltage input to the AVREF pin to the VSS level. (10) VSS pin This is the ground potential pin. Caution In the 78K0S/KA1+, VSS and AVSS are internally connected. Be sure to connect VSS to a stable GND, and stabilize VSS via GND (= 0 V). (11) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) Analog input channel specification register (ADS) This register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (13) Port mode control register 2 (PMC2) This register is used when the P20/ANI0 to P23/ANI3 pins are used as the analog input pins of the A/D converter. 156 Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER 10.3 Registers Used by A/D Converter The A/D converter uses the following six registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) * Port mode control register 2 (PMC2) * Port mode register 2 (PM2) Preliminary User's Manual U16898EJ1V0UD 157 CHAPTER 10 A/D CONVERTER (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-4. Format of A/D Converter Mode Register (ADM) Address: FF80H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> ADM ADCS 0 FR2 FR1 FR0 0 0 ADCE ADCS A/D conversion operation control 0 Stops conversion operation 1 Enables conversion operation FR2 FR1 FR0 Sampling Note 1 Time Conversion Note 2 Time fXP = 10 MHz Conversion Note 2 Time Sampling Note 1 Time Conversion Note 2 Time 0 0 0 12/fXP 36/fXP 1.5 s 4.5 s 1.2 s 3.6 s 0 0 1 24/fXP 48/fXP 3.0 s 6.0 s 2.4 s 4.8 s 0 1 0 48/fXP 72/fXP 6.0 s 9.0 s 4.8 s 7.2 s 0 1 1 88/fXP 112/fXP 11.0 s 14.0 s 8.8 s 11.2 s 1 0 0 24/fXP 72/fXP 3.0 s 9.0 s 2.4 s 7.2 s 1 0 1 48/fXP 96/fXP 6.0 s 12.0 s 4.8 s 9.6 s 1 1 0 96/fXP 144/fXP 12.0 s 18.0 s 9.6 s 14.4 s 1 1 1 176/fXP 224/fXP 22.0 s 28.0 s 17.2 s 22.4 s ADCE Boost reference voltage generator operation control 0 Stops operation of reference voltage generator 1 Enables operation of reference voltage generator Notes fXP = 8 MHz Sampling Note 1 Time Note 3 1. Set the sampling time as follows. * AVREF 4.5 V: 1.0 s or more * AVREF 4.0 V: 2.4 s or more * AVREF 2.85 V: 3.0 s or more * AVREF 2.7 V: 11.0 s or more 2. Set the A/D conversion time as follows. * AVREF 4.5 V: 3.0 s or more and less than 100 s * AVREF 4.0 V: 4.8 s or more and less than 100 s * AVREF 2.85 V: 6.0 s or more and less than 100 s * AVREF 2.7 V: 14.0 s or more and less than 100 s 3. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that generates the reference voltage for boosting is controlled by ADCE, and it takes 1 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. 158 Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER Table 10-3. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation 0 0 Stop status (DC power consumption path does not exist) 0 1 Conversion waiting mode (only reference voltage generator consumes power) 1 0 Conversion mode (reference voltage generator operation stopped 1 1 Conversion mode (reference voltage generator operates) Note ) Note Data of first conversion cannot be used. Figure 10-5. Timing Chart When Boost Reference Voltage Generator Is Used Boost reference voltage generator: operating ADCE Boost reference voltage Conversion operation Conversion waiting Conversion operation Conversion stopped ADCS Note Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 s or longer to stabilize the reference voltage. Caution A/D conversion must be stopped before rewriting bits FR0 to FR2. Remark fXP: Oscillation frequency of clock to peripheral hardware Preliminary User's Manual U16898EJ1V0UD 159 CHAPTER 10 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-6. Format of Analog Input Channel Specification Register (ADS) Address: FF81H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS 0 0 0 0 0 0 ADS1 ADS0 ADS1 ADS0 0 0 ANI0 0 1 ANI1 1 0 ANI2 1 1 ANI3 Analog input channel specification Caution Be sure to clear bits 2 to 7 of ADS to 0. (3) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from bit 1 of FF19H. FF19H indicates the higher 2 bits of the conversion result, and FF18H indicates the lower 8 bits of the conversion result. ADCR can be read by a 16-bit memory manipulation instruction. Reset input makes ADCR undefined. Figure 10-7. Format of 10-Bit A/D Conversion Result Register (ADCR) Address: FF18H, FF19H R FF19H Symbol ADCR After reset: Undefined 0 0 0 0 0 FF18H 0 Caution When writing to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using timing other than the above may cause an incorrect conversion result to be read. 160 Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER (4) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. Reset input makes ADCRH undefined. Figure 10-8. Format of 8-Bit A/D Conversion Result Register (ADCRH) Address: FF1AH Symbol After reset: Undefined 7 6 R 5 4 3 2 1 0 ADCRH (5) Port mode control register 2 (PMC2) and port mode register 2 (PM2) When using the P20/ANI0 to P23/ANI3 pins for analog input, set PMC20 to PMC23 and PM20 to PM23 to 1. At this time, the output latches of P20 to P23 may be 0 or 1. PMC2 and PM2 are set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears PMC2 to 00H and sets PM2 to FFH. Figure 10-9. Format of Port Mode Control Register 2 (PMC2) Address: FF84H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Operation mode specification (n = 0 to 3) 0 Port mode 1 Alternate-function mode (A/D converter) Figure 10-10. Format of Port Mode Register 2 (PM2) Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 PM2n Pmn pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Caution When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot be used as port pins. Preliminary User's Manual U16898EJ1V0UD 161 CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). <2> Set ADCE to 1 and wait for 1 s or longer. <3> Set ADCS to 1 and start the conversion operation. (<4> to <10> are operations performed by hardware.) <4> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <5> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation has ended. <6> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <7> The voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB is reset to 0. <8> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 8 = 1 * Analog input voltage < Voltage tap: Bit 8 = 0 <9> Comparison is continued in this way up to bit 0 of SAR. <10> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. <11> Repeat steps <4> to <10>, until ADCS is cleared to 0. To stop the A/D converter, clear ADCS to 0. To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the status of ADCE = 0, however, start from <2>. Remark The following two types of A/D conversion result registers can be used. <1> ADCR (16 bits): Stores a 10-bit A/D conversion value. <2> ADCRH (8 bits): Stores an 8-bit A/D conversion value. 162 Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER Figure 10-11. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion Conversion result SAR Undefined ADCR, ADCRH Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to ADM or the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset input makes the A/D conversion result register (ADCR, ADCRH) undefined. Preliminary User's Manual U16898EJ1V0UD 163 CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or (ADCR - 0.5) x where, INT( ): AVREF 1024 VAIN < (ADCR + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses VAIN: Analog input voltage AVREF: AVREF pin voltage ADCR: 10-bit A/D conversion result register (ADCR) value SAR: Successive approximation register Figure 10-12 shows the relationship between the analog input voltage and the A/D conversion result. Figure 10-12. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 FF40H 3 00C0H 2 0080H 1 0040H A/D conversion result (ADCR) 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF 164 Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has started and when one A/D conversion has been completed, the next A/D conversion operation is immediately started. The A/D conversion operations are repeated until new data is written to ADS. If ADM or ADS is written during A/D conversion, the A/D conversion operation under execution is stopped and restarted from the beginning. If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the conversion result is undefined. Figure 10-13. A/D Conversion Operation Rewriting ADM ADCS = 1 A/D conversion ANIn Rewriting ADS ANIn ANIn ADCS = 0 ANIm ANIm Conversion is stopped Conversion result is not retained ADCR, ADCRH ANIn ANIn Stopped ANIm INTAD Remarks 1. n = 0 to 3 2. m = 0 to 3 Preliminary User's Manual U16898EJ1V0UD 165 CHAPTER 10 A/D CONVERTER The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM. <3> Set bit 7 (ADCS) of ADM to 1. <4> An interrupt request signal (INTAD) is generated. <5> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Change the channel> <6> Change the channel using bits 1 and 0 (ADS1, ADS0) of ADS. <7> An interrupt request signal (INTAD) is generated. <8> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). <Complete A/D conversion> <9> Clear ADCS to 0. <10> Clear ADCE to 0. Cautions 1. Make sure the period of <1> to <3> is 1 s or more. 2. It is no problem if the order of <1> and <2> is reversed. 3. <1> can be omitted. However, do not use the first conversion result after <3> in this case. 4. The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0. 166 Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER 10.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 10-14. Overall Error Figure 10-15. Quantization Error 1......1 1......1 Overall error Digital output Digital output Ideal line 1/2LSB Quantization error 1/2LSB 0......0 AVREF 0 Analog input 0......0 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. Preliminary User's Manual U16898EJ1V0UD 167 CHAPTER 10 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 10-16. Zero-Scale Error Figure 10-17. Full-Scale Error Full-scale error Digital output (Lower 3 bits) Digital output (Lower 3 bits) 111 Ideal line 011 010 001 Zero-scale error 000 111 110 101 Ideal line 000 0 1 2 3 AVREF AVREF-3 0 Analog input (LSB) AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 10-18. Integral Linearity Error Figure 10-19. Differential Linearity Error 1......1 1......1 Ideal 1LSB width Digital output Digital output Ideal line Differential linearity error Integral linearity error 0......0 0 Analog input 0......0 0 AVREF Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time 168 Conversion time Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER 10.6 Cautions for A/D Converter (1) Operating current in standby mode The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 (see Figure 10-3). (2) Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AVREF or higher and VSS or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by instruction upon the end of conversion ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR, ADCRH. <2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input channel specification register (ADS) write upon the end of conversion ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI3. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 10-20, to reduce noise. Figure 10-20. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than VSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI3 C = 100 to 1,000 pF VSS Preliminary User's Manual U16898EJ1V0UD 169 CHAPTER 10 A/D CONVERTER (5) ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 while conversion is in progress; otherwise the conversion resolution may be degraded. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI3 pins In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI3 pins (see Figure 10-20). (7) AVREF pin input impedance A series resistor string of several tens of 10 k is connected between the AVREF and VSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and VSS pins, resulting in a large reference voltage error. 170 Preliminary User's Manual U16898EJ1V0UD CHAPTER 10 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 10-21. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ADCR, ADCRH ANIn ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ANIm ANIm ANIm ADIF Remarks 1. n = 0 to 3 2. m = 0 to 3 (9) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM) and analog input channel specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an incorrect conversion result to be read. Preliminary User's Manual U16898EJ1V0UD 171 CHAPTER 10 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-22. Internal Equivalent Circuit of ANIn Pin RIN ANIn COUT CIN LSI internal Table 10-4. Resistance and Capacitance Values of Equivalent Circuit AVREF RIN COUT CIN 2.7 V T.B.D. T.B.D. T.B.D. 4.5 V T.B.D. T.B.D. T.B.D. Remarks 1. The resistance and capacitance values shown in Table 10-4 are not guaranteed values. 2. n = 0 to 3 RIN: Input equivalent resistance CIN: Input equivalent capacitance COUT: Package pin capacitance 172 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 11.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 11.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 11.4.2 Asynchronous serial interface (UART) mode and 11.4.3 Dedicated baud rate generator. * Two-pin configuration TXD6: Transmit data output pin RXB6: Receive data input pin * Data length of communication data can be selected from 7 or 8 bits. * Dedicated internal 8-bit baud rate generator allowing any baud rate to be set * Transmission and reception can be performed independently. * Twelve operating clock inputs selectable * MSB- or LSB-first communication selectable * Inverted transmission operation * Synchronous break field transmission from 13 to 20 bits * More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided). Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception side. To use this function, the reception side must be ready for reception of inverted data. 2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP mode), each register stops operating, and holds the value immediately before clock supply was stopped. The TXD6 pin also holds the value immediately before clock supply was stopped and outputs it. However, the operation is not guaranteed after clock supply is resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0. 3. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is incorporated in LIN. Preliminary User's Manual U16898EJ1V0UD 173 CHAPTER 11 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. Figures 11-1 and 11-2 outline the transmission and reception operations of LIN. Figure 11-1. LIN Transmission Operation Wakeup signal frame Synchronous break field Synchronous field Indent field Data field Data field Checksum field Sleep bus Note 1 8 bits 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission TX6 Note 3 INTST6 Notes 1. 2. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The synchronous break field is output by hardware. The output width is equal to the bit length set by bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6). If the output width needs to be adjusted more accurately, use baud rate generator control register 6 (BRGC6) (see 11.4.2 (h) SBF transmission). 3. Remark 174 INTST6 is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-2. LIN Reception Operation Wakeup signal frame Synchronous break field Synchronous field Indent field Data field Data field Checksum field 13 bitsNote 2 SF reception ID reception Data reception Data Data reception receptionNote 5 Sleep bus RX6 Disable SBF reception Enable Note 3 Reception interrupt (INTSR6) Edge detection Note 1 (INTP0) Note 4 Capture timer Notes 1. Disable Enable The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. 2. Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored. 3. If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH. 4. Calculate the baud rate error from the bit length of the synchronous field, disable UART6 after SF reception, and then re-set baud rate generator control register 6 (BRGC6). 5. Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again. To perform a LIN receive operation, use a configuration like the one shown in Figure 11-3. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally. Preliminary User's Manual U16898EJ1V0UD 175 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-3. Port Configuration for LIN Reception Operation Selector P44/RXD6 RXD6 input Port mode (PM44) Output latch (P44) Selector Selector P30/INTP0/TI000 INTP0 input Port mode (PM30) Output latch (P30) Port input selection control (ISC0) <ISC0> 0: Selects INTP0 (P30). 1: Selects RxD6 (P44). Selector TI000 input Port input selection control (ISC1) <ISC1> 0: Selects TI000 (P30). 1: Selects RxD6 (P44). Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 11-11) The peripheral functions used in the LIN communication operation are shown below. <Peripheral functions used> * External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication. * 16-bit timer/event counter 00 (TI000); baud rate error detection Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the synchronous break field (SBF) length and divides it by the number of bits. * Serial interface UART6 176 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 11.2 Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 11-1. Configuration of Serial Interface UART6 Item Registers Configuration Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 (ASIF6) Clock selection register 6 (CKSR6) Baud rate generator control register 6 (BRGC6) Asynchronous serial interface control register 6 (ASICL6) Input switch control register (ISC) Port mode register 4 (PM4) Port register 4 (P4) Preliminary User's Manual U16898EJ1V0UD 177 178 Figure 11-4. Block Diagram of Serial Interface UART6 TI000, INTP0Note Filter INTSR6 Reception control INTSRE6 Selector Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Baud rate generator Receive shift register 6 (RXS6) Asynchronous serial interface control register 6 (ASICL6) Receive buffer register 6 (RXB6) Asynchronous serial interface control register 6 (ASICL6) Transmit buffer register 6 (TXB6) Transmission control Transmit shift register 6 (TXS6) Reception unit Internal bus Baud rate generator control register 6 (BRGC6) 8 Asynchronous serial Clock selection interface transmission register 6 (CKSR6) status register 6 (ASIF6) Baud rate generator 8 INTST6 TXD6/ INTP1/P43 Registers Output latch (P43) Transmission unit Note Selectable with input switch control register (ISC). PM43 CHAPTER 11 SERIAL INTERFACE UART6 Preliminary User's Manual U16898EJ1V0UD fXP fXP/2 fXP/22 fXP/23 fXP/24 fXP/25 fXP/26 fXP/27 fXP/28 fXP/29 fXP/210 fXP/211 RXD6/ P44 CHAPTER 11 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0. If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6. RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset input sets this register to FFH. (2) Receive shift register 6 (RXS6) This register converts the serial data input to the RXD6 pin into parallel data. RXS6 cannot be directly manipulated by a program. (3) Transmit buffer register 6 (TXB6) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6. This register can be read or written by an 8-bit memory manipulation instruction. Reset input sets this register to FFH. Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission status register 6 (ASIF6) is 1. 2. Do not refresh (write the same value to) TXB6 by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). (4) Transmit shift register 6 (TXS6) This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6 pin at the falling edge of the base clock. TXS6 cannot be directly manipulated by a program. Preliminary User's Manual U16898EJ1V0UD 179 CHAPTER 11 SERIAL INTERFACE UART6 11.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 4 (PM4) * Port register 4 (P4) (1) Asynchronous serial interface operation mode register 6 (ASIM6) This 8-bit register controls the serial communication operations of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 01H. Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF90H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enabling/disabling operation of internal operation clock Disable operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 Note 3 . Enable operation of the internal operation clock TXE6 Notes 1. Note 2 Enabling/disabling transmission 0 Disable transmission (synchronously reset the transmission circuit). 1 Enable transmission The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when POWER6 = 0. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. 3. Operation of the 8-bit counter output is enabled at the second base clock after 1 is written to the POWER6 bit. 180 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enabling/disabling reception 0 Disable reception (synchronously reset the reception circuit). 1 Enable reception PS61 PS60 0 0 Parity bit not output. Reception without parity 0 1 Output 0 parity. Reception as 0 parity 1 0 Output odd parity. Judge as odd parity. 1 1 Output even parity. Judge as even parity. CL6 Transmission operation Note Specification of character length of transmit/receive data 0 Character length of data = 7 bits 1 Character length of data = 8 bits SL6 Specification of number of stop bits of transmit data 0 Number of stop bits = 1 1 Number of stop bits = 2 ISRM6 Reception operation Enabling/disabling occurrence of reception completion interrupt in case of error 0 "INTSRE6" occurs in case of error (at this time, INTSR6 does not occur). 1 "INTSR6" occurs in case of error (at this time, INTSRE6 does not occur). Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur. Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0, and then clear POWER6 to 0. 2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0, and then clear POWER6 to 0. 3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started. 4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. 5. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN. 6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit. 7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit. Preliminary User's Manual U16898EJ1V0UD 181 CHAPTER 11 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this register is read. Figure 11-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Address: FF93H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIS6 0 0 0 0 0 PE6 FE6 OVE6 PE6 Status flag indicating parity error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read 1 If receive data is set to the RXB register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 (ASIM6). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 6 (RXB6) but discarded. 182 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register. This register is read-only by an 8-bit memory manipulation instruction. Reset input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0. Figure 11-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Address: FF95H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 ASIF6 0 0 0 0 0 0 TXBF6 TXSF6 TXBF6 Transmit buffer data flag 0 If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6) 1 If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6) TXSF6 0 Transmit shift register data flag If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6 (TXB6) after completion of transfer 1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. Preliminary User's Manual U16898EJ1V0UD 183 CHAPTER 11 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 11-8. Format of Clock Selection Register 6 (CKSR6) Address: FF96H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 0 0 0 0 fXP (10 MHz) 0 0 0 1 fXP/2 (5 MHz) 0 0 1 0 fXP/2 (2.5 MHz) 0 0 1 1 fXP/2 (1.25 MHz) 0 1 0 0 fXP/2 (625 kHz) 0 1 0 1 fXP/2 (312.5 kHz) 0 1 1 0 fXP/2 (156.25 kHz) 0 1 1 1 fXP/2 (78.13 kHz) 1 0 0 0 fXP/2 (39.06 kHz) 1 0 0 1 fXP/2 (19.53 kHz) 1 0 1 0 fXP/2 (9.77 kHz) 1 0 1 1 fXP/2 (4.89 kHz) Other than above Base clock (fXCLK6) selection 2 3 4 5 6 7 8 9 10 11 Setting prohibited Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60. Remarks 1. Figures in parentheses are for operation with fXP = 10 MHz 2. fXP: Oscillation frequency of clock to peripheral hardware 184 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Figure 11-9. Format of Baud Rate Generator Control Register 6 (BRGC6) Address: FF97H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8-bit counter 0 0 0 0 0 x x x x Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK6/8 0 0 0 0 1 0 0 1 9 fXCLK6/9 0 0 0 0 1 0 1 0 10 fXCLK6/10 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1 1 1 1 1 1 0 0 252 fXCLK6/252 1 1 1 1 1 1 0 1 253 fXCLK6/253 1 1 1 1 1 1 1 0 254 fXCLK6/254 1 1 1 1 1 1 1 1 255 fXCLK6/255 Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67 to MDL60 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255) 3. x: Don't care Preliminary User's Manual U16898EJ1V0UD 185 CHAPTER 11 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh operation because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is completed (when an interrupt signal is generated). Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2) Address: FF98H After reset: 16H R/W Note Symbol <7> <6> 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6 SBRF6 SBF reception status flag 0 If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly 1 SBF reception in progress SBRT6 SBF reception trigger - 0 1 SBF reception trigger SBTT6 SBF transmission trigger 0 - 1 SBF transmission trigger Note Bit 7 is read-only. 186 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control 1 0 1 SBF is output with 13-bit length. 1 1 0 SBF is output with 14-bit length. 1 1 1 SBF is output with 15-bit length. 0 0 0 SBF is output with 16-bit length. 0 0 1 SBF is output with 17-bit length. 0 1 0 SBF is output with 18-bit length. 0 1 1 SBF is output with 19-bit length. 1 0 0 SBF is output with 20-bit length. DIR6 Specification of first bit 0 MSB 1 LSB TXDLV6 Enabling/disabling inverting TXD6 output 0 Normal output of TXD6 1 Inverted output of TXD6 Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode and hold the status of the SBRF6 flag. 2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1. 3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1. 5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of SBF transmission. 6. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. Preliminary User's Manual U16898EJ1V0UD 187 CHAPTER 11 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input signal is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 11-11. Format of Input Switch Control Register (ISC) Address: FF8CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ISC 0 0 0 0 0 0 ISC1 ISC0 ISC1 TI000 input source selection 0 TI000 (P30) 1 RxD6 (P44) ISC0 INTP0 input source selection 0 INTP0 (P30) 1 RxD6 (P44) (8) Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P43/TxD6/INTP1 pin for serial interface data output, clear PM43 to 0 and set the output latch of P43 to 1. When using the P44/RxD6 pin for serial interface data input, set PM44 to 1. The output latch of P44 at this time may be 0 or 1. PM4 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to FFH. Figure 11-12. Format of Port Mode Register 4 (PM4) Address: FF24H R/W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40 PM4n 188 After reset: FFH P4n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 11.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 11.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6). ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 01H. Address: FF90H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enabling/disabling operation of internal operation clock Disable operation of the internal operation clock (fix the clock to low level) and asynchronously reset the internal circuit TXE6 0 Notes 1. . Enabling/disabling transmission Disable transmission operation (synchronously reset the transmission circuit). RXE6 0 Note 2 Enabling/disabling reception Disable reception (synchronously reset the reception circuit). The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when POWER6 = 0. 2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset. Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode. To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1. Remark To use the RxD6/P44 and TxD6/INTP1/P43 pins as general-purpose port pins, see CHAPTER 4 PORT FUNCTIONS. Preliminary User's Manual U16898EJ1V0UD 189 CHAPTER 11 SERIAL INTERFACE UART6 11.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6 (ASIM6) * Asynchronous serial interface reception error status register 6 (ASIS6) * Asynchronous serial interface transmission status register 6 (ASIF6) * Clock selection register 6 (CKSR6) * Baud rate generator control register 6 (BRGC6) * Asynchronous serial interface control register 6 (ASICL6) * Input switch control register (ISC) * Port mode register 4 (PM4) * Port register 4 (P4) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6 register (see Figure 11-8). <2> Set the BRGC6 register (see Figure 11-9). <3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 11-5). <4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 11-10). <5> Set bit 7 (POWER6) of the ASIM6 register to 1. <6> Set bit 6 (TXE6) of the ASIM6 register to 1. Transmission is enabled. Set bit 5 (RXE6) of the ASIM6 register to 1. Reception is enabled. <7> Write data to transmit buffer register 6 (TXB6). Data transmission is started. Caution Take relationship with the other party of communication into consideration when setting the port mode register and port register. 190 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 11-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM43 P43 PM44 P44 UART6 Operation 0 0 0 x Note x Note 1 0 1 x Note x Note 1 0 0 1 1 1 0 1 x Note 1 x Note 1 x Note Pin Function TxD6/INTP1/P43 RxD6/P44 Stop P43 P44 Reception P43 RxD6 Note Transmission TxD6 P44 x Transmission/ TxD6 RxD6 x x reception Note Can be set as port function. Remark x: don't care POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 PM4x: Port mode register P4x: Port output latch Preliminary User's Manual U16898EJ1V0UD 191 CHAPTER 11 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data. Figure 11-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit D1 D0 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (ASIM6). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6 (ASICL6). Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6. 192 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 Preliminary User's Manual U16898EJ1V0UD D6 D7 Stop 193 CHAPTER 11 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. 194 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 (c) Normal transmission The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that, the data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated. Transmission is stopped until the data to be transmitted next is written to TXB6. Figure 11-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt occurs as soon as the last stop bit has been output. Figure 11-15. Normal Transmission Completion Interrupt Request Timing 1. Stop bit length: 1 TXD6 (output) Start D0 D1 D2 D6 D7 Parity Start D0 D1 D2 D6 D7 Parity Stop INTST6 2. Stop bit length: 2 TXD6 (output) Stop INTST6 Preliminary User's Manual U16898EJ1V0UD 195 CHAPTER 11 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written, and then write the data. Cautions 1. The TXBF6 and TXSF6 flags of the ASIS register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing continuous transmission. 2. When the device is incorporated in a LIN, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6). TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register. Be sure to check that the TXBF6 flag is "0". If so, write the next transmit data (second byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6 flag. TXSF6 Transmission Status 0 Transmission is completed. 1 Transmission is in progress. Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6 flag is "1", the transmit data cannot be guaranteed. 2. During continuous transmission, an overrun error may occur, which means that the next transmission was completed before execution of INTST6 interrupt servicing after transmission of one data frame. An overrun error can be detected by developing a program that can count the number of transmit data and by referencing the TXSF6 flag. 196 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-16 shows an example of the continuous transmission processing flow. Figure 11-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Yes No Read ASIF6 TXBF6 = 0? No Yes Write TXB6. Transmission completion interrupt occurred? No Yes Transfer executed necessary number of times? Yes No Read ASIF6 TXSF6 = 0? No Yes Yes of Completion transmission processing Remark TXB6: Transmit buffer register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 (transmit buffer data flag) TXSF6: Bit 0 of ASIF6 (transmit shift register data flag) Preliminary User's Manual U16898EJ1V0UD 197 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-17 shows the timing of starting continuous transmission, and Figure 11-18 shows the timing of ending continuous transmission. Figure 11-17. Timing of Starting Continuous Transmission Start TXD6 Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6 TXB6 FF TXS6 FF Data (1) Data (2) Data (1) Data (3) Data (2) Data (3) TXBF6 Note TXSF6 Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6 bit. Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 198 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-18. Timing of Ending Continuous Transmission TXD6 Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop INTST6 TXB6 Data (n - 1) Data (n) Data (n - 1) TXS6 Data (n) FF TXBF6 TXSF6 POWER6 or TXE6 Remark TXD6: TXD6 pin (output) INTST6: Interrupt request signal TXB6: Transmit buffer register 6 TXS6: Transmit shift register 6 ASIF6: Asynchronous serial interface transmission status register 6 TXBF6: Bit 1 of ASIF6 TXSF6: Bit 0 of ASIF6 POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6) TXE6: Bit 6 of asynchronous serial interface operation mode register (ASIM6) Preliminary User's Manual U16898EJ1V0UD 199 CHAPTER 11 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin input is sampled again ( in Figure 11-19). If the RXD6 pin is low level at this time, it is recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error (OVE6) occurs, however, the receive data is not written to RXB6. Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception. Figure 11-19. Reception Completion Interrupt Request Timing RXD6 (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6 RXB6 Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6) before reading RXB6. 200 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt servicing (INTSR6/INTSRE6) (see Figure 11-6). The contents of ASIS6 are reset to 0 when ASIS6 is read. Table 11-3. Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data. Framing error Stop bit is not detected. Overrun error Reception of the next data is completed before data is read from receive buffer register 6 (RXB6). The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0. Figure 11-20. Reception Error Interrupt 1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are separated) (a) No error during reception (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 2. If ISRM6 is set to 1 (error interrupt is included in INTSR6) (a) No error during reception (b) Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 Preliminary User's Manual U16898EJ1V0UD 201 CHAPTER 11 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 11-21, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 11-21. Noise Filter Circuit Base clock RXD6/P44 In Q Internal signal A Match detector 202 Preliminary User's Manual U16898EJ1V0UD In LD_EN Q Internal signal B CHAPTER 11 SERIAL INTERFACE UART6 (h) SBF transmission When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 11-1 LIN Transmission Operation. An SBF length that is a low-level width of 13 bits or more is set by bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6). If the output width needs to be adjusted more accurately, use the baud rate value of the normal UART transmission function. [Setting method] Transmit 00H by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even parity. This enables a low-level transmission of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits (character bits) + 1 bit (parity bit)). Adjust the baud rate value to adjust this 10-bit low level to the targeted 13-bit SBF length (SBL62, SBL61, SBL60 = 1, 0, 1). Example If LIN is to be transmitted under the following conditions * Base clock of UART6 = 5 MHz (set by clock selection register 6 (CKSR6)) * Target baud rate value = 19200 bps To realize the above baud rate value, the length of a 13-bit SBF is as follows if the baud rate generator control register 6 (BRGC6) is set to 130. * 13-bit SBF length = 0.2 s x 130 x 2 x 13 = 676 s To realize a 13-bit SBF length in 10 bits, set a value 1.3 times the targeted baud rate to BRGC6. In this example, set 169 to BRGC6. The transmission length of a 10-bit low level in this case is as follows, and matches the 13-bit SBF length. * 10-bit low-level transmission length = 0.2 s x 169 x 2 x 10 = 676 s If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of UART6. Preliminary User's Manual U16898EJ1V0UD 203 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to generalpurpose register. Clear TXE6 and RXE6 bits of ASIM6 register to 0 (to disable transmission/ reception). Set value to BRGC6 register to realize desired SBF length. Clear TXE6 and RXE6 bits of ASIM6 register to 0. (SBTT6 bit is automatically cleared.) Set character length of data to 8 bits and parity to 0 or even using ASIM6 register. Rewrite saved BRGC6 value to BRGC6 register. Set TXE6 bit of ASIM6 register to 1 to enable transmission. Re-set PS61 bit, PS60 bit, and CL6 bit of ASIM6 register to desired value. Set TXE6 bit of ASIM6 register to 1 to enable transmission. Set SBTT6 bit to 1, and set TXB6 register to "00H" to start transmission. End No INTST6 occurred? Yes Figure 11-23. SBF Transmission 1 TXD6 2 3 4 5 6 7 8 9 10 11 12 INTST6 SBTT6 Remark TXD6: TXD6 pin (output) INTST6: Transmission completion interrupt request SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6) 204 Preliminary User's Manual U16898EJ1V0UD 13 Stop CHAPTER 11 SERIAL INTERFACE UART6 (i) SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 11-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and SBRT6 bits are not cleared. Figure 11-24. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) 1 RXD6 2 3 4 5 6 7 8 9 10 11 SBRT6 /SBRF6 INTSR6 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) 1 RXD6 2 3 4 5 6 7 8 9 10 SBRT6 /SBRF6 INTSR6 Remark RXD6: "0" RXD6 pin (input) SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6) SBRF6: Bit 7 of ASICL6 INTSR6: Reception completion interrupt request Preliminary User's Manual U16898EJ1V0UD 205 CHAPTER 11 SERIAL INTERFACE UART6 11.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6 = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when POWER6 = 1 and TXE6 = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial interface operation mode register 6 (ASIM6) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. 206 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-25. Configuration of Baud Rate Generator POWER6 fXP Baud rate generator fXP/2 fXP/22 POWER6, TXE6 (or RXE6) fXP/23 fXP/24 fXP/25 Selector fXP/26 8-bit counter fXCLK6 fXP/27 fXP/28 fXP/29 fXP/210 Match detector fXP/211 CKSR6: TPS63 to TPS60 Remark 1/2 Baud rate BRGC6: MDL67 to MDL60 POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6: Bit 5 of ASIM6 CKSR6: Clock selection register 6 BRGC6: Baud rate generator control register 6 Preliminary User's Manual U16898EJ1V0UD 207 CHAPTER 11 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 2xk [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255) (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M/(2 x 33) = 10000000/(2 x 33) = 151,515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] 208 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 11-4. Set Data of Baud Rate Generator Baud Rate [bps] fXP = 10.0 MHz TPS63 to k TPS60 fXP = 8.0 MHz Calculated ERR[%] TPS63 to Value TPS60 k fXP = 4.19 MHz Calculated ERR[%] TPS63 to Value TPS60 k Calculated ERR[%] Value 600 6H 130 601 0.16 6H 104 601 0.16 5H 109 601 0.11 1200 5H 130 1202 0.16 5H 104 1202 0.16 4H 109 1201 0.11 2400 4H 130 2404 0.16 4H 104 2404 0.16 3H 109 2403 0.11 4800 3H 130 4808 0.16 3H 104 4808 0.16 2H 109 4805 0.11 9600 2H 130 9615 0.16 2H 104 9615 0.16 1H 109 9610 0.11 10400 2H 120 10417 0.16 2H 96 10417 0.16 1H 101 10475 -0.28 19200 1H 130 19231 0.16 1H 104 19231 0.16 0H 109 19220 0.11 31250 1H 80 31250 0.00 0H 128 31250 0.00 0H 67 31268 0.06 38400 0H 130 38462 0.16 0H 104 38462 0.16 0H 55 38090 -0.80 76800 0H 65 76923 0.16 0H 52 76923 0.16 0H 27 77593 1.03 115200 0H 43 116279 0.94 0H 35 114286 -0.79 0H 18 116389 1.03 153600 0H 33 151515 -1.36 0H 26 153846 0.16 0H 14 149643 -2.58 230400 0H 22 227272 -1.36 0H 17 235294 2.12 0H 9 232778 1.03 Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6)) k: Value set by MDL67 to MDL60 bits of baud rate generator control register 6 (BRGC6) (k = 8, 9, 10, ..., 255) fXP: Oscillation frequency of clock to peripheral hardware ERR: Baud rate error Preliminary User's Manual U16898EJ1V0UD 209 CHAPTER 11 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 11-26. Permissible Baud Rate Range During Reception Latch timing Data frame length of UART6 Start bit Bit 0 Bit 1 Bit 7 Stop bit Parity bit FL 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 11-26, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART6 k: Set value of BRGC6 FL: 1-bit data length Margin of latch timing: 2 clocks 210 Preliminary User's Manual U16898EJ1V0UD CHAPTER 11 SERIAL INTERFACE UART6 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k BRmax = (FLmin/11)-1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 x FLmax = 11 x FL - FLmax = 21k - 2 20k k+2 2xk x FL = 21k - 2 2xk FL FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 11-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 +3.53% -3.61% 20 +4.26% -4.31% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.73% Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: Set value of BRGC6 Preliminary User's Manual U16898EJ1V0UD 211 CHAPTER 11 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 11-27. Data Frame Length During Continuous Transmission Start bit of second byte 1 data frame Start bit FL Bit 0 Bit 1 Bit 7 FL FL FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 212 Preliminary User's Manual U16898EJ1V0UD CHAPTER 12 INTERRUPT FUNCTIONS 12.1 Interrupt Function Types All interrupts are controlled as maskable interrupts. * Maskable interrupts These interrupts undergo mask control. If two or more interrupt requests are simultaneously generated, each interrupt has a predetermined priority as shown in Table 12-1. A standby release signal is generated. There are ten internal sources and four external sources of maskable interrupts. Preliminary User's Manual U16898EJ1V0UD 213 CHAPTER 12 INTERRUPT FUNCTIONS 12.2 Interrupt Sources and Configuration There are a total of 14 interrupt sources, and up to four reset sources (see Table 12-1). Table 12-1. Interrupt Sources Interrupt Type Note 1 Priority Interrupt Source Name Trigger Internal/ Vector Table Basic External Address Configuration Note 2 Type Maskable Note 3 1 INTLVI Low-voltage detection 2 INTP0 Pin input edge detection 3 INTP1 4 INTTMH1 Internal 0006H (A) External 0008H (B) 000AH Match between TMH1 and CMP01 Internal 000CH (A) (when compare register is specified) 5 INTTM000 Match between TM00 and CR000 000EH (when compare register is specified) 6 INTTM010 Match between TM00 and CR010 0010H (when compare register is specified) Reset 7 INTAD End of A/D conversion 0012H 8 INTFLC End of flash memory programming 0014H 9 INTP2 Pin input edge detection 10 INTP3 11 INTTM80 Match between TM80 and CR80 12 INTSRE6 UART6 reception error occurrence 001CH 13 INTSR6 End of UART6 reception 001EH 14 INTST6 End of UART6 transmission 0020H - RESET Reset input POC Power-on-clear LVI Low-voltage detection WDT WDT overflow External 0016H (B) 0018H Internal - 001AH 0000H (A) - Note 4 Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 1 is the highest and 14 is the lowest. 2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 12-1. 3. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 0 is selected. 4. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 1 is selected. 214 Preliminary User's Manual U16898EJ1V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (B) External maskable interrupt Internal bus External interrupt mode register (INTM0, INTM1) Interrupt request Edge detector MK IE IF Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag Preliminary User's Manual U16898EJ1V0UD 215 CHAPTER 12 INTERRUPT FUNCTIONS 12.3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers. * Interrupt request flag registers (IF0, IF1) * Interrupt mask flag registers (MK0, MK1) * External interrupt mode registers (INTM0, INTM1) * Program status word (PSW) Table 12-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags. Table 12-2. Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag INTLVI LVIIF LVIMK INTP0 PIF0 PMK0 INTP1 PIF1 PMK1 INTTMH1 TMIFH1 TMMKH1 INTTM000 TMIF000 TMMK000 INTTM010 TMIF010 TMMK010 INTAD ADIF ADMK INTFLC FLIF FLMK INTP2 PIF2 PMK2 INTP3 PIF3 PMK3 INTTM80 TMIF80 TMMK80 INTSRE6 SREIF6 SREMK6 INTSR6 SRIF6 SRMK6 INTST6 STIF6 STMK6 216 Preliminary User's Manual U16898EJ1V0UD CHAPTER 12 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0, IF1) An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is acknowledged or when a reset signal is input. IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears IF0 and IF1 to 00H. Figure 12-2. Format of Interrupt Request Flag Registers (IF0, IF1) Address: FFE0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF0 ADIF TMIF010 TMIF000 TMIFH1 PIF1 PIF0 LVIIF 0 Address: FFE1H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF1 0 STIF6 SRIF6 SREIF6 TMIF80 PIF3 PIF2 FLIF xxIFx Interrupt request flag 0 No interrupt request signal has been issued. 1 An interrupt request signal has been issued; an interrupt request status. Caution Because P30, P31, P41, and P43 have an alternate function as external interrupt inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. Preliminary User's Manual U16898EJ1V0UD 217 CHAPTER 12 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0, MK1) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets MK0 and MK1 to FFH. Figure 12-3. Format of Interrupt Mask Flag Registers (MK0, MK1) Address: FFE4H Symbol <7> MK0 ADMK Address: FFE5H After reset: FFH <6> R/W <5> <4> TMMK010 TMMK000 TMMKH1 After reset: FFH <3> <2> <1> <0> PMK1 PMK0 LVIMK 1 R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK1 1 STMK6 SRMK6 SREMK6 TMMK80 PMK3 PMK2 FLMK xxMKx Interrupt servicing control 0 Enables interrupt servicing. 1 Disables interrupt servicing. Caution Because P30, P31, P41, and P43 have an alternate function as external interrupt inputs, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 218 Preliminary User's Manual U16898EJ1V0UD CHAPTER 12 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. Reset input clears INTM0 to 00H. Figure 12-4. Format of External Interrupt Mode Register 0 (INTM0) Address: FFECH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 INTM0 ES21 ES20 ES11 ES10 ES01 ES00 0 0 ES21 ES20 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES11 ES10 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES01 ES00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges INTP2 valid edge selection INTP1 valid edge selection INTP0 valid edge selection Cautions 1. Be sure to clear bits 0 and 1 to 0. 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag (xxMKx = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt request flag (xxIFx = 0), then clear the interrupt mask flag (xxMKx = 0), which will enable interrupts. Preliminary User's Manual U16898EJ1V0UD 219 CHAPTER 12 INTERRUPT FUNCTIONS (4) External interrupt mode register 1 (INTM1) INTM1 is used to specify the valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. Reset input clears INTM1 to 00H. Figure 12-5. Format of External Interrupt Mode Register 1 (INTM1) Address: FFEDH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 INTM1 0 0 0 0 0 0 ES31 ES30 ES31 ES30 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges INTP3 valid edge selection Cautions 1. Be sure to clear bits 2 to 7 to 0. 2. Before setting INTM1, set PMK3 to 1 to disable interrupts. To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0. (5) Program status word (PSW) The program status word is used to hold the instruction execution result and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW. PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically saved to a stack, and the IE flag is reset to 0. Reset input sets PSW to 02H. Figure 12-6. Program Status Word Configuration Symbol 7 6 5 4 3 2 1 0 After reset PSW IE Z 0 AC 0 0 1 CY 02H Used in the execution of ordinary instructions IE 220 Whether to enable/disable interrupt acknowledgment 0 Disabled 1 Enabled Preliminary User's Manual U16898EJ1V0UD CHAPTER 12 INTERRUPT FUNCTIONS 12.4 Interrupt Servicing Operation 12.4.1 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in Table 12-3. See Figures 12-8 and 12-9 for the interrupt request acknowledgment timing. Table 12-3. Time from Generation of Maskable Interrupt Request to Servicing Note Minimum Time 9 clocks Maximum Time 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instructions. Remark 1 clock: 1 (fCPU: CPU clock) fCPU When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. A pending interrupt is acknowledged when a status in which it can be acknowledged is set. Figure 12-7 shows the algorithm of interrupt request acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt servicing, use the RETI instruction. Preliminary User's Manual U16898EJ1V0UD 221 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-7. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (Interrupt request generated) xxMK = 0? No Yes Interrupt request pending No IE = 1? Yes Interrupt request pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag IE: Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable) Figure 12-8. Interrupt Request Acknowledgment Timing (Example of MOV A, r) 8 clocks Clock CPU MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set before an instruction clock n (n = 4 to 10) under execution becomes n - 1, the interrupt is acknowledged after the instruction under execution is complete. Figure 12-8 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment processing is performed after the MOV A, r instruction is executed. 222 Preliminary User's Manual U16898EJ1V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-9. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock CPU NOP MOV A, r Saving PSW and PC, jump to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag (xxIF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed. Figure 12-9 shows an example of the interrupt request acknowledgment timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is executed, and then the interrupt acknowledgment processing is performed. Caution Interrupt requests will be held pending while the interrupt request flag registers (IF0, IF1) or interrupt mask flag registers (MK0, MK1) are being accessed. Preliminary User's Manual U16898EJ1V0UD 223 CHAPTER 12 INTERRUPT FUNCTIONS 12.4.2 Multiple interrupt servicing Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing is performed according to the priority assigned to each interrupt request in advance (see Table 12-1). Figure 12-10. Example of Multiple Interrupts Example 1. Multiple interrupts are acknowledged INTxx servicing Main processing EI IE = 0 EI INTyy servicing IE = 0 INTyy INTxx RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. The EI instruction is issued before each interrupt request acknowledgment, and the interrupt request acknowledgment enable state is set. Example 2. Multiple interrupts are not generated because interrupts are not enabled INTxx servicing Main processing EI IE = 0 INTyy servicing INTyy is held pending INTyy RETI INTxx IE = 0 RETI Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is held pending and acknowledged after the INTxx servicing is performed. IE = 0: Interrupt request acknowledgment disabled 224 Preliminary User's Manual U16898EJ1V0UD CHAPTER 12 INTERRUPT FUNCTIONS 12.4.3 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated during the execution. The following shows such instructions (interrupt request pending instruction). * Manipulation instruction for interrupt request flag registers (IF0, IF1) * Manipulation instruction for interrupt mask flag registers (MK0, MK1) Preliminary User's Manual U16898EJ1V0UD 225 CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration 13.1.1 Standby function Table 13-1. Relationship Between Operation Clocks in Each Operation Status Status Low-Speed Ring-OSC Oscillator Note 1 Operation Mode Reset LSRSTOP = 0 Oscillating Oscillating Note 3 2. Hardware LSRSTOP = 1 Stopped Stopped Oscillating Oscillating Stopped HALT Notes 1. Clock Supplied to Peripheral Note 2 Stopped STOP System Clock When "Cannot be stopped" is selected for low-speed Ring-OSC by the option byte. When it is selected that the low-speed Ring-OSC oscillator "can be stopped by software", oscillation of the low-speed Ring-OSC oscillator can be stopped by LSRSTOP. 3. If the operating clock of the watchdog timer is the low-speed Ring-OSC clock, the watchdog timer is stopped. Caution The LSRSTOP setting is valid only when "Can be stopped by software" is set for the low-speed Ring-OSC oscillator by the option byte. Remark LSRSTOP: Bit 0 of the low-speed Ring-OSC mode register (LSRCM) The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. Oscillation of the system clock oscillator continues. If the low-speed Ring-OSC oscillator is operating before the HALT mode is set, oscillation of the clock of the low-speed Ring-OSC oscillator continues (refer to Table 13-1. Oscillation of the low-speed Ring-OSC clock (whether it cannot be stopped or can be stopped by software) is set by the option byte). In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations. 226 Preliminary User's Manual U16898EJ1V0UD CHAPTER 13 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, select the HALT mode if processing must be immediately started by an interrupt request when the STOP mode is released because the operation stops for the duration of eight clocks of the low-speed RingOSC clock (because an additional wait time for stabilizing oscillation elapses when crystal/ceramic oscillation is used). In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing STOP instruction (except the peripheral hardware that operates on the low-speed Ring-OSC clock). 2. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 3. If the low-speed Ring-OSC oscillator is operating before the STOP mode is set, oscillation of the low-speed Ring-OSC clock cannot be stopped in the STOP mode (refer to Table 13-1). Preliminary User's Manual U16898EJ1V0UD 227 CHAPTER 13 STANDBY FUNCTION 13.1.2 Registers used during standby The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time select register (OSTS). Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS. (1) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released. If the high-speed Ring-OSC oscillator or external clock input is selected as the system clock source, no wait time elapses. The system clock oscillator and the oscillation stabilization time that elapses after power application or release of reset are selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. OSTS is set by using the 8-bit memory manipulation instruction. Figure 13-1. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFF4H, After reset: Undefined, R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 0 0 2 /fX (102.4 s) 0 1 2 /fX (409.6 s) 1 0 2 /fX (3.27 ms) 1 1 2 /fX (13.1 ms) Selection of oscillation stabilization time 10 12 15 17 Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows. Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS 2. The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of whether STOP mode was released by reset input or interrupt generation. STOP mode is released Voltage waveform of X1 pin a 3. The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. Remarks 1. ( ): fX = 10 MHz 2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used. 228 Preliminary User's Manual U16898EJ1V0UD CHAPTER 13 STANDBY FUNCTION 13.2 Standby Function Operation 13.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Table 13-2. Operating Statuses in HALT Mode Setting of HALT Mode Item When Low-speed Ring-OSC Oscillation Continues System clock When Low-speed Ring-OSC Oscillation Stops Note 1 Clock supply to CPU is stopped. CPU Operation stops. Port (latch) Holds status before HALT mode was set. 16-bit timer/event counter 00 Operable 8-bit timer 80 Operable 8-bit timer Sets count clock to fXP to fXP/2 H1 Sets count clock to fRL/2 7 12 Operable Low-speed Ring-OSC - Operable Note 2 . cannot be stopped Low-speed Ring-OSC Operation stops. Note 2 can be stopped Watchdog "Clock to peripheral hardware" selected as timer operating clock . Operation stops. "Low-speed Ring-OSC Low-speed Ring-OSC clock" selected as cannot be stopped operating clock Low-speed Ring-OSC Operable - Note 2 . Operation stops. Note 2 can be stopped . A/D converter Operable Serial interface UART6 Operable Low-voltage detector Operable External interrupt Operable Notes 1. When "Stopped by software" is selected for low-speed Ring-OSC by the option byte and low-speed Ring- 2. "Low-speed Ring-OSC cannot be stopped" or "low-speed Ring-OSC can be stopped by software" can be OSC is stopped by software (for the option byte, see CHAPTER 17 OPTION BYTE). selected by the option byte. Preliminary User's Manual U16898EJ1V0UD 229 CHAPTER 13 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed. Figure 13-2. HALT Mode Release by Interrupt Request Generation Interrupt request HALT instruction Wait Standby release signal Status of CPU Operating mode HALT mode Wait Operating mode Oscillation System clock oscillation Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is carried out: 9 or 10 clocks * When vectored interrupt servicing is not carried out: 1 or 2 clocks 230 Preliminary User's Manual U16898EJ1V0UD CHAPTER 13 STANDBY FUNCTION (b) Release by reset input When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 13-3. HALT Mode Release by Reset Input (1) When CPU clock is high-speed Ring-OSC clock or external input clock HALT instruction Reset signal CPU status Operation mode Reset period HALT mode Oscillates System clock oscillation Operation stopsNote Oscillation stops Operation mode Oscillates (2) When CPU clock is crystal/ceramic oscillation clock HALT instruction Reset signal CPU status Operation mode Oscillation Reset Operation Operation period stopsNote stabilization waits mode HALT mode Oscillates System clock oscillation Oscillation stops Oscillates Oscillation stabilization time (210/fX to 217/fX) Note The operation is stopped (8/fRL + 96/fRH) because the option byte is referenced. Remark fX: System clock oscillation frequency fRL: Low-speed Ring-OSC clock oscillation frequency fRH: High-speed Ring-OSC clock oscillation frequency Table 13-3. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt request Reset input MKxx IE Operation 0 0 Next address instruction execution 0 1 Interrupt servicing execution 1 x HALT mode held - x Reset processing x: don't care Preliminary User's Manual U16898EJ1V0UD 231 CHAPTER 13 STANDBY FUNCTION 13.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, in the STOP mode, the normal operation mode is restored after the STOP instruction is executed and then the operation is stopped for the duration of eight low-speed Ring-OSC clocks (after an additional wait time for stabilizing oscillation set by the oscillation stabilization time select register (OSTS) has elapsed when crystal/ceramic oscillation is used). The operating statuses in the STOP mode are shown below. Table 13-4. Operating Statuses in STOP Mode Setting of STOP Mode Item When Low-Speed Ring-OSC Oscillation Continues When Low-Speed Ring-OSC Oscillation Stops System clock Oscillation stops. CPU Operation stops. Port (latch) Holds status before STOP mode is set. 16-bit timer/event counter 00 Operation stops. 8-bit timer 80 Note 1 Operation stops. 8-bit timer Sets count clock to fXP to fXP/2 H1 Sets count clock to fRL/2 7 12 Operation stops. Low-speed Ring-OSC - Operable Note 2 . cannot be stopped Low-speed Ring-OSC Operation stops. Note 2 can be stopped Watchdog "Clock to peripheral hardware" selected as timer operating clock . Operation stops. "Low-speed Ring-OSC Low-speed Ring-OSC clock" selected as cannot be stopped operating clock Low-speed Ring-OSC Operable - Note 2 . Operation stops. Note 2 can be stopped . A/D converter Operation stops. Serial interface UART6 Operation stops. Low-voltage detector Operable External interrupt Operable Notes 1. When "Stopped by software" is selected for low-speed Ring-OSC by the option byte the low-speed RingOSC is stopped by software (for the option byte, see CHAPTER 17 OPTION BYTE). 2. "Low-speed Ring-OSC cannot be stopped" or "low-speed Ring-OSC can be stopped by software" can be selected by the option byte. 232 Preliminary User's Manual U16898EJ1V0UD CHAPTER 13 STANDBY FUNCTION (2) STOP mode release Figure 13-4. Operation Timing When STOP Mode Is Released <1> If high-speed Ring-OSC clock or external input clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation CPU clock Operation stops (8/fRL). High-speed Ring-OSC clock or external clock input <2> If crystal/ceramic oscillation clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation CPU clock Remark Operation stops (8/fRL). HALT status (oscillation stabilization time set by OSTS) Crystal/ceramic oscillation clock fRL: Low-speed Ring-OSC clock oscillation frequency The STOP mode can be released by the following two sources. Preliminary User's Manual U16898EJ1V0UD 233 CHAPTER 13 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 13-5. STOP Mode Release by Interrupt Request Generation (1) If CPU clock is high-speed Ring-OSC clock or external input clock Interrupt request STOP instruction Standby release signal Operation mode CPU status STOP mode Operation stops. Operation mode (8/fRL) Oscillation stops. Oscillation System clock oscillation Oscillation (2) If CPU clock is crystal/ceramic oscillation clock Interrupt request STOP instruction Standby release signal CPU status Operation mode System clock Oscillation STOP mode Operation Waiting for stabilization stops. of oscillation (HALT mode status) (8/fRL) Operation mode Oscillation Oscillation stops. Oscillation stabilization time (set by OSTS) Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 2. fRL: Low-speed Ring-OSC clock oscillation frequency 234 Preliminary User's Manual U16898EJ1V0UD CHAPTER 13 STANDBY FUNCTION (b) Release by reset input When the reset signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 13-6. STOP Mode Release by Reset Input (1) If CPU clock is high-speed Ring-OSC clock or external input clock STOP instruction Reset signal CPU status System clock oscillation Operation mode Reset period STOP mode Oscillation Operation stopsNote. Oscillation stops. Operation mode Oscillation (2) If CPU clock is crystal/ceramic oscillation clock STOP instruction Reset signal CPU status System clock oscillation Operation mode Reset period STOP mode Oscillation Oscillation Operation Operation stopsNote. stabilization waits mode Oscillation stops. Oscillation Oscillation stabilization time (210/fX to 217/fX) Note The operation is stopped (8/fRL + 96/fRH) because the option byte is referenced. Remark fX: System clock oscillation frequency fRL: Low-speed Ring-OSC clock oscillation frequency fRH: High-speed Ring-OSC clock oscillation frequency Table 13-5. Operation in Response to Interrupt Request in STOP Mode Release Source MKxx Maskable interrupt request Reset input IE Operation 0 0 Next address instruction execution 0 1 Interrupt servicing execution 1 x STOP mode held - x Reset processing x: don't care Preliminary User's Manual U16898EJ1V0UD 235 CHAPTER 14 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H when the reset signal is input. A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit voltage detection, and each item of hardware is set to the status shown in Table 14-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset release, except for P130, which is low-level output. When a high level is input to the RESET pin, the reset is released and program execution starts using the CPU clock after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). A reset generated by the watchdog timer source is automatically released after the reset, and program execution starts using the CPU clock after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). (see Figures 14-2 to 14-4). Reset by POC and LVI circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and program execution starts using the CPU clock after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected) (see CHAPTER 15 POWER-ON-CLEAR CIRCUIT and CHAPTER 16 LOW-VOLTAGE DETECTOR). Cautions 1. For an external reset, input a low level for 1 s or more to the RESET pin. 2. During reset input, the system clock and low-speed Ring-OSC clock stop oscillating. 3. When the RESET pin is used as an input-only port pin (P34), the 78K0S/KA1+ is reset if a low level is input to the RESET pin after reset is released by the POC circuit and before the option byte is referenced again. The reset status is retained until a high level is input to the RESET pin. 236 Preliminary User's Manual U16898EJ1V0UD CHAPTER 14 RESET FUNCTION Figure 14-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF Reset signal of watchdog timer Set LVIRF Set Clear Clear Reset signal RESET Reset signal to LVIM/LVIS register Reset signal of power-on-clear circuit Reset signal Reset signal of low-voltage detector Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit. Remarks 1. LVIM: Low-voltage detect register 2. LVIS: Low-voltage detection level select register Preliminary User's Manual U16898EJ1V0UD 237 CHAPTER 14 RESET FUNCTION Figure 14-2. Timing of Reset by RESET Input <1> With high-speed Ring-OSC clock or external clock input High-speed Ring-OSC clock or external clock input CPU clock Normal operation in progress Reset period (oscillation stops) Normal operation (reset processing, CPU clock) RESET Operation stops because option byte is referenced. (8/fRL + 96/fRH) Internal reset signal Delay Delay Hi-ZNote Port pin <2> With crystal/ceramic oscillation clock Crystal/ceramic oscillation clock CPU clock Normal operation in progress Reset period (oscillation stops) RESET Oscillation stabilization time (210/fX to 217/fX) Normal operation (reset processing, CPU clock) Operation stops because option byte is referenced. (8/fRL + 96/fRH) Internal reset signal Delay Delay Hi-ZNote Port pin Note P130 outputs a low level, and the other port pins go into a high-impedance state. Remark fX: System clock oscillation frequency fRL: Low-speed Ring-OSC clock oscillation frequency fRH: High-speed Ring-OSC clock oscillation frequency 238 Preliminary User's Manual U16898EJ1V0UD CHAPTER 14 RESET FUNCTION Figure 14-3. Timing of Reset by Overflow of Watchdog Timer <1> With high-speed Ring-OSC clock or external clock input High-speed Ring-OSC clock or external clock input CPU clock Normal operation in progress Reset period (oscillation stops) Normal operation (reset processing, CPU clock) Operation stops because option byte is referenced. (8/fRL + 96/fRH) Watchdog timer overflow Internal reset signal Hi-ZNote Port pin <2> With crystal/ceramic oscillation clock Crystal/ceramic oscillation clock CPU clock Normal operation in progress Reset period (oscillation stops) Oscillation stabilization time (210/fX to 217/fX) Normal operation (reset processing, CPU clock) Operation stops because option byte is referenced. (8/fRL + 96/fRH) Watchdog timer overflow Internal reset signal Hi-ZNote Port pin Note P130 outputs a low level, and the other port pins go into a high-impedance state. Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer. Remark fX: System clock oscillation frequency fRL: Low-speed Ring-OSC clock oscillation frequency fRH: High-speed Ring-OSC clock oscillation frequency Preliminary User's Manual U16898EJ1V0UD 239 CHAPTER 14 RESET FUNCTION Figure 14-4. Reset Timing by RESET Input in STOP Mode <1> With high-speed Ring-OSC clock or external clock input STOP instruction is executed. High-speed Ring-OSC clock or external clock input CPU clock Normal operation in progress Stop status (oscillation stops) Reset period (oscillation stops) Normal operation (reset processing, CPU clock) RESET Operation stops because option byte is referenced. (8/fRL + 96/fRH) Internal reset signal Delay Delay Hi-ZNote Port pin <2> With crystal/ceramic oscillation clock STOP instruction is executed. Crystal/ceramic oscillation clock CPU clock Normal operation in progress Stop status (oscillation stops) Reset period (oscillation stops) RESET Oscillation stabilization time (210/fX to 217/fX) Normal operation (reset processing, CPU clock) Operation stops because option byte is referenced. (8/fRL + 96/fRH) Internal reset signal Delay Delay Hi-ZNote Port pin Note P130 outputs a low level, and the other port pins go into a high-impedance state. Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 15 POWER-ON-CLEAR CIRCUIT and CHAPTER 16 LOW-VOLTAGE DETECTOR. 2. fX: System clock oscillation frequency fRL: Low-speed Ring-OSC clock oscillation frequency fRH: High-speed Ring-OSC clock oscillation frequency 240 Preliminary User's Manual U16898EJ1V0UD CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Program counter (PC) Note 1 Status After Reset Contents of reset vector table (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined General-purpose registers Undefined Ports (P2 to P4, P12, P13) (output latches) 00H Port mode registers (PM2 to PM4, PM12) FFH Port mode control register (PMC2) 00H Pull-up resistor option registers (PU2, PU3, PU4, PU12) 00H Processor clock control register (PCC) 02H Preprocessor clock control register (PPCC) 02H Low-speed Ring-OSC mode register (LSRCM) 00H High-speed Ring-OSC mode register (HSRCM) 00H Oscillation stabilization time select register (OSTS) Undefined 16-bit timer 00 Timer counter 00 (TM00) 0000H Capture/compare registers 000, 010 (CR000, CR010) 0000H Mode control register 00 (TMC00) 00H Prescaler mode register 00 (PRM00) 00H Capture/compare control register 00 (CRC00) 00H Timer output control register 00 (TOC00) 00H Timer counter 80 (TM80) 00H Compare register (CR80) Undefined Mode control register 80 (TMC80) 00H Compare registers (CMP01, CMP11) 00H Mode register 1 (TMHMD1) 00H Mode register (WDTM) 67H Enable register (WDTE) 9AH Conversion result registers (ADCR, ADCRH) Undefined Mode register (ADM) 00H Analog input channel specification register (ADS) 00H 8-bit timer 80 8-bit timer H1 Watchdog timer A/D converter Notes 1. Note 2 Note 2 Only the contents of PC are undefined while reset is being input and while the oscillation stabilization time elapses. The statuses of the other hardware units remain unchanged. 2. The status after reset is held in the standby mode. Preliminary User's Manual U16898EJ1V0UD 241 CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Serial interface UART6 Status After Reset Receive buffer register 6 (RXB6) FFH Transmit buffer register 6 (TXB6) FFH Asynchronous serial interface operation mode register 6 (ASIM6) 01H Asynchronous serial interface reception error status register 6 00H (ASIS6) Asynchronous serial interface transmission error status register 6 00H (ASIF6) Clock select register 6 (CKSR6) 00H Baud rate generator control register 6 (BRGC6) FFH Asynchronous serial interface control register 6 (ASICL6) 16H Input select control register (ISC) 00H Reset function Reset control flag register (RESF) 00H Low-voltage detector Low-voltage detection register (LVIM) 00H Low-voltage detection level select register (LVIS) 00H Request flag registers (IF0, IF1) 00H Mask flag registers (MK0, MK1) FFH External interrupt mode registers (INTM0, INTM1) 00H Interrupt Note Note Note Note These values change as follows depending on the reset source. Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Register RESF See Table 14-2. LVIM Cleared (00H) Cleared (00H) Cleared (00H) LVIS 242 Preliminary User's Manual U16898EJ1V0UD Held CHAPTER 14 RESET FUNCTION 14.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0S/KA1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H. Figure 14-5. Format of Reset Control Flag Register (RESF) Address: FF54H After reset: 00H Note R Symbol 7 6 5 4 3 2 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer (WDT) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. LVIRF Internal reset request by low-voltage detector (LVI) 0 Internal reset request is not generated, or RESF is cleared. 1 Internal reset request is generated. Note The value after reset varies depending on the reset source. Caution Do not read data by a 1-bit memory manipulation instruction. The status of RESF when a reset request is generated is shown in Table 14-2. Table 14-2. RESF Status When Reset Request Is Generated Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Flag WDTRF LVIRF Cleared (0) Cleared (0) Set (1) Held Held Set (1) Preliminary User's Manual U16898EJ1V0UD 243 CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. * Generates internal reset signal at power on. * Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V 0.1 V), and generates internal reset signal when VDD < VPOC. Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is cleared to 00H. 2. Because the detection voltage (VPOC) of the POC circuit is in a range of 2.1 V 0.1 V, use a voltage in the range of 2.2 to 5.5 V. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT) or low-voltage-detection (LVI) circuit. RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI. For details of RESF, see CHAPTER 14 RESET FUNCTION. 244 Preliminary User's Manual U16898EJ1V0UD CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 15-1. Figure 15-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal - Detection voltage source (VPOC) 15.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC = 2.1 V 0.1 V) are compared, and when VDD < VPOC, an internal reset signal is generated. Figure 15-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit Supply voltage (VDD) POC detection voltage (VPOC = 2.1 V0.1V) Time Internal reset signal Preliminary User's Manual U16898EJ1V0UD 245 CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. <Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. Figure 15-3. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Reset Check reset source Note 2 ; The reset source (power-on clear, WDT, or LVI) can be identified by the RESF register. Power-on clear Timer starts (set to 50 ms) ; 8-bit timer H1 can operate on the low-speed Ring-OSC clock. Source: fRL (480 kHz (MAX.))/27 x compare value 200 = 53 ms (fRL: Low-speed Ring-OSC clock oscillation frequency) Note 1 No 50 ms has passed? (TMIFH1 = 1?) ; TMIFH1 = 1: Interrupt request is generated. Yes Initialization processing Notes 1. 2. 246 ; Initialization of ports, etc. If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page. Preliminary User's Manual U16898EJ1V0UD CHAPTER 15 POWER-ON-CLEAR CIRCUIT Figure 15-3. Example of Software Processing After Release of Reset (2/2) * Checking reset cause Check reset source Yes WDTRF of RESF register = 1? No Reset processing by watchdog timer Yes LVIRF of RESF register = 1? No Reset processing by low-voltage detector Power-on clear/external reset generated Preliminary User's Manual U16898EJ1V0UD 247 CHAPTER 16 LOW-VOLTAGE DETECTOR 16.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. * Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or internal reset signal when VDD < VLVI. * Detection levels (ten levels) of supply voltage can be changed by software. * Interrupt or reset function can be selected by software. * Operable in STOP mode. When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of RESF, refer to CHAPTER 14 RESET FUNCTION. 16.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 16-1. Figure 16-1. Block Diagram of Low-Voltage Detector Low-voltage detection level selector VDD VDD N-ch Selector Internal reset signal + - INTLVI Detection voltage source (VLVI) 4 LVION LVIMD LVIS3 LVIS2 LVIS1 LVIS0 Low-voltage detection level select register (LVIS) LVIF Low-voltage detect register (LVIM) Internal bus 248 Preliminary User's Manual U16898EJ1V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR 16.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. * Low-voltage detect register (LVIM) * Low-voltage detection level select register (LVIS) (1) Low-voltage detect register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 16-2. Format of Low-Voltage Detect Register (LVIM) Address: FF50H After reset: 00H R/WNote 1 Symbol <7> 6 5 4 3 2 <1> <0> LVIM LVION 0 0 0 0 0 LVIMD LVIF Notes 2, 3 LVION Enabling low-voltage detection operation 0 Disable operation 1 Enable operation Note 2 LVIMD Low-voltage detection operation mode selection 0 Generate interrupt signal when supply voltage (VDD) < detection voltage (VLVI) 1 Generate internal reset signal when supply voltage (VDD) < detection voltage (VLVI) Note 4 LVIF Low-voltage detection flag 0 Supply voltage (VDD) > detection voltage (VLVI), or when operation is disabled 1 Supply voltage (VDD) < detection voltage (VLVI) Notes 1. Bit 0 is a read-only bit. 2. LVION, and LVIMD are cleared to 0 at a reset other than an LVI reset. These are not cleared 3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. to 0 at an LVI reset. Use software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is confirmed at LVIF. 4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and LVIMD = 0. Cautions 1. To stop LVI, follow either of the procedures below. * When using 8-bit manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Be sure to set bits 2 to 6 to 0. Preliminary User's Manual U16898EJ1V0UD 249 CHAPTER 16 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 16-3. Format of Low-Voltage Detection Level Select Register (LVIS) Address: FF51H, After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 0 0 0 0 VLVI0 (4.3 V 0.2 V) 0 0 0 1 VLVI1 (4.1 V 0.2 V) 0 0 1 0 VLVI2 (3.9 V 0.2 V) 0 0 1 1 VLVI3 (3.7 V 0.2 V) 0 1 0 0 VLVI4 (3.5 V 0.2 V) 0 1 0 1 VLVI5 (3.3 V 0.15 V) 0 1 1 0 VLVI6 (3.1 V 0.15 V) 0 1 1 1 VLVI7 (2.85 V 0.15 V) 1 0 0 0 VLVI8 (2.6 V 0.15 V) 1 0 0 1 VLVI9 (2.35 V 0.15 V) Other than above Caution 250 Detection level Setting prohibited Bits 4 to 7 must be set to 0. Preliminary User's Manual U16898EJ1V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR 16.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. * Used as reset Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when VDD < VLVI. * Used as interrupt Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI) when VDD < VLVI. The operation is set as follows. (1) When used as reset * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to instigate a wait of at least 0.2 ms. <5> Wait until "supply voltage (VDD) > detection voltage (VLVI)" at bit 0 (LVIF) of LVIM is confirmed. <6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)). Figure 16-4 shows the timing of generating the internal reset signal of the low-voltage detector. Numbers <1> to <6> in this figure correspond to <1> to <6> above. Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after the processing in <3>. 2. If supply voltage (VDD) > detection voltage (VLVI) when LVIM is set to 1, an internal reset signal is not generated. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order. Preliminary User's Manual U16898EJ1V0UD 251 CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) Time <2> LVIMK flag (set by software) <1> LVION flag (set by software) Not cleared Not cleared <3> Clear <4> 0.2 ms or longer LVIF flag <5> LVIMD flag (set by software) Clear Not cleared Not cleared <6> Clear LVIRF flagNote LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Note LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 14 RESET FUNCTION. Remark <1> to <6> in Figure 16-4 above correspond to <1> to <6> in the description of "when starting operation" in 16.4 (1) When used as reset. 252 Preliminary User's Manual U16898EJ1V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR (2) When used as interrupt * When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to instigate a wait of at least 0.2 ms. <5> Wait until "supply voltage (VDD) > detection voltage (VLVI)" at bit 0 (LVIF) of LVIM is confirmed. <6> Clear the interrupt request flag of LVI (LVIIF) to 0. <7> Release the interrupt mask flag of LVI (LVIMK). <8> Execute the EI instruction (when vector interrupts are used). Figure 16-5 shows the timing of generating the interrupt signal of the low-voltage detector. Numbers <1> to <7> in this figure correspond to <1> to <7> above. * When stopping operation Either of the following procedures must be executed. * When using 8-bit memory manipulation instruction: Write 00H to LVIM. * When using 1-bit memory manipulation instruction: Clear LVION to 0. Figure 16-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (VDD) LVI detection voltage (VLVI) POC detection voltage (VPOC) Time <2> LVIMK flag (set by software) <1> <7> Cleared by software LVION flag (set by software) <3> <4> 0.2 ms or longer LVIF flag <5> INTLVI LVIIF flag <6> Cleared by software Internal reset signal Remark <1> to <7> in Figure 16-5 above correspond to <1> to <7> in the description of "when starting operation" in 16.4 (2) When used as interrupt. Preliminary User's Manual U16898EJ1V0UD 253 CHAPTER 16 LOW-VOLTAGE DETECTOR 16.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. <1> When used as reset The system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. <2> When used as interrupt Interrupt requests may be frequently generated. Take action (2) below. In this system, take the following actions. <Action> (1) When used as reset After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. 254 Preliminary User's Manual U16898EJ1V0UD CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-6. Example of Software Processing After Release of Reset (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Check reset sourceNote 2 ; The reset source (power-on clear, WDT, or LVI) can be identified by the RESF register. LVI Start timer (set to 50 ms) ; 8-bit timer H1 can operate with the low-speed Ring-OSC clock. Source: fRL (480 kHz (MAX.))/27 x compare value 200 = 53 ms (fRL: low-speed Ring-OSC clock oscillation frequency) Note 1 No 50 ms has passed? (TMIFH1 = 1?) ; TMIFH1 = 1: Interrupt request is generated. Yes Initialization processing Notes 1. 2. ; Initialization of ports If reset is generated again during this period, initialization processing is not started. A flowchart is shown on the next page. Preliminary User's Manual U16898EJ1V0UD 255 CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-6. Example of Software Processing After Release of Reset (2/2) * Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector (2) When used as interrupt Check that "supply voltage (VDD) > detection voltage (VLVI)" in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt request flag register 0 (IF0) to 0 and enable interrupts (EI). In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for the supply voltage fluctuation period, check that "supply voltage (VDD) > detection voltage (VLVI)" using the LVIF flag, and then enable interrupts (EI). 256 Preliminary User's Manual U16898EJ1V0UD CHAPTER 17 OPTION BYTE The 78K0S/KA1+ has an area called an option byte at address 0080H of the flash memory. When using the product, be sure to set the following functions by using the option byte. 1. Selection of system clock source * High-speed Ring-OSC clock * Crystal/ceramic oscillation clock * External clock input 2. Low-speed Ring-OSC clock oscillation * Cannot be stopped. * Can be stopped by software. 3. Control of RESET pin * Used as RESET pin * RESET pin is used as an input port pin (P34). 4. Oscillation stabilization time on power application or reset input * 210/fX * 212/fX * 215/fX 17 * 2 /fX Figure 17-1. Positioning of Option Byte 07FFH/0FFFH Flash memory (2048/4096 x 8 bits) 0080H Option byte 1 0000H DEF DEF OSTS1 OSTS0 Preliminary User's Manual U16898EJ1V0UD 1 RMCE OSCSEL1 OSCSEL0 RINGOSC 257 CHAPTER 17 OPTION BYTE Figure 17-2. Format of Option Byte (1/2) Address: FF80H 7 6 5 4 3 2 1 0 1 DEFOSTS1 DEFOSTS0 1 RMCE OSCSEL1 OSCSEL0 RINGOSC RINGOSC Low-speed Ring-OSC clock oscillation 1 Cannot be stopped 0 Can be stopped by software Cautions 1. If it is selected that low-speed Ring-OSC clock oscillation cannot be stopped, the count clock to the watchdog timer (WDT) is fixed to low-speed Ring-OSC. 2. If it is selected that low-speed Ring-OSC can be stopped by software, supply of the count clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of bit 0 (LSRSTOP) of the low-speed Ring-OSC mode register (LSRCM). If low-speed Ring-OSC is selected as the count clock to 8-bit timer H1, however, the count clock is supplied in the HALT/STOP mode while low-speed Ring-OSC operates (LSRSTOP = 0). OSCSEL1 OSCSEL0 Selection of system clock source 0 0 Crystal/ceramic oscillation clock 0 1 External clock input 1 x High-speed Ring-OSC clock Caution Because the X1 and X2 pins are also used as the P121 and P122 pins, the conditions under which the X1 and X2 pins can be used as port pins differ depending on the selected system clock source. (1) High-speed Ring-OSC clock P121 and P122 can be used as I/O port pins. (2) Crystal/ceramic oscillation clock The X1 and X2 pins cannot be used as I/O port pins because they are used as clock input pins. (3) External clock input Because the X1 pin is used as an external clock input pin, P121 cannot be used as an I/O port pin. Remark x : don't care RMCE Control of RESET pin 1 RESET pin is used as is. 0 RESET pin is used as input port pin (P34). Caution If a low level is input to the RESET pin after reset is released by the power-on clear function and before the option byte is referenced again, the 78K0S/KA1+ is reset, and the status is held until a high level is input to the RESET pin. 258 Preliminary User's Manual U16898EJ1V0UD CHAPTER 17 OPTION BYTE Figure 17-2. Format of Option Byte (2/2) DEFOSTS1 DEFOSTS0 Oscillation stabilization time on power application or reset input 0 0 2 /fx (102.4 s) 0 1 2 /fx (409.6 s) 1 0 2 /fx (3.27 ms) 1 1 2 /fx (13.1 ms) 10 12 15 17 Caution The setting of this option is valid only when the crystal/ceramic oscillation clock is selected as the system clock source. No wait time elapses if the high-speed Ring-OSC or external clock input is selected as the system clock source. Remarks 1. ( ): fX = 10 MHz 2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator to be used. Preliminary User's Manual U16898EJ1V0UD 259 CHAPTER 18 FLASH MEMORY Flash memory versions are commonly used in the following development environments and mass production applications. { For altering software after the 78K0S/KA1+ is soldered onto the target system. { For data adjustment when starting mass production. { For differentiating software according to the specification in small scale production of various models. { For facilitating inventory management. { For updating software after shipment. Caution For the electrical specifications related to the flash memory rewriting, refer to CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES). 18.1 Features { Capacity: 4 KB/2 KB { Write voltage: Erase/write with a single power supply { Rewriting method * Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) * Rewriting flash memory by user program (self programming) { Flash memory write prohibit function supported (security function) 260 Preliminary User's Manual U16898EJ1V0UD CHAPTER 18 FLASH MEMORY 18.2 Memory Configuration The 4/2 KB internal flash memory area is divided into 16/8 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. Figure 18-1. Flash Memory Mapping 0FFFH Block 15 (256 bytes) 0F00H 0EFFH Block 14 (256 bytes) 0E00H 0DFFH FFFFH Block 13 (256 bytes) 0D00H 0CFFH Special function resister (256 bytes) Block 12 (256 bytes) FF00H FEFFH 0C00H 0BFFH Block 11 (256 bytes) 0B00H 0AFFH Internal high-speed RAM (128/256 bytes) Block 10 (256 bytes) 0A00H 09FFH Block 9 (256 bytes) 0900H 08FFH Block 8 (256 bytes) 0800H 07FFH Use prohibited Block 7 (256 bytes) Block 7 (256 bytes) Block 6 (256 bytes) Block 6 (256 bytes) Block 5 (256 bytes) Block 5 (256 bytes) 0700H 06FFH 0600H 05FFH 0500H 04FFH Block 4 (256 bytes) Block 4 (256 bytes) 0400H 03FFH Block 3 (256 bytes) Flash memory (2/4 KB) Block 2 (256 bytes) Block 3 (256 bytes) Block 2 (256 bytes) 0300H 02FFH 0200H 01FFH 0000H Block 1 (256 bytes) Block 1 (256 bytes) Block 0 (256 bytes) Block 0 (256 bytes) 2 KB 4 KB Preliminary User's Manual U16898EJ1V0UD 0100H 00FFH 0000H 261 CHAPTER 18 FLASH MEMORY 18.3 Functional Outline The internal flash memory of the 78K0S/KA1+ can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the 78K0S/KA1+ has already been mounted on the target system or not (onboard/off-board programming). In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program cannot be changed by an unauthorized person. The rewrite function using the user program (self programming) is ideal for an application where it is assumed that the program is changed after production/shipment of the target system. Table 18-1. Rewrite Method Rewrite Method On-board programming Off-board programming Functional Outline Operation Mode Flash memory can be rewritten after the device is mounted on the Flash memory target system, by using a dedicated flash programmer. programming mode Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (FA series). Self programming Flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/offboard programming. Remark 262 The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Preliminary User's Manual U16898EJ1V0UD Normal operation mode CHAPTER 18 FLASH MEMORY Table 18-2. Basic Functions Function Block erasure Chip erasure Functional Outline Support ({: Supported, x: Not supported) On-Board/Off-Board Programming Self Programming The contents of specified memory blocks are erased. { { The contents of the entire memory area { x { { { x are erased all at once. Write Writing to specified addresses, and a verify check to see if write level is secured are performed. Checksum Data read from the flash memory is compared with data transferred from the flash programmer. Security setting Use of the block erase command, chip { erase command, and program command can be prohibited. x (Only values set by onboard/off-board programming can be retained) The following table lists the security functions. The block erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. Each security function can be used in combination with the others at the same time. Table 18-3. Security Functions Function Function Outline Rewriting Operation When Prohibited ({: Executable, x: Not Executable) On-Board/Off-Board Self Programming Programming Block erase Execution of a block erase command on Block erase command: x Can always be rewritten command prohibit all blocks is prohibited. Setting of Chip erase command: { Program command: { regardless of setting of prohibition Chip erase Execution of block erase and chip erase Block erase command: x command prohibit commands on all the blocks is prohibited. Chip erase command: x Program command: { prohibition can be initialized by execution of a chip erase command. Once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. Program Write and block erase commands on all Block erase command: x command prohibit the blocks are prohibited. Setting of Chip erase command: { Program command: x prohibition can be initialized by execution of the chip erase command. Preliminary User's Manual U16898EJ1V0UD 263 CHAPTER 18 FLASH MEMORY 18.4 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0S/KA1+ has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0S/KA1+ is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. Table 18-4. Wiring Between 78K0S/KA1+ and Dedicated Flash Programmer Pin Configuration of Dedicated Flash Programmer Pin Name CLK Note I/O Pin Function Output Clock to 78K0S/KA1+ Output On-board mode signal Note Input Receive signal Note Output Receive signal/on-board mode signal /RESET Output VDD I/O FLMD0 Note RxD TxD GND - Pin Configuration of 78K0S/KA1+ Pin Name Pin No. X1 2 X2 3 Reset signal RESET 6 VDD voltage generation VDD 5 Ground VSS 1 Note In the 78K0S/KA1+, the CLK and FLMD0 signals are connected to the X1 pin and the RxD and TxD signals to the X2 signal; therefore, these signals need to be directly connected. However, the dedicated flash programmer provides a dedicated adapter for the 78K0S/KA1+, so signals do not need to be internally connected. Therefore, connect the X1 or X2 pin on-board to either one of the corresponding signal lines. 264 Preliminary User's Manual U16898EJ1V0UD CHAPTER 18 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 18-2. Example of Wiring Adapter for Flash Memory Writing VDD (2.7 to 5.5 V) GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 GND VDD VDD2 RFU3 FLASH WRITER INTERFACE SI SO RFU2 SCK RFU1 CLK VDE /RESET FLMD1 VPP Preliminary User's Manual U16898EJ1V0UD FLMD0 RESERVE/HS 265 CHAPTER 18 FLASH MEMORY 18.5 Programming Environment The environment required for writing a program to the flash memory is illustrated below. Figure 18-3. Environment for Writing Program to Flash Memory VDD XXX YYY XXXXXX VSS XXXX XXXX YYYY Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 (Flash Pro4) XXXXX RS-232C RESET USB DGCLKNote Dedicated flash programmer 78K0S/KA1+ DGDATANote Host machine Note DGCLK and DGDATA are single-wire bidirectional communication interfaces. They use UART as the communication mode. A host machine that controls the dedicated flash programmer is necessary. UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash programmer and the 78K0S/KA1+. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. 18.6 Communication Mode Communication between the dedicated flash programmer and the 78K0S/KA1+ is established by serial communication via UART using the X1 or X2 pin of the 78K0S/KA1+. * Transfer rate: 115200 bps Figure 18-4. Communication with Dedicated Flash Programmer VDD GND VSS XXXXXX XXXX Bxxxxx Cxxxxxx STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx VDD /RESET CLK Dedicated flash programmer RESET X1 FLMD0 RxD 78K0S/KA1+ X2 TxD 266 Preliminary User's Manual U16898EJ1V0UD CHAPTER 18 FLASH MEMORY 18.7 Processing of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be processed as described below. 18.7.1 X1 and X2 pins The X1 and X2 pins are used as the serial interface of flash memory programming. Therefore, if the X1 and X2 pins are connected to an external device, a signal conflict occurs. To prevent the conflict of signals, isolate the connection with the external device. 18.7.2 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash programmer. Figure 18-5. Signal Collision (RESET Pin) 78K0S/KA1+ Signal collision RESET Dedicated flash programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer. Therefore, isolate the signal of the reset signal generator. 18.7.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to VDD or VSS via a resistor. 18.7.4 Power supply Connect the VDD pin to VDD of the flash programmer, and the VSS pin to VSS of the flash programmer. Supply AVREF with the same power supply as that in the normal operation mode. Preliminary User's Manual U16898EJ1V0UD 267 CHAPTER 18 FLASH MEMORY 18.8 Programming Method 18.8.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 18-6. Flash Memory Manipulation Procedure Start Flash memory programming mode is set Manipulate flash memory End? No Yes End 268 Preliminary User's Manual U16898EJ1V0UD CHAPTER 18 FLASH MEMORY 18.8.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0S/KA1+ in the flash memory programming mode. When the 78K0S/KA1+ is connected to the flash programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory programming mode. Change the mode by using a jumper when writing the flash memory on-board. 18.8.3 Communication commands The 78K0S/KA1+ communicates with the dedicated flash programmer by using commands. The signals sent from the flash programmer to the 78K0S/KA1+ are called commands, and the commands sent from the 78K0S/KA1+ to the dedicated flash programmer are called response commands. Figure 18-7. Communication Commands XXXXXX Command XXXX STATVE PG-FP4 (Flash Pro4) XXXXX XXX YYY XXXX YYYY Axxxx Bxxxxx Cxxxxxx Dedicated flash programmer Response command 78K0S/KA1+ The flash memory control commands of the 78K0S/KA1+ are listed in the table below. All these commands are issued from the programmer and the 78K0S/KA1+ perform processing corresponding to the respective commands. Table 18-5. Flash Memory Control Commands Classification Command Name Erase Write Function Batch erase command Erases the contents of the entire memory Block erase command Erases the contents of the memory of the specified block Write command Writes to the specified address range and executes a verify check of the contents. Checksum Checksum command Reads the checksum of the specified address range and compares with the written data. Security Security set command Prohibits chip erase command, block erase command, and write command to prevent operation by third parties. The 78K0S/KA1+ returns a response command for the command issued by the dedicated flash programmer. The response commands sent from the 78K0S/KA1+ are listed below. Table 18-6. Response Commands Command Name Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. Preliminary User's Manual U16898EJ1V0UD 269 CHAPTER 18 FLASH MEMORY 18.9 Flash Memory Programming by Self Writing The 78K0S/KA1+ supports a self programming function that can be used to rewrite the flash memory via a user program, making it possible to upgrade programs in the field. Cautions 1. Self programming processing must have been implemented before performing self writing. 2. Temporarily store the data to be rewritten in the internal high-speed RAM. 3. Switch the CPU clock to high-speed Ring-OSC when executing self programming. 4. Interrupt processing cannot be used while self programming is in progress. 270 Preliminary User's Manual U16898EJ1V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the 78K0S/KA1+. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E). 19.1 Operation 19.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 19-1. Operand Identifiers and Description Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp sfr AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even addresses only) addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) addr5 0040H to 007FH Immediate data or labels (even addresses only) word 16-bit immediate data or label byte bit 8-bit immediate data or label 3-bit immediate data or label Remark For symbols of special function registers, see Table 4-3 Special Function Registers. Preliminary User's Manual U16898EJ1V0UD 271 CHAPTER 19 INSTRUCTION SET OVERVIEW 19.1.2 Description of "Operation" column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag indicating non-maskable interrupt servicing in progress ( ): Memory contents indicated by address or register contents in parentheses xH, xL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : : Inverted data Exclusive logical sum (exclusive OR) addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 19.1.3 Description of "Flag" column 272 (Blank): Unchanged 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is stored Preliminary User's Manual U16898EJ1V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW 19.2 Operation List Mnemonic Operand Bytes Clocks Operation Flag Z MOV XCH r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte A, r Note 1 2 4 Ar r, A Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL + byte] 2 6 A (HL + byte) [HL + byte], A 2 6 (HL + byte) A 1 4 AX 2 6 Ar A, saddr 2 6 A (saddr) A, sfr 2 6 A sfr A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL, byte] 2 8 A (HL + byte) A, X A, r Note 2 AC CY x x x x x x Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). Preliminary User's Manual U16898EJ1V0UD 273 CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z MOVW rp, #word 3 6 rp word AX, saddrp 2 6 AX (saddrp) AC CY 2 8 (saddrp) AX AX, rp Note 1 4 AX rp rp, AX Note 1 4 rp AX XCHW AX, rp Note 1 8 AX rp ADD A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A, CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) x x x saddrp, AX ADDC SUB Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 274 Preliminary User's Manual U16898EJ1V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z SUBC AND OR XOR Remark AC CY A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). Preliminary User's Manual U16898EJ1V0UD 275 CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z AC CY A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL + byte] 2 6 A - (HL + byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am-1 Am) x 1 x ROL A, 1 1 2 (CY, A0 A7, Am+1 Am) x 1 x RORC A, 1 1 2 (CY A0, A7 CY, Am-1 Am) x 1 x ROLC A, 1 1 2 (CY A7, A0 CY, Am+1 Am) x 1 x SET1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 A.bit 2 4 A.bit 1 PSW.bit 3 6 PSW.bit 1 [HL].bit 2 10 (HL).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 A.bit 2 4 A.bit 0 PSW.bit 3 6 PSW.bit 0 [HL].bit 2 10 (HL).bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CMP DEC CLR1 Remark x x x x x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 276 x Preliminary User's Manual U16898EJ1V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag Z CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 8 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X BC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 1 saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1 (Enable Interrupt) DI 3 6 IE 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode PUSH POP MOVW BR BF DBNZ Remark AC CY R R R R R R One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). Preliminary User's Manual U16898EJ1V0UD 277 CHAPTER 19 INSTRUCTION SET OVERVIEW 19.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL + byte] $addr16 1 None 1st Operand A r ADD MOVNote MOV MOV ADDC XCHNote XCH SUB ADD ADD SUBC ADDC ADDC AND SUB OR XOR CMP MOV MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD ADD RORC ADDC ADDC ADDC ROLC SUB SUB SUB SUB SUBC SUBC SUBC SUBC SUBC AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP XCH MOV MOV INC DEC B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC DEC ADD ADDC SUB SUBC AND OR XOR CMP !addr16 MOV PSW MOV MOV PUSH POP [DE] MOV [HL] MOV [HL + byte] MOV Note Except r = A. 278 Preliminary User's Manual U16898EJ1V0UD CHAPTER 19 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rp Note saddrp SP None 1st Operand AX rp ADDW SUBW MOVW CMPW XCHW MOVW MOVW MOVW Note MOVW INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 None 1st Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 SET1 CLR1 CY SET1 CLR1 NOT1 Preliminary User's Manual U16898EJ1V0UD 279 CHAPTER 19 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX !addr16 [addr5] $addr16 1st Operand Basic instructions BR CALL CALLT BR BR BC BNC BZ BNZ Compound instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP 280 Preliminary User's Manual U16898EJ1V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) These specifications are only target values, and may not be satisfied by mass-produced products. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit VDD -0.3 to +6.5 V VSS -0.3 to +0.3 V AVREF -0.3 to VDD + 0.3 VI1 -0.3 to VDD + 0.3 VI2 P30, P31, P34, P40 to P45, P121 to P123 P20 to 23 Note Note - 0.3 to AVREF + 0.3 Note V V V and -0.3 to VDD + 0.3 Note Output voltage Analog input voltage VO -0.3 to VDD + 0.3 VAN - 0.3 to AVREF + 0.3 Note Note V V and -0.3 to VDD + 0.3 Note Output current, high Output current, low Operating ambient IOH IOL TA temperature Storage temperature Per pin -10 mA Total of pins other than P20 to P23 -30 mA Per pin 20 mA Total of all pins 35 mA In normal operation mode -40 to +85 C During flash memory programming -10 to +70 C -40 to +125 C Tstg Note Must be 6.5 V or lower Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary User's Manual U16898EJ1V0UD 281 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) X1 Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Resonator Ceramic Recommended Circuit VSS X1 X2 Oscillation Note resonator frequency (fX) C1 Crystal Parameter C2 VSS X1 X2 Oscillation Note resonator frequency (fX) C1 C2 External X1 input clock frequency (fX) Note X1 Conditions MIN. TYP. MAX. Unit MHz 4.0 V VDD 5.5 V 0.5 10.0 3.0 V VDD < 4.0 V 0.5 6.0 2.7 V VDD < 3.0 V 0.5 5.0 2.0 V VDD < 2.7 V 0.5 0.5 4.0 V VDD 5.5 V 0.5 10.0 3.0 V VDD < 4.0 V 0.5 6.0 2.7 V VDD < 3.0 V 0.5 5.0 2.0 V VDD < 2.7 V 0.5 0.5 4.5 V VDD 5.5 V 0.5 10.0 4.0 V VDD < 4.5 V 0.5 6.0 2.7 V VDD < 4.0 V 0.5 5.0 2.0 V VDD < 2.7 V 0.5 0.5 X1 input high- 4.5 V VDD 5.5 V 0.045 1 /low-level width 4.0 V VDD < 4.5 V 0.075 1 2.7 V VDD < 4.0 V 0.085 1 2.0 V VDD < 2.7 V 1 1 (tXH, tXL) MHz MHz s Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 282 Preliminary User's Manual U16898EJ1V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) High-Speed Ring-OSC Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Resonator On-chip high-speed Ring-OSC Parameter Oscillation frequency (fX) Conditions MIN. TYP. MAX. Unit 2.7 V VDD 5.5 V 7.60 8.00 8.40 MHz 2.0 V VDD < 2.7 V T.B.D MHz Low-Speed Ring-OSC Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Resonator On-chip low-speed Ring-OSC Parameter Oscillation frequency (fRL) Conditions MIN. TYP. MAX. Unit 2.7 V VDD 5.5 V 120 240 480 kHz 2.0 V VDD < 2.7 V Preliminary User's Manual U16898EJ1V0UD T.B.D kHz 283 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) (1/2) Parameter Output current, high Symbol IOH1 IOH2 Output current, low Input voltage, high Input voltage, low Output voltage, high IOL Conditions MIN. TYP. MAX. Unit Pins other than Per pin 2.0 V VDD 5.5 V -5 mA P20 to P23 Total 4.0 V VDD 5.5 V -25 mA 2.0 V VDD < 4.0 V -15 mA Per pin 2.0 V VDD 5.5 V -15 mA Total 2.0 V VDD 5.5 V -5 mA Per pin 2.0 V VDD 5.5 V 10 mA Total of all pins 4.0 V VDD 5.5 V 30 mA 2.0 V VDD < 4.0 V 15 mA 0.8VDD VDD V P20 to P23 VIH1 P30, P31, P34, P40 to P45, P123 VIH2 P20 to P23 0.7AVREF AVREF V VIH3 P121, P122 0.7VDD VDD V VIL1 P30, P31, P34, P40 to P45, P123 0 0.2VDD V VIL2 P20 to P23 0 0.3AVREF V VIL3 P121, P122 0 0.3VDD V VOH1 Total of pins other than 4.0 V VDD 5.5 V P20 to P23 IOH = -5 mA T.B.D V VDD - 0.5 V T.B.D V T.B.D V T.B.D V T.B.D V IOH = -15 mA VOH2 IOH = -100 A 2.0 V VDD < 4.0 V Total of pins P20 to P23 4.5 V AVREF 5.5 V IOH = -10 mA IOH = -5 mA 4.0 V AVREF < 4.5 V IOH = -5 mA 2.85 V AVREF < 4.0 V IOH = -5 mA 2.7 V AVREF < 2.85 V IOH = -5 mA Output voltage, low VOL Total of pins IOL = 30 mA IOL = 10 mA Input leakage current, high ILIH1 VI = VDD ILIH2 Input leakage current, low ILIL1 X1 VI = 0 V ILIL2 Output leakage current, ILOH Pins other than X1 X1 VO = VDD high Output leakage current, low Pins other than X1 Pins other than X2 X2 ILOL VO = 0 V Pins other than X2 X2 T.B.D V 3 A T.B.D A -3 A T.B.D A 3 A T.B.D A -3 A T.B.D A Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 284 Preliminary User's Manual U16898EJ1V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) (2/2) Parameter Pull-up Symbol Conditions MIN. TYP. MAX. Unit VI = 0 V R 10 30 100 k When A/D converter is stopped 6.1 12.2 mA Note 7 7.6 15.2 resistance value Note 2 Supply current IDD1 Note 1 Crystal/ceramic fX = 10 MHz oscillation, VDD = 5.0 V 10% When A/D converter is operating fX = 6 MHz When A/D converter is stopped external clock input oscillation operating mode Note 5 Note 3 When A/D converter is operating T.B.D T.B.D fX = 5 MHz When A/D converter is stopped T.B.D T.B.D mA Note 3 Note 7 VDD = 2.7 V 10% When A/D converter is operating T.B.D T.B.D Crystal/ceramic fX = 10 MHz When peripheral functions are stopped T.B.D T.B.D mA oscillation, VDD = 5.0 V 10% When peripheral functions are operating T.B.D T.B.D fX = 6 MHz Note 4 IDD2 T.B.D T.B.D mA VDD = 3.0 V 10% external clock input HALT mode Note 5 Note 7 Note 3 When peripheral functions are stopped T.B.D T.B.D mA VDD = 3.0 V 10% When peripheral functions are operating T.B.D T.B.D fX = 5 MHz Note 3 When peripheral functions are stopped T.B.D T.B.D mA VDD = 2.7 V 10% When peripheral functions are operating T.B.D T.B.D High-speed fX = 8 MHz When A/D converter is stopped Ring-OSC VDD = 5.0 V 10% When A/D converter is operating fX = 4 MHz When A/D converter is stopped Note 4 IDD3 operation mode IDD4 Note 6 Note 3 Note 7 11.0 7 14.0 mA T.B.D T.B.D mA VDD = 2.7 V 10% When A/D converter is operating T.B.D T.B.D fX = 8 MHz When peripheral functions are stopped T.B.D T.B.D mA When peripheral functions are operating T.B.D T.B.D Note 3 High-speed 5.5 Ring-OSC HALT VDD = 5.0 V 10% Note 7 Note 3 mode Note 6 fX = 4 MHz When peripheral functions are stopped T.B.D T.B.D mA VDD = 2.7 V 10% When peripheral functions are operating T.B.D T.B.D VDD = 5.0 V 10% When low-speed Ring-OSC is stopped 3.5 35.5 When low-speed Ring-OSC is operating 17.5 63.5 When low-speed Ring-OSC is stopped 3.5 15.5 When low-speed Ring-OSC is operating 11 30.5 Note 3 IDD5 STOP mode VDD = 3.0 V 10% VDD = 2.7 V 10% Notes 1. When low-speed Ring-OSC is stopped T.B.D T.B.D When low-speed Ring-OSC is operating T.B.D T.B.D A A A Total current flowing through the internal power supply (VDD). Peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. IDD1 includes peripheral operation current. 3. When the processor clock control register (PCC) is set to 00H. 4. When the processor clock control register (PCC) is set to 02H. 5. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using the option byte. 6. When the high-speed Ring-OSC is selected as the system clock source using the option byte. 7. The current that flows through the AVREF pin is included. Preliminary User's Manual U16898EJ1V0UD 285 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Parameter Cycle time (minimum Symbol TCY instruction execution time) TI000 input high-level width, low-level width tTIH, Conditions MIN. 4.0 V VDD 5.5 V 0.2 4 s 3.0 V VDD < 4.0 V 0.33 4 s 2.7 V VDD < 3.0 V 0.4 4 s 2.0 V VDD < 2.7 V 4 4 s High-speed Ring-OSC 4.0 V VDD 5.5 V 0.25 4 s clock 2.7 V VDD < 4.0 V 0.5 4 s 2.0 V VDD < 2.7 V 4 4 s 4.0 V VDD 5.5 V 2/fsam+ 0.1 tINTL RESET input low-level tRSL s Note 2/fsam+ 0.2 tINTH, Unit clock, external clock input 2.0 V VDD < 4.0 V width, low-level width MAX. Crystal/ceramic oscillation tTIL Interrupt input high-level TYP. s Note 1 s 1 s width Note Selection of fsam = fXP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP. 286 Preliminary User's Manual U16898EJ1V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) TCY vs. VDD (Crystal/Ceramic Oscillation Clock, External Clock Input) 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.4 0.33 0.1 1 2 2.7 3 4 5 5.5 6 Supply voltage VDD [V] TCY vs. VDD (High-speed Ring-OSC Clock) 60 Cycle time TCY [ s] 10 Guaranteed operation range 1.0 0.5 0.25 0.1 1 2 3 4 5 6 5.5 2.7 Supply voltage VDD [V] Preliminary User's Manual U16898EJ1V0UD 287 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) (2) Serial interface (TA = -40 to +85C, VDD = 2.0 to 5.5 V) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. Transfer rate AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH tTIL0 tTIH0 X1 input TI000 Timing TI000 Interrupt Input Timing tINTL tINTH INTP0 to INTP3 RESET Input Timing tRSL RESET 288 Preliminary User's Manual U16898EJ1V0UD TYP. MAX. Unit 312.5 kbps CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) A/D Converter Characteristics (TA = -40 to +85C, 2.7 V AVREF VDD 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.0 V AVREF 4.5 V 0.2 0.4 %FSR 2.7 V AVREF < 4.0 V 0.3 0.6 %FSR Resolution Notes 1, 2 Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Ezs Notes 1, 2 Efs Note 1 Integral non-linearity error Differential non-linearity error Analog input voltage Notes 1. Note 1 ILE DLE 4.5 V AVREF 5.5 V 3.0 100 s 4.0 V AVREF < 4.5 V 4.8 100 s 2.85 V AVREF < 4.0 V 6.0 100 s 2.7 V AVREF < 2.85 V 14.0 100 s 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 4.0 V AVREF 5.5 V 0.4 %FSR 2.7 V AVREF < 4.0 V 0.6 %FSR 4.0 V AVREF 5.5 V 2.5 LSB 2.7 V AVREF < 4.0 V 4.5 LSB 4.0 V AVREF 5.5 V 1.5 LSB 2.7 V AVREF < 4.0 V 2.0 LSB AVREF V Note 3 VIAN VSS Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. VSS and AVSS are internally connected in the 78K0S/KA1+. Be sure to stabilize VSS by connecting it to a stable GND (= 0 V). If the status of the output port is varied during A/D conversion, the conversion characteristics may be degraded. Preliminary User's Manual U16898EJ1V0UD 289 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) POC Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Conditions VPOC Detection voltage MIN. TYP. MAX. Unit 2.0 2.1 2.2 V s tPTH VDD: 0 V 2.0 V Response delay time 1 Note tPTHD When power supply rises, after reaching detection voltage (MAX.) 3.0 ms Response delay time 2 Note tPD When power supply falls 1.0 ms Power supply rise time Minimum pulse width 1.5 tPW 0.2 ms Note Time required from voltage detection to reset release. POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tPW tPTH tPTHD tPD Time 290 Preliminary User's Manual U16898EJ1V0UD CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) LVI Circuit Characteristics (TA = -40 to +85C) Parameter Symbol Detection voltage Note 1 Response time TYP. MAX. Unit VLVI0 4.1 4.3 4.5 V VLVI1 3.9 4.1 4.3 V VLVI2 3.7 3.9 4.1 V VLVI3 3.5 3.7 3.9 V VLVI4 3.3 3.5 3.7 V VLVI5 3.15 3.3 3.45 V VLVI6 2.95 3.1 3.25 V VLVI7 2.7 2.85 3.0 V VLVI8 2.5 2.6 2.7 V VLVI9 2.25 2.35 2.45 V 0.2 2.0 ms tLW Operation stabilization wait time 2. MIN. tLD Minimum pulse width Notes 1. Conditions Note 2 0.2 tWAIT ms 0.1 0.2 ms Time required from voltage detection to interrupt output or RESET output. Time required from setting LVION to 1 to operation stabilization. Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9 2. VPOC < VLVIm (m = 0 to 9) LVI Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.) tLW tWAIT LVION tLD 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Conditions MIN. Data retention supply voltage VDDDR 2.0 Release signal set time tSREL 0 Preliminary User's Manual U16898EJ1V0UD TYP. MAX. Unit 5.5 V s 291 CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES) Flash Memory Programming Characteristics (TA = -10C to +70C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Note 1 Erase time TYP. MAX. Unit T.B.D T.B.D ms Sector unit terasa T.B.D T.B.D ms T.B.D T.B.D s twrwa Cerwr Note 2 1 erase + 1 write after erase = 1 rewrite 100 Times The erase verify time is not included. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. 292 MIN. teraca Number of rewrites per chip 2. Conditions Chip unit Write time Notes 1. Symbol Preliminary User's Manual U16898EJ1V0UD CHAPTER 21 PACKAGE DRAWING 20-PIN PLASTIC SSOP (7.62 mm (300)) 20 11 detail of lead end F G T P L U E 1 10 A H J I S N S K C D M M B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 6.650.15 B 0.475 MAX. C 0.65 (T.P.) D 0.24 +0.08 -0.07 E 0.10.05 F 1.30.1 G 1.2 H 8.10.2 I 6.10.2 J 1.00.2 K 0.170.03 L 0.5 M 0.13 N 0.10 P 3 +5 -3 T 0.25 U 0.60.15 S20MC-65-5A4-2 Preliminary User's Manual U16898EJ1V0UD 293 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the 78K0S/KA1+. Figure A-1 shows development tools. * Compatibility with PC98-NX series Unless stated otherwise, products which are supported by IBM PC/ATTM and compatibles can also be used with the PC98-NX series. When using the PC98-NX series, therefore, refer to the explanations for IBM PC/AT and compatibles. * Windows Unless stated otherwise, "Windows" refers to the following operating systems. * Windows 3.1 * Windows 95, 98, 2000, XP * Windows NTTM Ver. 4.0 294 Preliminary User's Manual U16898EJ1V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package * Software package Language processing software Debugging software * Assembler package * C compiler package * Device file * C library source fileNote 1 * Integrated debugger * System simulator Control software * Project Manager (Windows version only)Note 2 Host machine (PC or EWS) Interface adapter Power supply unit Flash memory writing environment In-circuit emulator Flash programmer Emulation board Flash memory writing adapter Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. 2. The C library source file is not included in the software package. The Project Manager is included in the assembler package. The Project Manager is used only in the Windows environment. Preliminary User's Manual U16898EJ1V0UD 295 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Software package This is a package that bundles the software tools required for development of the 78K/0S Series. The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S/Kx1 (provisional name), and device files Part number: SxxxxSP78K0S Remark xxxx in the part number differs depending on the operating system to be used. SxxxxSP78K0S xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows Supply Medium CD-ROM English Windows A.2 Language Processing Software RA78K0S Assembler package Program that converts program written in mnemonic into object code that can be executed by microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided. Used in combination with device file (DF78K0S/Kx1 (provisional name)) (sold separately). <Caution when used in PC environment> The assembler package is a DOS-based application but may be used under the Windows environment by using Project Manager of Windows (included in the assembler package). Part number: SxxxxRA78K0S CC78K0S Program that converts program written in C language into object codes that can be executed by C library package microcontroller. Used in combination with assembler package (RA78K0S) and device file (DF78K0S/Kx1) (both sold separately). <Caution when used in PC environment> The C compiler package is a DOS-based application but may be used under the Windows environment by using Project Manager of Windows (included in the assembler package). Part number: SxxxxCC78K0S DF78K0S/Kx1 File containing the information inherent to the device. Notes 1, 2 (provisional name) Device file Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, or SM78K0S/Kx1 (provisional name)) (all sold separately). Part number: T.B.D. CC78K0S-L Note 3 C library source file Source file of functions constituting object library included in C compiler package. Necessary for changing object library included in C compiler package according to customer's specifications. Since this is the source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0S-L Notes 1. DF78K0S/Kx1 (provisional name) is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S/Kx1 (provisional name). 296 2. Under development 3. CC78K0S-L is not included in the software package (SP78K0S). Preliminary User's Manual U16898EJ1V0UD APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and operating system to be used. SxxxxRA78K0S SxxxxCC78K0S xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT and compatibles Japanese Windows BB17 3K17 Japanese Windows Supply Media 3.5" 2HD FD English Windows AB17 3P17 OS CD-ROM English Windows HP9000 series 700 SPARCstation TM TM HP-UX TM SunOS TM TM Solaris (Rel.10.10) (Rel.4.1.4), (Rel.2.5.1) SxxxxCC78K0S-L xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows Supply Media 3.5" 2HD FD English Windows 3P16 HP9000 series 700 HP-UX (Rel.10.10) DAT 3K13 SPARCstation SunOS (Rel.4.1.4), Solaris (Rel.2.5.1) 3.5" 2HD FD 3K15 1/4" CGMT A.3 Control Software Project Manager This is control software designed so that the user program can be efficiently developed in the Windows environment. With this software, a series of user program development operations, including starting the editor, build, and starting the debugger, can be executed on the Project Manager. <Caution> The Project Manager is included in the assembler package (RA78K0S). It can be used only in the Windows environment. A.4 Flash Memory Writing Tools Flashpro IV (FL-PR4, PG-FP4) Flash programmer dedicated to the microcontrollers incorporating a flash memory Flash programmer FA-20MC Flash memory writing adapter Remark Flash memory writing adapter. Used in connection with Flashpro IV. Designed for use with a 20-pin plastic SSOP (MC-5A4 type). FL-PR4 and FA-20MC are products of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191) Preliminary User's Manual U16898EJ1V0UD 297 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging hardware and software of application system using 78K/0S IE-78K0S-NS-A This in-circuit emulator has a coverage function in addition to the functions of the IE-78K0S- In-circuit emulator NS, and enhanced debugging functions such as an enhanced tracer function and timer function. IE-70000-MC-PS-B Adapter for supplying power from 100 to 240 VAC outlet. Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. AC adapter IE-70000-98-IF-C Adapter required when using a PC-9800 series (except notebook type) as the host machine (C Interface adapter bus supported). IE-70000-CD-IF-A PC card and interface cable required when using a notebook type PC as the host machine PC card interface (PCMCIA socket supported). IE-70000-PC-IF-C Adapter required when using IBM PC/AT and compatibles as the host machine (ISA bus Interface adapter supported). IE-70000-PCI-IF-A Adapter required when using a personal computer incorporating the PCI bus is used as the Interface adapter host machine. IE-789244-NS-EM1 (provisional Emulation board for emulating the peripheral hardware inherent to the device. Note name) Emulation board Used in combination with in-circuit emulator. NP-20GS Probe for connecting in-circuit emulator and target system. Emulation probe For 20-pin plastic SSOP (MC-5A4 type) EV-9500GS-20 Conversion adapter for connecting target system board for mounting 20-pin plastic SSOP Conversion adapter (MC-5A4 type) and NP-20GS. NP-30MC This probe is used to connect the in-circuit emulator to the target system and is designed for Emulation probe use with a 30-pin plastic SSOP (MC-5A4 type). NSPACK20BK This conversion socket connects the NP-30MC to a target system board designed to mount a YSPACK30BK Conversion socket 20-pin plastic SSOP (MC-5A4 type). * NSPACK20BK: Socket for connecting target * YSPACK30BK: Socket for connecting emulator Note Under development Remarks 1. NP-20GS and NP-30MC are products of Naito Densei Machida Mfg. Co., Ltd. For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191) 2. NSPACK20BK and YSPACK30BK are products of TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo Co., Ltd. Tokyo Electronics Department (TEL: +81-3-3820-7112) Osaka Electronics Department (TEL: +81-6-6244-6672) 298 Preliminary User's Manual U16898EJ1V0UD APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS Integrated debugger This debugger supports the in-circuit emulators for the 78K/0S Series, IE-78K0S-NS and IE78K0S-NS-A. ID78K0S-NS is Windows-based software. This debugger has enhanced debugging functions supporting C language. By using its window integration function that associates the source program, disassemble display, and memory display with trace results, the trace results can be displayed corresponding to the source program. It is used with a device file (DF78K0S/Kx1 (provisional name)) (sold separately). Part number: SxxxxID78K0S-NS SM78K0S/Kx1 (provisional Notes 1, 2 name) System simulator This is a system simulator for the 78K/0S series. SM78K0S/Kx1 (provisional name) is Windowsbased software. This simulator can execute C-source-level or assembler-level debugging while simulating the operations of the target system on the host machine. By using SM78K0S/Kx1 (provisional name), the logic and performance of the application can be verified independently of hardware development. Therefore, the development efficiency can be enhanced and the software quality can be improved. This simulator is used with a device file (DF78K0S/Kx1 (provisional name)) (sold separately). Part number: T.B.D. DF78K0S/Kx1 (provisional Notes 1, 2 name) Device file This is a file that has device-specific information. It is used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S/Kx1 (provisional name) (all sold separately). Part number: T.B.D. Notes 1. DF78K0S/Kx1 (provisional name) is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S/Kx1 (provisional name). 2. Remark Under development xxxx in the part number differs depending on the operating system to be used and the supply medium. SxxxxID78K0S-NS xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Japanese Windows Supply Medium 3.5" 2HD FD English Windows AB17 Japanese Windows BB17 English Windows Preliminary User's Manual U16898EJ1V0UD CD-ROM 299 APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion connector and conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Figure B-1. Connection Condition of Target In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Target system Emulation board IE-789244-NS-EM1 (provisional name) 185 mm CN1 Emulation probe NP-20GS Conversion socket: EV-9500GS-20 Emulation board IE-789244-NS-EM1 (provisional name) 10 mm 43 mm 45 mm Emulation probe NP-20GS Target system Conversion connector: EV-9500GS-20 30 mm 1 pin 15 mm 100 mm Remark 300 The NP-20GS is a product made by Naito Densei Machida Mfg. Co., Ltd. Preliminary User's Manual U16898EJ1V0UD APPENDIX C REGISTER INDEX C.1 Register Index (Register Name) 8-bit A/D conversion result register (ADCRH) ... 161 8-bit compare register 80 (CR80) ... 120 8-bit timer counter 80 (TM80) ... 120 8-bit timer H compare register 01 (CMP01) ... 127 8-bit timer H compare register 11 (CMP11) ... 127 8-bit timer H mode register 1 (TMHMD1) ... 128 8-bit timer mode control register 80 (TMC80) ... 121 10-bit A/D conversion result register (ADCR) ... 160 16-bit timer capture/compare register 000 (CR000) ... 81 16-bit timer capture/compare register 010 (CR010) ... 83 16-bit timer counter 00 (TM00) ... 81 16-bit timer mode control register 00 (TMC00) ... 84 16-bit timer output control register 00 (TOC00) ... 87 [A] A/D converter mode register (ADM) ... 158 Analog input channel specify register (ADS) ... 160 Asynchronous serial interface operation mode register 6 (ASIM6) ... 180 Asynchronous serial interface reception error status register 6 (ASIS6) ... 182 Asynchronous serial interface transmission status register 6 (ASIF6) ... 183 Asynchronous serial interface control register 6 (ASICL6) ... 186 [B] Baud rate generator control register 6 (BRGC6) ... 185 [C] Capture/compare control register 00 (CRC00) ... 86 Clock selection register 6 (CKSR6) ... 184 [E] External interrupt mode register 0 (INTM0) ... 219 External interrupt mode register 1 (INTM1) ... 220 [H] High-speed Ring-OSC mode register (HSRCM) ... 66 [I] Input switching control register (ISC) ... 188 Interrupt mask flag register 0 (MK0) ... 218 Interrupt mask flag register 0 (MK0) ... 218 Interrupt request flag register 0 (IF0) ... 217 Interrupt request flag register 1 (IF1) ... 217 Preliminary User's Manual U16898EJ1V0UD 301 APPENDIX C REGISTER INDEX [L] Low voltage detect register (LVIM) ... 249 Low voltage detection level select register (LVIS) ... 250 Low-speed Ring-OSC mode register (LSRCM) ... 66 [O] Oscillation stabilization time selection register (OSTS) ... 67 [P] Port mode control register 2 (PMC2) ... 58, 161 Port mode register 2 (PM2) ... 56, 161 Port mode register 3 (PM3) ... 56, 89 Port mode register 4 (PM4) ... 56, 130, 188 Port mode register 12 (PM12) ... 56 Port register 2 (P2) ... 57 Port register 3 (P3) ... 57 Port register 4 (P4) ... 57 Port register 12 (P12) ... 57 Port register 13 (P13) ... 57 Preprocessor clock control register (PPCC) ... 65 Prescaler mode register 00 (PRM00) ... 88 Processor clock control register (PCC) ... 65 Pull-up resistance option register 2 (PU2) ... 60 Pull-up resistance option register 3 (PU3) ... 60 Pull-up resistance option register 4 (PU4) ... 60 Pull-up resistance option register 12 (PU12) ... 60 [R] Receive buffer register 6 (RXB6) ... 179 Reset control flag register (RESF) ... 243 [T] Transmit buffer register 6 (TXB6) ... 179 302 Preliminary User's Manual U16898EJ1V0UD APPENDIX C REGISTER INDEX C.2 Register Index (Symbol) [A] ADCR: 10-bit A/D conversion result register ... 160 ADCRH: 8-bit A/D conversion result register ... 161 ADM: A/D converter mode register ... 158 ADS: Analog input channel specify register ... 160 ASICL6: Asynchronous serial interface control register 6 ... 186 ASIF6: Asynchronous serial interface transmission status register 6 ... 183 ASIM6: Asynchronous serial interface operation mode register 6 ... 180 ASIS6: Asynchronous serial interface reception error status register 6 ... 182 [B] BRGC6: Baud rate generator control register 6 ... 185 [C] CKSR6: Clock selection register 6 ... 184 CMP01: 8-bit timer H compare register 01 ... 127 CMP11: 8-bit timer H compare register 11 ... 127 CR000: 16-bit timer capture/compare register 000 ... 81 CR010: 16-bit timer capture/compare register 010 ... 83 CR80: 8-bit compare register 80 ... 120 CRC00: Capture/compare control register 00 ... 86 [H] HSRCM: High-speed Ring-OSC mode register ... 66 [I] IF0: Interrupt request flag register 0 ... 217 IF1: Interrupt request flag register 1 ... 217 INTM0: External interrupt mode register 0 ... 219 INTM1: External interrupt mode register 1 ... 220 ISC: Input switching control register ... 188 [L] LSRCM: Low-speed Ring-OSC mode register ... 66 LVIM: Low voltage detect register ... 249 LVIS: Low voltage detection level select register ... 250 [M] MK0: Interrupt mask flag register 0 ... 218 MK0: Interrupt mask flag register 0 ... 218 [O] OSTS: Oscillation stabilization time selection register ... 67 Preliminary User's Manual U16898EJ1V0UD 303 APPENDIX C REGISTER INDEX [P] P2: Port register 2 ... 57 P3: Port register 3 ... 57 P4: Port register 4 ... 57 P12: Port register 12 ... 57 P13: Port register 13 ... 57 PCC: Processor clock control register ... 65 PM2: Port mode register 2 ... 56, 161 PM3: Port mode register 3 ... 56, 89 PM4: Port mode register 4 ... 56, 130, 188 PM12: Port mode register 12 ... 56 PMC2: Port mode control register 2 ... 58, 161 PPCC: Preprocessor clock control register ... 65 PRM00: Prescaler mode register 00 ... 88 PU2: Pull-up resistance option register 2 ... 60 PU3: Pull-up resistance option register 3 ... 60 PU4: Pull-up resistance option register 4 ... 60 PU12: Pull-up resistance option register 12 ... 60 [R] RESF: Reset control flag register ... 243 RXB6: Receive buffer register 6 ... 179 [T] TM00: 16-bit timer counter 00 ... 81 TM80: 8-bit timer counter 80 ... 120 TMC00: 16-bit timer mode control register 00 ... 84 TMC80: 8-bit timer mode control register 80 ... 121 TMHMD1: 8-bit timer H mode register 1 ... 128 TOC00: 16-bit timer output control register 00 ... 87 TXB6: Transmit buffer register 6 ... 179 304 Preliminary User's Manual U16898EJ1V0UD