TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 2 LOW-VOLTAGE 24-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS Check for Samples: TCA6424A FEATURES 1 P04 P05 P06 P07 5 7 8 4 6 P02 P03 3 P00 P01 RGJ/RSM PACKAGE (BOTTOM VIEW) 1 INT VCCI 32 9 P10 31 10 P11 SDA 30 11 P12 SCL 29 12 P13 RESET VCCP 28 13 P14 27 14 P15 ADDR 26 15 P16 GND 25 16 P17 22 21 20 19 18 17 P24 P23 P22 P21 P20 Exposed Center Pad P25 * 2 * 23 * * * * * * * * Polarity Inversion Register Internal Power-On Reset Power Up With All Channels Configured as Inputs No Glitch On Power Up Noise Filter on SCL/SDA Inputs Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) 24 * * * * * * P26 * Operating Power-Supply Voltage Range of 1.65 V to 5.5 V Allows Bidirectional Voltage-Level Translation and GPIO Expansion Between: - 1.8-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port - 2.5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port - 3.3-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port - 5-V SCL/SDA and 1.8-V, 2.5-V, 3.3-V, or 5-V P Port 2 I C to Parallel Port Expander Low Standby Current Consumption of 1 mA Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the SCL and SDA Inputs - Vhys = 0.18 V Typ at 1.8 V - Vhys = 0.25 V Typ at 2.5 V - Vhys = 0.33 V Typ at 3.3 V - Vhys = 0.5 V Typ at 5 V 5-V Tolerant I/O Ports Active-Low Reset Input (RESET) Open-Drain Active-Low Interrupt Output (INT) 400-kHz Fast I2C Bus Input/Output Configuration Register P27 * If used, the exposed center pad must be connected as a secondary ground or left electrically open. DESCRIPTION/ORDERING INFORMATION This 24-bit I/O expander for the two-line bidirectional bus (I2C) is designed to provide general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)]. The major benefit of this device is its wide VCC range. It can operate from 1.65 V to 5.5 V on the P-port side and on the SDA/SCL side. This allows the TCA6424A to interface with next-generation microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs, remain at a 5-V power supply. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010, Texas Instruments Incorporated TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage level on the P-port of the TCA6424A is determined by the VCCP. The TCA6424A consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The system master can reset the TCA6424A in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. The TCA6424A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6424A can remain a simple slave device. The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current. One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to share the same I2C bus or SMBus. ORDERING INFORMATION PACKAGE (1) TA -40C to 85C (1) (2) 2 (2) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN - RGJ Reel of 3000 TCA6424ARGJR PH424 QFN - RSM TBD TCA6424ARSMR TBD Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION PIN NO. NAME 1 P00 P-port input/output (push-pull design structure). At power on, P00 is configured as an input. 2 P01 P-port input/output (push-pull design structure). At power on, P01 is configured as an input. 3 P02 P-port input/output (push-pull design structure). At power on, P02 is configured as an input. 4 P03 P-port input/output (push-pull design structure). At power on, P03 is configured as an input. 5 P04 P-port input/output (push-pull design structure). At power on, P04 is configured as an input. 6 P05 P-port input/output (push-pull design structure). At power on, P05 is configured as an input. 7 P06 P-port input/output (push-pull design structure). At power on, P06 is configured as an input. 8 P07 P-port input/output (push-pull design structure). At power on, P07 is configured as an input. 9 P10 P-port input/output (push-pull design structure). At power on, P10 is configured as an input. 10 P11 P-port input/output (push-pull design structure). At power on, P11 is configured as an input. 11 P12 P-port input/output (push-pull design structure). At power on, P12 is configured as an input. 12 P13 P-port input/output (push-pull design structure). At power on, P13 is configured as an input. 13 P14 P-port input/output (push-pull design structure). At power on, P14 is configured as an input. 14 P15 P-port input/output (push-pull design structure). At power on, P15 is configured as an input. 15 P16 P-port input/output (push-pull design structure). At power on, P16 is configured as an input. 16 P17 P-port input/output (push-pull design structure). At power on, P17 is configured as an input. 17 P20 P-port input/output (push-pull design structure). At power on, P20 is configured as an input. 18 P21 P-port input/output (push-pull design structure). At power on, P21 is configured as an input. 19 P22 P-port input/output (push-pull design structure). At power on, P22 is configured as an input. 20 P23 P-port input/output (push-pull design structure). At power on, P23 is configured as an input. 21 P24 P-port input/output (push-pull design structure). At power on, P24 is configured as an input. 22 P25 P-port input/output (push-pull design structure). At power on, P25 is configured as an input. 23 P26 P-port input/output (push-pull design structure). At power on, P26 is configured as an input. 24 P27 P-port input/output (push-pull design structure). At power on, P27 is configured as an input. 25 GND Ground 26 ADDR Address input. Connect directly to VCCP or ground. 27 VCCP Supply voltage of TCA6424A for P port 28 RESET 29 SCL Serial clock bus. Connect to VCCI through a pullup resistor. 30 SDA Serial data bus. Connect to VCCI through a pullup resistor. 31 VCCI Supply voltage of I2C bus. Connect directly to the VCC of the external I2C master. Provides voltage-level translation. 32 INT Interrupt output. Connect to VCCI through a pullup resistor. Active-low reset input. Connect to VCCI through a pullup resistor, if no active connection is used. Voltage Translation Table 2 shows how to set up VCC levels for the necessary voltage translation between the I2C bus and the TCA6424A. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 3 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com Table 2. Voltage Translation VCCI (SDA AND SCL OF I2C MASTER) (V) VCCP (P PORT) (V) 1.8 1.8 1.8 2.5 1.8 3.3 1.8 5 2.5 1.8 2.5 2.5 2.5 3.3 2.5 5 3.3 1.8 3.3 2.5 3.3 3.3 3.3 5 5 1.8 5 2.5 5 3.3 5 5 LOGIC DIAGRAM (POSITIVE LOGIC) 32 INT 26 ADDR 29 SCL 30 SDA Input Filter 2 I C Bus Control 31 VCCI 28 RESET Shift Register 24 Bits I/O Port P27-P20 P17-P10 P07-P00 Write Pulse Read Pulse 27 VCCP Power-On Reset 25 GND 4 Interrupt Logic LP Filter A. All I/Os are set to inputs at reset. B. Pin numbers shown are for the RGJ package. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 Simplified Schematic of P00 to P27 Data From Shift Register Data From Shift Register Output Port Register Data VCCP Configuration Register D Q Q1 FF Write Configuration Pulse CK Q D Q FF Write Pulse P00 to P27 CK Q Output Port Register Q2 Input Port Register Q D FF Read Pulse ESD Protection Diode GND Input Port Register Data CK Q To INT Data From Shift Register D Q FF Write Polarity Pulse Polarity Register Data CK Q Polarity Inversion Register A. On power up or reset, all registers return to default values. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 5 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com I/O Port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure 1). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must not be changed between the Start and the Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. SDA SCL S P Stop Condition Start Condition Figure 1. Definition of Start and Stop Conditions SDA SCL Data Line Change Figure 2. Bit Transfer 6 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 3. Acknowledgment on the I2C Bus Table 3. Interface Definition BYTE I2C slave address I/O data bus BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) L H L L L H ADDR R/W P07 P06 P05 P04 P03 P02 P01 P00 P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 Device Address The address of the TCA6424A is shown in Figure 4. Slave Address 0 1 0 0 Fixed 0 AD 1 DR R/W Programmable Figure 4. TCA6424A Address Table 4. Address Reference ADDR I2C BUS SLAVE ADDRESS L 34 (decimal), 22 (hexadecimal) H 35 (decimal), 23 (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation. Control Register and Command Byte Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is stored in the control register in the TCA6424A. Four bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversion, or configuration) that will be affected. The control register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 7 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com The control register includes an Auto-Increment (AI) bit which is the most significant bit (bit 7) of the command byte. At power-up, the control register defaults to 00 (hex), with the AI bit set to logic 1, and the lowest 7 bits set to logic 0. If AI is 1, the 2 least significant bits are automatically incremented after a read or write. This allows the user to program and/or read the 3 register banks sequentially. If more than 3 bytes of data are written when AI is 1, previous data in the selected registers will be overwritten. Reserved registers are skipped and not accessed (refer to Table 5). If AI is 0, the 2 least significant bits are not incremented after data is read or written. During a read operation, the same register bank is read each time. During a write operation, data is written to the same register bank each time. Reserved command codes and command byte outside the range stated in the Command Byte table must not be accessed for proper device functionality. AI B6 B5 B4 B3 B2 B1 B0 Figure 5. Control Register Bits 8 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 Table 5. Command Byte CONTROL REGISTER BITS AI B6 B5 B4 B3 B2 B1 B0 AUTOINCREMENT STATE 0 0 0 0 0 0 0 0 Disable 00 1 0 0 0 0 0 0 0 Enable 80 0 0 0 0 0 0 0 1 Disable 01 1 0 0 0 0 0 0 1 Enable 81 0 0 0 0 0 0 1 0 Disable 02 1 0 0 0 0 0 1 0 Enable 82 0 0 0 0 0 0 1 1 Disable 03 1 0 0 0 0 0 1 1 Enable 83 0 0 0 0 0 1 0 0 Disable 04 1 0 0 0 0 1 0 0 Enable 84 0 0 0 0 0 1 0 1 Disable 05 1 0 0 0 0 1 0 1 Enable 85 0 0 0 0 0 1 1 0 Disable 06 1 0 0 0 0 1 1 0 Enable 86 0 0 0 0 0 1 1 1 Disable 07 1 0 0 0 0 1 1 1 Enable 87 0 0 0 0 1 0 0 0 Disable 08 1 0 0 0 1 0 0 0 Enable 88 0 0 0 0 1 0 0 1 Disable 09 1 0 0 0 1 0 0 1 Enable 89 0 0 0 0 1 0 1 0 Disable 0A 1 0 0 0 1 0 1 0 Enable 8A 0 0 0 0 1 0 1 1 Disable 0B 1 0 0 0 1 0 1 1 Enable 8B 0 0 0 0 1 1 0 0 Disable 0C 1 0 0 0 1 1 0 0 Enable 8C 0 0 0 0 1 1 0 1 Disable 0D 1 0 0 0 1 1 0 1 Enable 8D 0 0 0 0 1 1 1 0 Disable 0E 1 0 0 0 1 1 1 0 Enable 8E 0 0 0 0 1 1 1 1 Disable 0F 1 0 0 0 1 1 1 1 Enable 8F (1) COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULT Input Port 0 Read byte xxxx xxxx (1) Input Port 1 Read byte xxxx xxxx (1) Input Port 2 Read byte xxxx xxxx (1) Reserved Reserved Reserved Output Port 0 Read/write byte 1111 1111 Output Port 1 Read/write byte 1111 1111 Output Port 2 Read/write byte 1111 1111 Reserved Reserved Reserved Polarity Inversion Port 0 Read/write byte 0000 0000 Polarity Inversion Port 1 Read/write byte 0000 0000 Polarity Inversion Port 2 Read/write byte 0000 0000 Reserved Reserved Reserved Configuration Port 0 Read/write byte 1111 1111 Configuration Port 1 Read/write byte 1111 1111 Configuration Port 2 Read/write byte 1111 1111 Reserved Reserved Reserved Undefined Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 9 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com Register Descriptions The Input Port registers (registers 0, 1 and 2) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes to these registers have no effect. The default value (X) is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register will be accessed next. Table 6. Registers 0 and 1 (Input Port Registers) BIT I-07 I-06 I-05 I-04 I-03 I-02 I-01 I-00 DEFAULT X X X X X X X X I-10 BIT I-17 I-16 I-15 I-14 I-13 I-12 I-11 DEFAULT X X X X X X X X BIT I-27 I-26 I-25 I-24 I-23 I-22 I-21 I-20 DEFAULT X X X X X X X X The Output Port registers (registers 4, 5 and 6) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value. Table 7. Registers 2 and 3 (Output Port Registers) BIT O-07 O-06 O-05 O-04 O-03 O-02 O-01 O-00 DEFAULT 1 1 1 1 1 1 1 1 BIT O-17 O-16 O-15 O-14 O-13 O-12 O-11 O-10 DEFAULT 1 1 1 1 1 1 1 1 BIT O-27 O-26 O-25 O-24 O-23 O-22 O-21 O-20 DEFAULT 1 1 1 1 1 1 1 1 The Polarity Inversion registers (registers 8, 9 and 10) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is retained. Table 8. Registers 4 and 5 (Polarity Inversion Registers) BIT P-07 P-06 P-05 P-04 P-03 P-02 P-01 DEFAULT 0 0 0 0 0 0 0 P-00 0 BIT P-17 P-16 P-15 P-14 P-13 P-12 P-11 P-10 DEFAULT 0 0 0 0 0 0 0 0 BIT P-27 P-26 P-25 P-24 P-23 P-22 P-21 P-20 DEFAULT 0 0 0 0 0 0 0 0 The Configuration registers (registers 12, 13 and 14) configure the direction of the I/O pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output. Table 9. Registers 6 and 7 (Configuration Registers) 10 BIT C-07 C-06 C-05 C-04 C-03 C-02 C-01 C-00 DEFAULT 1 1 1 1 1 1 1 1 C-10 BIT C-17 C-16 C-15 C-14 C-13 C-12 C-11 DEFAULT 1 1 1 1 1 1 1 1 BIT C-27 C-26 C-25 C-24 C-23 C-22 C-21 C-20 DEFAULT 1 1 1 1 1 1 1 1 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 Power-On Reset When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6424A in a reset condition until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6424A registers and I2C/SMBus state machine initializes to their default states. After that, VCCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle. ADD TABLE WITH SPECS AND DEFINITIONS TO SUPPORT POR OPERATION Reset Input (RESET) The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6424A registers and I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor to VCCI, if no active connection is used. Interrupt Output (INT) An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. The INT output has an open-drain structure and requires pullup resistor to VCCP or VCCI depending on the application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6424A then the INT pin has to be connected to VCCI. If not, the INT pin can be connected to VCCP. Bus Transactions Data is exchanged between the master and TCA6424A through write and read commands. Writes Data is transmitted to the TCA6424A by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. The twelve registers within the TCA6424A are grouped into four different sets. The four sets of registers are input ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next data byte is sent to the next register in the group of 3 registers (see Figure 6 and Figure 7). For example, if the first byte is send to Output Port 2 (register 6), the next byte is stored in Output Port 0 (register 4). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 11 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 SCL 1 2 3 4 5 6 7 8 9 Command Byte Slave Address SDA 0 S 1 0 0 0 www.ti.com 1 AD DR 0 A 0 0 0 0 0 Data to Port 0 1 0/1 0/1 A 0.7 R/W Acknowledge From Slave Start Condition Data to Port 1 0.0 A 1.7 Data 0 Acknowledge From Slave Data 1 1.0 A P Acknowledge From Slave Write to Port Data Out from Port 0 tpv Data Valid Data Out from Port 1 tpv Figure 6. Write to Output Port Register <br/> SCL 1 2 3 4 5 6 7 8 9 1 2 3 Slave Address SDA 0 S 1 0 Start Condition 0 0 4 5 6 7 8 9 1 A 0 0 0 R/W Acknowledge From Slave 0 3 4 5 6 7 8 9 1 Data to Register Command Byte 1 AD DR 0 2 1 0/1 0/1 0/1 A MSB Data 0 Acknowledge From Slave 3 2 4 5 Data to Register LSB A MSB Data1 LSB A P Acknowledge From Slave Figure 7. Write to Configuration or Polarity Inversion Registers Reads The bus master first must send the TCA6424A address with the LSB set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the TCA6424A (see Figure 8 and Figure 9). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. 12 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 Slave Address S 0 0 1 0 0 Acknowledge From Slave Acknowledge From Slave 1 AD DR 0 Command Byte A R/W A S Acknowledge From Slave Slave Address 0 1 0 0 0 AD 1 DR 1 Data A MSB LSB A First Byte R/W At this moment, master transmitter becomes master receiver, and slave receiver becomes slave transmitter. Data From Lower or Upper Byte Acknowledge of Register From Master Data From Upper or Lower Byte No Acknowledge of Register From Master MSB Data LSB NA P Last Byte Figure 8. Read From Register <br/> SCL 1 2 3 4 5 6 7 8 9 I0.x SDA S 0 1 0 0 0 1 AD DR 1 A Data 1 R/W Acknowledge From Slave I1.x A Data 2 Acknowledge From Master I2.x A Data 3 Acknowledge From Master I0.x A Data 4 Acknowledge From Master 1 P No Acknowledge From Master Read From Port 0 Data Into Port 0 Read From Port 1 Data Into Port 1 INT tiv tir Read From Port 2 Data Into Port 2 A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 8). C. Auto-increment mode is enabled. Figure 9. Read Input Port Register Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 13 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCCI Supply voltage range -0.5 6.5 V VCCP Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V VO Output voltage range (2) -0.5 6.5 V IIK Input clamp current ADDR, RESET, SCL VI < 0 20 mA IOK Output clamp current INT VO < 0 20 mA P port VO < 0 or VO > VCCP 20 SDA VO < 0 or VO > VCCI 20 P port VO = 0 to VCCP 25 SDA, INT VO = 0 to VCCI 15 P port VO = 0 to VCCP 25 IIOK Input/output clamp current IOL Continuous output low current IOH Continuous output high current ICC Continuous current through GND 200 Continuous current through VCCP 160 Continuous current through VCCI 10 qJA Package thermal impedance (3) Tstg Storage temperature range (1) (2) (3) RGJ package 50.05 RSM package TBD -65 150 UNIT mA mA mA mA C/W C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VCCI Supply voltage 1.65 5.5 V VCCP Supply voltage 1.65 5.5 V SCL, SDA, RESET 0.7 x VCCI 5.5 ADDR, P27-P00 0.7 x VCCP 5.5 VIH High-level input voltage VIL Low-level input voltage IOH High-level output current P27-P00 IOL Low-level output current P27-P00 TA Operating free-air temperature 14 SCL, SDA, RESET -0.5 0.3 x VCCI ADDR, P27-P00 -0.5 0.3 x VCCP -40 Submit Documentation Feedback V V 10 mA 25 mA 85 C Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCP MIN -1.2 VIK Input diode clamp voltage II = -18 mA 1.65 V to 5.5 V VPOR Power-on reset voltage VI = VCCP or GND, IO = 0 1.65 V to 5.5 V IOH = -8 mA P-port high-level output voltage VOH IOH = -10 mA IOL = 8mA P-port low-level output voltage VOL IOL = 10 mA TYP (1) 1.2 2.3 V 1.8 3V 2.6 4.5 V 4.1 1.65 V 1 2.3 V 1.7 3V 2.5 4.5 V 4.0 2.3 V 0.25 3V 0.25 4.5 V 0.23 1.65 V 0.6 2.3 V 0.3 3V 0.25 4.5 V 3 INT VOL = 0.4 V 1.65 V to 5.5 V 3 SCL, SDA, RESET VI = VCCI or GND ADDR VI = VCCP or GND IIH P port VI = VCCP IIL P port VI = GND ICC (ICCP + ICCI) Standby mode 0.1 mA 1 mA 1.65 V to 5.5 V 8 30 SDA, P port, ADDR, RESET VI on SDA and RESET= VCCI or GND, VI on P port and ADDR = VCCP, IO = 0, I/O = inputs, fSCL = 100 kHz 1.65 V to 5.5 V 1.7 10 SCL, SDA, P port, ADDR, RESET VI on SCL, SDA and RESET = VCCI or GND, VI on P port and ADDR = VCCP, IO = 0, I/O = inputs, fSCL = 0 1.65 V to 5.5 V 0.1 3 SCL,SDA RESET One input at VCCI - 0.6 V, Other inputs at VCCI or GND P port, ADDR, One input at VCCP - 0.6 V, Other inputs at VCCP or GND SCL VI = VCCI or GND SDA VIO = VCCI or GND P port VIO = VCCP or GND mA 1 VI on SDA and RESET= VCCI or GND, VI on P port and ADDR = VCCP, IO = 0, I/O = inputs, fSCL = 400 kHz CI (1) 0.1 1.65 V to 5.5 V SDA, P port, ADDR, RESET ICCP Cio mA 15 1.65 V to 5.5 V Additional current in Standby mode ICCI V 0.24 1.65 V to 5.5 V Operating mode V V 0.45 VOL = 0.4 V II 1.4 1.65 V SDA IOL UNIT V 1 1.65 V MAX mA 25 1.65 V to 5.5 V mA 60 1.65 V to 5.5 V 1.65 V to 5.5 V 6 7 7 8 7.5 8.5 pF pF Except for ICC, all typical values are at nominal supply voltage (VCCP = VCCI =1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25C. For ICC, all typical values are at VCCP = VCCI = 3.3 V and TA = 25C. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 15 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com I2C INTERFACE TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 ms tscl I2C clock low time 4.7 1.3 ms 2 tsp I C spike time tsds I2C serial data setup time tsdh I2C serial data hold time 0 50 0 50 kHz ns 250 100 ns 0 0 ns 2 ticr I C input rise time 1000 20 + 0.1Cb (1) ticf I2C input fall time 300 20 + 0.1Cb (1) 300 ns tocf I2C output fall time; 10 pF to 400 pF bus 300 20 + 0.1Cb (1) 300 ms tbuf I2C bus free time between Stop and Start 2 300 ns 4.7 1.3 ms tsts I C Start or repeater Start condition setup time 4.7 0.6 ms tsth I2C Start or repeater Start condition hold time 4 0.6 ms tsps I2C Stop condition setup time 4 0.6 ms tvd(data) Valid data time; SCL low to SDA output valid 1 1 ms tvd(ack) Valid data time of ACK condition; ACK signal from SCL low to SDA (out) low 1 1 ms (1) Cb = total capacitance of one bus line in pF RESET TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13) STANDARD MODE I2C BUS MIN MAX FAST MODE I2C BUS MIN UNIT MAX tW Reset pulse duration 4 4 ns tREC Reset recovery time 0 0 ns 600 600 ns tRESET Time to reset (1) (1) 16 Minimum time for SDA to become high or minimum time to wait before doing a START. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL 100 pF (unless otherwise noted) (see Figure 10) PARAMETER FROM TO STANDARD MODE I2C BUS MIN FAST MODE I2C BUS MAX MIN UNIT MAX tIV Interrupt valid time P port INT 4 4 ms tIR Interrupt reset delay time SCL INT 4 4 ms tPV Output data valid SCL P27-P00 400 400 ns tPS Input data setup time P port SCL 0 0 ns tPH Input data hold time P port SCL 300 300 ns Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 17 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS TA = 25C (unless otherwise noted) SUPPLY CURRENT vs TEMPERATURE 60 VCC = 3.3 V 40 30 VCC = 2.5 V 20 VCC = 1.8 V 10 -15 35 60 5 VCC = 2.5 V 4 3 2 0 1.65 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 85 0 0.1 0.2 0.3 0.4 0.5 50 VCC = 2.5 V 22 20 TA = -40C TA = 85C 18 TA = 25C 16 14 12 10 8 TA = 85C 6 4 0.2 0.3 0.4 0.5 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE I/O LOW VOLTAGE vs TEMPERATURE 20 15 TA = 85C 10 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 Output Low Voltage, VOL (V) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 400 20 Output Low Voltage, VOL (mV) VCC = 1.8 V TA = -40C TA = 25C 30 25 20 15 10 TA = 85C 5 0 0.1 25 5 0.1 TA = 25C 30 0 Output Low Voltage, VOL (V) 40 35 2 0 TA = -40C 40 0 0.6 VCC = 3.3 V 45 TA = -40C Output Low Voltage, VOL (V) VCC = 5 V 0 20 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 4 35 30 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 6 45 40 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 8 50 60 50 Supply Voltage, VCC (V) 10 0 35 60 Temperature, TA (C) TA = 25C 12 10 70 Temperature, TA (C) 16 14 -15 80 10 VCC = 1.8 V 0 -40 85 2 Sink Current, ISINK (mA) VCC = 3.3 V 1 10 VCC = 1.8 V 18 0.2 0.3 0.4 Output Low Voltage, VOL (V) 18 6 fSCL = 400 kHz All I/Os unloaded 90 VCC = 5 V 7 24 20 100 SCL = VCC All I/Os unloaded Sink Current, ISINK (mA) 50 8 Supply Current, ICC (A) Supply Current, ICC (A) VCC = 5 V 70 Sink Current, ISINK (mA) Supply Current, ICC (A) 80 0 -40 Sink Current, ISINK (mA) 9 fSCL = 400 kHz All I/Os unloaded 90 SUPPLY CURRENT vs SUPPLY VOLTAGE 0.5 Source Current, ISOURCE (mA) 100 STANDBY SUPPLY CURRENT vs TEMPERATURE 350 VCC = 5 V, ISINK = 10 mA 300 250 200 150 100 50 0 -40 VCC = 1.8 V, ISINK = 10 mA VCC = 5 V, ISINK = 1 mA VCC = 1.8 V, ISINK = 1 mA TA = -40C 16 TA = 25C 12 8 TA = 85C 4 0 -15 10 35 60 Temperature, TA (C) Submit Documentation Feedback 85 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VCC - VOH (V) Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) TA = 25C (unless otherwise noted) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 50 50 VCC = 2.5 V VCC = 3.3 V 45 Source Current, ISOURCE (mA) TA = -40C 20 TA = 25C 15 10 TA = 85C 5 40 35 TA = 25C 30 25 20 15 TA = 85C 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.7 TA = -40C 40 TA = 25C 35 30 25 20 15 TA = 85C 10 5 0 0 0 VCC = 5 V 45 TA = -40C Source Current, ISOURCE (mA) 25 Source Current, ISOURCE (mA) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 0.1 0.2 0.3 0.4 0.6 0.7 0.5 VCC - VOH (V) 0 0.1 0.2 0.3 0.4 0.5 0.6 VCC - VOH (V) VCC - VOH (V) I/O HIGH VOLTAGE vs TEMPERATURE 5 VCC - VOH (V) 4 3 VCC = 1.8 V, ISOURCE = 10 mA 2 1 VCC = 5 V, ISOURCE = 10 mA 0 -40 -15 10 35 60 85 Temperature, TA (C) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 19 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION VCCI RL = 1 kW SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Two Bytes for READ Input Port Register (see Figure 9) Address Bit 7 (MSB) Stop Start Condition Condition (P) (S) tscl Address Bit 1 R/W Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 VCCI SCL 0.3 VCCI ticr tsp ticf tbuf tvd tvd tocf tsts tsps SDA 0.7 VCCI 0.3 VCCI ticr ticf tsth tsdh tsds tvd(ack) Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 2 1 I C address 2 Input register port data A. CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 10. I2C Interface Load Circuit and Voltage Waveforms 20 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) VCCI RL = 4.7 kW INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 0 1 0 0 0 AD 1 DR 1 A 1 2 3 4 5 6 A 7 8 Data 1 ACK From Slave Data From Port Data 2 A 1 P A tir tir B B INT tiv A tsps A Data Into Port Address Data 1 0.5 VCCI INT SCL Data 2 0.7 VCCI R/W tiv A tir 0.5 VCCP Pn 0.5 VCCI INT View A-A View B-B A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 11. Interrupt Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 21 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 500 W Pn DUT 2 VCCP CL = 50 pF (see Note A) 500 W P PORT LOAD CONFIGURATION SCL P0 A P3 0.7 VCCP 0.3 VCCI Slave ACK SDA tpv (see Note B) Pn Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.7 VCCI SCL P0 A tps P3 0.3 VCCI tph Pn 0.5 VCCP READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 x VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 12. P-Port Load Circuit and Timing Waveforms 22 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) VCCI R L = 1 kW 500 W Pn SDA DUT DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION 2 VCCP CL = 50 pF (see Note A) 500 W P PORT LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 VCCI tRESET VCCP/2 RESET tREC tREC tW VCCP/2 Pn tRESET A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. The outputs are measured one at a time, with one transition per measurement. D. I/Os are configured as inputs. E. All parameters and waveforms are not applicable to all devices. Figure 13. Reset Load Circuits and Voltage Waveforms Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 23 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION Figure 14 shows an application in which the TCA6424A can be used. VCCI VCCP 10 kW ( 7) VCCI (1.8 V) 10 kW VCC 10 kW 10 kW 31 10 kW 29 SCL Master Controller SDA 30 32 INT GND 29 RESET Status Monitor VCCI SCL 27 VCCP P00 ALARM (see Note D) Subsystem 1 (e.g., Alarm) 1 A SDA P01 INT 2 ENABLE RESET P02 TCA6424A P03 P04 24 P05 P27 23 P06 P26 22 P07 P25 21 P10 P24 20 P11 P23 19 P12 P22 18 P13 P21 17 P14 P20 P15 26 ADDR P16 P17 GND B 3 4 5 6 7 8 9 10 Keypad 11 12 13 14 15 16 25 A. Device address configured as 0100000 for this example. B. P00 and P02-P10 are configured as inputs. C. P01, P11-P17, and P20-P27 are configured as outputs. D. Resistors are required for inputs (on P port) that may float. If a driver to an input will not let the input float, a resistor is not needed. Outputs (in the P port) do not need pullup resistors. Figure 14. Typical Application 24 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 Minimizing ICC When I/Os Control LEDs When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in Figure 14. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs that must minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VCC when the LED is off. Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional supply current consumption when the LED is off. VCC LED 100 kW VCC Px Figure 15. High-Value Resistor in Parallel With the LED 3.3 V 5V LED VCC Px Figure 16. Device Supplied by a Low Voltage Power-On Reset Requirements In the event of a glitch or data corruption, TCA6424A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 17 and Figure 18. VCC Ramp-Up Ramp-Down Re-Ramp-Up VCC_TRR_GND Time VCC_RT VCC_FT Time to Re-Ramp VCC_RT Figure 17. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 25 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com VCC Ramp-Up Ramp-Down VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 18. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 10 specifies the performance of the power-on reset feature for TCA6424A for both types of power-on reset. Table 10. Recommended Supply Sequencing and Rates PARAMETER (1) MAX UNIT tVCC_FT Fall rate See Figure 17 1 100 ms tVCC_RT Rise rate See Figure 17 0.01 100 ms tVCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 17 40 ms tVCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN - 50 mV) See Figure 18 40 ms VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 ms See Figure 19 1.2 V tVCC_GW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 x VCCx See Figure 19 10 ms VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V (1) MIN TYP TA = -40C to 85C (unless otherwise noted) Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 19 and Table 10 provide more information on how to measure these specifications. VCC VCC_GH Time VCC_GW Figure 19. Glitch Width and Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 20 and Table 10 provide more details on this specification. 26 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A TCA6424A www.ti.com SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 VCC VPOR VPORF Time POR Time Figure 20. VPOR Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A 27 TCA6424A SCPS193B - JULY 2010 - REVISED SEPTEMBER 2010 www.ti.com REVISION HISTORY Changes from Original (July 2010) to Revision A * 28 Page Changed Recommended Supply Sequencing and Rates Table ........................................................................................ 26 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TCA6424A PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2010 PACKAGING INFORMATION Orderable Device TCA6424ARGJR Status (1) ACTIVE Package Type Package Drawing UQFN RGJ Pins Package Qty 32 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device TCA6424ARGJR Package Package Pins Type Drawing UQFN RGJ 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 5.3 0.75 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA6424ARGJR UQFN RGJ 32 3000 346.0 346.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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